Memory access method, computing system and electronic device

Abstract

Disclosed in embodiments of the present application are a memory access method, a computing system and an electronic device. The method is applied to a first computing device in a computing system. The computing system comprises a memory pool and a plurality of computing devices, the memory pool comprises a plurality of compute express link (CXL) memory devices, each CXL memory device comprises a plurality of CXL ports, and each computing device comprises a plurality of CXL ports, wherein the plurality of CXL ports of each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports of each computing device are respectively connected to different CXL memory devices, and any two computing devices among the plurality of computing devices are connected via at least one CXL memory device. The method comprises: in response to a communication request sent by a second computing device, sending a memory access request to a first CXL memory device, so as to request to access a memory space of the first CXL memory device.

Description

Memory access method, computing system, and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202410452151.4 filed on April 15, 2024, and entitled "Memory access method, computing system, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of server, and in particular to a memory access method, a computing system, and an electronic device. BACKGROUND

[0003] Compute Express Link (CXL) is a high-speed interconnection technology that supports multiple computing devices to use a remotely pooled memory pool, reduces the memory gap between computing devices, enables high-speed data transmission and memory sharing, and provides higher data throughput and lower latency, thereby meeting the needs of modern computing and storage systems.

[0004] Currently, the related technology plans to connect multiple computing devices and multiple CXL memory devices through a CXL switch, so that multiple computing devices share a memory pool formed by multiple CXL memory devices.

[0005] However, the current CXL switch is not yet mature, and the above technical solution needs to rely on the CXL switch to form the memory pool. When the computing device accesses the memory space based on the CXL switch, it may cause a large delay in memory access, and when facing multiple levels of CXL switches, it will bring even greater latency, seriously affecting the performance of the memory pool. SUMMARY

[0006] Embodiments of the present application provide a memory access method, a computing system, and an electronic device, which can effectively reduce the latency of memory access and thus guarantee the performance of the memory pool.

[0007] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0008] In an aspect, a memory access method is provided for a first computing device in a computing system, the computing system comprising a memory pool and a plurality of computing devices, the memory pool comprising a plurality of computing express link (CXL) memory devices, each CXL memory device comprising a plurality of CXL ports, each computing device comprising a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are connected to different computing devices, the plurality of CXL ports on each computing device are connected to different CXL memory devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device; the method comprising:

[0009] sending a memory access request to the first CXL memory device in response to a communication request sent by a second computing device, the communication request being used to request access to a memory space of the first CXL memory device, the memory access request being used to request access to the memory space of the first CXL memory device; wherein the first computing device is a computing device connected to a CXL port of the first CXL memory device, and the second computing device is a computing device connected to the first computing device through a second CXL memory device.

[0010] In the above technical solution, the plurality of computing devices are connected to the plurality of CXL memory devices, wherein each computing device is connected to a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected thereto. And each CXL memory device is connected to a plurality of different computing devices, wherein any two computing devices are connected to a CXL memory device in common, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected thereto, but also access the CXL memory device connected to other computing devices through other computing devices connected to a CXL memory device in common, thereby realizing memory sharing among the plurality of computing devices in the memory pool. Through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed. In this way, the memory pool can be formed without relying on a CXL switch, the latency of memory access can be effectively reduced, the performance of the memory pool can be guaranteed, and the access performance of the computing device can be effectively guaranteed.

[0011] In some possible implementation manners, the memory access request is a data read request, the data read request being used to request to perform a read operation on the memory space of the first CXL memory device; after the memory access request is sent to the first CXL memory device, the method further comprises: writing the read first data to a second CXL memory device.

[0012] In the implementation manner, the first data read is written to the second CXL memory device, so that the second CXL memory device reads the first data by accessing the second CXL memory device subsequently.

[0013] In some possible implementation manners, the memory access request is a data write request, and the data write request is used to request to perform a write operation on the memory space of the first CXL memory device; before the memory access request is sent to the first CXL memory device, the method further includes: reading second data from the second CXL memory device; and generating the memory access request based on the read second data.

[0014] In the implementation manner, the memory access request is generated based on the read second data to request to write the second data in the first CXL memory device.

[0015] In another aspect, a memory access method is provided, which is applied to a management device, and the management device is used to perform memory management on a memory pool in a computing system; the computing system includes the memory pool and a plurality of computing devices, the memory pool includes a plurality of CXL memory devices, each CXL memory device includes a plurality of CXL ports, and each computing device includes a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are connected to different computing devices respectively, the plurality of CXL ports on each computing device are connected to different CXL memory devices respectively, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device; and the method includes:

[0016] In response to a memory allocation request of a second computing device, memory requirement of the second computing device is obtained; if the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the plurality of CXL memory devices connected to a first computing device meets the memory requirement of the second computing device, memory of a first CXL memory device that meets the memory requirement is allocated to the second computing device from the plurality of CXL memory devices connected to the first computing device; wherein the first computing device is a computing device connected to a CXL port of the first CXL memory device, and the second computing device is a computing device connected to the first computing device through a second CXL memory device.

[0017] In the technical solution, the plurality of computing devices are connected with the plurality of CXL memory devices, wherein each computing device is connected with a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected therewith. Each CXL memory device is connected with a plurality of different computing devices, wherein any two computing devices are connected with a CXL memory device in common, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected therewith, but also access the CXL memory device connected with other computing devices through other computing devices connected with the CXL memory device in common, thereby realizing memory sharing among the plurality of computing devices in the memory pool. The management device is deployed to manage the plurality of CXL memory devices in the memory pool. In a case where the memory of the plurality of CXL memory devices connected with the second computing device does not meet the memory requirement of the second computing device, but the memory of the plurality of CXL memory devices connected with the first computing device meets the memory requirement of the second computing device, the memory of the first CXL memory device meeting the memory requirement of the second computing device among the plurality of CXL memory devices connected with the first computing device can be allocated to the second computing device, so that the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed through subsequent network communication between the first computing device and the second computing device. In this way, the memory pool can be formed without relying on the CXL switch, the latency of memory access can be effectively reduced, the performance of the memory pool can be guaranteed, and the access performance of the computing device can be effectively guaranteed.

[0018] In some possible implementation manners, the memory requirement indicates that the memory type is a target type and the memory size is a target capacity.

[0019] The method further includes: if the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected with the second computing device is greater than or equal to the target capacity, determining that the memory of the plurality of CXL memory devices connected with the second computing device meets the memory requirement of the second computing device; and if the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected with the second computing device is less than the target capacity, determining that the memory of the plurality of CXL memory devices connected with the second computing device does not meet the memory requirement of the second computing device.

[0020] In the implementation manners, a manner of judging whether the memory requirement of the second computing device is met based on the memory type and the memory size is provided. In this way, the memory meeting the memory requirement can be allocated to the second computing device, so that the accuracy of memory allocation is ensured.

[0021] In some possible implementations, the first CXL memory device is connected to the first computing device through a first CXL port of the first CXL memory device, and the second CXL memory device is connected to the second computing device through a second CXL port of the second CXL memory device.

[0022] In the above implementations, by sending the device information of the first computing device and the memory address of the first CXL memory device to the second computing device, the second computing device can subsequently implement network communication with the first computing device based on the device information of the first computing device and the memory address of the first CXL memory device, so as to ensure smooth memory access.

[0023] In another aspect, a memory pool is provided, which is configured to provide memory resources for a plurality of computing devices; the memory pool comprises a plurality of CXL memory devices, each of which comprises a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively configured to connect different computing devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device.

[0024] The first CXL memory device is configured to receive a memory access request sent by the first computing device, the memory access request being configured to request access to a memory space of the first CXL memory device; the first computing device is a computing device connected to the first CXL memory device through a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device through the second CXL memory device.

[0025] The first CXL memory device is further configured to execute a memory access operation indicated by the memory access request based on the memory access request.

[0026] In the above memory pool, each CXL memory device includes a plurality of CXL ports to respectively connect a plurality of different computing devices, wherein any two computing devices in the plurality of computing devices are connected through at least one CXL memory device, so that each computing device and other computing devices have at least one CXL memory device that can share data. On this basis, each computing device can not only access the CXL memory device connected thereto, but also access the CXL memory device connected to other computing devices through other computing devices that are connected to the CXL memory device together, realizing memory sharing between a plurality of computing devices in the memory pool. Through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed. In this way, the memory pool can be formed without relying on a CXL switch, which can effectively reduce the latency of memory access, not only guaranteeing the performance of the memory pool, but also effectively guaranteeing the access performance of the computing device.

[0027] In some possible implementation manners, the CXL port is at least one of a multi-channel input / output (MCIO) port, a universal serial bus (USB-C) port, or another port supporting the CXL protocol.

[0028] In the above implementation manner, a plurality of types of CXL ports are provided, enriching the types of CXL ports. Further, the CXL port supporting the CXL protocol is provided, so as to realize memory sharing of different computing devices based on a plurality of CXL memory devices based on the CXL protocol.

[0029] In some possible implementation manners, the plurality of CXL ports are a plurality of physical ports, that is, one CXL port corresponds to one physical port, or the plurality of CXL ports are a plurality of ports split from one physical port, that is, one CXL port can be split into two or more CXL ports through a CXL adapter cable, for connecting two or more different computing devices.

[0030] In the above implementation manner, one CXL port can be flexibly split into two or more CXL ports, improving the flexibility of the CXL port setting.

[0031] In some possible implementation manners, each CXL memory device includes a memory medium, and the memory medium includes at least one of a dynamic random access memory (DRAM) particle or a dual in-line memory module (DIMM) memory stick.

[0032] In the above implementation manner, a plurality of types of memory media are provided, enriching the types of memory media.

[0033] In some possible implementation manners, the number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, the first number of CXL ports in each computing device, and the second number of CXL ports in each CXL memory device; wherein the number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices, and negatively correlated with the second number.

[0034] In the implementation manners described above, a manner of calculating the number of the plurality of CXL memory devices is provided. The number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, the number of CXL ports in each computing device, and the number of CXL ports in each CXL memory device, so that the determined number of the plurality of CXL memory devices can meet the requirement of the number of CXL memory devices for establishing the memory pool subsequently.

[0035] In some possible implementation manners, the memory access operation includes a read operation or a write operation.

[0036] In the implementation manners described above, a memory access scheme based on the read operation or the write operation is provided, so that the computing device can implement the read operation or the write operation based on the CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0037] In another aspect, a computing system is provided, which includes a memory pool and a plurality of computing devices, the memory pool includes a plurality of CXL memory devices, each CXL memory device includes a plurality of CXL ports, and each computing device includes a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are connected to different computing devices respectively, the plurality of CXL ports on each computing device are connected to different CXL memory devices respectively, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device.

[0038] The first computing device is configured to send a memory access request to the first CXL memory device in response to a communication request sent by the second computing device, the communication request being used to request to access the memory space of the first CXL memory device, and the memory access request being used to request to access the memory space of the first CXL memory device; the first computing device is a computing device connected to one CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device through the second CXL memory device.

[0039] The first CXL memory device is configured to receive the memory access request sent by the first computing device, and perform a memory access operation indicated by the memory access request based on the memory access request.

[0040] In the above computing system, a plurality of computing devices are connected with a plurality of CXL memory devices, wherein each computing device is connected with a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected therewith. And each CXL memory device is connected with a plurality of different computing devices, wherein any two computing devices are connected with one CXL memory device, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected therewith, but also access the CXL memory device connected with other computing devices through other computing devices connected with one CXL memory device, realizing memory sharing between a plurality of computing devices in the memory pool. Through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed. In this way, the memory pool can be formed without relying on the CXL switch, which can effectively reduce the latency of memory access, not only guaranteeing the performance of the memory pool, but also effectively guaranteeing the access performance of the computing device.

[0041] In some possible implementations, the first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices and the second number of CXL ports in each CXL memory device; wherein the first number is positively correlated with the number of the plurality of computing devices and negatively correlated with the second number.

[0042] In the above implementation, by deploying the first number of CXL ports, each computing device can connect the first number of CXL memory devices through the first number of CXL ports, so as to realize the interconnection between the plurality of computing devices and the plurality of CXL memory devices, thereby guaranteeing that each computing device can access the memory space of any CXL memory device.

[0043] In some possible implementations, the CXL port is at least one of a multi-channel input / output (MCIO) port, a universal serial bus (USB-C) port, or other CXL protocol supported port.

[0044] In the above implementation, a plurality of types of CXL ports are provided, which enriches the types of CXL ports. And by setting the CXL port supporting the CXL protocol, the memory sharing of different computing devices based on a plurality of CXL memory devices is realized based on the CXL protocol.

[0045] In some possible implementation manners, the number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, the first number of CXL ports in each computing device, and the second number of CXL ports in each CXL memory device; wherein the number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices and the first number, and is negatively correlated with the second number.

[0046] In the implementation manners described above, the number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, the number of CXL ports in each computing device, and the number of CXL ports in each CXL memory device, so that the determined number of the plurality of CXL memory devices can meet the requirement of the number of CXL memory devices for establishing a memory pool subsequently, and interconnection between the plurality of computing devices and the plurality of CXL memory devices is implemented, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0047] In some possible implementation manners, the memory access operation includes a read operation or a write operation.

[0048] In the implementation manners described above, a memory access scheme based on a read operation or a write operation is provided, so that a computing device can implement a read operation or a write operation based on a CXL memory device by accessing the memory space of a CXL memory device in a memory pool.

[0049] In another aspect, a memory access method is provided, which is applied to a first CXL memory device in a memory pool, and the memory pool is used to provide memory resources for a plurality of computing devices; the memory pool includes a plurality of CXL memory devices, and each CXL memory device includes a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively used to connect different computing devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device; and the method includes:

[0050] The first CXL memory device receives a memory access request sent by a first computing device, and the memory access request indicates a request to access the memory space of the first CXL memory device; the first computing device is a computing device connected to one CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device through a second CXL memory device;

[0051] The first CXL memory device performs a memory access operation indicated by the memory access request based on the memory access request.

[0052] In the technical solution, each CXL memory device includes a plurality of CXL ports to connect a plurality of different computing devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device. In this way, there is at least one CXL memory device shared by each computing device and other computing devices. On this basis, each computing device can not only access the CXL memory device connected thereto, but also access the CXL memory device connected to other computing devices through other computing devices connected to the CXL memory device, thereby realizing memory sharing among a plurality of computing devices in a memory pool. Through network communication between the first computing device and the second computing device, the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed. In this way, the memory pool can be formed without relying on a CXL switch, the latency of memory access can be effectively reduced, the performance of the memory pool can be guaranteed, and the access performance of the computing device can be effectively guaranteed.

[0053] In some possible implementation manners, the memory access operation includes a read operation or a write operation.

[0054] In the implementation manners, a memory access scheme based on a read operation or a write operation is provided, so that the computing device can implement a read operation or a write operation based on the CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0055] In another aspect, a CXL memory device is provided, which includes a CXL controller and a memory medium; the CXL controller and the memory medium are coupled. The memory medium is configured to store computer program instructions, and the CXL controller is configured to invoke the computer program instructions in the memory medium to execute the content performed by the CXL memory device in the memory access method shown in the above embodiments.

[0056] In another aspect, an electronic device is provided, which includes a processor and a memory; the processor and the memory are coupled. The memory is configured to store computer program instructions, and the processor is configured to invoke the computer program instructions in the memory to execute the content performed by the computing device or the management device in the memory access method shown in the above embodiments. In the embodiments of the present application, the computing device or the management device can be the electronic device.

[0057] In another aspect, a computer readable storage medium is provided, which stores computer program instructions for causing the CXL memory device or the electronic device to perform the memory access method shown in the above embodiments.

[0058] In another aspect, a computer program product is provided, including computer program instructions that, when executed on a CXL memory device or an electronic device, cause the CXL memory device or the electronic device to perform the memory access method as shown in the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0059] FIG. 1 is a schematic diagram of an architecture of a data center system provided by the related art;

[0060] FIG. 2 is a schematic diagram of another architecture of a data center system provided by the related art;

[0061] FIG. 3 is a schematic diagram of an architecture of a CXL switch-based memory pool provided by the related art;

[0062] FIG. 4 is a schematic diagram of an architecture of a computing system provided by an embodiment of the present application;

[0063] FIG. 5 is a schematic diagram of a hardware structure of a CXL memory expansion card provided by an embodiment of the present application;

[0064] FIG. 6 is a schematic diagram of a hardware structure of a computing device provided by an embodiment of the present application;

[0065] FIG. 7 is a schematic diagram of a hardware structure of a management device provided by an embodiment of the present application;

[0066] FIG. 8 is a schematic diagram of a memory access method provided by an embodiment of the present application;

[0067] FIG. 9 is a schematic diagram of a memory access method provided by an embodiment of the present application;

[0068] FIG. 10 is a schematic diagram of a structure of a memory access device provided by an embodiment of the present application;

[0069] FIG. 11 is a schematic diagram of a structure of a memory access device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0070] In the description of the embodiments of the present application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this document only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can mean that A exists alone, A and B exist together, and B exists alone. In addition, "at least one" means one or more, and "multiple" means two or more. "First", "second", and the like do not limit the quantity and execution order, and "first", "second", and the like do not necessarily mean different.

[0071] It should be noted that the terms "exemplary" or "for example" when used in this specification mean "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other embodiments or suitable designs. Rather, use of these terms is intended to present concepts in a concrete manner.

[0072] With the continuous popularization of large data processing scenarios such as artificial intelligence (AI) large models, the applications running on the computing device are usually resource occupation intensive applications, such as compute-intensive applications, memory-intensive applications, communication-intensive applications, and the like. Among them, the compute-intensive application refers to an application in which the central processing unit (CPU) is biased towards computation. The memory-intensive application refers to an application in which the CPU is biased towards reading or writing data from the memory. The communication-intensive application refers to an application in which the CPU is biased towards reading or writing data from the network card.

[0073] When the computing device performs data computation on the above resource occupation intensive application, it is usually necessary to save a large amount of data to the memory space, and then perform the next step of data computation in the memory space. However, the current data center system cannot provide a large amount of memory space for the data computation of the above resource occupation intensive application.

[0074] For example, FIG. 1 is a schematic diagram of an architecture of a data center system provided by the related art. Referring to FIG. 1, in the data center system of the related art, a conventional data center system as shown in FIG. 1 is connected to general-purpose computing nodes, special-purpose computing nodes, heterogeneous computing nodes, and storage nodes through top-of-rack switches (TOR switches). The general-purpose computing nodes can include computing devices for various application fields and various algorithms, such as personal computers, notebook computers, servers, and general-purpose computers. In some possible implementation manners, the general-purpose computing nodes can be deployed with CPUs. The special-purpose computing nodes can include computing devices specially designed for a certain application field or for a certain algorithm, such as automated teller machines (ATMs), medical devices, industrial control systems, and special-purpose computers. In some possible implementation manners, the special-purpose computing nodes can be deployed with ×PUs, such as graphics processing units (GPUs), tensor processing units (TPUs), neural network processing units (NPUs), data processing units (DPUs), and the like. The heterogeneous computing nodes refer to a special parallel distributed computing system that can efficiently utilize computing resources to effectively achieve high computing power. In some possible implementation manners, the heterogeneous computing nodes can be deployed with CPUs and ×PUs. The storage nodes can include computing devices for storing and managing data, such as storage servers.

[0075] Referring to FIG. 1, for any one of the general-purpose computing nodes, the special-purpose computing nodes, and the heterogeneous computing nodes in the data center system, a memory of the computing node is separately deployed, and the memory cannot be further expanded, so that each computing node can only access the memory space of the computing node, and the memory space is limited.

[0076] Exemplarily, FIG. 2 is a schematic diagram of an architecture of another data center system provided by the related art. Referring to FIG. 2, in the data center system of the related art, as shown in the next-generation data center system of FIG. 2, the general computing nodes, the special computing nodes, the memory-pooled nodes, and the storage nodes are connected to the high-bandwidth IB network through the top-of-rack switches. Among them, the general computing nodes and the special computing nodes do not contain too much memory space (such as local memory) by themselves, but deploy the memory-pooled nodes to concentrate the massive memory space of multiple CXL memory devices to form a memory pool. And the general computing nodes, the special computing nodes, the memory-pooled nodes, and the storage nodes in the data center are connected through low-latency CXL, thereby realizing memory pooling.

[0077] Among them, CXL is a high-speed interconnection technology that supports multiple computing devices to use a remotely pooled memory pool, reduces the memory gap between computing devices and computing devices, can realize high-speed data transmission and memory sharing, provides higher data throughput and lower latency, and thus can meet the needs of modern computing and storage systems.

[0078] Exemplarily, FIG. 3 is a schematic diagram of an architecture of a CXL switch-based memory pool provided by the related art. Referring to FIG. 3, it is usually necessary to connect multiple computing devices (such as host 1, host 2, …, host n shown in FIG. 3, n is a positive integer greater than or equal to 2) and multiple CXL memory devices through a CXL switch, thereby realizing that multiple computing devices share the memory pool formed by multiple CXL memory devices.

[0079] However, in the related art, the CXL switch needs to be relied on to form a memory pool. On the one hand, due to the low technical maturity of the CXL switch, it is difficult to be widely used in a short period of time, and on the other hand, when the computing device accesses the memory space based on the CXL switch, it may cause a large delay in memory access, and when facing multiple levels of CXL switches, it will bring greater delay, which seriously affects the performance of the memory pool.

[0080] In view of this, the embodiment of the present application provides a memory pool and a computing system based on the memory pool. The computing system provided by the embodiment of the present application comprises a plurality of computing devices and a plurality of CXL memory devices connected by CXL cables, wherein each computing device is connected to a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected thereto through the CXL cables. And each CXL memory device is connected to a plurality of different computing devices, wherein any two computing devices are connected to at least one CXL memory device, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected thereto through the CXL cable, but also access the CXL memory device connected to other computing devices through other computing devices connected to the CXL memory device, thereby realizing memory sharing among the plurality of computing devices in the memory pool. In this way, the memory pool does not need to rely on a CXL switch, which can effectively reduce the latency of memory access, not only guaranteeing the performance of the memory pool, but also effectively guaranteeing the access performance of the computing device.

[0081] FIG. 4 is a schematic diagram of the architecture of a computing system provided by the embodiment of the present application. Referring to FIG. 4, the computing system 400 comprises a memory pool 401 and a plurality of computing devices 402.

[0082] The memory pool 401 comprises a plurality of CXL memory devices, which can also be referred to as a CXL memory pool, for providing memory resources for the plurality of computing devices 402. Referring to FIG. 4, the plurality of CXL memory devices can be CXL memory device ①, CXL memory device ②, …, CXL memory device ⑥, etc. shown in FIG. 4. The plurality of computing devices 402 can be computing device ①, computing device ②, computing device ③, computing device ④, etc. shown in FIG. 4.

[0083] In some possible implementation manners, the CXL memory device can be a CXL memory expansion card. For example, FIG. 5 is a schematic diagram of the hardware structure of a CXL memory expansion card provided by the embodiment of the present application. Referring to FIG. 5, each CXL memory expansion card can comprise a CXL controller and a memory medium connected to the CXL controller. For example, the CXL controller can be referred to as a CXL memory expander chip or a CXL memory expander controller. In some possible implementation manners, the CXL controller can be connected to a plurality of CXL ports of the CXL memory device.

[0084] Exemplarily, the memory medium can include at least one of a dynamic random access memory (DRAM) grain or a dual inline memory module (DIMM) memory stick. Of course, in other implementations, the memory medium can also include a flash grain. In this way, a variety of types of memory medium are provided, enriching the types of memory medium. It should be understood that the computing device is able to access the memory space of the memory medium connected to the CXL memory device by accessing the CXL memory device connected thereto.

[0085] Each CXL memory device includes a plurality of CXL ports, wherein the plurality is two or more. The CXL port of the CXL memory device can be an access port of the computing device. In some possible implementations, the CXL port is at least one of a mini cool edge input / output (MCIO) port, a universal serial bus type-C (USB-C) port or other CXL protocol supported port.

[0086] Embodiments of the present application do not limit the type of CXL port. In this way, a variety of types of CXL port are provided, enriching the types of CXL port. And, by setting the CXL port supporting the CXL protocol, memory sharing of different computing devices based on the plurality of CXL memory devices is realized based on the CXL protocol.

[0087] In some possible implementations, the CXL memory device can be a dual-port CXL memory expansion card, that is, the CXL memory device includes two CXL ports.

[0088] Exemplarily, referring to (5-1) in FIG. 5, an internal architecture of a dual-port CXL memory expansion card is shown, wherein the dual-port CXL memory expansion card can include port 1 and port 2. At this time, two computing devices connected with the two CXL ports of the dual-port CXL memory expansion card are able to access the memory space of the dual-port CXL memory expansion card.

[0089] In yet some possible implementations, the CXL memory device can be a multi-port CXL memory expansion card, that is, the CXL memory device includes a plurality of CXL ports.

[0090] For example, as shown in FIG. 5 (5-2), an internal architecture of a multi-port CXL memory expansion card is shown, where the multi-port CXL memory expansion card can include port 1, port 2, port 3, …, and so on. At this time, the multiple computing devices connected to the multiple CXL ports of the multi-port CXL memory expansion card can access the memory space of the multi-port CXL memory expansion card.

[0091] It should be noted that the multiple CXL ports involved in the embodiments of the present application can be multiple physical ports, that is, one CXL port corresponds to one physical port, or can be multiple ports split from one physical port, for example, one x16 port can be split into two x8 ports, that is, multiple CXL ports correspond to one physical port.

[0092] In some possible implementation manners, one physical port can be split into two or more ports through a CXL adapter cable for connecting two or more different computing devices. For example, as shown in FIG. 5 (5-2), taking port 3 as an example, port 3 can be split into two ports, such as port 3.1 and port 3.2. In this way, one physical port can be flexibly split into two or more CXL ports, improving the flexibility of CXL port setting.

[0093] In some possible implementation manners, in the case of a CXL memory device being a CXL memory expansion card, the memory pool 401 can be in the form of a chassis (or box). For example, in some possible implementation manners, multiple CXL memory expansion cards can be arranged (or arranged side by side) in a chassis (or box) to facilitate centralized management of the multiple CXL memory expansion cards. For example, the chassis can be provided with multiple slots for inserting CXL memory expansion cards. In this way, a memory pool can be formed based on the multiple CXL memory expansion cards. In this way, by centrally deploying the massive memory devices of the multiple CXL memory expansion cards in a chassis, high scalability, high utilization, high maintainability, and high manageability of the memory can be achieved.

[0094] In the case of the memory pool 401 being in the form of a chassis, the multiple CXL memory expansion cards can be powered by the same power supply or powered by multiple power supplies respectively. The embodiments of the present application do not limit this. It should be noted that when multiple CXL memory expansion cards are actually arranged in the chassis, part of the CXL memory expansion cards can be used to connect computing devices, for example, a part of the CXL memory expansion cards are connected to multiple computing devices 402 to form a memory pool, and the remaining CXL memory expansion cards can be used for other purposes, such as implementing other functions of the computing devices.

[0095] The above embodiments take the CXL memory device as a CXL memory expansion card to introduce the memory pool 401. In other possible implementation manners, the CXL memory device can also be a server deployed with a CXL memory expansion card, and correspondingly, the memory pool 401 can be a server cluster composed of multiple servers deployed with CXL memory expansion cards. In this way, the memory pool can also be formed based on multiple servers deployed with CXL memory expansion cards.

[0096] The computing device can be at least one of an independent physical server such as a general server, a graphics processing server, a data processing server, an artificial intelligence server, or the like, or a server cluster or a distributed file system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content distribution networks, and big data or artificial intelligence platforms. The embodiments of the present application do not limit this.

[0097] For example, FIG. 6 is a schematic diagram of a hardware structure of a computing device provided by an embodiment of the present application. Referring to FIG. 6, the computing device 600 shown in FIG. 6 can include a processor 601, a memory 602, a communication interface 603, multiple CXL ports 604, and a bus 605. The processor 601, the memory 602, the communication interface 603, and the multiple CXL ports 604 can be connected through the bus 605.

[0098] The processor 601 is the control center of the computing device 600, which can be a general central processing unit such as a CPU, or other general-purpose processors, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. In the embodiments of the present application, the processor 601 in the computing device 600 can be used to execute the content performed by the computing device in the memory access method. For example, the processor 601 can include one or more CPUs, such as CPU 0 and CPU 1 shown in FIG. 6.

[0099] The memory 602 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, or other type of dynamic storage device that can store information and instructions, and can be an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium, or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto. In an embodiment of the present application, the memory 602 can be connected to the processor 601 through the bus 604, and is used to store data, instructions, or program code. When the processor 601 invokes and executes the instructions or program code stored in the memory 602, the memory access method provided in the embodiments of the present application can be implemented.

[0100] The communication interface 603 is used for connecting the computing device 600 to other devices through a communication network. The communication interface 603 can include a receiving unit for receiving data, and a sending unit for sending data.

[0101] The number of the plurality of CXL ports 604 can be two or more. In some possible implementation manners, the CXL port is at least one of an MCIO port, a USB-C port, or other port supporting the CXL protocol. The embodiments of the present application do not limit the type of the CXL port.

[0102] It should be noted that the structure shown in FIG. 6 does not constitute a limitation on the computing device 600. In addition to the components shown in FIG. 6, the computing device 600 can include more or fewer components than those shown, or combine certain components, or different arrangement of components.

[0103] In the computing system 400, the plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the plurality of computing devices 402 are connected through at least one CXL memory device.

[0104] The computing device can connect the CXL port of the CXL memory device through a CXL cable. In some possible implementations, the CXL cable is a cable that supports the CXL protocol. For example, the CXL cable can be a peripheral component interconnect express (PCIE) cable. It should be noted that the CXL cable can also be other types of cables that support the CXL protocol. Embodiments of the present application do not limit the type of CXL cable. Thus, by arranging the CXL cable that supports the CXL protocol, the memory sharing of different computing devices based on multiple CXL memory devices can be implemented based on the CXL protocol.

[0105] In embodiments of the present application, any two computing devices are connected to one CXL memory device. In this way, each computing device and other computing devices have at least one CXL memory device that can share data, so as to share data through the commonly connected CXL memory device. For example, referring to FIG. 4, taking computing device 1 and computing device 2 as an example, since computing device 1 and computing device 2 are connected to CXL memory device 1, computing device 1 and computing device 2 can share data through the commonly connected CXL memory device 1. Other computing devices are similar and will not be described here.

[0106] Each computing device includes a first number of CXL ports, which are used to connect different CXL memory devices. It should be noted that the number of CXL ports included in each computing device is the same. It should also be noted that the first number of CXL ports included in each computing device are respectively connected to different CXL memory devices. In this way, each computing device can access the memory space of one or more CXL memory devices connected thereto through the CXL cable, which can better meet the memory and bandwidth requirements of a single computing device.

[0107] Each CXL memory device includes a second number of CXL ports, which are used to connect different computing devices. It should be noted that the number of CXL ports included in each CXL memory device is the same. It should also be noted that the second number of CXL ports included in each CXL memory device are respectively connected to different computing devices. In this way, the problem of repeated connection of the CXL memory device to the same computing device can be avoided, and the problem of memory waste can be reduced. By deploying the second number of CXL ports, each CXL memory device can be connected to the second number of computing devices through the second number of CXL ports, so as to achieve the effect that the second number of computing devices share the same CXL memory device.

[0108] In some possible implementation manners, the first quantity of CXL ports in each computing device is determined based on the quantity of the plurality of computing devices 402 and the second quantity of CXL ports in each CXL memory device.

[0109] The first quantity is positively correlated with the quantity of the plurality of computing devices 402 and negatively correlated with the second quantity.

[0110] For example, taking a dual-port CXL memory expansion card as an example, that is, taking the second quantity as 2 as an example, the determination process of the first quantity can be: determining the first quantity based on the quantity of the plurality of computing devices 402, the second quantity, and the following formula (1). Q≥N-P+1 (1)

[0111] In the formula, Q represents the first quantity, that is, the quantity of CXL ports included in each computing device; N represents the quantity of the plurality of computing devices 402; and P represents the second quantity, that is, the quantity of CXL ports included in each CXL memory device. It should be noted that the first quantity specifically refers to the quantity of CXL memory devices connected to each computing device, and does not mean that the computing device only includes the first quantity of CXL ports. For example, the computing device can include more CXL ports than the first quantity.

[0112] In this way, by deploying the first quantity of CXL ports, each computing device can connect the first quantity of CXL memory devices through the first quantity of CXL ports, so as to realize interconnection between the plurality of computing devices and the plurality of CXL memory devices, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0113] In some possible implementation manners, the quantity of the plurality of CXL memory devices is determined based on the quantity of the plurality of computing devices 402, the first quantity of CXL ports in each computing device, and the second quantity of CXL ports in each CXL memory device.

[0114] The quantity of the plurality of CXL memory devices is positively correlated with the quantity of the plurality of computing devices 402 and the first quantity, and negatively correlated with the second quantity.

[0115] For example, taking a dual-port CXL memory device as an example, that is, taking the second quantity as 2 as an example, the determination process of the quantity of the plurality of CXL memory devices can be: determining the quantity of the plurality of CXL memory devices based on the quantity of the plurality of computing devices 402, the first quantity, the second quantity, and the following formula (2). M≥N*Q / P (2)

[0116] In the formula, M represents the number of the plurality of CXL memory devices; N represents the number of the plurality of computing devices 402; Q represents a first number, i.e., the number of CXL ports included in each computing device; and P represents a second number, i.e., the number of CXL ports included in each CXL memory device.

[0117] With regard to the above formula (2), it can be understood that the value of N*Q is used to indicate the total number of CXL cables connected to the plurality of computing devices 402, and considering that the total number of CXL cables connected to the plurality of computing devices 402 should be consistent with the total number of CXL cables connected to the plurality of CXL memory devices, the number of the plurality of CXL memory devices can be quickly determined by dividing by P. In this way, based on the number of the plurality of computing devices 402, the number of CXL ports in each computing device, and the number of CXL ports in each CXL memory device, the number of the plurality of CXL memory devices is determined, so that the determined number of the plurality of CXL memory devices can meet the number requirement of CXL memory devices for establishing a memory pool subsequently, and the interconnection between the plurality of computing devices and the plurality of CXL memory devices is realized, thereby ensuring that each computing device can access the memory space of any CXL memory device.

[0118] Taking the first computing device and the first CXL memory device as an example, the first computing device is a computing device connected to the first CXL memory device through a CXL cable.

[0119] In an embodiment of the present application, the first computing device is configured to: in response to a communication request sent by a second computing device, send a memory access request to the first CXL memory device, the communication request being used to request access to the memory space of the first CXL memory device, and the memory access request being used to request access to the memory space of the first CXL memory device. The second computing device is a computing device connected to the first computing device through a second CXL memory device.

[0120] In an embodiment of the present application, the first CXL memory device is configured to: receive the memory access request sent by the first computing device, and perform a memory access operation indicated by the memory access request based on the memory access request.

[0121] For example, referring to FIG. 4, taking computing device ① as an example, since the computing device ① is connected to the CXL memory device ①, the CXL memory device ②, and the CXL memory device ③, the computing device ① can access the memory space of one or more of the CXL memory device ①, the CXL memory device ②, and the CXL memory device ③ through a CXL cable.

[0122] As another example, referring to FIG. 4, taking the computing device 1 and the computing device 4 as an example, the computing device 1 and the computing device 4 are connected with the CXL memory device 3. On this basis, the computing device 1 can share the CXL memory device 1 or the CXL memory device 2 connected thereto for use by the computing device 4. For example, taking the computing device 1 sharing the CXL memory device 1 connected thereto for use by the computing device 4 as an example, the computing device 4 can write data into the CXL memory device 3 and notify the computing device 1, and then the computing device 1 can read the data in the CXL memory device 3 and write the data into the CXL memory device 1. Alternatively, the computing device 1 can read data in the CXL memory device 1 and write the data into the CXL memory device 3 for use by the computing device 4.

[0123] Similarly, the computing device 4 can also share the CXL memory device 4 or the CXL memory device 5 connected thereto for use by the computing device 1. For example, taking the computing device 4 sharing the CXL memory device 4 connected thereto for use by the computing device 1 as an example, the computing device 1 can write data into the CXL memory device 3 and notify the computing device 4, and then the computing device 4 can read the data in the CXL memory device 3 and write the data into the CXL memory device 4. Alternatively, the computing device 4 can read data in the CXL memory device 4 and write the data into the CXL memory device 3 for use by the computing device 1.

[0124] In this way, by ensuring that any two computing devices are connected with a CXL memory device, a basis is laid for subsequent access to the memory space of the CXL memory device connected to other computing devices, and thus through network communication between the computing devices, the effect of accessing the memory space of the CXL memory device connected to other computing devices can be achieved.

[0125] In the example shown in FIG. 4, taking the CXL memory device with two ports and the computing device with three ports as an example, any two computing devices are connected through at least one CXL memory device. Each CXL memory device is connected to two different computing devices, and each computing device is connected to three different CXL memory devices. In this way, a full interconnection network topology of CXL memory devices and computing devices can be formed, so that each computing device can access the memory space of any CXL memory device in the memory pool, and at most one computing device jump, for example, a computing device can access the memory space of the CXL memory device connected to other computing devices through network communication with other computing devices connected with a CXL memory device to itself, the time delay of memory access is low, thereby ensuring stable performance of the memory pool.

[0126] In some possible implementation manners, the computing system can further include a management device 403.

[0127] The management device 403 can be a server deployed separately from the plurality of computing devices 402, or can be any one (or any multiple) of the plurality of computing devices 402. It should be noted that the management device 403 is described by taking the server deployed separately from the plurality of computing devices 402 as an example in FIG. 4.

[0128] For example, FIG. 7 is a schematic diagram of a hardware structure of a management device provided in an embodiment of the present application. Referring to FIG. 7, the management device 700 shown in FIG. 7 can include a processor 701, a memory 702, a communication interface 703, and a bus 704. The processor 701, the memory 702, and the communication interface 703 can be connected through the bus 704. Details of the processor 701, the memory 702, the communication interface 703, and the bus 704 can refer to the descriptions of the processor 601, the memory 602, the communication interface 603, and the bus 605 in FIG. 6, and will not be repeated here. It should be noted that the structure shown in FIG. 7 does not limit the management device 700, and the management device 700 can include more or fewer components than those shown in FIG. 7, or combine some components, or arrange different components.

[0129] In some possible implementation manners, the management device 403 runs an FM process for managing memory resources provided by each CXL memory device in the memory pool 401, and accordingly, the management device 403 is configured to perform memory management, such as memory allocation, on the plurality of CXL memory devices.

[0130] In some possible implementation manners, the management device 403 can maintain information about memory resources of the plurality of CXL memory devices, such as information about memory types, memory sizes, or memory addresses. In some other possible implementation manners, the management device 403 can also maintain connection relationships between the plurality of computing devices and the plurality of CXL memory devices. In some other possible implementation manners, the management device 403 can also maintain memory allocation of the plurality of CXL memory devices. For example, the management device 403 can use a table to maintain the information about memory resources of the plurality of CXL memory devices, the connection relationships between the plurality of computing devices and the plurality of CXL memory devices, and the memory allocation of the plurality of CXL memory devices.

[0131] In the embodiment of the present application, the management device 403 is configured to obtain a memory requirement of the first computing device or a memory requirement of the second computing device, and allocate memory resources in the plurality of CXL memory devices to the first computing device or the second computing device based on the memory requirement of the first computing device or the memory requirement of the second computing device.

[0132] FIG. 8 is a schematic diagram of a memory access method according to an embodiment of the present application. The scheme is described by taking the interaction between a first computing device and a first CXL memory device as an example, where the first computing device is a computing device connected to a CXL port of the first CXL memory device. Referring to FIG. 8, the memory access method can include the following steps:

[0133] S801. The first computing device sends a memory access request to the first CXL memory device in response to a communication request sent by a second computing device.

[0134] The second computing device is a computing device connected to the first CXL memory device through a second CXL memory device. The communication request is used to request access to the memory space of the first CXL memory device. The memory access request is used to request access to the memory space of the first CXL memory device.

[0135] In some possible implementation manners, the first computing device receives the communication request from the second computing device, and sends the memory access request to the first CXL memory device based on the communication request. In this implementation manner, the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed through network communication between the first computing device and the second computing device.

[0136] Specifically, the memory access request can be a data read request or a data write request. Accordingly, the first computing device sending the memory access request to the first CXL memory device in S801 described above can include the first computing device sending a data read request or a data write request to the first CXL memory device. The data read request is used to request performing a read operation on the memory space of the first CXL memory device. The data write request is used to request performing a write operation on the memory space of the first CXL memory device.

[0137] For example, taking the data read request as an example, the communication request can carry the storage location of the first data in the first CXL memory device. Accordingly, the process of triggering the first computing device to send the memory access request to the first CXL memory device can be that the first computing device generates the memory access request based on the storage location of the first data in the first CXL memory device, to request reading the first data from the first CXL memory device.

[0138] In the above example, through network communication between the first computing device and the second computing device, and carrying the storage location of the first data in the first CXL memory device in the communication request, the process of the second computing device performing a read operation on the first CXL memory device through the first computing device can be quickly and efficiently completed.

[0139] In some possible implementation, the communication request can carry a storage location of the second data in the second CXL memory device. Accordingly, triggering the first computing device to send a memory access request to the first CXL memory device includes: the first computing device reading the second data from the second CXL memory device based on the storage location of the second data in the second CXL memory device, and generating the memory access request based on the read second data to request writing the second data in the first CXL memory device.

[0140] In the above example, through the network communication between the first computing device and the second computing device, and carrying the storage location of the second data in the second CXL memory device in the communication request, the process of the second computing device performing the write operation in the first CXL memory device through the first computing device can be quickly and efficiently completed. Moreover, through the second CXL memory device commonly connected between the first computing device and the second computing device to perform the data transmission, the data transmission based on the shared memory is realized, which can effectively reduce the latency of the memory access. In addition, by carrying the storage location of the second data in the second CXL memory device in the communication request instead of the storage data itself, the data size of the communication request can be greatly reduced, so that the communication request can be quickly sent to the first computing device, effectively reducing the data write delay and improving the data write efficiency.

[0141] S802, the first CXL memory device receives the memory access request sent by the first computing device.

[0142] S803, the first CXL memory device performs the memory access operation indicated by the memory access request based on the memory access request.

[0143] In some possible implementation, the memory access operation can be a read operation or a write operation based on the memory access request being a data read request or a data write request.

[0144] In some possible implementation, in the case that the memory access request indicates the read operation, the first CXL memory device performs the read operation to read the first data and returns the read first data to the first computing device. For example, the first CXL memory device can obtain the storage location of the first data in the first CXL memory device carried by the memory access request, and perform the read operation to read the first data based on the storage location of the first data in the first CXL memory device.

[0145] For example, after obtaining the read first data, the first computing device can write the read first data into the second CXL memory device for the second computing device to read. In this way, by writing the read first data into the second CXL memory device, the second CXL memory device can subsequently read the first data by accessing the second CXL memory device.

[0146] Further, in some possible implementation, after the first computing device writes the read first data to the second CXL memory device, the first computing device can further return a successful write notification to the second computing device to inform the second computing device that the first data has been successfully written in the second CXL memory device.

[0147] In some possible implementation, in case that the memory access request indicates a write operation, the first CXL memory device performs the write operation to write the second data. For example, the first CXL memory device can obtain the second data carried by the memory access request and write the second data to the first CXL memory device.

[0148] Further, in some possible implementation, after the second data is written to the first CXL memory device, the first CXL memory device can further return a successful write notification to the first computing device to inform the first computing device that the second data has been written in the first CXL memory device. In turn, after receiving the successful write notification, the first computing device can further return the successful write notification to the second computing device to inform the second computing device that the second data has been successfully written in the first CXL memory device.

[0149] In this way, the memory access scheme based on the read operation or the write operation is provided, so that the computing device can implement the read operation or the write operation based on the CXL memory device by accessing the memory space of the CXL memory device in the memory pool.

[0150] The technical scheme provided by the embodiments of the present application is that a plurality of computing devices and a plurality of CXL memory devices are connected through CXL cables, wherein each computing device is connected to a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected thereto through the CXL cable. And each CXL memory device is connected to a plurality of different computing devices, wherein any two computing devices are connected to a CXL memory device, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected thereto through the CXL cable, but also access the CXL memory device connected to other computing devices through other computing devices connected to the CXL memory device, thereby realizing memory sharing among a plurality of computing devices in the memory pool. Through network communication between the first computing device and the second computing device, the process that the second computing device accesses the first CXL memory device through the first computing device can be quickly and efficiently completed. In this way, the memory pool can be formed without relying on the CXL switch, the latency of memory access can be effectively reduced, the performance of the memory pool can be guaranteed, and the access performance of the computing device can be effectively guaranteed.

[0151] The above Figure 8 takes the computing device and the CXL memory device as an example to illustrate the process of memory access. The following takes the triggering of the memory allocation request of the second computing device as an example to illustrate the process of memory access in detail in combination with Figure 9. Figure 9 is a flowchart of a memory access method provided by an embodiment of the present application, taking the interaction process among the management device, the first computing device and the second computing device as an example, and the method comprises the following S901-S910:

[0152] S901, the second computing device sends a memory allocation request to the management device.

[0153] The memory allocation request is used to request the management device to allocate the memory resource in the memory pool for the second computing device. In some possible implementation ways, the memory allocation request can carry the memory requirement of the second computing device, such as the memory type, the memory size and the like.

[0154] S902, the management device receives the memory allocation request.

[0155] S903, the management device acquires the memory requirement of the second computing device in response to the memory allocation request of the second computing device.

[0156] In some possible implementation ways, the management device acquires the memory requirement of the second computing device from the memory allocation request in response to the memory allocation request of the second computing device.

[0157] S904, the management device judges whether the memory of the plurality of CXL memory devices connected by the second computing device satisfies the memory requirement of the second computing device. If the memory of the plurality of CXL memory devices connected by the second computing device satisfies the memory requirement of the second computing device, S905-S906 are executed. If the memory of the plurality of CXL memory devices connected by the second computing device does not satisfy the memory requirement of the second computing device, S907 is executed.

[0158] In some possible implementation ways, taking the memory type indicated by the memory requirement as the target type and the memory size as the target capacity as an example, the process of judging whether the memory of the plurality of CXL memory devices connected by the second computing device satisfies the memory requirement of the second computing device can be that the management device judges whether the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected by the second computing device is greater than or equal to the target capacity. In this way, a way of judging whether the memory requirement of the second computing device is satisfied based on the memory type and the memory size is provided. In this way, it can be ensured that the memory satisfying the memory requirement is allocated for the second computing device, thereby ensuring the accuracy of memory allocation.

[0159] If the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected by the second computing device is greater than or equal to the target capacity, it is determined that the memory of the plurality of CXL memory devices connected by the second computing device meets the memory requirement of the second computing device. If the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected by the second computing device is less than the target capacity, it is determined that the memory of the plurality of CXL memory devices connected by the second computing device does not meet the memory requirement of the second computing device.

[0160] The management device can maintain relevant information of the memory resources of the plurality of CXL memory devices, such as memory type, memory size, or memory address, etc. In some possible implementation manners, the management device can perform the process of determining whether the memory of the plurality of CXL memory devices connected by the second computing device meets the memory requirement of the second computing device in S904 according to the maintained relevant information of the memory resources of the plurality of CXL memory devices.

[0161] S905, the management device allocates a first memory matching the memory requirement for the second computing device from the plurality of CXL memory devices connected by the second computing device.

[0162] The matching of the memory requirement refers to the same memory type and the same memory size indicated by the memory requirement. The first memory can be the memory resource provided by one or more CXL memory devices in the plurality of CXL memory devices connected by the second computing device.

[0163] In some possible implementation manners, after the management device determines the first memory matching the memory requirement in the plurality of CXL memory devices, the management device can send the memory address of the first memory to the second computing device, so that the second computing device accesses the memory space of the first memory based on the memory address subsequently. The memory address can be an address segment of the memory.

[0164] S906, the second computing device accesses the memory space of the first memory through the CXL cable.

[0165] In some possible implementation manners, the process of the second computing device accessing the memory space of the first memory through the CXL cable in S906 can include the following steps one to three:

[0166] Step one, the second computing device sends a memory access request to the CXL memory device where the first memory is located.

[0167] The second computing device can send the memory access request to the CXL memory device where the first memory is located based on the memory address of the first memory.

[0168] Step two, the CXL memory device where the first memory is located receives the memory access request sent by the second computing device.

[0169] Step three, the CXL memory device where the first memory is located performs the memory access operation indicated by the memory access request based on the memory access request.

[0170] In some possible implementation manners, the CXL memory device where the first memory is located performs the memory access operation, such as a read operation or a write operation, of the second computing device in the memory space. For related content, refer to the content shown in S703 described above, which will not be described herein again.

[0171] The embodiments shown in S905 to S906 described above detail the case where the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device.

[0172] S907, the management device determines whether the memory of the plurality of CXL memory devices connected to the first computing device meets the memory requirement of the second computing device. If the memory of the plurality of CXL memory devices connected to the first computing device meets the memory requirement of the second computing device, S908 to S909 are performed. If the memory of the plurality of CXL memory devices connected to the first computing device does not meet the memory requirement of the second computing device, S910 is performed.

[0173] The first computing device can be any one of the plurality of computing devices except the second computing device.

[0174] S908, the management device allocates, for the second computing device, the second memory matching the memory requirement from the plurality of CXL memory devices connected to the first computing device.

[0175] The second memory can be the memory resource provided by one or more CXL memory devices of the plurality of CXL memory devices connected to the first computing device.

[0176] In some possible implementation manners, taking the memory of the first CXL memory device as an example, after the management device determines the memory of the first CXL memory device matching the memory requirement from the plurality of CXL memory devices, the management device can send the device information of the first computing device and the memory address of the first CXL memory device to the second computing device, so that the second computing device accesses the memory space of the first CXL memory device through the first computing device subsequently.

[0177] Thus, by sending the device information of the first computing device and the memory address of the first CXL memory device to the second computing device, the second computing device can subsequently implement network communication with the first computing device based on the device information of the first computing device and the memory address of the first CXL memory device, thereby ensuring smooth memory access.

[0178] S909, the second computing device accesses the memory space of the second memory through the first computing device.

[0179] In some possible implementation manners, taking the memory of the first CXL memory device as the second memory for example, the process that the second computing device accesses the memory space of the second memory through the first computing device in S909 can include the following steps one to four:

[0180] Step one, the second computing device sends a communication request to the first computing device based on the device information of the first computing device.

[0181] The communication request is used to request access to the memory space of the first CXL memory device. In some possible implementation manners, the communication request can carry the memory address of the second memory, such as the memory address of the first CXL memory device. Further, the communication request can also carry the type of the requested operation, such as information used to indicate a read operation or a write operation.

[0182] Step two, the first computing device receives the communication request from the second computing device, and sends a memory access request to the first CXL memory device based on the communication request.

[0183] The first computing device can send the memory access request to the first CXL memory device based on the memory address of the first CXL memory device and the type of the requested operation carried in the communication request. The memory access request can carry the memory address of the first CXL memory device and the type of the requested operation.

[0184] Step three, the first CXL memory device receives the memory access request sent by the first computing device.

[0185] Step four, the first CXL memory device performs the memory access operation indicated by the memory access request based on the memory access request.

[0186] In some possible implementation manners, the first CXL memory device performs a read operation or a write operation in the memory space. For related content, refer to the content shown in S803, which will not be described herein again.

[0187] The embodiments shown in S907 to S909 above have been described in detail for the case that the memory of the plurality of CXL memory devices connected by the second computing device does not meet the memory requirement of the second computing device.

[0188] S910, the management device returns a memory application failure to the second computing device.

[0189] In the above embodiment, the management device preferentially allocates the memory of one or more CXL memory devices directly connected to the second computing device, and secondarily allocates the memory of the CXL memory device connected to the first computing device.

[0190] In addition, in other embodiments, if the memory of the plurality of CXL memory devices connected to the second computing device can meet the memory demand of the second computing device, but part of the memory is occupied by other computing devices, the management device can coordinate interrupting the other computing devices, and control a third computing device occupying the memory to release the memory, so as to ensure that the memory is preferentially supplied to the current computing device.

[0191] The technical scheme provided by the embodiments of the present application is that a plurality of computing devices and a plurality of CXL memory devices are connected through CXL cables, wherein each computing device is connected to a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected thereto through the CXL cables. Each CXL memory device is connected to a plurality of different computing devices, wherein any two computing devices are connected to a CXL memory device, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected thereto through the CXL cable, but also access the CXL memory device connected to other computing devices through other computing devices connected to the same CXL memory device, thereby realizing memory sharing between a plurality of computing devices in the memory pool. By deploying a management device, the management device is used to manage the memory of the plurality of CXL memory devices in the memory pool. In the case that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory demand of the second computing device, but the memory of the plurality of CXL memory devices connected to the first computing device meets the memory demand of the second computing device, the memory of the first CXL memory device in the plurality of CXL memory devices connected to the first computing device that meets the memory demand of the second computing device can be allocated to the second computing device, and then the process of the second computing device accessing the first CXL memory device through the first computing device is quickly and efficiently completed through network communication between the first computing device and the second computing device. In this way, the memory pool does not need to rely on the CXL switch, which can effectively reduce the latency of memory access, not only guarantee the performance of the memory pool, but also effectively guarantee the access performance of the computing device.

[0192] It should be noted that by applying the memory pool provided in the embodiments of the present application, each computing device can access the memory space of any CXL memory device in the memory pool, such as by accessing the memory space of the CXL memory device directly connected thereto, the required consumed latency is within 200ns, even if through a computing device jump, at most one computing device jump, the latency can be stabilized within 400ns, so that the memory access latency is low, thereby ensuring the stable performance of the memory pool. Compared with the related art, the latency required for accessing the memory space based on the CXL switch is larger, especially when facing multiple levels of CXL switches, which will bring greater latency, seriously affecting the performance of the memory pool.

[0193] The above mainly introduces the scheme of the embodiments of the present application from the perspective of the method. It can be understood that the computing device (such as a server) in the embodiments of the present application includes the corresponding hardware structure and / or software module for executing each function in order to implement the above functions. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the examples described in the embodiments disclosed herein, the embodiments of the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in hardware or computer software driven hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0194] FIG. 10 is a structural schematic diagram of a memory access apparatus provided by an embodiment of the present application, which is applied to a first computing device in a computing system, the computing system including a memory pool and a plurality of computing devices, the memory pool including a plurality of computing interconnection protocol (CXL) memory devices, each CXL memory device including a plurality of CXL ports, and each computing device including a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device. Referring to FIG. 10, the memory access apparatus includes a sending module 1001. Wherein,

[0195] The sending module 1001 is configured to, in response to a communication request sent by a second computing device, send a memory access request to a first CXL memory device, the communication request being used to request to access the memory space of the first CXL memory device, and the memory access request being used to request to access the memory space of the first CXL memory device.

[0196] The first computing device is a computing device connected with a CXL port of the first CXL memory device, and the second computing device is a computing device connected with the first computing device through the second CXL memory device.

[0197] The technical scheme provided by the embodiment of the application is that a plurality of computing devices are connected with a plurality of CXL memory devices through CXL cables, each computing device is connected with a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected therewith through the CXL cables. Each CXL memory device is connected with a plurality of different computing devices, and any two computing devices are connected with one CXL memory device, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected therewith through the CXL cable, but also access the CXL memory device connected with other computing devices through the other computing devices connected with one CXL memory device, so as to realize the memory sharing between the plurality of computing devices in the memory pool. Through the network communication between the first computing device and the second computing device, the process that the second computing device accesses the first CXL memory device through the first computing device can be quickly and efficiently completed. In this way, the CXL switch is not needed to form the memory pool, the time delay of memory access can be effectively reduced, the performance of the memory pool can be guaranteed, and the access performance of the computing device can be effectively guaranteed.

[0198] In some possible implementation manners, the memory access request is a data read request, and the data read request is used to request to perform a read operation on the memory space of the first CXL memory device.

[0199] The apparatus further includes a writing module configured to:

[0200] write the read first data into the second CXL memory device.

[0201] In some possible implementation manners, the memory access request is a data write request, and the data write request is used to request to perform a write operation on the memory space of the first CXL memory device.

[0202] The apparatus further includes:

[0203] a reading module configured to read second data from the second CXL memory device;

[0204] a generating module configured to generate the memory access request based on the read second data.

[0205] Figure 11 is a structural schematic diagram of a memory access device provided by an embodiment of the present application, the memory access device being applied to a management device, the management device being used for memory management on a memory pool in a computing system; the computing system comprising the memory pool and a plurality of computing devices, the memory pool comprising a plurality of CXL memory devices, each CXL memory device comprising a plurality of CXL ports, each computing device comprising a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device. Referring to Figure 11, the memory access device comprises an obtaining module 1101 and an allocating module 1102. Wherein,

[0206] The obtaining module 1101 is configured to obtain the memory requirement of the second computing device in response to a memory allocation request of the second computing device.

[0207] The allocating module 1102 is configured to, if the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the plurality of CXL memory devices connected to the first computing device meets the memory requirement of the second computing device, allocate the memory of the first CXL memory device meeting the memory requirement from the plurality of CXL memory devices connected to the first computing device to the second computing device.

[0208] Wherein, the first computing device is a computing device connected to one CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device through a second CXL memory device.

[0209] The technical scheme provided by the embodiments of the present application is that a plurality of computing devices and a plurality of CXL memory devices are connected through CXL cables, wherein each computing device is connected to a plurality of different CXL memory devices, so that each computing device can access one or more CXL memory devices connected thereto through the CXL cables. And each CXL memory device is connected to a plurality of different computing devices, wherein any two computing devices are connected to one CXL memory device, so that each computing device and other computing devices have at least one memory space that can share data. On this basis, each computing device can not only access the CXL memory device connected thereto through the CXL cable, but also access the CXL memory device connected to other computing devices through other computing devices connected to one CXL memory device, thereby realizing memory sharing between a plurality of computing devices in a memory pool. Wherein, by deploying a management device, the management device is used to manage the memory of a plurality of CXL memory devices in the memory pool. In the case that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the plurality of CXL memory devices connected to the first computing device meets the memory requirement of the second computing device, the memory of the first CXL memory device in the plurality of CXL memory devices connected to the first computing device that meets the memory requirement of the second computing device can be allocated to the second computing device, so that the process of the second computing device accessing the first CXL memory device through the first computing device can be quickly and efficiently completed through subsequent network communication between the first computing device and the second computing device. In this way, the memory pool does not need to rely on a CXL switch, the time delay of memory access can be effectively reduced, the performance of the memory pool can be guaranteed, and the access performance of the computing device can be effectively guaranteed.

[0210] In some possible implementation manners, the memory requirement indicates that the memory type is a target type and the memory size is a target capacity.

[0211] The apparatus further includes a determination module configured to:

[0212] If the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected to the second computing device is greater than or equal to the target capacity, it is determined that the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device.

[0213] If the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected to the second computing device is less than the target capacity, it is determined that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

[0214] In some possible implementation manners, the allocation module 1102 is specifically configured to:

[0215] The device information of the first computing device and the memory address of the first CXL memory device are sent to a second computing device, for the second computing device to send a communication request to the first computing device, the communication request being used to request access to the memory space of the first CXL memory device.

[0216] The embodiment of the present application also provides a CXL memory device, which comprises a CXL controller and a memory medium; the CXL controller and the memory medium are coupled. The memory medium is used to store computer program instructions, and the CXL controller is used to invoke the computer program instructions in the memory medium to execute the content performed by the CXL memory device in the memory access method shown in the above embodiment.

[0217] The embodiment of the present application also provides an electronic device, which comprises a processor and a memory; the processor and the memory are coupled. The memory is used to store computer program instructions, and the processor is used to invoke the computer program instructions in the memory to execute the content performed by the computing device or the management device in the memory access method shown in the above embodiment. In the embodiment of the present application, the computing device or the management device can be the electronic device.

[0218] The embodiment of the present application also provides a computer readable storage medium, which stores computer program instructions, and the computer program instructions are used to make the CXL memory device or the electronic device execute the memory access method shown in the above embodiment.

[0219] The embodiment of the present application also provides a computer program product, which comprises computer program instructions, and when the computer program instructions run on the CXL memory device or the computing device, the CXL memory device or the electronic device executes the memory access method shown in the above embodiment.

[0220] The CXL memory device, the electronic device (such as the computing device or the management device), the computer readable storage medium or the computer program product provided by the embodiment of the present application are used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be described here.

[0221] Through the description of the above embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device (such as the computing device) is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, the device (such as the computing device) and the unit described above can refer to the corresponding process in the foregoing method embodiments, and will not be described here.

[0222] In several embodiments provided in the present application, it should be understood that the disclosed system, apparatus (such as a computing device) and method can be implemented in other manners. For example, the apparatus (such as a computing device) embodiments described above are merely illustrative. For example, the division of the modules or units can be different, and each can contain a plurality of sub-units. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0223] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0224] In addition, each functional unit in the various embodiments of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0225] The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods in the various embodiments of the present application. The foregoing storage medium includes: a flash memory, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0226] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory access method, characterized by, A first computing device applied to a computing system, the computing system comprising a memory pool and a plurality of computing devices, the memory pool comprising a plurality of computing interconnect protocol (CXL) memory devices, each CXL memory device comprising a plurality of CXL ports, each computing device comprising a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device; The method comprises: in response to a communication request sent by a second computing device, sending a memory access request to a first CXL memory device, the communication request being used to request access to a memory space of the first CXL memory device, and the memory access request being used to request access to the memory space of the first CXL memory device; wherein the first computing device is a computing device connected to a CXL port of the first CXL memory device; and the second computing device is a computing device connected to the first computing device through a second CXL memory device.

2. The method of claim 1, wherein, The memory access request is a data read request, and the data read request is used to request to perform a read operation on the memory space of the first CXL memory device. After sending the memory access request to the first CXL memory device, the method further comprises: writing the read first data to the second CXL memory device.

3. The method of claim 1, wherein, The memory access request is a data write request, and the data write request is used to request to perform a write operation on the memory space of the first CXL memory device. Before sending the memory access request to the first CXL memory device, the method further comprises: reading second data from the second CXL memory device; generating the memory access request based on the read second data.

4. A memory access method, characterized by, A management device applied to manage a memory pool in a computing system, the computing system comprising the memory pool and a plurality of computing devices, the memory pool comprising a plurality of computing interconnect protocol (CXL) memory devices, each CXL memory device comprising a plurality of CXL ports, and each computing device comprising a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device; The method comprises: in response to a memory allocation request of a second computing device, obtaining a memory requirement of the second computing device; if the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device, but the memory of the plurality of CXL memory devices connected to the first computing device meets the memory requirement of the second computing device, allocating the memory of the first CXL memory device that meets the memory requirement from the plurality of CXL memory devices connected to the first computing device to the second computing device; The first computing device is a computing device connected to one CXL port of the first CXL memory device, and the second computing device is a computing device connected to the first computing device through a second CXL memory device.

5. The method of claim 4, wherein, The memory requirement indicates that the memory type is a target type and the memory size is a target capacity. The method further includes: If the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected to the second computing device is greater than or equal to the target capacity, it is determined that the memory of the plurality of CXL memory devices connected to the second computing device meets the memory requirement of the second computing device. If the sum of the remaining available capacities of the memory of the target type in the plurality of CXL memory devices connected to the second computing device is less than the target capacity, it is determined that the memory of the plurality of CXL memory devices connected to the second computing device does not meet the memory requirement of the second computing device.

6. The method according to claim 4 or 5, characterized in that, The allocation of the memory of the first CXL memory device that meets the memory requirement of the second computing device from the plurality of CXL memory devices connected to the first computing device includes: sending device information of the first computing device and a memory address of the first CXL memory device to the second computing device, so that the second computing device sends a communication request to the first computing device, and the communication request is used to request access to a memory space of the first CXL memory device.

7. A computing system, comprising: The computing system includes a memory pool and a plurality of computing devices, the memory pool includes a plurality of computing interconnection protocol (CXL) memory devices, each CXL memory device includes a plurality of CXL ports, and each computing device includes a plurality of CXL ports; wherein the plurality of CXL ports on each CXL memory device are respectively connected to different computing devices, the plurality of CXL ports on each computing device are respectively connected to different CXL memory devices, and any two computing devices in the plurality of computing devices are connected through at least one CXL memory device; The first computing device is configured to send a memory access request to the first CXL memory device in response to a communication request sent by the second computing device, the communication request is used to request access to a memory space of the first CXL memory device, and the memory access request is used to request access to the memory space of the first CXL memory device; the first computing device is a computing device connected to one CXL port of the first CXL memory device, and the second computing device is a computing device connected to the first computing device through a second CXL memory device; The first CXL memory device is configured to receive the memory access request sent by the first computing device and perform a memory access operation indicated by the memory access request based on the memory access request.

8. The system of claim 7, wherein, The first number of CXL ports in each computing device is determined based on the number of the plurality of computing devices and the second number of CXL ports in each CXL memory device; wherein the first number is positively correlated with the number of the plurality of computing devices and negatively correlated with the second number.

9. The system of claim 7 or 8, wherein, The number of the plurality of CXL memory devices is determined based on the number of the plurality of computing devices, a first number of CXL ports in each computing device, and a second number of CXL ports in each CXL memory device; wherein the number of the plurality of CXL memory devices is positively correlated with the number of the plurality of computing devices and the first number, and is negatively correlated with the second number.

10. An electronic device, comprising: The electronic device includes a processor and a memory; the processor and the memory are coupled; The memory is configured to store computer program instructions; The processor is configured to invoke the computer program instructions in the memory to execute the method in any one of claims 1-3 or 4-6.

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