Hybrid virtual memory system and method for range-based address translation in a hybrid virtual memory system

Abstract

Embodiments herein provide a method for range-based address translation of a virtual memory in a hybrid virtual memory system (400) from a source address space (605S, 615S, 625S, 635S) to a target address space (520, 615T). The hybrid virtual memory system (400) comprises at least one page table (421) configured by rules of page-based address translation. The method includes allocating a memory block within the virtual memory as a virtual segment (530S, 531S) in the source address space and the target address space. The memory block consists of a plurality of contiguous memory addresses (530, 531). The virtual segment consists of at least one page, each page is associated with a page table entry, PTE (530P, 531P). The method includes creating virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 643, 644, 656, 657, 702, 703, 704, 840) for the virtual segment.

Description

[0001] HYBRID VIRTUAL MEMORY SYSTEM AND METHOD FOR RANGE-BASED ADDRESS TRANSLATION IN A

[0002] HYBRID VIRTUAL MEMORY SYSTEM

[0003] TECHNICAL FIELD

[0004] The disclosure relates to virtual memory management on computers and other electronic devices and more particularly, the disclosure relates to a method for range-based address translation of a virtual memory in a hybrid virtual memory system from a source address space to a target address space. The disclosure relates to a hybrid virtual memory system configured to perform the range-based address translation of the virtual memory from the source address space to the target address space.

[0005] BACKGROUND

[0006] Virtual memory systems are commonly seen in modem computer systems and electronic devices. Virtual memory is a vital component of general-purpose computing that introduces an additional layer in memory access, enhancing programming ease and portability while ensuring data protection. With the virtual memory, a program accesses its data and instructions by virtual addresses, which are then translated into physical addresses on demand by the hardware. The address translation is a key process in the virtual memory and is performed during a process of address mapping of a virtual address space to a physical memory in a physical address space.

[0007] FIG. 1 illustrates a block diagram of a generic virtual memory system. The virtual memory system 100 includes a processor 110 and a physical memory 120 including unallocated memory 124 and other metadata 122. Inside the processor 110 (which can be a central processing unit, CPU, graphics processing unit, GPU, or neural processing unit, NPU), a memory management unit, MMU, 111 an address is translated from one address space to another address space. Without losing generality, the first address space is referred as the source address space and the second address space is referred as the target address space. Commonly, an address in the source address space is a virtual address, whereas an address in the target address space is a physical address. In other cases, either the source address space or the target address space may be a form of intermediate address space, such as guest physical address, GPA, or intermediate physical address, IPA.

[0008] The MMU 111 implements a look-up mechanism to perform the address translation, which is ultimately provided as mappings, by in-memory data structures commonly known as page tables 121. When requested by software, memory is allocated and organized as data pages 123. The MMU 111 maintains an internal cache for frequently used memory mappings to accelerate address translation. Most often, this cache in the MMU 111 is a Translation Look-aside Buffer, TLB 112. If the TLB does not contain a mapping for the requested translation, the MMU 111 employs a procedure known as the page table walk to retrieve one from the page tables. A hardware module that performs the page table walk, is known as the page table walker, PTW, 113. If the translation still cannot be found, an exception may be raised for privileged software to intervene, often resulting in a page being installed at the requested address, i.e. backing the address with physical memory location(s).

[0009] In the wider system, peripherals such as an input / output (I / O) device, an accelerator or a DMA engine 140 may also use a virtual address and thus need address translation as well. This functionality is usually fulfilled by a System MMU 130.

[0010] FIG. 2 illustrates an exemplary generalized view of address translation. As an example, a process 210 runs in its own address space, where all memory references are given as virtual addresses 211A. Because system resources 220, such as physical memory and memory-mapped input / output, are accessible in physical addresses 221A only, a mapping mechanism 200 is needed to provide the address translation. Page-based address translation regimes, either with radix-tree page tables or hashed page tables, are the most common mapping mechanism. A page is a power-of-2 sized and naturally-aligned block of memory, all addresses of which are translated using the same mapping information. Likewise, a range-based address translation also uses a block of memory for addresses to be mapped together, but without the size and alignment restrictions.

[0011] FIG. 3 illustrates the most common method for page-based address translation that is performed by traversing radix-tree of page tables (also commonly referred to as traversing radix page tables). As described on FIG. 1, the physical memory is organized into naturally aligned power-of-2 size pages. Physical pages are also referred to as a physical frame, and their counterpart in the virtual address space is called virtual pages. Each page is assigned with an identifier, known respectively as a physical frame number, PFN, 371 for a physical page, and as a virtual page number, VPN, 361, 362, 363 for a virtual page. The physical frame number is calculated by truncating the frame’s bottom address bits, the number of which equals to the binary logarithm of the base page size in the virtual memory system. The space for these truncated bits is reserved for page offset 364, which is concatenated to the physical frame number as the traversal concludes. The virtual page number is a slice of the virtual address for memory access 360.

[0012] The radix-tree lives in the physical address space and contains many physical pages as page tables. In each radix-tree page table, multiple page table entries, PTE, 370, 301, 302 311, 312, 331 may exist, each pointing to a physical page by its physical frame number 371. Each page optionally includes attributes 372.

[0013] The traversal starts with a root pointer 350, which points to a root page table 300 at level 0. The page table’s base address is its physical frame number with a page offset of 0 concatenated on the right. Using a virtual page number, denoted as VPN[0] 361, as the entry index into the page table, the relevant page table entry (e.g. 302) is retrieved. VPN[0] is sliced off the most significant portion of the virtual address. Then, the physical frame number of the relevant page table entry 302 is used to find the page table at level 1, and another slice is taken off from the virtual address to form VPN[1], These virtual address slices are denoted as VPN[z], for use with the zth level of page table.

[0014] As these steps are repeated at each level, all virtual address bits except the page offset have been sliced off for indices, and the traversal finally reaches the last level of the radix-tree page table. At the last level 320, 330 of the radix-tree page table, the page table entry 331 no longer points to another page table but to a data page 340. This time, the page offset 364 is used as an index inside the data page to locate the requested piece of data to access. The process of address translation also concludes with the concatenation of this last physical frame number and the page offset as the returned physical address.

[0015] SUMMARY

[0016] It is an object of the disclosure to provide a method for range-based address translation of a virtual memory in a hybrid virtual memory system from a source address space to a target address space, and a hybrid virtual memory system configured to perform range-based address translation of the virtual memory in the hybrid virtual memory system from the source address space to the target address space.

[0017] This object is achieved by the features of the independent claims. Further, implementation forms are apparent from the dependent claims, the description, and the figures.

[0018] According to a first aspect, there is a method for range-based address translation of a virtual memory in a hybrid virtual memory system from a source address space to a target address space. The hybrid virtual memory system comprises at least one page table configured by rules of page-based address translation. The method includes allocating a memory block within the virtual memory as a virtual segment in the source address space and the target address space. The memory block consists of a plurality of contiguous memory addresses. The virtual segment consists of at least one page, and each page is associated with a page table entry, PTE. The method includes creating virtual segment metadata for the virtual segment. The virtual segment metadata comprises at least three elements. The first element indicates an address range of the virtual segment in the source address space, the second element indicates an address range of the virtual segment in the target address space and the third element indicates a length of the virtual segment. The method includes configuring each page table entry associated with each page of the virtual segment by embedding an indicator. The indicator indicates the location of virtual segment metadata in the target address space. The method includes mapping a source address of the virtual segment into an address of the target address space according to the virtual segment metadata. The virtual segment metadata is retrieved according to the indicator embedded in a page table entry associated with one of the pages in the virtual segment. The indicator is identified by page table walk through the at least one page table.

[0019] The method enhances the efficiency of address translation within the hybrid virtual memory system by streamlining the translation process for virtual segments. The primary advantage of the virtual segment lies in the metadata's capability to cover multiple pages. Consequently, when cached in the Range Translation Look-aside Buffer, R-TLB, the Virtual Segment (VS) mapping expedites address translations across all its ranges without having to cache the page’s mapping in the Translation Look-aside Buffer, TLB. Due to its limited capacity, the page mappings are swapped in and out of the TLB, thereby incurring significant delays. These delays typically arise from extra page table walks, which the virtual segment’s mapping effectively eliminates. The virtual segment adopted range-based address translation provides the best solution to the TLB reach problem, significantly enhancing TLB performance while reducing power consumption. This range-based address translation partially eliminates software overheads, such as page faults and scans. Moreover, the adoption of range-based address translation reduces area overhead as a smaller and more efficient R-TLB replaces conventional TLBs for equivalent coverage.

[0020] As the memory references for the page table walk are shared between the page and the range mapping lookups, the method ensures that no step of the page table walk is wasted. Further, the method minimizes intrusion into the Instruction Set Architecture, ISA, because supporting the virtual segment metadata only requires an extra hop on top of the existing page table walk. In contrast existing techniques, such as the Redundant Memory Mappings, RMM, requires traversal of the B-tree range table into the ISA.

[0021] The separation of pointers and mapping information allows for ample space for mapping, and hence more data can be represented without the resorting to contrived encoding schemes.

[0022] If fetching the virtual segment metadata into the R-TLB is performed by the software through page faulting on the indicator, then no substantial change to the ISA is required. Additionally, the method ensures low hardware complexity due to the efficient extended page table walk.

[0023] As an overall effect, the method reduces Memory Management Unit, MMU, latency due to the low hardware complexity and the decrease in the lookup depth.

[0024] Further, under the virtual segment, both the page-based and the range-based address translation regimes coexist. This ensures downward compatibility with legacy software that assumes page-based translation, protecting existing business investments and past investments. Moreover, the virtual segment as an opt-in feature provides a painless migration path. Furthermore, the flexibility provided by minimal specification on the organization of virtual segment metadata enables software to choose the best data structure and evolve with time. With a one-hop indirection mechanism, the method ensures lower latency and simpler hardware. Additionally, the method provides the widest range and finest resolution in Unit for Address Translation, UAT, sizes, which is unmatched by any page-based translation regime. The method effectively reduces memory bloat and memory usage, thereby decreasing DRAM costs. For instance, the virtual segment may match 4KB pages in reducing internal fragmentation. Total memory usage may become even smaller if folding of page tables is performed, with fewer page tables and a shallower radix tree. Furthermore, as the size and alignment constraints of the virtual segment are relaxed, it can be easily fit to available memory space, therefore less wastage by external fragmentation. Further, the method aids in reducing latency spikes as software performs partial work on smaller virtual segments before joining them. The complexity overhead of such operations is reduced because the virtual segement imposes the least constraints on the software, unlike hugepages or NAPOT (Naturally - Aligned-Power-Of-Two) pages.

[0025] Optionally, the first element of the virtual segment metadata comprises a bottom address for the virtual segment in the source address space and the second element of the virtual segment metadata comprises a bottom address for the virtual segment in the target address space.

[0026] Optionally, the first element of the virtual segment metadata comprises a bottom address of the virtual segment in the source address space and the second element of the virtual segment metadata comprises a numerical difference of the two respective bottom addresses of the virtual segment in the source and target address spaces.

[0027] Optionally, the first element of the virtual segment metadata comprises a top address of the virtual segment in the source address space and the second element of the virtual segment metadata comprises a top address of the virtual segment in the target address space.

[0028] Optionally, the first element of the virtual segment metadata comprises a top address of the virtual segment in the source address space and the second element of the virtual segment metadata comprises a numerical difference of the two respective top addresses for the virtual segment in the source and target address spaces.

[0029] Optionally, each indicator embedded in each page table entry associated with each page of the virtual segment is identical and indicates the same virtual segment metadata via absolute addressing.

[0030] Furthermore, the flexibility provided by minimal specification on the organization of virtual segment metadata enables software to choose the best data structure and evolve with time.

[0031] Optionally, the hybrid virtual memory system comprises a plurality of virtual segments and an array of virtual segment metadata associated with the plurality of virtual segments, and wherein the indicator comprises an index element and an offset element, wherein the index element contains an index value indicating the virtual segment metadata of the corresponding virtual segment from the array of virtual segment metadata, and wherein the offset element contains an address offset value of the corresponding page relative to a bottom page of the corresponding virtual segment, wherein the bottom of the corresponding virtual segment is located via indirect addressing.

[0032] Optionally, the indicator further comprises a subset of elements, wherein the subset of elements is used for indicating attributes of the page table entry. This means that some common status and attributes are supported at the page level / granularity, providing software convenience and ensuring backward compatibility with page-based address translation.

[0033] Optionally, the at least one page table comprises at least one radix-tree page table and / or at least one hashed page table. Optionally, the hybrid virtual memory system comprises a plurality of virtual segments being associated with a plurality of virtual segment metadata, and wherein each virtual segment comprises a plurality of pages being allocated in a plurality of page tables, wherein the plurality of page tables is arranged in a radix-tree comprising a plurality of tree-levels, and wherein each page contains a plurality of page table entries having indicators indicating to the plurality of virtual segment metadata, and wherein if all indicators contained in a page table in a lower tree-level of the radix-tree indicate to a same virtual segment metadata, creating a sum-indicator in a page table in a higher tree-level of the radix-tree and folding or collapsing or deleting the page table in the lower tree-level of the radix-tree, wherein the sum-indicator indicates to the same virtual segment metadata as a replacement of all indicators contained in the page table. This method minimizes the number of indicators required in large virtual segments and effectively reduces the depth of average EPTW, thereby improving table walk latency.

[0034] Further, by consolidating Page Table Entries, PTEs, into a single upper-level entry, the method reduces the average depth of the extended page table walk, EPTW, and simplifies the address translation process, thereby reducing complexity and overhead

[0035] According to a second aspect, there is provided a hybrid virtual memory system comprising a memory, a processor, a memory management unit, MMU, and a storage medium for storing instructions. The hybrid virtual memory system is configured to allocate a memory block within the virtual memory as a virtual segment in a source address space and a target address space. The memory block consists of a plurality of contiguous memory addresses. The virtual segment consists of at least one page, and each page is associated with a page table entry, PTE. The hybrid virtual memory system is configured to create virtual segment metadata for the virtual segment. The virtual segment metadata comprises at least three elements. The first element indicates an address range of the virtual segment in the source address space, the second element indicates an address range of the virtual segment in the target address space and the third element indicates a length of the virtual segment. The hybrid virtual memory system configures each page table entry associated with each page of the virtual segment by embedding an indicator. The indicator indicates the location of virtual segment metadata in the target address space. The hybrid virtual memory system maps a source address of the virtual segment into an address of the target address space according to the virtual segment metadata. The virtual segment metadata is retrieved according to the indicator embedded in a page table entry associated with one of the pages in the virtual segment. The indicator is identified by page table walk through the at least one page table.

[0036] The hybrid virtual memory system enhances the efficiency of address translation within the hybrid virtual memory system by streamlining the translation process for virtual segments. The primary advantage of the virtual segment lies in the metadata's capability to cover multiple pages. Consequently, when cached in the Range Translation Look-aside Buffer, R-TLB, the Virtual Segment (VS) mapping expedites address translations across all its ranges without having to cache the page’s mapping in the Translation Look-aside Buffer, TLB. Due to its limited capacity, the page mappings are swapped in and out of the TLB, thereby incurring significant delays. These delays typically arise from extra page table walks, which the virtual segment’s mapping effectively eliminates. The virtual segment adopted range-based address translation provides the best solution to the TLB reach problem, significantly enhancing TLB performance while reducing power consumption. This range-based address translation eliminates software overheads, such as page faults and scans. Moreover, the adoption of range-based address translation reduces area overhead as a smaller and more efficient R-TLB replaces conventional TLBs for equivalent coverage.

[0037] Further, by consolidating Page Table Entries, PTEs, into a single upper-level entry, the hybrid virtual memory system reduces the average depth of the extended page table walk, EPTW, and simplifies the address translation process, thereby reducing complexity and overhead. As the memory references for the page table walk are shared between the page and the range mapping lookups, the method ensures that no step of the page table walk is wasted. Further, the hybrid virtual memory system minimizes intrusion into the Instruction Set Architecture, ISA, because supporting the virtual segment metadata only requires an extra hop on top of the existing page table walk. In contrast, the Range Mapping Mechanism, RMM, requires traversal of the B-tree range table into the ISA. If fetching the virtual segment metadata into the R-TLB is performed by the software through page faulting on the indicator, then no substantial change to the ISA is required. Additionally, the hybrid virtual memory system ensures low hardware complexity due to the efficient extended page table walk, focusing on hardware rather than the ISA. The method also reduces Memory Management Unit (MMU) latency due to the low hardware complexity and the decrease in the lookup depth.

[0038] Optionally, the virtual segment metadata is cached in a Translation Look-aside Buffer, TLB, in part or as a whole, or in a Range TLB according to a set of preselected conditions, wherein the set of preselected condition includes size of the virtual segment. The advantageous effect of this claim lies in implementation flexibility. The hardware may choose the best approach to implement this Instruction Set Architecture (ISA) feature under different sets of design constraints. For instance, in high-end processors, complex implementation is chosen to maximize performance gains, whereas, on low-end processors, simple hardware can be used to support this feature, perhaps not getting the best performance.

[0039] Optionally, the first element of the virtual segment metadata comprises a bottom address for the virtual segment in the source address space and the second element of the virtual segment metadata comprises a bottom address for the virtual segment in the target address space. Optionally, the first element of the virtual segment metadata comprises a bottom address of the virtual segment in the source address space and the second element of the virtual segment metadata comprises a numerical difference of the two respective bottom addresses of the virtual segment in the source and target address spaces. Optionally, the first element of the virtual segment metadata comprises a top address of the virtual segment in the source address space and the second element of the virtual segment metadata comprises a top address of the virtual segment in the target address space. Optionally, the first element of the virtual segment metadata comprises a top address of the virtual segment in the source address space and the second element of the virtual segment metadata comprises a numerical difference of the two respective top addresses for the virtual segment in the source and target address spaces.

[0040] According to a third aspect, there is provided a computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the above method.

[0041] According to a fourth aspect, there is provided a computer-readable medium comprising instructions which, when executed by a computer, cause the computer to carry out the above method.

[0042] Therefore, in contradistinction to the existing solutions, the hybrid virtual memory system is configured to perform the address translation of a virtual segment as described above.

[0043] These and other aspects of the disclosure will be apparent from the implementation s) described below.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] Implementations of the disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0046] FIG. 1 illustrates a block diagram of a generic virtual memory system;

[0047] FIG. 2 illustrates an exemplary generalized view of address translation;

[0048] FIG. 3 illustrates the most common method for page-based address translation that is performed by traversing radix-tree page tables; FIG. 4 illustrates a block diagram of a hybrid virtual memory system with virtual segments enabled in accordance with an implementation of the disclosure;

[0049] FIG. 5 is an exemplary diagram that illustrates mapping address translation with virtual segments in accordance with an implementation of the disclosure;

[0050] FIGS. 6A-6D are exemplary diagrams that illustrate virtual segment metadata in accordance with an implementation of the disclosure;

[0051] FIGS. 6E and 6F are exemplary diagrams that illustrate indicators and virtual segment metadata in accordance with an implementation of the disclosure;

[0052] FIG. 7 illustrates an exemplary representation of accelerating address translation with virtual segments in accordance with an implementation of the disclosure;

[0053] FIG. 8 illustrates an exemplary representation of a virtual segment that covers a contiguous set of pages in accordance with an implementation of the disclosure; and

[0054] FIGS. 9A and 9B are flow diagrams that illustrate a method for range-based address translation of a virtual memory in a hybrid virtual memory system from a source address space to a target address space in accordance with an implementation of the disclosure.

[0055] DETAILED DESCRIPTION OF THE DRAWINGS

[0056] Implementations of the disclosure provide a hybrid virtual memory system and a method for range-based address translation of a virtual memory in the hybrid virtual memory system from a source address space to a target address space. To make solutions of the disclosure more comprehensible for a person skilled in the art, the following implementations of the disclosure are described with reference to the accompanying drawings. Terms such as "a first", "a second", "a third", and "a fourth" (if any) in the summary, claims, and foregoing accompanying drawings of the disclosure are used to distinguish between similar objects and are not necessarily used to describe a specific sequence or order. It should be understood that the terms so used are interchangeable under appropriate circumstances, so that the implementations of the disclosure described herein are, for example, capable of being implemented in sequences other than the sequences illustrated or described herein. Furthermore, the terms "include" and "have" and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, a method, a system, a product, or a device that includes a series of steps or units, is not necessarily limited to expressly listed steps or units but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or device.

[0057] A virtual segment is defined herein as a collection of contiguous pages, mapping addresses as a whole. The virtual segment takes up an equal-sized address range in the source address space and in the target address space, but commonly with different start addresses. By definition, the virtual segments are multiple pages in size and are required to have page-alignment, which is not directly linked to the size of each virtual segment.

[0058] FIG. 4 illustrates a block diagram of a hybrid virtual memory system 400 with virtual segments enabled in accordance with an implementation of the disclosure. The hybrid virtual memory system 400 includes a processor 410, a physical memory 420, a system MMU 430, and peripherals 440. The processor 410 includes a Memory Management unit, MMU, 411 that includes a Translation Look-aside Buffer, TLB, 412C, a Range TLB, R-TLB, 412R, and an Extended Page Table Walker, EPTW, 413. The physical memory 420 includes page tables, PT, 421, Virtual segment metadata 425, other metadata 422, allocated data pages 423, and unallocated memory 424.

[0059] The page tables 421 (unlike the memory system of FIG. 1) have an in-memory companion, virtual segment metadata 425, to describe the range-based mappings, for each virtual segment. The MMU 411 also gains the Range TLB 412R for accelerating the address translation on the virtual segments. But note that not every virtual segment’s metadata has to be cached in the R- TLB. In some such embodiments, the hardware is allowed or enabled to to cache the translation mapping for part or the entire virtual segment in the TLB 412C. It is thus possible to have a virtual_segment-enabled system without a hardware Range TLB.

[0060] Optionally, the page table walker 413 is extended to support retrieval of the virtual segment metadata 425 on demand. In some embodiments, the software may be used to retrieve the virtual segment metadata 425 while managing the R-TLB 412R.

[0061] The functions of the hybrid virtual memory system 400 are described as follows. The hybrid virtual memory system 400 allocates a memory block within the virtual memory as a virtual segment in a source address space and a target address space. The memory block consists of one or more contiguous memory addresses and at least one page. Each page is associated with a page table entry, PTE. The hybrid virtual memory system 400 then creates the virtual segment metadata 425 for the virtual segment.

[0062] The hybrid virtual memory system 400 configures each page table entry associated with each page of the virtual segment by embedding an indicator. The indicator indicates the location of the virtual segment metadata 425 in the target address space. The hybrid virtual memory system 400 then maps a source address of the virtual segment into an address of the target address space according to the virtual segment metadata 425. The virtual segment metadata 425 is retrieved according to the indicator embedded in a page table entry associated with one of the pages in the virtual segment. The indicator is identified by page table walk through the at least one page table.

[0063] FIG. 5 is an exemplary diagram that illustrates mapping address translation with virtual segments in accordance with an implementation of the disclosure. In the exemplary diagram, two virtual segments 530S, 531S and two pages 532S, 533S are mapped from a source address space 510 to a target address space 520 respectively as physical memory chunks 530T, 531T, 532T, 533T

[0064] In the page cases, both mappings are directly done with a structure of radix-tree page tables 500. For example, a page table entry 532P carries the mapping information from 532S to 532T.

[0065] In either virtual segment’s case, the mapping is done via a piece of virtual segment metadata 530M, 531M in the memory . This piece of metadata needs at least 3 specific values to define the mapping and allow the MMU to quickly perform the address translation for a particular address lookup. For example, virtual segment 1 (e.g., 530S) has its bottom and top addresses given in the source address space, in order for the lookup process to work out if the queried address is a part of the virtual segment 1, hence the mapping is applicable. The virtual segment metadata 530M also contains a third value, which is the difference 530D between the source and target bottom addresses. The source address space of the lookup is referred as SA and its translation in the target address space 520 is referred as TA. When the SA is a part of the virtual segment 1, then TA can be computed simply by adding the difference 530D to the SA.

[0066] In order to locate the metadata of the virtual segment 1, a bunch of page table entries 530P are converted to indicators, each of which points to the location of the virtual segment metadata 530M. Each indicator corresponds to a page in the virtual segment. All pages of the virtual segment have their corresponding indicators, just as in page-based address translation, all pages have a valid page table entry corresponding to the page. As an ordinary page table walk ends with an indicator, the translation process continues by following the indicator to the virtual segment’s metadata 530M, 531M completing the translation as described above.

[0067] FIGS. 6A-6D are exemplary diagrams that illustrate virtual segment metadata 600, 610, 620, and 630 in accordance with an implementation of the disclosure. The virtual segment metadata includes at least three elements such as a first element, a second element, and a third element. The first element indicates an address range of the virtual segment in the source address space. In other words, the first element anchors the address range of the virtual segment to a place in the source address space. The second element indicates an address range of the virtual segment in the target address space. The third element indicates a length of the virtual segment.

[0068] In FIG. 6A, the first element of the virtual segment metadata 600 includes a source’s bottom address, SRCBOT, 603 of the virtual segment in the source address space 605S, and the second element of the virtual segment metadata 600 includes a numerical difference, DIFF, 602 of the two respective bottom addresses 603, 606 of the virtual segment in the source address space 605S and target address spaces 605T. In FIG. 6A, the virtual segment within the source address space 605S is specified with a pair of values, i.e. a bottom address 603 and a virtual segment length, SEGLEN, 601, and where its counterpart in the target address space 605T is additionally specified with the difference 602 between both bottom addresses 603, 606 of the virtual segment in the source and target address spaces 605S, 605T.

[0069] In FIG. 6B, the bottom address numerical difference is replaced with a target’s bottom address 612 in a target address space 615T. The rest is exactly the same as the previous embodiment. That is, the first element of the virtual segment metadata 610 includes a source’s bottom address, SRCBOT, 613 for a virtual segment in a source address space 615S and the second element of the virtual segment metadata 610 includes the target’s bottom address, TGTBOT, 612 for a virtual segment in the target address space 615T. The virtual segment metadata 610 includes a third element that indicates the length of the virtual segment, SEGLEN, 611.

[0070] In FIG. 6C, where a virtual segment in a source address space 625S is anchored by a source’s top address 623 and the length of the virtual segment, SEGLEN, 621, and where the target address space counterpart is further specified with the numerical difference, DIFF, 622 between the two top addresses 623, 626. That is, the first element of the virtual segment metadata 620 includes the source’s top address, SRCTOP, 623 of the virtual segment in the source address space and the second element of the virtual segment metadata 620 includes the numerical difference, DIFF, 622 of two respective top addresses 623, 626 for the virtual segment in the source and target address spaces 625S, 625T.

[0071] In FIG. 6D, the top address numerical difference is replaced with a target’s top address 632 in a target address space 635T. The rest is exactly the same as the previous embodiment. That is, the first element of the virtual segment metadata 630 includes a source’s top address, SRCTOP, 633 of the virtual segment in a source address space 635S and the second element of the virtual segment metadata 630 includes the target’s top address 632 of the virtual segment in the target address space 635T. The virtual segment metadata 630 includes a third element that indicates the length of the virtual segment, SEGLEN, 631.

[0072] In all these embodiments, the virtual segment metadata is allowed to carry attributes 604, 614, 624, 634 for the virtual segment. These attributes 604, 614, 624, 634 include permissions, specifiers for certain behaviour, and bits reflecting the status of the virtual segment. In essence, such attributes are no different to page-based attributes found in existing virtual memory management schemes. FIG. 6E is an exemplary diagram that illustrates an indicator 640, for the virtual segment metadata 643, 644 in accordance with an implementation of the disclosure. In FIG. 6E, each indicator 640 embedded in each page table entry associated with each page of the virtual segment is identical and indicates the same virtual segment metadata via absolute addressing. In FIG. 6E, the indicator 640 includes a pointer 641 which is used to locate target metadata, i.e., the virtual segment metadata 643, 644 in a target address space. The target address for the virtual segment metadata 643, 644 is encoded, without losing information, as a shortened pointer, and placed in the indicator 640.

[0073] FIG. 6F is an exemplary diagram that illustrates an indicator 650 for the virtual segment metadata 656, 657 in accordance with an implementation of the disclosure. In FIG. 6F, the indicator 650 additionally includes the offset element 651 to the virtual segment’s bottom page 660 from the page associated with the current indicator 659. This gives the software some convenience in the determination of the page, without the originally requested address in its context, e.g. a function of the Linux kernel. The offset element 651 contains an address offset value of a page associated with the current indicator 659 relative to a bottom page 660 of the corresponding virtual segment 656S.

[0074] Additionally, the indicator 650 includes an index 652. The combination of the index 652 and a base to metadata array 655 for an array of metadata 654 of the virtual segment metadata 656, 657, replaces the pointer in the previous embodiment. The base to metadata array 655 is provided elsewhere in the hybrid virtual memory system, for example as a system register of the processor. When encoded in the indicator 650, the index 652 takes fewer bits than an absolute pointer. This does incur a new constraint, however. All metadata in the same process space has to be packed into an array.

[0075] FIG. 7 illustrates an exemplary representation of accelerating address translation with virtual segments in accordance with an implementation of the disclosure. The exemplary representation shows a virtual segment’s metadata that is retrieved with a look-up of an address. The exemplary representation depicts a system that includes a processor 740, and a memory 700. The processor 740 includes an instruction fetch unit 741, a load store unit 742, a Memory Management Unit, MMU, 744, and a caches and bus unit 743. The MMU 744 includes a Range Translation Look-aside Buffer, R-TLB, 720, a Translation Lookaside Buffer, TLB 730, an extended page table walker 710. The memory 700 includes radix-tree page tables 701, and one or more virtual segment metadata 702, 703, 704. When either the instruction fetch unit 741 or the load store unit 742 request an address translation from the MMU 744, the address look-up request is forwarded to both the page-based conventional TLB 730 and the Range TLB 720. If either the TLB 730 or the Range TLB 720 finds a hit, an address translation is returned from the hit unit, as the response to the address translation request. If both the TLB 730 and the Range TLB 720 miss, i.e. no relevant translation is found there, the extended page table walker 710 receives a miss signal with the address translation request. The extended page table walker 710 starts a page table walk by traversing the radix-tree page tables 701. Assume at this point both the radix-tree page tables 701 and the virtual segment metadata are all setup by software correctly.

[0076] If a page table entry for a normal page is found on the page table walk, an address translation is returned to the extended page table walker 710. Subsequently, the TLB 730 is filled and the address translation is returned to the requester, concluding the address look-up request. If an indicator for metadata is found on the page table walk, the relevant virtual segment’s metadata 704, from the virtual segment metadata, is located using the indicator. With the address translation retrieved from the virtual segment metadata, the extended page table walker 710 then fills the Range TLB 720 and the MMU 744 then concludes the address look-up request with a response to the requester. If none (i.e. no indicator) was found on the page table walk, a translation fault exception, sometimes known as a page fault, is raised for privileged software to step in.

[0077] In an alternative embodiment, the MMU 744 raises an exception as soon as the indicator is found on the page table walk, to allow the software to fill the Range TLB 720 through a management interface. Once the Range TLB 720 includes correct mapping by virtual segment, the processor 740 restarts the original operation, which has been faulted on and is to get the address translation this time, to resume the execution.

[0078] On setting up the page tables for a certain virtual segment’s metadata, there exist options for the software. FIG. 8 illustrates an exemplary representation, where a virtual segment covers a contiguous set of pages in accordance with an implementation of the disclosure. The virtual segment’s metadata 840, therefore, is pointed to by all these page’s associated indicators(e.g. indicators 811, 812, 813, 821, 822, 831, 832 and those ones between 821 and 822. By rules of radix-tree traversal, the three page tables 810, 820, 830 involved, which are in the level n, by these indicators, are pointed to by Page Table Entries, PTE 801, 803P, 802 in a level-(n-l) page table 800. Furthermore, these page table entries 801, 803P, 802 are consecutive in space.

[0079] Unlike the other two level-n page tables 810, 830 in this example, the middle page table 820 contains no other information but only indicators to the virtual segment metadata 840. For this reason, the entire page table 820 may be replaced with one sumindicator 803S-I, which also points to the same virtual segment metadata 840. This means that the original PTE 803P is substituted by the sum-indicator 803S-I, and the page table 820 is eliminated. In other words, the page table 820 is folded or collapsed into the sum-indicator 803S-I. This level-(n-l) sum- indicator corresponds to a large conceptual page, which is contiguous and equal to the size of a base page times the number of entries in the page table.

[0080] Fewer page tables not only saves radix-tree memory but also reduces average page table walk depth. In this case, paths through the level-n page tables 810, 820, 830 are 1-hop deeper than those through the sum indicator 803S-I. As the PTE 802 contain more entries, the latter outnumbers the former, probabilistically bringing significant reduction in walk depth.

[0081] Thus, the concept of collapsing page tables is for explaining this property of virtual segment and radix-tree page tables. The software does not have to create these collapsible page tables only to eliminate them later. Sum-indicators and their locations can be calculated based on virtual segment metadata alone.

[0082] Further, the process of page table collapsing may be reverted if the software needs to change the virtual segment’s span, or to track the properties of its pages at finer granularity.

[0083] FIGS. 9A and 9B are flow diagrams that illustrate a method for range-based address translation of a virtual memory in a hybrid virtual memory system from a source address space to a target address space in accordance with an implementation of the disclosure. The hybrid virtual memory system includes at least one page table configured by rules of page-based address translation. At a step 902, a memory block is allocated within the hybrid virtual memory system as a virtual segment in the source address space and the target address space. The memory block consists of a plurality of contiguous memory addresses. The virtual segment consists of at least one page, and each page is associated with a page table entry, PTE. At a step 904, a virtual segment metadata is created for the virtual segment. The virtual segment metadata includes at least three elements including a first element that indicates an address range of the virtual segment in the source address space, a second element that indicates an address range of the virtual segment in the target address space, and a third element that indicates a length of the virtual segment. At a step 906, each page table entry associated with each page of the virtual segment is configured by embedding an indicator. The indicator indicates a location of virtual segment metadata in the target address space. At a step 908, a source address of the virtual segment is mapped into an address of the target address space according to the virtual segment metadata. The virtual segment metadata is retrieved according to the indicator embedded in a Page Table Entry, PTE associated with one of the pages in the virtual segment. The indicator is identified by page table walk through the at least one page table.

[0084] It should be understood that the arrangement of components illustrated in the figures described is exemplary and that other arrangement may be possible. It should also be understood that the various system components (and means) defined by the claims, described below, and illustrated in the various block diagrams represent components in some systems configured according to the subject matter disclosed herein. For example, one or more of these system components (and means) may be realized, in whole or in part, by at least some of the components illustrated in the arrangements illustrated in the described figures.

[0085] In addition, while at least one of these components is implemented at least partially as an electronic hardware component, and therefore constitutes a machine, the other components may be implemented in software that when included in an execution environment constitutes a machine, hardware, or a combination of software and hardware.

[0086] Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

CLAIMS1. A method for range-based address translation of a virtual memory in a hybrid virtual memory system (400) from a source address space (605S, 615S, 625S, 635S) to a target address space (520, 605T, 615T, 625T, 635T), wherein the hybrid virtual memory system (400) comprises at least one page table (421) configured by rules of page-based address translation, the method comprising: allocating a memory block within the virtual memory as a virtual segment (530S, 531S) in the source address space (605S, 615S, 625S, 635S) and the target address space, wherein the memory block consists of a plurality of contiguous memory addresses (530, 531), and wherein the virtual segment (530S, 531S) consists of at least one page, each page is associated with a page table entry, PTE (530P, 531 P); and creating virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 702, 703, 704, 840) for the virtual segment (530S, 531S), wherein the virtual segment metadata comprises at least three elements (600, 610, 620, 630), wherein the first element indicates an address range of the virtual segment (530S, 531S) in the source address space (605S, 615S, 625S, 635S), the second element indicates an address range of the virtual segment (530S, 531S) in the target address space (520, 605T, 615T, 625T, 635T) and the third element indicates a length of the virtual segment (601, 611, 621,631); and configuring each page table entry associated with each page of the virtual segment (530S, 53 IS) by embedding an indicator (640, 650, 811, 812, 813, 821, 822, 831, 832), wherein the indicator indicates the location of virtual segment metadata in the target address space (520, 605T, 615T, 625T, 635T); and mapping a source address of the virtual segment (530S, 531S) into an address of the target address space (520, 605T, 615T, 625T, 635T) according to the virtual segment metadata, wherein the virtual segment metadata is retrieved according to the indicator embedded in a page table entry (530P, 531P) associated with one of the pages in the virtual segment (530S, 531S), wherein the indicator is identified by page table walk through the at least one page table (701).

2. A method according to claim 1 , wherein the first element of the virtual segment metadata (610) comprises a source’s bottom address (613) for the virtual segment in the source address space (615S) and the second element of the virtual segment metadata (610) comprises a target’s bottom address (612) for the virtual segment in the target address space (615T).

3. The method of claim 1, wherein the first element of the virtual segment metadata (600) comprises a source’s bottom address (603) of the virtual segment in the source address space (605S) and the second element of the virtual segment metadata (600) comprises a numerical difference (602) of the two respective bottom addresses (603, 606) of the virtual segment in the source address space (605S) and the target address space (605T).

4. The method according to claim 1, wherein the first element of the virtual segment metadata (630) comprises a source’s top address (633) of the virtual segment in the source address space (635S) and the second element of the virtual segment metadata (630) comprises a target’s top address (632) of the virtual segment in the target address space (635T).

5. The method of claim 1, wherein the first element of the virtual segment metadata (620) comprises a source’s top address (623) of the virtual segment in the source address space (625S) and the second element of the virtual segment metadata (620) comprises a numerical difference (622) of the two respective top addresses (623, 626) for the virtual segment in the source and target address spaces.

6. The method according to any one of previous claims, wherein each indicator (640, 650, 811, 812, 813, 821, 822, 831, 832) embedded in each page table entry associated with each page of the virtual segment is identical and indicates the same virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 643, 644, 656, 657, 702, 703, 704, 840) via absolute addressing.

7. The method according to any one of claims 1-5, wherein the hybrid virtual memory system comprises a plurality of virtual segments and an array (654) of virtual segment metadata (656, 657) associated with the plurality of virtual segments, and wherein the indicator (650) comprises an index (652) and an offset element (651), wherein the index (652) contains an index value indicating the virtual segment metadata of the corresponding virtual segment from the array of virtual segment metadata (656, 657), and wherein the offset element (651) contains an address offset value of the corresponding page (659) relative to a bottom page of the corresponding virtual segment, wherein the bottom of the corresponding virtual segment (656S) is located via indirect addressing.

8. The method according to claim 7, wherein the indicator (650) further comprises a subset of elements, wherein the subset of elements is used for indicating attributes (642, 652) of the page table entry.

9. The method according to any one of previous claims, wherein the at least one page table comprises at least one radixtree page table (500) and / or at least one hashed page table.

10. The method according to any one of previous claims, wherein the hybrid virtual memory system comprises a plurality of virtual segments being associated with a plurality of virtual segment metadata, and wherein each virtual segment comprises a plurality of pages being allocated in a plurality of page tables (810, 820, 830), wherein the plurality of page tables (810, 820, 830) is arranged in a radix-tree comprising a plurality of tree-levels, and wherein each page contains a plurality of page table entries (801, 803P, 802) having indicators (811, 812, 813, 821, 822, 831, 832) indicating to the plurality of virtual segment metadata, and wherein if all indicators (811, 812, 813, 821, 822, 831, 832) contained in a page table (820) in a lower tree-level of the radix-tree indicate to a same virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 643, 644, 656, 657, 702, 703, 704, 840), creating a sum-indicator (803S-I) in a page table (820) in a higher tree-level of the radix-tree and folding or collapsing or deleting the page table (820) in the lower tree-level of the radix-tree, wherein the sum- indicator (803S-I) indicates to the same virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 643, 644, 656, 657, 702, 703, 704, 840) as a replacement of all indicators (811to 832) contained in the page table (820).

11. A hybrid virtual memory system (400) comprising a memory (700), a processor (410, 740), a memory management unit, MMU (411, 744) and a storage medium for storing instructions, wherein the hybrid virtual memory system (400) is configured to allocate a memory block (530, 531) within the virtual memory as a virtual segment (530S, 531S) in a source address space (605S, 615S, 625S, 635S) and a target address space, wherein the memory block (530, 531) consists of a plurality of contiguous memory addresses, and wherein the virtual segment (530S, 53 IS) consists of at least one page, each page is associated with a page table entry, PTE (530P, 531 P); and creating virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 643, 644, 656, 657, 702, 703, 704, 840) for the virtual segment (530S, 531S), wherein the virtual segment metadata comprises at least three elements (600, 610, 620, 630), wherein the first element indicates an address range of the virtual segment (530S, 531S) in the source address space (605S, 615S, 625S, 635S), the second element indicates an address range of the virtual segment (530S, 531S) in the target address space (605T, 615T, 625T, 635T) and the third element indicates a length of the virtual segment (601, 611, 621, 631); and configure each page table entry associated with each page of the virtual segment (530S, 531S) by embedding an indicator (640, 650, 811, 812, 813, 821, 822, 831, 832), wherein the indicator indicates the location of virtual segment metadata in the target address space 520, 605T, 615T, 625T, 635T); and map a source address of the virtual segment (530S, 531S) into an address of the target address space (520, 605T, 615T, 625T, 635T) according to the virtual segment metadata, wherein the virtual segment metadata is retrieved according toan indicator embedded in a page table entry (530P, 531P) associated with anyone of the pages in the virtual segment (530S, 531S), wherein the indicator is identified by page table walk through the at least one page table (701).

12. The system according to claims 11, wherein the virtual segment metadata (425, 530M, 531M, 600, 610, 620, 630, 643, 644, 656, 657, 702, 703, 704, 840) is cached in a Translation Look-aside Buffer, TLB (730), in part or as a whole, or in a Range TLB (720) according to a set of preselected conditions, wherein the set of preselected condition includes size of the virtual segment (530S, 531S).

13. The system according to claims 11 or 12, wherein the first element of the virtual segment metadata (610) comprises a bottom address (613) for the virtual segment in the source address space (615S) and the second element of the virtual segment metadata (610) comprises a source’s bottom address (612) for the virtual segment in the target address space (615T); or wherein the first element of the virtual segment metadata (600) comprises a source’s bottom address (603) of the virtual segment in the source address space (605S) and the second element of the virtual segment metadata (600) comprises a numerical difference (602) of the two respective bottom addresses (603, 606) for the virtual segment in the source and target address spaces; or wherein the first element of the virtual segment metadata (630) comprises a source’s top address (633) of the virtual segment in the source address space (635S) and the second element of the virtual segment metadata (630) comprises a top address (632) of the virtual segment in the target address space (635T); or wherein the first element of the virtual segment metadata (620) comprises a source’s top address (623) of the virtual segment in the source address space (625S) and the second element of the virtual segment metadata (620) comprises a numerical difference (622) of the two respective top addresses (623, 626) for the virtual segment in the source and target address spaces.

14. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method of claim 1.

15. A computer-readable medium comprising instructions which, when executed by a computer, cause the computer to carry out the method of claim 1.

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