Integrated circuit structure

Abstract

A method for forming a stacked electronic structure, the method comprising: providing a first integrated circuit (IC) on a carrier, the first IC having a first surface and a second surface, wherein the first surface of the first IC is proximal to an upper surface of the carrier and the second surface of the first IC opposing the first surface of the first IC; and contacting a second IC with the first IC and mechanically coupling the second IC with the first IC to form a stacked electronic structure, wherein at least a portion of a first surface of the second IC is arranged to contact at least a portion of the second surface of the first IC, and wherein the second IC has a second surface opposing the first surface of the second IC; and separating the stacked electronic structure from the carrier; wherein the first IC is a flexible IC.

Description

Integrated Circuit Structure

[0001] The present invention relates to a method for forming an electronic structure. In particular, the present disclosure relates to a stacked integrated circuit (IC) structure and a method of manufacturing a stacked IC structure. Furthermore, the present disclosure relates to a method of forming a stacked IC structure by coupling an IC to another IC.BACKGROUND

[0002] In the past decade, flexible circuitry has been branching out significantly from its initial role as a simple wire replacement to providing very cost-effective, but more complex interconnects, as well as, low-cost flexible integrated circuits (ICs) that can easily be embedded into everyday objects.

[0003] A flexible circuit element or structure, such as, for example, a flexible integrated circuit (flexible IC), is a patterned arrangement of circuitry and components provided on a flexible base material with or without a flexible overlay. The circuitry patterned on each flexible circuit element may comprise any of resistors, capacitors, transistors, diodes, inductors, conductors, etc. The flexible base material (or flexible substrate) may be a polymer layer. The flexible base material provides mechanical support to the patterned arrangement of circuitry and components, such as a higher tensile strength and durability. As such, the flexible IC can be bent or even stretched while maintaining the integrity and functionality of the integrated circuit.

[0004] Flexible ICs are capable of providing a wide variety of different functions and being used in many applications. However, improvements can be made in relation to broadening the ubiquity of such ICs, and their further optimisation. Furthermore, the width of an IC may be relatively large, resulting in arrangements with larger areas.BRIEF SUMMARY OF THE DISCLOSURE

[0005] In accordance with a first aspect of the present disclosure, there is provided a method for forming a stacked electronic structure, the method comprising: providing a first integrated circuit (IC) on a carrier, the first IC having a first surface and a second surface, wherein the first surface of the first IC is proximal to an upper surface of the carrier and the second surface of the first IC opposing the first surface of the first IC; and contacting a second IC with the first IC and mechanically coupling the second IC with the first IC to form a stacked electronic structure, wherein at least a portion of a first surface of the second IC is arranged to contact at least a portion of the second surface of the first IC, and wherein the second IC has a second surface opposing the first surface of the second IC; and separating the stacked electronic structure from the carrier; wherein the first IC is a flexible IC.

[0006] In an example, the second surface of the first IC and the first surface of the second IC are the same size or a different size.

[0007] In an example, both the first IC and the second IC are flexible ICs.

[0008] In an example, the step of providing a first IC on the carrier comprises manufacturing the first IC on the carrier.

[0009] In an example, manufacturing the first IC on the carrier comprises manufacturing a plurality of flexible ICs on a flexible IC wafer and singulating the wafer to form the first IC.

[0010] In an example, the step of providing the first IC on the carrier comprises: depositing a polymer layer on the carrier; and forming a component layer on the polymer layer.

[0011] In an example, the step of providing the first IC on the carrier comprises: depositing a first polymer layer on the carrier; depositing a second polymer layer on the first polymer layer, wherein the second polymer layer comprises the first surface of the first IC; and forming a component layer on the second polymer layer; wherein the step of separating the stacked electronic structure from the carrier comprises detaching the second polymer layer from the first polymer layer to separate the first IC from the first polymer layer and the carrier.

[0012] In an example, the second polymer layer has a thickness of between 5pm and 0.01 pm.

[0013] In an example, the method further comprises the step of: depositing a barrier layer on the second polymer layer; and forming the component layer on the barrier layer.

[0014] In an example, the step of providing the first IC on the carrier comprises: depositing a barrier layer on the carrier; and forming a component layer on the barrier layer.

[0015] In an example, the barrier layer has a thickness of between 5pm and 0.001 pm.

[0016] In an example, the step of separating the stacked electronic structure from the carrier comprises detaching the barrier layer from the carrier to separate the first IC from the carrier, wherein the surface of the barrier layer proximal to the carrier is the first surface of the first IC.

[0017] In an example, the step of separating the stacked electronic structure from the carrier comprises detaching the component layer from the barrier layer to separate the first IC from the barrier layer and the carrier, wherein the surface of the component layer proximal to the carrier is the first surface of the first IC.

[0018] In an example, a release layer is disposed between the carrier and the first surface of the first IC for aiding separation of the stacked electronic structure from the carrier.

[0019] In an example, the stacked IC structure is separated from the carrier after the second IC is mechanically coupled to the first IC.

[0020] In an example, the method further comprises the step of electrically coupling the first IC to the second IC.

[0021] In an example, one, or both, of the first IC and the second IC comprise one or more contact members.

[0022] In an example, the first IC comprises one or more contact members proximal to the second surface of the first IC, and the second IC comprises one or more contact members proximal to the first surface of the second IC; and wherein one or more of the contact members proximal to the second surface of the first IC are configured to electrically couple with one or more of the contact members proximal to the first surface of the second IC to electrically couple the first IC and the second IC.

[0023] In an example, one or more of: the first IC comprises one or more contact members proximal to the first and / or second surface of the first IC, said one or more contact members being configured to electrically and / or mechanically couple to a first external circuit; and the second IC comprises one or more contact members proximal to the first and / or second surface of the second IC structure, said one or more contact members being configured to electrically and / or mechanically couple to a second external circuit.

[0024] In an example, the first IC and the second IC are electrically coupled by one or more of: conductive coupling, capacitive coupling and inductive coupling.

[0025] In an example, the contact members of the first IC and the second IC configured to electrically couple have an insulating layer therebetween.

[0026] In an example, the first IC and / or the second IC comprises a contact member proximal to their respective first surface and a contact member proximal to their respective second surface, and a via connecting the contact member proximal to their respective first surface and the contact member proximal to their respective second surface.

[0027] In an example, the method further comprises providing a third IC on the second IC, wherein a first surface of the third IC is configured to contact the second surface of the second IC; and mechanically coupling the third IC with the second IC.

[0028] In an example, at least one via is provided through one or more of the first IC, the second IC and the third IC.

[0029] In an example, a via is provided through the second IC to electrically connect the first IC and the third IC, and the via is not electrically connected to electronic components of the second IC so as to operationally skip the second IC.

[0030] In an example, the first IC has an irregular shape.

[0031] In an example, one or more external devices are encapsulated between the first IC and the second IC.

[0032] In an example, the method further comprises folding the first IC such that one or more external devices and / or the second IC is encapsulated by the folded first IC.

[0033] In an example, the method further comprises sealing a space between the folded first IC and the at least one external device and / or the second IC encapsulated by the folded first IC.

[0034] In an example, folding the first IC comprises thermal treatment of one or more of the layers of the first IC to induce a curl in the first IC upon removal from the carrier.

[0035] In an example, the at least one external device comprises at least one of a further IC, an antenna, a sensor, a display device, a light emitting diode (LED), an LED circuit or LED driver, a microLED, a microLED circuit or microLED driver, an organic light-emitting diode (OLED), an OLED circuit or an OLED driver, a photovoltaic (PV) cell, or a PV device or PV circuit, a capacitor, a capacitor circuit or capacitor driver, a super-capacitor, a supercapacitor circuit or super-capacitor driver, or piezoelectric actuator, and a battery.

[0036] In an example, the first IC comprises a plurality of contact members provided on the second surface; wherein the second IC comprises one or more contact members provided on the first surface of the second IC and one or more contact members provided on the second surface of the second IC; and wherein the method comprises: folding the first IC to encapsulate the second IC such that each of the plurality of contact members provided on the second surface of the first IC are proximate one or more contact members provided on the first surface or the second surface of the second IC .

[0037] In an example, the first IC comprises one or more contact members provided on the second surface; wherein the second IC comprises a plurality of contact members provided on the first surface of the second IC; and wherein the method comprises: folding the first IC and folding the second IC to at least partially encapsulate the second IC with the first IC such that the one or more contact members provided at the second surface of the first IC is proximate to one or more of the plurality of contact members provided at the first surface of the second IC.

[0038] In an example, the method further comprises depositing an adhesive on at least a portion of the second surface of the first IC such that at least part of the first surface of the second IC contacts the adhesive to mechanically and / or electrically couple the first IC and the second IC.

[0039] In an example, depositing the adhesive includes patterning the adhesive.

[0040] In an example, the at least a portion of the second surface of the first IC and the at least a portion of the first surface of the second IC comprise one or more contact members and the adhesive is a conductive adhesive.

[0041] In an example, the second IC is mechanically coupled to the first IC through an adhesive applied to the first surface of the second IC, the first surface of the second IC being in contact with the second surface of the first IC.

[0042] In an example, the method further comprises providing an adhesive on the first surface of the first IC; and attaching the first IC to an external object by contacting the adhesive on the first surface of the first IC to a surface of the external object.

[0043] In an example, the third IC is mechanically coupled to the second IC through an adhesive applied to the first surface of the third IC, the first surface of the third IC being in contact with the second surface of the second IC.

[0044] In an example, the ICs of the stacked electronic structure include at least one data bus connecting each of the ICs to one another.

[0045] In an example, the stacked electronic structure provides a self-contained electronic system and each of the ICs provide a sub-system of the electronic system.

[0046] In accordance with a second aspect of the present disclosure, there is provided a stacked electronic structure comprising a first integrated circuit (IC) and a second IC, wherein the first IC is a flexible IC and is folded to surround at least a portion of the second IC such that a first portion of a surface of the first IC opposes a first portion of a surface of the second IC, and wherein the first portion of a surface of the first IC includes a first contact member configured to electrically couple to a first contact member included in the first portion of a surface of the second IC.

[0047] In an example, the second IC is a flexible IC and is folded.

[0048] In an example, all contact members of the first IC configured to electrically couple to contact members of the second IC are provided on a same surface of the first IC.

[0049] In an example, all contact members of the second IC configured to electrically couple to contact members of the first IC are provided on a same surface of the second IC.

[0050] In an example, the first IC includes a second portion of a surface that opposes a second portion of a surface of the second IC, and the second portion of a surface of the first IC includes a second contact member configured to electrically couple to a second contact member included in a second portion of a surface of the second IC, and wherein the first and second portions of the first IC are folded with respect to one another.

[0051] In an example, the first and second portions of the second IC are folded with respect to each other.

[0052] In an example, the first IC and the second IC are mechanically coupled.

[0053] In an example, at least one of the first IC and the second IC at least partially encapsulates an external device.BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The invention will now be described, purely by way of example, with reference to the accompanying drawings, in which:Figure 1 provides a flow diagram of a manufacturing process for a conventional flexible integrated circuit (IC);Figure 2 provides a schematic diagram of an architecture of a conventional flexible IC wafer;Figure 3 provides schematic diagram of an architecture of a conventional flexible IC;Figure 4 provides a flow diagram of a manufacturing process for a flexible IC wafer;Figure 5 provides a schematic diagram of a flexible IC wafer;Figure 6 provides a schematic diagram of a flexible IC;Figure 7 provides schematic diagram of an architecture of a flexible IC;Figure 8 provides a flow diagram of a manufacturing process for a flexible IC wafer;Figure 9 provides a schematic diagram of a flexible IC wafer;Figures 10a and 10b provide schematic diagrams of flexible ICs;Figure 11 provides schematic diagram of an architecture of a flexible IC;Figure 12 provides schematic diagram of an architecture of a flexible IC;Figure 13 provides a flow diagram of a method for forming or manufacturing a stacked IC structure;Figures 14A, 14B, and 14C show simplified schematic illustrations of stacked IC structures;Figures 15A and 15B show simplified schematic illustrations of one or more ICs at least partially encapsulating a component;Figure 16 shows a simplified schematic illustration of stacked IC structures in a daisy chain arrangement;Figures 17A, 17B, 17C, 17D, 17E, 17F, and 17G show simplified schematic illustrations of stacked IC structures;Figure 18 shows a simplified schematic illustration of a ribbon cable type IC;Figure 19 shows a simplified schematic illustration of a sticker-type IC for providing a stacked IC structure;Figure 20A shows a simplified schematic illustration of a stacked IC structure with one or more buses;Figures 20B and 20C show simplified schematic illustrations of stacked IC structures coupled by capacitive coupling; andFigure 20D shows a simplified schematic illustration of a stacked IC structure coupled by inductive coupling.DETAILED DESCRIPTION

[0055] Throughout the present disclosure, the term “connected” is understood to mean a direct connection between objects. Such direct connections include electrical, mechanical, magnetic, electromagnetic, inductive, or capacitive. The term “coupled” is understood to mean a direct or indirect connection (i.e. through one or more passive or active intermediary devices), where the connection may be for example electrical, mechanical, magnetic, electromagnetic, inductive, or capacitive. The term “scaling” may be understood to generally refer to converting one layout pitch to another layout pitch. Further, unless otherwise specified, the use of ordinal adjectives, such as, “first”, “second”, “third” etc. merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Orientation terminology, such as, “horizontal” is understood with respect to a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” may refer to a direction perpendicular to the horizontal as defined previously. Prepositions, such as, “on”, “side”, “higher”, “upper”, “lower”, “over”, “bottom” and “under” may be understood with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the electrical interconnects or the electronic package.

[0056] In the present disclosure, a flexible IC comprises the electronic components of the flexible IC, such as insulating, conducting, active, passive and connecting components. The flexible IC may also comprise one or more material layers used as mechanical support forthe electronic components, protection for the flexible IC, or as part of the manufacturing process. The term integrated circuit (IC) refers to circuitry that has been fabricated as a single integrated entity as opposed to component(s) being discrete and fabricated separately prior to assembly of the circuitry. The flexible ICs may be thin-film flexible ICs, however the flexible ICs of the present disclosure may take any other suitable form and are not restricted to being thin-film flexible ICs. A plurality of flexible ICs fabricated on the same substrate or other material layers may be referred to as a flexible IC wafer. A plurality of flexible ICs, where the electronic components of the plurality of flexible ICs have been formed from one or more common component layers, and fabricated on the same substrate or other material layer, may be referred to as a flexible IC wafer. The plurality of flexible ICs on a flexible IC wafer may be singulated, separated, and picked and placed with respect to an application item, such as an external application circuit or any other external item or circuitry.

[0057] Figure 1 provides a flow diagram of an example manufacturing process for a flexible IC or flexible IC wafer, where Figure 2 provides a schematic diagram of a flexible IC wafer that may result from the manufacturing process of Figure 1.

[0058] Flexible IC wafers and flexible ICs in accordance with present disclosure may be formed using known thin-film and lithographic processes. For example, materials may be deposited in layers using thin-film processes such as, for example: physical vapour deposition (e.g. sputter) chemical vapour deposition (e.g. plasma-enhanced chemical vapour deposition (PECVD)), vacuum deposition (e.g. thermal or electron-beam evaporation); coating (e.g. spin, dip, blade, bar, spray, or slot-die), printing (e.g. jet, gravure, offset, screen, or flexographic), pulsed-laser deposition (PLD), atomic layer deposition (ALD) and / or any other known processes. Patterning of deposited materials may be performed using lithographic processes such as, for example: photolithography, electron-beam lithography, X-ray lithography, or ion-beam lithography; printing and / or other known processes. Patterning may be combined with one or more of: wet etching, dry etching (e.g. plasma etching), ablation, milling, lift-off patterning, and any other known processes.

[0059] Referring to Figures 1 and 2, the flexible IC wafer 210 is fabricated on a substantially rigid carrier 200, such as a glass carrier.

[0060] At step S102, a flexible polymer layer 202 (i.e. flexible substrate layer) is deposited onto the carrier 200. Throughout this disclosure, the terminology of “deposited on", “deposited onto" covers the direct deposition onto a surface but also the indirect deposition, such that this terminology does not exclude the presence of one or more optional intermediate layers between the surface and the deposited material, such as a barrier layer / material for example. The carrier may be a rigid carrier. The carrier 200 may be formedfrom glass, polycarbonate, quartz, silicon or any other suitable material. The flexible polymer layer (i.e. flexible substrate layer) 202 may be deposited using thin-film processes such as, for example: physical vapour deposition (e.g. sputter) chemical vapour deposition (e.g. plasma-enhanced chemical vapour deposition (PECVD)), vacuum deposition (e.g. thermal or electron-beam evaporation); coating (e.g. spin, dip, blade, bar, spray, or slot-die), printing (e.g. jet, gravure, offset, screen, or flexographic), pulsed-laser deposition (PLD), atomic layer deposition (ALD) and / or any other known processes.

[0061] Although a polymer layer is referred to, flexible polymer layer 202 is not restricted to being formed from polymers and may be formed from any other materials that provide suitable electrical, chemical, and / or structural properties. The flexible polymer layer (i.e. flexible substrate layer) 202 may be formed from the same material, different materials, or different types of a same material. The flexible polymer layer (i.e. flexible substrate layer) 202 may comprise materials selected from one or more of: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0062] Polymer materials may comprise polymers selected from one or more of: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1-Methoxy-2-propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0063] Metal oxide materials comprise metal oxides selected from one or more of: AI2O3, SiOxNy, SiC>2, SisN4, or any other suitable metal oxide. Resin materials comprise resins selected from one or more of: a UV-curable resin or any other suitable resin. Resist materials comprise resists selected from one or more of: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (Sll-8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Foil materials comprise foils selected from one or more of: polymeric foils or any other suitable foil. Insulator-coated metals comprise one or more of: insulator coated stainless-steel or any other suitable insulator-coated metal.

[0064] Optionally, a barrier layer (not shown) is deposited on flexible polymer layer 202. Although the use of a barrier layer may allow for improved formation of the component layer, the use of a barrier layer is not essential and the component layer 206 may be formed directly onto the flexible polymer layer 202. The barrier layer may be deposited using any of theaforementioned thin film processes, and may comprise one or more layers of dielectric materials. The one or more layers of dielectric material may be formed from the same or different materials. The one or more layers of dielectric material may be formed using the same or different thin film processes and / or the same or different processing conditions.

[0065] Dielectric materials may be selected from one or more of: metal oxides, metal phosphates, metal sulphates, metal sulphites, metal nitrides, metal oxynitrides, inorganic insulators, spin-on glass, polymeric dielectric materials, UV-curable resins, nanoimprint resists, photoresists or any other suitable dielectric material. Dielectric materials may be selected from one or more of: metal oxides such as AI2O3, ZrC>2, HfC>2, Y2O3, SisNs, TiC>2, Ta2<D5 or any other suitable metal oxide; metal phosphates such as AhPOxor any other suitable metal phosphate; metal sulphates such as HfSOxor any other suitable metal sulphate, metal sulphites such as HfSOxor any other suitable metal sulphite; metal nitrides such as AIN, TiN, ZrN, TaN, HfN or any other suitable metal nitride; metal oxynitrides such as AIOxNy Or any other suitable metal oxynitride; inorganic insulators such as SiC>2, SisN^ SiNxor any other suitable inorganic insulator; spin on glass such as polyhydroxybenzyl silsesquioxane or any other suitable spin on glass; polymeric dielectric materials such as amorphous fluoropolymers (Cytop®), Bisphenol A novolac epoxy (Sll-8), benzocyclobutenes (BCB), polyimides, polymethyl methacrylates, polybutyl methacrylates, polyethyl methacrylates, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl alcohols, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyethylenes, polycarbonates, parylenes, silicone, or any other suitable polymeric dielectric materials. The dielectric material may have a relatively low dielectric constant K (IOW-K) such as Cytop®, polyhydroxybenzyl silsesquioxane, parylenes) or a relatively high dielectric constant K (high- K) such as Ta2C>5, HfC>2, or any other insulating oxides, oxynitrides, silicates, etc. The barrier layer may be formed from one or more layers of metal such as, for example, titanium, steel, gold, or any other suitable metal.

[0066] At step S104, the flexible IC’s remaining architecture, including the component layer 206, is formed on the flexible polymer layer 202. The component layer 206 may be formed on the barrier layer (or flexible polymer layer 202 if a barrier layer is not present), where the component layer includes the electronic components of the flexible IC, including active, passive, conducting, insulating, and contact components. The component layer may comprise one or more layers that are sequentially formed using any of the aforementioned thin film deposition and patterning processes, or any other suitable fabrication processes, where each layer may include one or more of active, passive, conducting, insulating, and contact components. The component layer may also include a contact layer 208 that provides contacts for mechanically and / or electrically connecting the flexible ICs to externalcircuitry, such as, for example, an application item or any other external structure. The contact layer may be positioned at or towards the upper and / or lower surfaces of the component layer. The contacts may be connection pads or contact members. It will be appreciated that the number of contact members is variable, and, optionally, no contact members can be included in the flexible IC. Other surfaces of the flexible IC may also include one or more contact members, if desired. The contact members may be raised, recessed or substantially planar with the respective surface of the flexible IC.

[0067] The component layer 206 may include components of a plurality of flexible ICs such that the flexible polymer layer 202, the barrier layer (if present), and component layer 206 form a flexible IC wafer that includes a plurality of flexible ICs. Lines 212 illustrate the division of the flexible IC wafer of Figure 2 into individual flexible ICs 214.

[0068] The component layer may comprise one or more layers of conductive materials. Conductive materials may be selected from one or more of: metals, metal alloys, transparent conductive oxides, metal nitrides, carbon materials, conducting polymers, semiconductor materials, or any other suitable conducting material. For example, conductive materials may be selected from one or more of: metals such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W or any other suitable metal; metal alloys such as MoNi, MoCr, AlSi or any other suitable metal alloys; transparent conductive oxides such as ITO, IZO, AZO, or any other suitable transparent conductive oxide; metal nitrides such as TiN or any other suitable metal nitride; carbon materials such as carbon black, carbon nanotubes, graphene or any other suitable carbon material; conducting polymers such as polyaniline, poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) or any other suitable conducting polymer.

[0069] Semiconductor materials may be selected from one or more of: compound semiconductors, metal oxides, metal oxynitrides, inorganic semiconductors, organic semiconductors, polymer semiconductors, 2D semiconductor materials, chalcogenides, perovskites, or any other semiconductor material. For example, semiconductor materials may be selected from one or more of: GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, ZnO, SnO2, NiO, SnO, Cu2O, ln2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HflnZnO (HIZO), InGaZnO (IGZO) ZnxOyNzamorphous, microcrystalline or nanocrystalline Si, Copper(ll) phthalocyanine (CuPc), pentacene, Perylenetetracarboxylic dianhydride (PTCDA), methylene blue, Orange G, rubrene; PEDOT:PSS, poly(3-octylthiophene) (POT), poly(3- octylthiophene-2,5-diyl) (P3OT), poly(3-hexylthiophene) (P3HT), polyaniline, polycarbazole, grapheneMoS2, GeSbTeSrTiOs, CHsNHsPbCIs, H2NCHNH2PbCl3, CsSnh, or any other suitable semiconductor material. These semiconductor materials may also be doped or contain a doping gradient and may be n-type or p-type. Further treatments may be appliedto the component layers to modify their semiconductor properties such as, for example, thermal or laser annealing, or any other known processes.

[0070] At step S106, the flexible polymer layer 202 is detached from the carrier 200 such that the flexible IC or flexible IC wafer 210 is detached from the carrier 200. The detachment may be performed by peeling, which may follow one or more optional processes for assisting with the detachment of the polymer layer 202 from the carrier 200. For example, the interface between the polymer layer 202 and the carrier 200 may be laser ablated to assist with the release of the polymer layer 202 from the carrier 200.

[0071] When manufacturing a flexible IC wafer, the process of Figure 1 may also include one or more steps to singualate the individual flexible ICs (i.e. divide the flexible ICs along the lines 212). For example, one of more singulation steps may be performed following step S106 or singulation steps may be distributed throughout the process of Figure 1.

[0072] Figure 3 shows a schematic diagram of a conventional flexible IC 214 which may be formed from the method of Figure 1 .

[0073] As shown in Figure 3, flexible IC 214 comprises a first horizontal surface 20-1 and a second horizontal surface 20-2 opposing the first surface 20-1. The flexible IC (which may also be referred to as flexible IC structure or IC structure) 214 further includes flexible substrate layer (i.e. flexible polymer layer) 202, which comprises first surface 20-1 of the flexible IC 214 on its lowermost surface, contact members 21 , and through substrate vias 25. The component layer 206 of flexible IC 214, including one or more layers 206-0, 206-2, 206-4, is provided over the topmost surface of flexible substrate layer 202. One or more layers 206-0, 206-2, 206-4 may comprise one or more layers of dielectric materials or component layers. Component layers may comprise the electronic components of flexible IC 214, such as insulating, conducting, active, passive and connecting components. Topmost layer 206-0 of component layer 206 comprises second surface 20-2 of flexible IC 214 on its topmost surface, and contact members 22.

[0074] One or more contact members 21 (herein, contact members may also be termed contacts, contact elements, contact portions, contact regions etc., as appropriate) may be included in or on flexible IC 214, being provided on the first surface 20-1. Additionally, or alternatively, one or more contact members 22 may be included in or on flexible IC 214, being provided on the second surface 20-2.

[0075] One or more of contact members 21 , 22 may be used for coupling IC 214 with one or more of: an external IC, an external circuit such as an application circuit, or any other external structure(s). For example, one or more of the contact members 21 , 22 may be for electrically coupling or mechanically coupling IC 214 with an external item or circuit. It willbe appreciated that the number of contact members on the first surface 20-1 and on the second surface 20-2 is variable. Optionally, flexible IC 214 may not include contact members on the first and / or second surfaces 20-1 , 20-2. Alternatively, flexible IC 214 may not include any contact members. Other surfaces of the flexible IC 214, further to the first surface 20-1 and second surface 20-2, may include one or more contact members.

[0076] As shown in Figure 3, flexible IC 214 includes three layers: layers 206-0, 206-2, 206-4. It will be appreciated that this is merely for illustrative purposes, and that any number of layers may be included in flexible IC 214. One or more of layers 206-0, 206-2, 206-4 may comprise a dielectric material. For example, one or more of layers 206-0, 206-2, 206-4 may comprise a layer of dielectric material, or one or more of layers 206-0, 206-2, 206-4 may be a layer of dielectric material.

[0077] Dielectric materials may be selected from one or more of: metal oxides, metal phosphates, metal sulphates, metal sulphites, metal oxynitrides, inorganic insulators, spin- on glass, polymeric dielectric materials or any other dielectric material. Dielectric materials may be selected from one or more of: metal oxides such as AI2O3, ZrC>2, HfC>2, Y2O3, SisNs, TiC>2, Ta2Os; metal phosphates such as A^POx; metal sulphates such as HfSOx, metal sulphites such as HfSOx; metal nitrides such as AIN, TiN, ZrN, TaN, HfN; metal oxynitrides such as AIOxNy; inorganic insulators such as SiC>2, SisN^ SiNx; spin on glass such as polyhydroxybenzyl silsesquioxane, polymeric dielectric materials such as amorphous fluoropolymers (Cytop®), Bisphenol A novolac epoxy (Sll-8), benzocyclobutenes (BCB), polyimides, polymethyl methacrylates, polybutyl methacrylates, polyethyl methacrylates, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl alcohols, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyethylenes, polycarbonates, parylenes, silicone; UV-curable resins; nanoimprint resists; or photoresists. The dielectric material may have a relatively low dielectric constant K (IOW-K) such as amorphous fluoropolymers (Cytop®), polyhydroxybenzyl silsesquioxane, parylenes or a relatively high dielectric constant K (high- K) such as Ta2C>5, HfC>2.

[0078] One or more of layers 206-0, 206-2, 206-4 may comprise one or more component layers. Component layers comprise the electronic circuitry / components of IC 214 such as active, passive, conducting, connecting and insulating components. Component layers may comprise one or more conductive materials, for example the component layer may comprise one or more layers of conductive material. Component layers may comprise one or more metals, for example the component layer may comprise one or more metal layers. Component layers may be a layer of conductive material, for example, the component layer may be a metal layer. Conductive materials may be used to form connectors such as, for example, contact members 21 ,22, one or more vias 25, etc of and / or to form conductiveelements of active and / or passive components of IC 214. The conductive elements may include, for example, capacitor plates, inductor windings or transistor electrodes, etc.

[0079] Conductive materials may be selected from one or more of: metals, metal alloys, transparent conductive oxides, metal nitrides, carbon materials, conducting polymers, semiconductor materials, or any other suitable conducting material. For example, conductive materials may be selected from one or more of: metals such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi; transparent conductive oxides such as ITO, IZO, AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene; conducting polymers such as polyaniline, poly(3,4- ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS); semiconductor materials; or any other suitable conductive material.

[0080] The electronic circuitry / components may comprise one or more layers of conductive material. The layers of the conductive material may be the same or different and may have the same or different thicknesses. The one or more conductive layers may correspond to one or more of layers 206-0, 206-2, 206-4. Alternatively, one or more of layers 206-0, 206- 2, 206-4 may each comprise the one or more conductive layers, which form the electronic circuitry / components. The one or more layers of conductive material may be metal layers. The thickness of the metal layer can be controlled using techniques such as, for example: (i) dry etching, to preserve definition at thickness, (ii) plating, (iii) the use of low resistance metals, such as gold, silver, copper and / or aluminium, and / or (iv) planarisation techniques.

[0081] One or more of layers 206-0, 206-2, 206-4 may comprise shielding metal layers. Shielding metal layers may serve, for example, to reduce unwanted coupling between components.

[0082] Flexible IC 214 may comprise contact members 21 , 22 and one more vias 25 formed on the first surface 20-1 and / or second surface 20-2. Contacts 21 ,22 may be metal pads. In such an example of flexible IC 214, metal pads 21 ,22 may be formed by patterning metal pad areas directly onto the carrier (e.g. glass carrier), or onto an intervening release layer, before depositing one or more layers of thin-film over the metal pad area. One or more vias, such as a through substrate via (TSV) 25 may then be etched through the one or more layers of thin-film, for example, using oxygen plasma dry etch, after photo-resist patterning. The connections may be made with an upper metal layer that routes over positively sloped sidewalls around the etched vias to form connections, or by other methods suitable to fill the vias, such as for example, electro / electro-less plating techniques. In this method, the area of interface of the connection between the one or more vias 25 in the substrate 202 and the metal pad may extend over a limited area, such that the metal pad extends beyond the interface area.

[0083] The contacts 21 , 22 may be metal pad areas defined by the width of the via at the first surface 20-1 and / or second surface 20-2. In such an example of flexible IC 214, the one more vias are formed by depositing a polymer film on a carrier (e.g. glass carrier), and subsequently etching one or more vias 25 through the polymer film, in this particular case, with positive sidewalls. A metal is then deposited over at least an area of the surface of the polymer film that includes the via, allowing for no or reduced breakages at the edges of via 25 and through the via such that the metal makes contact the carrier. Alternatively, through- film vias 25 of flexible IC 214 may be formed using mechanical processes.

[0084] Active components of the one or more component layers of flexible IC 214 (e.g. one or more of layers 206-0, 206-2, 206-4) may be formed from any known semiconductor material Semiconductor materials may be selected from one or more of: compound semiconductors, metal oxides, metal oxynitrides, inorganic semiconductors, organic semiconductors, polymer semiconductors, 2D semiconductor materials, chalcogenides, perovskites, or any other semiconductor material. For example, semiconductor materials may be selected from one or more of: GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, ZnO, SnO2, NiO, SnO, Cu2O, ln2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HflnZnO (HIZO), InGaZnO (IGZO) ZnxOyNzamorphous, microcrystalline or nanocrystalline Si, Copper(ll) phthalocyanine (CuPc), pentacene, Perylenetetracarboxylic dianhydride (PTCDA), methylene blue, Orange G, rubrene; PEDOT:PSS, poly(3-octylthiophene) (POT), poly(3- octylthiophene-2,5-diyl) (P3OT), poly(3-hexylthiophene) (P3HT), polyaniline, polycarbazole, grapheneMoS2, GeSbTeSrTiOs, CHsNHsPbCh, H2NCHNH2PbCl3, CsSnh, or any other semiconductor material. These semiconductor materials may also be doped or contain a doping gradient and may be n-type or p-type.REDUCED THICKNESS POLYMER SUBSTRATE

[0085] Figure 4 provides a flow diagram for the manufacture of flexible ICs / IC wafers having a reduced-thickness substrate (“reduced-substrate IC / IC wafer”), and Figure 5 provides a schematic diagram of a reduced-substrate flexible IC wafer, which may result from the manufacturing process of Figure 4. Figures 6 and 7 provide a schematic diagram of an individual reduced substrate flexible IC of the manufactured flexible IC wafer of Figure 5.

[0086] A reduced thickness polymer substrate may have a thickness of below 20pm, such as below 15pm, or below 10pm. In particular, the reduced thickness substrate may have a thickness of between 5pm and above a minimum required or practical thickness. For example, a reduced thickness polymer substrate may have a thickness of between 5pm and 0.01 pm, such as, for example, between 5pm and 0.015pm, between 4.5pm and 0.02pm, between 4pm and 0.025pm, between 3.5pm and 0.03pm, between 3pm and 0.035pm, orbetween 2pm and 0.04pm. The reduced thickness substrate may have a thickness of between 0.1 pm and 0.01pm such as, for example, between 0.95pm and 0.015pm, between 0.9pm and 0.02pm, between 0.85pm and 0.025pm, between 0.8pm and 0.03pm, between 0.75pm and 0.035pm, between 0.7pm and 0.04pm, between 0.65pm and 0.045pm, or between 0.6pm and 0.05pm. The reduced thickness substrate may have a thickness of between 0.05pm and 0.001pm such as, for example, between 0.045pm and 0.0015pm, between 0.04pm and 0.002pm, between 0.035pm and 0.0025pm, between 0.03pm and 0.003pm, between 0.025pm and 0.0035pm, between 0.02pm and 0.004pm, between 0.015pm and 0.0045pm, or between 0.01 pm and 0.005pm.

[0087] In an example of a reduced substrate flexible IC wafer, the flexible substrate layer 202 of Figure 2 may be composed of two separable / detachable (e.g. peelable) polymer layers. The polymer layer proximal to the component layer may be detached from the other polymer layer to separate the flexible IC or flexible IC wafer from the carrier, such that the resulting flexible IC wafer and flexible ICs comprise a reduced thickness polymer substrate.

[0088] Now referring to Figures 4 and 5. At step S402, a first polymer layer 502 is deposited on the carrier 500. The carrier 500 may be a rigid carrier. The carrier 500 may be formed from glass, polycarbonate, quartz, silicon or any other suitable material. The first polymer layer 502 may be deposited using any of the aforementioned thin film processes in relation to flexible polymer layer 202. Suitable materials and / or methods may be used to control the adhesion properties between the first polymer layer 502 and the carrier 500. For example, the first polymer layer 502 may be deposited in a manner such that it is permanently attached to the carrier 500, so that a separate deposition step is not required for each flexible IC wafer manufacturing instance.

[0089] At step S404, a second polymer layer 504 is deposited on the first polymer layer 502. The second polymer layer 502 may be deposited using any of the aforementioned thin film processes in relation to flexible polymer layer 202. As described in more detail below, in some examples an intermediate layer may be deposited between the first and second polymer layers in order to control the material interactions (e.g. adhesion properties) between the first and second polymer layers.

[0090] The first polymer layer 502 may be partially, substantially, or fully cured, prior to the deposition of the second polymer layer 504 in order to control adhesion properties, or any other properties or interactions, between the first and second polymer layers 502, 504. Intermolecular forces or material intermixing between the deposited first and second polymer layers 502, 504 may be weaker than those within each layer, so that the first and second polymer layers 502, 504 may be separated without damage or without functionaldamage to one or more of of the second polymer layer, a barrier layer 506 (if present) and the component layers 508 formed on the second polymer layer 504.

[0091] Although polymer layers are referred to, the layers 502 and 504 are not restricted to being formed from polymers and may be formed from any other materials that provide suitable electrical, chemical, and / or structural properties. The first and second polymer layers 502, 504 may be formed from the same material, different materials, or different types of a same material. The first and second polymer layers 502, 504 may comprise materials selected from one or more of the aforementioned flexible materials in relation to flexible polymer layer 202 of Figures 2 and 3.

[0092] At step S406, a barrier layer 506 is deposited on the second polymer layer 504. Although the use of a barrier layer may allow for improved formation of the component layer, the use of a barrier layer is not essential and the component layer may be formed directly onto the second polymer layer 504. The barrier layer 506 may be deposited using any of the aforementioned thin film processes, and may comprise one or more layers of dielectric materials. The one or more layers of dielectric material may be formed from the same or different materials. The one or more layers of dielectric material may be formed using the same or different thin film processes and / or the same or different processing conditions. Dielectric materials may be selected from one or more of the aforementioned dielectric materials in relation to the optional barrier layer of Figures 2 and 3.

[0093] At step S408, a component layer 508 is formed on the barrier layer 506 (or second polymer layer 504 if a barrier layer is not present), where the component layer includes the electronic components of the flexible IC(s), including active, passive, conducting, insulating, and contact components. The component layer may comprise one or more layers that are sequentially formed using any of the aforementioned thin film deposition and patterning processes, or any other suitable fabrication processes, where each layer may include one or more of active, passive, conducting, insulating, and contact components. The component layer may also include a contact layer 510 that provides contacts for mechanically and / or electrically connecting the flexible ICs to external circuitry, such as, for example, an application item or any other external structure. The contact layer may be positioned at or towards the upper and / or lower surfaces of the component layer. The contacts may be connection pads or contact members. It will be appreciated that the number of contact members is variable, and, optionally, no contact members can be included in the flexible IC. Other surfaces of the flexible IC may also include one or more contact members, if desired. The contact members may be raised, recessed or substantially planar with the respective surface of the flexible IC.

[0094] The component layer 508 may include components of a plurality of flexible ICs such that the second polymer layer 504, the barrier layer 506 (if present), and component layer 508 form a flexible IC wafer that includes a plurality of flexible ICs. Lines 512 illustrate the division of the flexible IC wafer of Figure 5 into individual flexible ICs.

[0095] The component layer may comprise one or more layers of conductive materials. Conductive materials may be selected from one or more of the aforementioned conductive materials in relation to component layer of Figures 2 and 3.

[0096] At step S410, the second polymer layer 504 is separated from the first polymer layer 502. The separation of the second polymer layer 504 from the first polymer layer 502 and the picking and placement of the formed flexible ICs may take a variety of forms, a number of examples of which are described in more detailed below.

[0097] Figures 6 and 7 provide a schematic diagram of an individual flexible IC 50 that is formed on the wafer of flexible ICs shown in Figure 5 via the process of Figure 4, but where the flexible IC has been removed from the carrier 500 and the first polymer layer 502. The flexible IC 50 comprises the component layer 508, which may include an upper contact layer 510 or contacts 52; however, as described in more detail below, flexible ICs formed via the method of Figure 4 are not limited to have contacts on the upper surface of the flexible IC. The component layer is formed on the barrier layer 506 (if present), which in turn is formed on the second polymer layer 504.

[0098] The first and second polymer layers 502, 504 may be formed from the same material, different materials, or different types of a same material. The use of different materials or different types of a same material allows for increased control over the adhesion properties between the separable polymer layers and the manner of their separation.

[0099] For example, the first and second polymer layers 502, 504 may be formed from two different polyimides, where the polyimide of the first polymer layer 502 may have a higher co-efficient of thermal expansion (CTE) than that of the second polymer layer 504, or where the polyimide of the first polymer layer 502 may have a lower CTE than that of the second polymer layer 504. In this way, separation of the second polymer layer 504 from the first polymer layer 502 may be facilitated by using a thermal process, for example, by heating the underside of the carrier 500.

[0100] The first polymer layer 502 may be a UV transparent material and the second polymer layer 504 may be a UV absorptive material. In this way, separation of the polymer substrate layers may be facilitated by irradiating the underside of the rigid carrier 500 (when at least partially transparent) with a source of UV light (e.g. UV laser or UV lamp).

[0101] The first and second polymer layers 502, 504 may be formed from two materials that have different solubility properties. In this way, separation of the second polymer layer 504 from the first polymer layer 502 may be facilitated by exposing both layers to a solvent in which the first polymer layer 502 is soluble and the second polymer layer is not. By exposing both layers to such a solvent, the first polymer layer will dissolve, thus allowing the second polymer layer, and remaining architecture of the flexible IC wafer or flexible IC, to be separated from the carrier 500. For example, the first polymer layer 502 may be formed from a material that is soluble in halogenated solvents such as, for example, fluorinated solvents, whereas the second polymer layer may be formed of a material that is insoluble in halogenated solvents.

[0102] Although the first and second polymer layers 502, 504 have been referred to, this first example is not limited to the use of only two polymer layers, and two or more polymer layers may be used. For example, a third layer, formed from any of the aforementioned materials in relation to the first and second polymer, may be provided between the first and second polymer layers 502, 504 in order to provide particular adhesion and separation characteristics, where the third layer may be configured to separate from the first polymer layer 502 or the second polymer layer 504. Additionally or alternatively, an adhesive layer may be provided between the first and second polymer layers 502, 504. Additionally or alternatively, the first and second polymer layers 502, 504 may each be formed from one or more layers.

[0103] The first polymer layer 502 may be reused after the second polymer layer 504 has detached from the first polymer layer. For example, the first polymer layer 502 may be cleaned and, optionally, surface-treated and / or planarized so that it may act as a first polymer layer in a subsequent flexible IC wafer manufacturing process. Reusing the first polymer layer in this manner may reduce the quantity of polymer used in the manufacture of flexible ICs compared to conventional approaches (e.g. that of Figures 1 and 2), as well as reducing the environmental impact of flexible IC manufacture. Since the first polymer layer 502 is not included in the flexible IC wafer, the first polymer layer may alternatively be considered to form part of the carrier 500 upon which the flexible IC wafer is formed.

[0104] The second polymer layer 504 may have a thickness of below 20pm, such as below 15pm, or below 10pm. In particular, the second polymer layer 504 may have a thickness of between 5pm and above a minimum required or practical thickness. For example, the second polymer layer 504 may have a thickness of between 5pm and 0.01 pm, such as, for example, between 5pm and 0.015pm, between 4.5pm and 0.02pm, between 4pm and 0.025pm, between 3.5pm and 0.03pm, between 3pm and 0.035pm, or between 2pm and 0.04pm. The second polymer layer 504 may have a thickness of between 0.1 pm and 0.01 pmsuch as, for example, between 0.95pm and 0.015pm, between 0.9pm and 0.02pm, between 0.85pm and 0.025pm, between 0.8pm and 0.03pm, between 0.75pm and 0.035pm, between 0.7pm and 0.04pm, between 0.65pm and 0.045pm, or between 0.6pm and 0.05pm. The second polymer layer 504 may have a thickness of between 0.05pm and 0.001 pm such as, for example, between 0.045pm and 0.0015pm, between 0.04pm and 0.002pm, between 0.035pm and 0.0025pm, between 0.03pm and 0.003pm, between 0.025pm and 0.0035pm, between 0.02pm and 0.004pm, between 0.015pm and 0.0045pm, or between 0.01 pm and 0.005pm

[0105] Figure 7 shows a schematic of a reduced-substrate flexible IC 50. As shown in Figure 7, flexible IC 50 comprises a first horizontal surface 50-1 and a second horizontal surface 50-2 opposing the first surface 50-1. Flexible IC structure 50 further includes a barrier layer 506 and a reduced-thickness-substrate 504 (i.e. second polymer layer of Figures 5 and 6), which comprises first surface 50-1 of flexible IC 50 on its lowermost surface, contact members 51 . Through substrate vias 55 span across barrier layer 506 and reduced thickness substrate layer 504. Although the flexible IC 50 of Figure 7 is shown to comprise barrier layer 506, barrier layers are optional and may be omitted. The remaining architecture or component layer 508 of flexible IC 50, including one or more layers 508-0, 508-2, 508-4, is provided over the topmost surface of substrate 504. One or more layers 508-0, 508-2, 508-4 may comprise one or more layers of dielectric materials, or component layers. Topmost layer 508-0 of substrate architecture or component layer 508 comprises second surface 508-2 of flexible IC 50 on it topmost surface, which comprises contact members 52. One or more contact members 51 (herein, contact members may also be termed contacts, contact elements, contact portions, contact regions etc., as appropriate) may be included in or on flexible IC 50, being provided on the first surface 50-1. Additionally or alternatively, one or more contact members 52 may be included in or on flexible IC 50, being provided on the second surface 50-2.

[0106] One or more of contact members 51 , 52 may be used for coupling flexible IC 50 with one or more of: an external IC, an external circuit such as an application circuit, or any other external structure(s). For example, one or more of the contact members 51 , 52 may be for electrically coupling or mechanically coupling flexible IC 50 with an external or circuit. It will be appreciated that the number of contact members on the first surface 50-1 and on the second surface 50-2 is variable. Optionally, flexible IC 50 may not include contact members on the first and / or second surfaces 50-1 , 50-2. Alternatively, flexible IC 50 may not include any contact members. Other surfaces of the IC 50, further to the first surface 50- 1 and second surface 50-2, may include one or more contact members.

[0107] Conventional flexible ICs are approximately 20-30pm thick, with the polymer substrate accounting for approximately 90% of the overall thickness of a flexible IC. Substantially reducing the thickness of the polymer substrate can result in flexible ICs having an overall thickness of less than 10 pm, such as 3-9pm. Flexible ICs with a reduced- thickness polymer substrate may therefore be below the 5-10 pm threshold of human indentation stimuli and may therefore be imperceptible to human touch. Such thin flexible ICs could also be disposed within an adhesive layer of a product, structure, object, or anything else, rendering them substantially undetectable. The thinness of the polymer layer may also increase the transparency of a flexible IC and / or reduce any colouration compared to conventional flexible ICs.

[0108] Thinner flexible ICs may be more robust to stress-induced damage during bending, since there is a smaller difference in the radii of curvature between the layers. Considerations of a neutral axis may therefore become less relevant in the design and placement of flexible ICs.

[0109] Flexible ICs comprising a reduced thickness polymer substrate may have broad utility in applications where failure or damage of the flexible IC is required. For example, such flexible ICs may be placed across a designed failure feature, such as, for example, a seal on product packaging or a weak point in a structure. Damage to the flexible IC or the eventual inoperability of the flexible IC may then be used to indicate prior use or interference in applications where product integrity is desirable or required such as, for example, in tamper detection.

[0110] The manufacture of flexible ICs comprising a reduced thickness polymer substrate may be less material intensive, and thus reduce the environmental impact of flexible IC manufacture, since the amount of polymer required for substrate formation will be reduced, particularly if the first polymer layer may be reused.

[0111] Flexible ICs comprising a reduced thickness polymer substrate may provide for increased scope for the formation of contacts through the substrate layer due to the reduced thickness of the polymer substrate layer. This may result in more versatile flexible ICs having broader application than conventional flexible ICs.SUBSTRATELESS

[0112] Figure 8 provides a flow diagram for the manufacture of a substrateless flexible IC wafer, and Figure 9 provides a schematic diagram of a substrateless flexible IC wafer, which may result from the manufacturing process of Figure 8. Figures 10a, 10b, 11 and 12 provide schematic diagrams of an individual flexible IC of the manufactured flexible IC wafer illustrated in Figure 9.

[0113] In a substrateless flexible IC / IC wafer the flexible polymer substrate 202 of figures 2 and 3 is completely omitted, with a barrier layer being used to form a base layer upon which a flexible IC is formed, such that a substrateless flexible IC wafer and flexible IC is formed.

[0114] At step S702, a barrier layer 802 is deposited on the carrier 800. The carrier 800 may be of a similar form and material to a conventional flexible IC carrier. The carrier 800 may be a rigid carrier. The carrier 800 may be formed from glass, polycarbonate, quartz, silicon or any other suitable material. The barrier layer may be deposited using one or more of the aforementioned thin film processes and may comprise one or more layers of dielectric materials. The one or more layers of dielectric material may be formed from the same or different materials. The one or more layers of dielectric material may be formed using the same or different thin film processes and / or the same or different processing conditions. Dielectric materials may be selected from one or more of the aforementioned dielectric materials in relation to the optional barrier layer of Figures 2 and 3. The barrier layer may provide control over the transport of chemical elements in and out of the component layer of the flexible ICs. Chemical elements may include, for example, one or more of: metals, hydrogen oxygen, or any other chemical element.

[0115] The barrier layer 802 may be deposited directly onto the rigid carrier 800. Alternatively, a release layer may be provided on the rigid carrier 800 prior to the deposition of the barrier layer 802. Depositing the barrier layer 802 onto a release layer may facilitate improved control of the balance between robust attachment during manufacture, and facilitate detachment of the completed flexible IC wafer after manufacture. A release layer may be, for example, one or more of a thin-film adhesion layer or a polymer layer, such as any of the polymers set out above for the polymer substates. The release layer may also be formed from thin-film materials comprising one more metals selected from: Hafnium (Hf), Vanadium (V), Niobium (Nb), Tantalum (Ta), Chromium (Cr), Molybdenum (Mo), Titanium (Ti), or Tungsten (W), oxides thereof, and alloys thereof. I release layer may be formed from thin-film compounds, such as benzocyclobutene, azo compounds or any other suitable compound. A polymer layer on the rigid carrier may provide a ‘bed’ arranged to receive the barrier layer. The strength of adhesion between the barrier layer 802 and the release layer may be weaker than the strength of adhesion between the release layer and the rigid carrier 802. This facilitates separation of the barrier layer 802 from the carrier 800. Alternatively, the strength of adhesion between the barrier layer 802 and the component layer 804 may be weaker than the strength of adhesion between the barrier layer 802 and the release layer. This facilitates separation of the component layer 804 from the barrier layer 802. The strength of adhesion between the release layer and the barrier layer (if present) may alsobe altered in order to facilitate separation by exposing the release layer to particular conditions. Such release layer materials may be termed switchable materials. For example, the release material may be activated (i.e. its adhesion altered) by thermal, light, electrical, and / or shock effects, such as using azo compounds or an electrical shock. With respect to light-based release, metals or other materials that absorb light of a suitable wavelength and convert the light to heat may be suitable, with example metals including titanium, tungsten, aluminium, copper, gold, silver, iron, tin, zinc, cobalt, chromium, germanium, palladium, platinum, rhodium, manganese, nickel, silicon, tellurium, and also oxides, alloys and compounds thereof. Mixtures comprising 50% or more by weight of these metals may also be suitable. The release layer may for example have a thickness of 5nm to 300nm but is not limited to this range. It some examples, the coefficient of thermal expansion of the release layer is chosen to be similar to that of the carrier in order to reduce delamination during heating from light absorption.

[0116] At step S704, a component layer 804 is formed on the barrier layer 802, where the component layer includes the electronic components of the flexible ICs, including active, conducting, insulating, and contact components. The component layer may include one or more layers that are sequentially formed using any of the aforementioned thin film deposition and patterning processes or any other suitable fabrication process, where each layer may include elements of one or more active, conducting, insulating, and contact components. The component layer may also include a contact layer 806 that provides contacts for electrically and / or mechanically connecting the flexible ICs to external circuitry, such as, for example, an application item or any other external structure. The contact layer may be positioned at or towards the upper or lower surfaces of the component layer. The contacts may be connection pads or contact members. It will be appreciated that the number of contact members is variable, and, optionally, no contact members can be included in the flexible IC. Other surfaces of the flexible IC may also include one or more contact members, if desired. The contact members may be raised, recessed or substantially planar with the respective surface of the flexible IC.

[0117] The component layer 804 may include components of a plurality of flexible ICs such that the barrier layer 802 and component layer 804 forms a flexible IC wafer that includes a plurality of flexible ICs. Lines 808 illustrate the division of the flexible IC wafer of Figure 9 into individual flexible ICs.

[0118] The component layer may comprise one or more layers of conductive materials. Conductive materials may be selected from one or more of the aforementioned conductive materials in relation to component layer of Figures 2 and 3.

[0119] At step S706, the barrier layer 802 is separated from the carrier 800 with or without the use of a release layer. The separation of the barrier layer 802 from the carrier and the picking and placement of the formed flexible ICs may take a variety of forms, a number of examples of which are described in more detailed below. The resulting flexible IC structure is shown in Figures 10a and 11.

[0120] Alternatively at step S706, the component layer 804 (i.e. the lowest layer of the one or more component layers) may be separated from the barrier layer 802 such that the barrier layer 802 remains attached to the carrier 800 and the resulting flexible IC wafer and flexible ICs do not include the barrier layer, as shown in Figures 10b and 12. The separation of the component layer 804 from the barrier layer 802 and the picking and placement of the formed flexible ICs is described in more detailed below. This alternative approach may require the relative adhesive strengths of the component layer 804 to the barrier layer 802 and the barrier layer 802 to the carrier 800 to be appropriately controlled, so that the component layer 804 detaches from the barrier layer 802 rather than the barrier layer 802 detaching from the carrier 800. The relative adhesive strengths may be controlled via one or more intermediate layers or release layers between one or more of the carrier 800, barrier layer 802, and component layer 804. An intermediate layer or a release layer may be, for example, one or more of an adhesion layer, a polymer layer, or any other layer of suitable material described above.

[0121] Figures 10a, 10b, 11 and 12 provide schematic diagrams of flexible ICs that have been formed via the process of Figure 8. The flexible ICs in Figures 10a, 10b, 11 and 12 do not have a polymer substrate, with the barrier layer 802 acting as a form of support structure in Figure 10a and no form of additional support structure being provided for the component layer in Figure 10b. The barrier layer may also be present whilst not acting as a support structure, for example, only limited to provide a surface that has properties required for formation of the component layer.

[0122] The barrier layer 802 may have a thickness between 5pm and 0.001 m, such as, for example, between 5pm and 0.0015pm, between 4.5pm and 0.002pm, between 4pm and 0.0025pm, between 3.5pm and 0.003pm, between 3pm and 0.0035pm, or between 2pm and 0.004pm. The barrier layer 802 may have a thickness of between 0.1 pm and 0.001 pm such as, for example, between 0.95pm and 0.0015pm, between 0.9pm and 0.002pm, between 0.85pm and 0.0025pm, between 0.8pm and 0.003pm, between 0.75pm and 0.0035pm, between 0.7pm and 0.004pm, between 0.65pm and 0.0045pm, or between 0.6pm and 0.005pm. The barrier layer 802 may have a thickness of between 0.05pm and 0.001 pm such as, for example, between 0.045pm and 0.0015pm, between 0.04pm and 0.002pm, between 0.035pm and 0.0025pm, between 0.03pm and 0.003pm, between0.025pm and 0.0035pm, between 0.02pm and 0.004pm, between 0.015pm and 0.0045pm, or between 0.01 pm and 0.005pm. However, the thickness of the barrier layer 802 is not limited to this, and may be chosen depending on the functional properties required for the barrier layer.

[0123] The barrier layer 802 may remain attached to the carrier or to the flexible IC wafer (i.e. component layer 804), once the flexible IC wafer has been separated from the carrier 800. In the case of a barrier layer formed from multiple depositions or multiple layers (e.g. a composite thin film), one or more constituent layers or depositions of the barrier layer, or barrier sub-layers, may remain attached to the carrier and / or to the flexible IC wafer when they are separated. Barrier layer constituents or barrier sub-layers that remain attached to the flexible IC wafer may serve as ‘backside encapsulation’ for the flexible ICs, thus providing an element of protection to the flexible ICs.

[0124] Figure 11 shows a schematic of a substrateless flexible IC 80 that includes a barrier layer. As shown in Figure 11 , flexible IC 80 comprises a first horizontal surface 80-1 and a second horizontal surface 80-2 opposing the first surface 80-1. Flexible IC structure 80 further includes a barrier layer 802, which comprises first surface 80-1 of IC 80 on its lowermost surface, and includes contact members 81 and vias 85. The remaining architecture 804 of flexible IC 80, including one or more layers 804-0, 804-2, 804-4, is provided over the topmost surface of barrier layer 802. One or more layers 804-0, 804-2, 804-4 may comprise one or more layers of dielectric materials, or component layers. Topmost layer 804-0 of flexible IC architecture or component layer 804 comprises second surface 80-2 of flexible IC 80 on its topmost surface, which comprises contact members 82. One or more contact members 81 (herein, contact members may also be termed contacts, contact elements, contact portions, contact regions etc., as appropriate) may be included in or on flexible IC 80, being provided on the first surface 80-1. Additionally or alternatively, one or more contact members 82 may be included in or on flexible IC 80, being provided on the second surface 80-2.

[0125] Figure 12 shows a schematic of a substrateless flexible IC 80’ that does not include a barrier layer. As shown in Figure 12, flexible IC 80’ is comprises a first horizontal surface 8O’-1 and a second horizontal surface 8O’-2 opposing the first surface 8O’-1. IC structure 80’ does not include either a barrier layer or a substrate. The architecture 804’ of flexible IC 80’, including one or more layers 804’-0, 8O4’-2, 8O4’-4. One or more layers 804’- 0, 8O4’-2, 8O4’-4 may comprise one or more layers of dielectric materials, or component layers. Lowermost layer 8O4’-4 of architecture 804’ comprises first surface 8O’-1 of flexible IC 80’ on its lowermost surface, which comprises contact members 8T. Topmost layer 804’- 0 of substrate architecture 804’ comprises second surface 8O’-2 of flexible IC 80’ on ittopmost surface, which comprises contact members 82’. One or more contact members 81’ (herein, contact members may also be termed contacts, contact elements, contact portions, contact regions etc., as appropriate) may be included in or on flexible IC 80’, being provided on the first surface 8O’-1 . Additionally or alternatively, one or more contact members 82’ may be included in or on flexible IC 80’, being provided on the second surface 8O’-2.

[0126] One or more of contact members 81 , 81’, 82, 82’ may be used for coupling flexible IC 80, 80’ with one or more of: an external IC, an external circuit such as an application circuit, or any other external structure(s). For example, one or more of the contact members 81 , 81’, 82, 82’ may be for electrically coupling or mechanically coupling flexible IC 80, 80’ with an external or circuit. It will be appreciated that the number of contact members on the first surface 80-1 , 8O’-1 and on the second surface 80-1 , 8O’-1 is variable. Optionally, flexible IC 80, 80’ may not include contact members on the first and / or second surfaces 80-1 , 8O’-1 , 80-2, 8O’-2. Alternatively, flexible IC 80, 80’ may not include any contact members. Other surfaces of the flexible IC 80, 80’, further to the first surface 80-1 , 8O’-1and second surface 80-2, 8O’-2, may include one or more contact members.

[0127] In an alternative approach, a substrateless flexible IC 80’ may be manufactured using the "Mount silicon first" approach, where components of flexible IC 80’ may be temporarily adhered to carrier 800, before the components are coated and patterned with a layer of dielectric material. A metal layer may be deposited over the dielectric, which may connect the components with one or more subsequent active and / or passive layers. Thereafter, a redistribution layer (RDL) is provided, the wafers are diced, detached from the carrier and subsequently attached to an external circuit such as, for example, a printed circuit board (PCB) or any other external structure.METHOD FOR DIE STACKING

[0128] In an example, there is a provided a method for forming a stacked IC structure. Methods of manufacturing, providing or forming arrangements of stacked IC structures may be referred to as die-level stacking and the resulting structure a stacked electronic structure.

[0129] Die-level stacking generally assumes (although it should not be constrained to) two or more vertically stacked IC dies, which optionally have vertical conductive inter-IC connections.

[0130] ICs, flexible ICs, and / or stacked IC structures (comprising two or more of: ICs or flexible ICs, for example) may be assembled and attached (e.g., mechanically, capacitively, inductively coupled or coupled in any other suitable manner) to each other, and to externalcircuits, in any appropriate assembly technology. Examples include, but are not limited to the following:• Die-by-die pick and place, such as those used to assemble many surface-mounted electronic systems.• Techniques similar to those used, or considered for use, in microLED display assembly, such as (but not limited to): o mass transfer pick and place; o fluidic assembly, in which components are suspended in a fluid that is flowed across a surface, the components being captured by trap structures on the surface; o elastomer stamping, in which dispersed arrays of components are picked from a densely packed source carrier and transferred to a product substrate; and o photo-mechanical actuation, in which selective transfer from an array of components is optically controlled.• Roller-transfer, in which arrays of components are transferred, with an optional reduction in density from a source carrier, onto a product substrate.

[0131] Figure 13 provides method for manufacturing or forming a stacked IC structure using a direct-die attach approach in accordance with the present disclosure, where at least one of the ICs is a flexible IC. For example, one or both of the ICs are flexible ICs. This method can avoid the use of further additional carriers further to the carrier upon which the flexible IC wafers are manufactured (i.e. carriers 200, 500, 800 of Figures 2, 5, and 9 respectively). Figures 14A and 14B show a schematic of a stacked IC arrangement formed in accordance with the approaches discussed in relation to Figure 13.

[0132] Figure 14A shows a stacked IC structure 70 comprising a first IC 100 and a second IC 700, where at least one of the first and second ICs 100 and 700 is a flexible IC. The first IC 100 comprises a first surface 101 , a second surface 103, contact members 120 and via 750. The second IC 700 comprises a first surface 701 , a second surface 703, contact members 710 and via 750. The second IC 700 is stacked on top of the first IC 100.

[0133] Figure 14B shows a stacked IC structure comprising first IC 100, second IC 700 and third IC 300 where at least one of the first, second, and third ICs 100, 700 and 300 is a flexible IC. The features of first IC 100 in Figure 14B correspond to those of 14A. The second IC 700 comprises a first surface 701 , a second surface 703, contact members 710, via 750and capacitive place 360. The third IC 300 comprises a first surface 301 , a second surface 303, contact members 310 and capacitive plate 360.

[0134] Assembly of a stacked IC structure may comprise: manufacturing or forming the lower IC (e.g., first IC 100), mechanically coupling a (first) upper IC (e.g., second IC 700) to an upper surface of the lower IC, making electrical interconnections through conductive capacitive or inductive coupling between the upper and lower ICs, if required; detaching the lower IC (i.e. separating the stacked IC structure) from the carrier (if applicable); and, optionally, attaching the lower IC’s under-side contacts to an external circuit. Alternatively, contacts of the upper surface of the upper IC may be attached to an external circuit. Further discussion of example methods of providing, assembling, manufacturing and / or forming a stacked IC are provided below.

[0135] As such, the present disclosure provides a system of complementary ICs (each of which may be a flexible IC) that are conveniently and vertically interconnected to form a stacked IC structure.

[0136] In an example, there is provided a method for forming an electronic structure, the method comprising: providing a first integrated circuit (IC) on a carrier, the first IC having a first surface and a second surface; wherein the first IC is a flexible IC, and the first surface of the first IC is proximal to an upper surface of the carrier and the second surface of the first IC opposing the first surface of the first IC; and contacting a second IC with the first IC and mechanically coupling the second IC with the first IC, wherein at least a portion of a first surface of the second IC is arranged to contact at least a portion of the second surface of the first IC, and wherein the second IC has a second surface opposing the first surface of the second IC; and separating the first IC from the carrier.

[0137] Wherein the step of providing the first IC on a carrier comprises manufacturing or forming a flexible IC on the carrier. Optionally, the step of manufacturing or forming the flexible IC on the carrier may be in accordance with the approaches described with respect to Figures 1 , 4 and 8. Optionally, the step of manufacturing or forming the flexible IC on the carrier may be in accordance with the approaches described with respect to Figures 1 , 4 and 8 up to but not including the step of detaching the flexible ICs or flexible IC wafers from the carrier (i.e. does not include steps S106, S410, or S706). Alternatively, providing the first IC on the carrier may refer to providing a manufactured IC onto a secondary carrier (i.e. one different to the one upon which it was manufactured) such as a tape for example, and the second IC is contacted with the first IC whilst the first IC is on the secondary carrier.

[0138] Referring to Figure 13, at step S1400, a first integrated circuit (IC) (214) is provided on a carrier, the first IC having a first surface 20-1 and a second surface 20-2; wherein the first IC is a flexible IC, and the first surface 20-1 of the first IC is proximal to an upper surface of the carrier and the second surface 20-2 of the first IC opposing the first surface of the first IC. Optionally, wherein the step of providing the first IC on the carrier comprises manufacturing or forming a flexible IC on the carrier. For example, a flexible IC wafer is formed or manufactured on a carrier in accordance with the approaches described with respect to Figures 1 , 4, and 8 up to but including the step of detaching the flexible ICs or flexible IC wafers from the carrier (i.e. does not include steps S106, S410, or S706 respectively).

[0139] For example, step S1400 may comprise the steps of depositing a polymer layer 202 on the carrier 200; and forming a component layer 206 on the polymer layer 202. Optionally, further comprising the step of forming a barrier layer on the polymer layer prior to forming the component layer.

[0140] For example, step S1400 may comprise the steps of depositing a first polymer layer 502 on the carrier; depositing a second polymer layer 504 on the first polymer layer, wherein the second polymer layer comprises the first surface of the first IC; and forming a component layer on the second polymer layer 504. Optionally, further comprising the step of forming a barrier layer on the second polymer layer prior to forming the component layer.

[0141] For example, step 1400 may comprise the steps of depositing a barrier layer 802 on the carrier 800; and forming a component layer 804 on the barrier layer 802.

[0142] At step S1402 the flexible IC wafer may be diced whilst still attached to the carrier in order to singulate the flexible IC dies. For example, when a plurality of ICs are formed on the flexile IC wafer, the method includes singulating the wafer to form the first IC 100. This dicing / singulation may be performed via laser ablation, mechanical sawing or any other suitable dicing method. Although Figure 13 shows the step of singulating the flexible IC dies being performed after formation of the flexible IC wafer, the singulation may be performed at an earlier stage, such as before or during formation of the component layer. Alternatively, singulation may performed before or after any of the steps of Figure 13 and / or the singulation processes divided such that different stages of the singulation process are performed at different times i.e. before or after different steps of Figure 13.

[0143] At step S1404, a second IC or an external IC structure is brought into contact with the first IC and the second IC or the external IC structure is mechanically coupled to the first IC, wherein at least a portion of a first surface of the second IC or the external IC structure is arranged to contact at least a portion of the second surface of the first IC. Wherein the second IC or the external IC structure has a second surface opposing the first surface of thesecond IC or the external IC structure. For example, an external IC structure is brought into contact with the intended singulated flexible IC die and the intended flexible IC die is mechanically coupled to the external IC structure and, if appropriate, electrical interconnections are formed between the external IC structure and singulated flexible IC die. These electrical interconnections (i.e. couplings) may be conductive, capacitive, and / or inductive.

[0144] An external IC structure or a second IC may be an IC, a rigid IC, a flexible IC, or an existing stacked IC structure. A stacked IC structure may comprise one or more of: a rigid IC, a flexible IC, or a combination thereof. A stacked IC structure may comprise one or more of: a rigid IC, a flexible IC, a reduced-substrate flexible IC, a substrateless flexible IC, or a combination thereof. The external IC structure may be a flexible IC formed or manufactured in accordance with the approaches according to one or more of Figures 1 , 4, and 8, and provided on a separate carrier, such that the surface of flexible IC that is in contact with the carrier is opposite to the surface that is brought into contact with the singulated flexible IC. An external IC structure or a second IC may be a silicon IC, a flexible IC, a display device, a light emitting diode (LED), an LED circuit or LED driver, a microLED, a microLED circuit or microLED driver, an organic light-emitting diode (OLED), an OLED circuit or an OLED driver, a photovoltaic (PV) cell, or a PV device or PV circuit, a capacitor, a capacitor circuit or capacitor driver, a super-capacitor, a super-capacitor circuit or super-capacitor driver, or piezoelectric actuator.

[0145] The singulated flexible IC die may be one or more of: a flexible IC, a reduced- substrate flexible IC, or a substrateless flexible IC.

[0146] Referring to Figure 14A, where first IC 100 corresponds to the singulated flexible IC, and the second IC 700 corresponds to the external IC structure, the first IC 100 may comprise if required, on the first surface 101 , at least one contact member 110 arranged to operably interface with an external circuit (not shown). For example, the first surface 101 may comprise a surface of a metal layer of the first IC 100. Part of this surface of the metal layer may correspond to the at least one contact member 110 for operably interfacing with the external circuit. Additionally or alternatively, at least one contact member 110 arranged to operably interface with the external circuit may be provided as a via through the substrate in the first IC 100. This may be achieved before, after or at the time of the second IC 700 being coupled to the first IC 100. The first IC 100 may be coupled to said external circuit via the at least one contact member 110.

[0147] Furthermore, the at least one contact member 110 may be connected with a via 750 through the IC 100; i.e., a via 750 extending to the second surface 103. The via 750 may be electrically connected to the second IC 700, thereby electrically connecting theexternal circuit with the second IC 700. In further examples, the via 750 may also be electrically connected to one or more active or passive components included in the first IC 100; alternatively, the via 750 may be electrically isolated from other components of the first IC 100.

[0148] Similarly, in some examples the second IC 700 may comprise, on the second surface 703 (assuming coupling with the first IC 100 will occur at the first surface 701 of the second IC 700) at least one contact member 720 arranged to operably interface with another external circuit (or a further stacked IC , as discussed later), or at least one contact member provided as a via and arranged to operably interface with another external circuit.

[0149] .

[0150] Mechanical coupling between the singulated flexible IC and the external IC structure (i.e. between the first IC and the second IC, and if present, a third or further IC) may be performed using any suitable materials and methods for mechanical coupling, and the first IC may be separated from the carrier before or after the second IC is mechanically coupled to the first IC. Mechanical coupling may be performed, for example, by applying an adhesive to at least a portion of one, or each, of the surfaces of the flexible IC die and the external IC structure which come into contact with one another. For example, an adhesive may be applied to the respective contacts of the singulated flexible IC die and / or the external IC structure. For example, a conductive adhesive (such as an anisotropic adhesive or anisotropic conductive adhesive (ASA)) may be applied to the respective contacts of the singulated flexible IC die and / or the external IC structure. For example, an adhesive (conductive or non-conductive) and / or a polymer layer may be applied (i.e. patterned or deposited) to other areas of the singulated flexible IC die and / or the external IC structure in addition to or as an alternative to application to the contacts, to provide mechanical and / or electrical coupling. For example, an adhesive and / or a polymer layer may be applied to the respective contacts, and other areas of the singulated flexible IC die and / or the external IC structure. By mechanically coupling the external IC structure to the singulated flexible IC before removing the singulated flexible IC from the carrier or from a substrate, if present (for example, if already removed from the carrier), the external IC structure may provide mechanical support to the singulated flexible IC.

[0151] For example, mechanical coupling may be achieved by a variety of methods. Referring to Figure 14A, where first IC 100 corresponds to the singulated flexible IC, and the second IC 700 corresponds to the external IC structure. The first IC 100 may be mechanically coupled to the second IC 700 around at least one of the one or more contact members 120, 710. For instance, at least one of the contact members 120 of the first IC 100 may be mechanically coupled to at least one of the contact members 710 of the second IC700. This may be achieved through the provision of an adhesive between the first and second ICs 100, 700, including between the at least one of the contact members 120 of the first IC 100 and the corresponding at least one of the contact members 710 of the second IC 700, such that the respective contact members 120, 710 are mechanically coupled via the adhesive (indirect contact).

[0152] Referring to Figure 14A, mechanical coupling of the first IC 100 and the second IC 700 may be performed by applying an adhesive between or along the surfaces of the contact members 120, 710, and / or across one or more of a second surface 103 of the first IC 100 and / or a first surface 701 of the second IC 700, so as to adhere the first IC 100 to the second IC 700 in small areas at high resolution. In such a case, mechanical coupling is therefore via the adhesive.

[0153] For example, for attachment of an external IC structure, anisotropic conductive adhesive (ACA) may be lithographically defined or otherwise patterned across the surface of the singulated flexible IC in small areas at high resolution. By appropriately specifying the size, distribution, and gaps between these areas, the singulated IC and external IC structure may be attached or mechanically coupled with relaxed accuracy on alignments.

[0154] The first IC 100 and the second IC 700 may be mechanically coupled at a point other than at the contact members. For example, the second surface 103 of the first IC 100 may be mechanically coupled to the first surface 701 of the second IC 700, where said coupling occurs at a region of the second surface 103 of the first IC 100 other than where contact members 120 are located and / or at a region of the first surface 701 of the second IC 700 other than that where the contact members 710 are located.

[0155] The mechanical coupling between first the singulated flexible IC die and the external IC structure may be applied between one or more of: the respective contact members of the first IC 100 and the second IC 700, or between other regions of the second surface 103 of the first IC 100 and respective other regions of the first surface 701 of the second IC 700. Of course, other methods of mechanically coupling the singulated flexible IC die and the external IC structure are available, as would be understood by the skilled person.

[0156] The singulated flexible IC and external IC structure may be further coupled via electrical coupling, including conductive coupling, capacitive coupling, inductive coupling, or a combination thereof . The electrical coupling may be achieved as part of the mechanical coupling step, a separate step, and / or by virtue of capacitive and / or inductive coupling structures in the ICs.

[0157] For example, the singulated flexible IC die and the external IC structure may be electrically coupled. Referring to Figure 14A where first I C 100 corresponds to the singulatedflexible IC, and the second IC 700 corresponds to the external IC structure. Electrical coupling may be provided by the one or more contact members 120 of the first IC 100 and the one or more contact members 710 of the second IC 700. It will therefore be appreciated that the one or more contact members 120, 710 may be conductive. Contact between corresponding contact members on the first IC 100 and the second IC 700 may provide the electrical coupling, where this may be by direct contact between the contact members or indirect contact between the contact members (for example, where an anisotropic conductive adhesive is provided between the contact members and allows for current to flow between the contact members).

[0158] For example, the singulated flexible IC die and the external IC structure may be capacitively coupled. Referring to Figure 14A where first IC 100 corresponds to the singulated flexible IC, and the second IC 700 corresponds to the external IC structure. The first and second ICs 100, 700 may be capacitively coupled. This may be achieved through the inclusion of a capacitive plate (a first capacitive plate) in or on the first IC 100 and the inclusion of a capacitive plate (a second capacitive plate) in or on the second IC 700. The first capacitive plate and the second capacitive plate may be arranged within their respective IC to capacitively couple with one another, once the first IC 100 and the second IC 700 are stacked. The first capacitive plate and / or the second capacitive plate may be located close to (i.e. proximal to) the requisite surface of the corresponding IC; for example, beneath an insulating layer or a dielectric layer.

[0159] Where the ICs in the resulting stacked IC structure are capacitively coupled, signals and / or power is transferred between relevant individual ICs via capacitive coupling between the respective capacitive plates in or on each of the ICs. Such use of capacitive coupling may simplify assembly, since the use of conductive adhesive, or any of means of forming conductive interconnections between the singulated flexible IC and the external IC structure may not be required.

[0160] Figure 14B illustrates the inclusion of capacitive plates capacitively coupling two ICs. Second IC 700 includes a first capacitive plate 760 where an insulating layer and / or a dielectric layer is provided between the first capacitive plate and the second surface 703 of the second IC 700, and a second capacitive plate 360 is included in the third IC 300, where an insulating layer and / or a dielectric layer may be provided between the second capacitive plate and the first surface 301 of third IC 300. With the third IC 300 stacked on the second IC 700, the first capacitive plate 260 and the second capacitive plate 360 are capacitively coupled, thereby establishing electrical interconnections between the second and third ICs 700, 300. Although Figure 14B does not show a capacitive plate provided in first IC 100 and / or capacitive coupling between first IC 100 and second IC 700, this should not beconstrued as limiting and capacitive coupling may be provided anywhere in a stacked IC structure, as appropriate. Furthermore, capacitive coupling is also not limited to being implemented in a stacked IC structure including three ICs but may be implemented when there are two or more ICs in the stacked IC structure.

[0161] Combinations of mechanical, conductive, capacitive, or inductive coupling as described above may be implemented. Figure 14B, for example, illustrates both capacitive coupling and electrical coupling between respective contact members.

[0162] Figure 14A, shows an example of a stacked IC structure which includes a combination of mechanical and electrical coupling between two ICs within the stack. The first IC 100 and the second IC 700 may be mechanically and electrically coupled through (or at the sites of) the respective contact members 120, 710. Additionally or alternatively, one of the mechanical coupling and the electrical coupling may be provided / achieved through the respective contact members 120, 710 while the other one of the mechanical coupling and the electrical coupling may be provided / achieved through some other means. The term contact member may refer to structures intended to provide some form of coupling between the ICs and / or other external items, where the coupling may include mechanical, conductive, capacitive, and / or inductive. Whilst the contact members are shown as provided on their respective surfaces, the contact members may be level with or below the respective surfaces, such that the contact members are proximal to the surfaces. For example, if the contact members are intended to provide capacitive and / or inductive coupling (i.e. the contact members are capacitive plates or inductors), mechanical contact between the contact members of the ICs may not be required. Furthermore, as described with respect to Figure 14B, the ICs may have a mix of contact members that are provided on or proximal to surfaces of the ICs.

[0163] Figure 14B shows an example of a stacked IC structure which includes, at least, a combination of electrical and capacitive coupling between two ICs within the stack. The first IC 100 may comprise at least one contact member 120 at the second surface 103, and the second IC 700 may comprise at least one contact member 710 at the first surface 701 ; wherein at least one of the contact member(s) 120 provided at the second surface 103 of the first IC 100 is configured to electrically couple to at least one of the contact member(s) 710 provided at the first surface 701 of the second IC 700. Additionally, the first IC 100 may include a first capacitive plate (not shown), where an insulating layer and / or a dielectric layer is provided between the first capacitive plate and the second surface 103; and the second IC 700 may include a second capacitive plate, where an insulating layer and / or a dielectric layer is provided between the second capacitive plate and the first surface 701 ; wherein thefirst capacitive plate and the second capacitive plate are capacitively coupled with one another.

[0164] In another example, referring to Figures 14A and 14B, two or more of the ICs 100, 300, 700 may be inductively coupled in order to provide for the transmission of power and / or data between the ICs. For example, a planar inductor may be included in each the ICs to be coupled, where the planar inductors are positioned close to (i.e. proximal to) the opposing surfaces of the ICs and appropriately configured for inductive transmissions between each other. For instance with respect to Figure 14B, the inductors may be provided in similar positions to the capacitive plates 760 and 260 when the ICs 300 and 700 are to be inductively coupled. Although pairs of planar inductors are considered here, this is merely an example configuration and any suitable arrangement of inductors suitable for the inductive transmission of power and / or data between ICs may be used.

[0165] With respect to both capacitive and inductive coupling, the corresponding plates and inductors may be specifically configured for operation with one another. Alternatively, plates and inductors may be configured to operate with a range of different configurations thus allowing a wider range of different ICs to be “paired” in the stacked IC structure.

[0166] The second IC 700 (external IC structure) may have been formed on a carrier in a similar manner to that discussed above in relation to the first IC 100 (singulated flexible IC). For example, the second IC 700 may be formed on a carrier, and a surface of the substrate contacting the surface of the carrier corresponds to the first surface 701 of the second IC 700. The second IC 700 may then be removed from the carrier.

[0167] The second IC 700 may then be mechanically coupled to a first IC 100. Here, the first IC 100 may be attached to the carrier when the second IC 700 is mechanically coupled with the first IC 100. For example, self-adhesive ICs (such as illustrated in Figure 19) may be applied to one another to form a stacked IC, where an individual self-adhesive IC corresponds to an embodiment.

[0168] At step S1406, detachment of the singulated flexible IC die from the carrier (i.e. separation of the stacked electronic structure from the carrier) is performed. The detachment may comprise peel release achieved by withdrawing the external IC structure from the carrier, such that the flexible substrate layer of the singulated flexible IC ultimately detach from the carrier in accordance with the approaches described with respect to steps S106, S410, and S706 of Figures 1 , 4, and 8 respectively, as appropriate. For example, detachment of the stacked electronic structure may be achieved by detaching the second polymer 504 layer from the first polymer layer 502 to separate the first IC from the first polymer layer 502 and the carrier 500. In another example, the component layer 804 of the first IC may be detached from the barrier layer 802. In another example, the barrier layer802 may be detached from the carrier 800 or the first polymer layer 502. In another example, a release layer may be disposed between the carrier and the first surface of the first IC for aiding separation of the first IC (and thus the stacked electronic structure) from the carrier, and the surface adjacent to the release layer detached from the carrier. The detachment may be assisted by laser ablation. Alternatively, a laser may be used to impart momentum to the flexible IC die towards the external IC structure, using a LIFT (light-induced forward transfer) methodology. Laser assisted release may be used for flexible IC dies on a glass, or an otherwise transparent or translucent carrier.

[0169] The detachment step of S1406 (e.g. peel release) may be performed under fluid, for example a fluoropolymer, which may provide protection during peeling without adhering to the underside of the singulated flexible IC. Any of the other suitable detachment processes may also be performed whilst the IC, IC wafer and / or carrier is at least partially submerged in a fluid.

[0170] Considering an example where the first IC 100 in the stacked arrangement does not include a substrate: the first IC 100 may be manufactured to include a release interface or release layer between a substrate and component layer; the second IC 700 may then be attached to the first IC 100 in a number of ways (note these are non-limiting examples, the skilled person would understand other ways may be used):• A process in which the second IC 700 is attached to the first IC 100 whilst the latter is still on the substrate on the carrier 10; subsequent withdrawal of the second IC 700 releases the first IC 100 from its substrate.• A process in which the first IC 100 is laminated onto an intermediate carrier, withdrawal of which separates the first IC 100 from its substrate. This approach is compatible with transfer of ICs from a carrier 10 onto a release tape, wafer frame or other temporary support that provides a convenient route for subsequent attachment to an upper IC.

[0171] The approaches for detachment of the stacked IC structure described above are examples only and any appropriate method may be used. Furthermore, detachment of the stacked IC structure from a carrier may refer to a carrier on which the first IC was manufactured or a carrier on which the first IC has been provided after manufacture.

[0172] Any of the approaches for die stacking set out above may be applied to the stacked IC structures described below.STACKED ICS

[0173] Figures 14A and 14B show a schematic of a stacked IC structure formed or manufactured in accordance with the approaches discussed in relation to Figure 13.

[0174] Figure 14A shows a stacked IC structure 70 comprising a first IC 100 and a second IC 700. In an example, the second IC 700 may be in contact with the first IC 100. Said contact may be direct such as, for example, where at least part of the second surface 103 of the first IC 100 may be in contact with at least part of a first surface 701 of the second IC 700. Said contact may be indirect such as, for example, where one or more materials, layers of materials, components, elements or further ICs are provided between the first and second ICs 100, 700 in a larger IC stack. In a stacked IC structure, the individual ICs may provide a degree of mechanical and / or structural support to one another.

[0175] One, or both, of the first IC 100 and the second IC 700 may be rigid or flexible IC. One, or both, of the first IC 100 and the second IC 700 may be a flexible IC. One, or both, of the first IC 100 and the second IC 700 may be a flexible IC formed or manufactured in accordance with approaches set out in relation to one or more of Figures 1 , 4, and 8. One of the first IC 100 or the second IC 700 may be a rigid IC. For example, the second IC 700 may be a rigid IC. One or more of the on-carrier (i.e. a ‘lower IC’; such as the first IC 100) and, where appropriate, the stacked IC (i.e. an ‘upper IC’, such as the second IC 700) may be: a flexible IC, a reduced-substrate flexible IC, or a substrateless flexible IC, or a combination thereof. In some examples, the upper IC may also be a flexible IC such as, for example, a thin film flexible IC, or a flexible IC having a thinned silicon substrate. Alternatively, the upper IC may be a rigid IC or chip.

[0176] Various example features of a lower IC (e.g., first IC 100) are discussed above in relation to flexible ICs 214, 50, 80, 80’ and the approaches in Figures 1 to 12 (although these should not be seen as limiting). Where the upper IC is a flexible IC, various example features of an upper IC (e.g. second IC 700) are discussed above in relation to flexible ICs 214, 50, 80, 80’ and the approaches in Figures 1 to 12 (although these should not be seen as limiting).

[0177] An upper IC (e.g second IC 700) may: be fully-formed, optionally without packaging (e.g., provided as a bare die or chip-scale package); be flexible or rigid; extend the capabilities of a lower flexible IC (e.g., first IC 100) beyond what is possible using known IC manufacture processes for flexible ICs (e.g., provide an overall: p-channel metal-oxide- semiconductor (PMOS) IC, a memory chip, an LED, a sensor, or any other capabilities not possible for individual flexible ICs alone); have similar capabilities to a lower flexible IC, but execution in the stacked arrangement enables a higher yield than if the combined functionalities were provided in a single flexible IC (e.g., due to shorted distances between circuit blocks and or lower fabrication complexity

[0178] The first IC 100 may be of a size which is smaller than, larger, than or equal to a size of the second IC 700. For example, the size (length and / or width) of a first surface 101 of the first IC 100 and / or the size of a second surface 103 of the first IC 100, opposing the first surface 101 , may be smaller than or equal to the size of a first surface 701 of the second IC 700 and / or smaller than or equal to the size of a second surface 703 of the second IC 700, opposing the first surface 701. For instance, a footprint of the second surface 103 of the first IC 100 may be smaller than a footprint of the first surface 701 of the second IC 700.

[0179] One or more of the first IC 100 or the second IC 700 may have an irregular shape or non-rectangular shape.

[0180] One or more contact members 120 / 710 may be included in / on the first IC 100 / second IC 700. For example, as shown in Figure 14A, two contact members 120 are shown on a second surface 103 of the first IC 100. At least one of these contact members 120 may be in contact (e.g., directly or indirectly) with one or more contact members 710 included in / on the second IC 700. In the example of Figure 14A, two contact members 710 are shown on a first surface 701 of the second IC 700. The contact members 120 of the first IC 100 may be in contact with the contact members 710 of the second IC 700. Referring to the above-mentioned relationship with reference to Figures 3, 7, 11 and 12, it will be appreciated that contact members 120 may correspond to contact members 22, 52, 80 and 80’, while contact members 710 may correspond to contact members 21 , 51 , 81 and 8T. Further, the first surface 20-1 , 50-1 , 80-1 , 8O’-1 and the second surface 20-2, 50-2, 80-2, 8O’-2 of the flexible ICs 214, 50, 80, and 80’ respectively, illustrated in Figures 3, 7, 11 and 12 correspond with the first surfaces 101 , 701 and second surfaces 103, 703 of the first and second IC 100, 700.

[0181] Although the contact members of the stacked IC structure of Figure 14A are shown to be raised portions on the surface of the ICs, the contact member(s) may also be substantially planar with the rest of the surface of the relevant IC. For example, contact members 120 could be planar with the remainder of the second surface 103, such that the second surface 103 is substantially flat with the contact members 120 being two conductive portions (such as those formed of a metal or graphite) on the second surface 103 of the first IC 100.

[0182] The first IC 100 may not include contact members on either the second surface 103, the first surface 101 or on any / all other surface(s). Additionally or alternatively, it will be appreciated that the second IC 700 may not include contact members on either the second surface 703, the first surface 701 and / or on any other surface(s). For example, the second surface 103 of the first IC 100 (or a portion thereof) and the first surface 701 of the secondIC 700 (or a portion thereof) may be in contact with one another, without contact members present or intervening.

[0183] Furthermore, one or more of the stacked ICs may include at least one via. For example, a via 750 (such as a through-substrate via, if a substrate is included, and may have similarity to via 25 in Figure 3) may pass through the first IC 100 from the first surface 101 to the second surface 103 (through the substrate, if present). The via 750 may electrically connect to a contact member 120 on the second surface 103, such as, for example, this contact member 120 may be regarded as a part of the via 750 arranged at the second surface 103, or may be separate from the via 750. The via 750 may electrically connect to a contact member 110 on the first surface 101 , where this contact member 110 may be regarded as a part of the via 750 arranged at the first surface 101 or separate from the via 750. Accordingly, through the via 750, an electrical connection may be made between a first external structure below the first surface 101 (e.g., an external circuit or another IC arranged to make an electrical connection with the via 750 at the first surface 101) and a second external structure stacked on top of the first IC 100 (e.g., a second IC 700 arranged to make an electrical connection with the via 750 at the second surface 103).

[0184] According to certain embodiments of the present disclosure, one or more additional ICs may be stacked on the second IC 700.

[0185] Fig 14B illustrates an example in which a third IC 900 is stacked on a second IC 700 which itself is stacked on a first IC 100 (for example, in accordance with any of the examples described above). The third IC 300 may have a first surface 301 and a second surface 303 opposing the first surface 301. The first surface 301 or one or more contact element 310 disposed on or included in the first surface 301 may be in contact with a second surface 703 of the second IC 700 or one or more contact element 720 disposed on or included in the second surface 703. Referring to Figure 13 and Figure 14B, the method of Figure 13 may example comprise a further step of providing a third IC on a second IC prior to step 1406. For example, the method may further include providing a third IC 300 on the second IC 700, wherein a first surface 301 of the third IC 300 is configured to contact the second surface 703 of the second IC 700; and mechanically coupling the third IC 300 with the second IC 700. In some examples, the third IC may be provided on the second IC before the second IC is provided on the first IC.

[0186] It will be appreciated that mechanical and / or electrical couplings between the second IC 700 and the third IC 300 may be in accordance with the any of the mechanical and / or electrical couplings between the first IC 100 and the second IC 700 as described above.

[0187] Optionally, one or more vias 750 are provided through one or more of the stacked ICs, thereby allowing electrical coupling of one or more components (such as an active component or a passive component) included in the first IC 100 to one or more component (such as an active or passive component) included in the third IC 900. Instead of, or in addition to, providing electrical coupling with one or more components of the first IC 100, coupled vias 750 through the first and second ICs 100, 700 may also provide an electrical contact at the first surface 101 of the first IC 100 (with via 750 passing through the substrate of the first IC 100, if a substrate is present), such that a connection may be made with a contact of an external circuit to electrically connect the contact of the external circuit with one or more component of the second IC 700 and / or the third IC 300 (through a contact member 110 of the first IC 100, for example).

[0188] In certain embodiments of the present disclosure, one or more vias passing through a lower IC (such as the first IC 100 and / or, depending on a number of stacked ICs, the second IC 700) to a higher IC (such as the second IC 700 and / or, depending on the number of stacked ICs, the third IC 300) may be electrically isolated from one or more of the ICs through which it passes (i.e. not electrically connected to any of the electronic components of the IC such that the IC through which the via passes is operationally skipped). Advantageously, this may reduce interference. For example, a via 750, included in the first IC 100, vertically connecting a component in an external circuit, to which the first IC 100 is electrically connected, with a component in the second IC 700 may pass through, but be electrically isolated from, an active layer in the first IC 100.

[0189] Although Figure 14B illustrates the inclusion / combination of contact members 110, 120, 710, 720, 310, vias 750 and capacitive plates 760, 360, it will be appreciated that one / some of these elements may be omitted and / or additional elements may be provided, if desired. For example, via 750 could be omitted, and / or contact members 120 and 310 could be omitted, and / or capacitive plates 760, 360 could be omitted, and / or one or more contact members could be provided on the second surface 303 of the third IC, and / or a capacitive plate could be provided in the first IC 100, etc.

[0190] Figures 14A and 14B illustrate examples of stacked IC structures. It will be appreciated that the transmission of power and data between one or more elements in a stack of ICs may be accomplished in a number of ways. The following examples may apply to stacked flexible ICs, stacked rigid ICs and mixed stacks of flexible ICs and rigid ICs, and also may illustrate how a single IC (such as may be for attachment to another IC) may be intended to transmit / receive power after attachment.

[0191] In certain examples, power and communications between ICs may be via one or more buses running vertically through the stack, with each layer (i.e., each IC in the stack)both tapping into the bus and routing it to the layer(s) (i.e., ICs) above and / or below. An example of this is illustrated in Figure 20A, in which communication (i.e. data) buses 50o run vertically through a stack of ICs 100o, 700o, 300o.

[0192] In another example, a variation of the examples in the previous paragraph may be used for a multi-layer neural network or switch with non-blocking connections: here, any top contact on an IC may be switched to any bottom contact of the flexible IC above it.

[0193] In certain examples, power, which may be in the form of an RF signal, may be transmitted to flexible ICs in the stack via capacitive coupling, rather than conductive connections. Examples of capacitive coupling between stacked ICs have also been discussed above. One or more of the flexible ICs receiving the power may include a rectifier coupled to a capacitor plate that couples through a non-conducting layer (e.g. a layer of dielectric, substrate or passivation) to a second capacitor plate in a power-transmitting element. The power-transmitting element may be in another flexible IC, in another device in the stack, or it may be a part of the device to which the stack is attached. Such chip-to-chip capacitive coupling, whilst theoretically possible in silicon ICs, is not considered likely to be done in silicon; the closer coupling and higher dielectric performance enabled by flexible ICs makes the concept much more feasible.

[0194] An example of this is shown in Figure 20B. Here, a second IC 700p (which may be a flexible IC) is stacked on a first IC 100p (which may be a flexible IC). The first IC 100p includes a first capacitive plate 160p, being a power transmitting element. The second IC 700p includes a second capacitive plate 760p, a rectifier 280p coupled to the second capacitive plate 760p, and a dielectric layer 740p to separate the capacitive plates 160p, 760p. The first and second ICs 100p, 700p are resultingly capacitively coupled, thereby providing power to the second IC 700p.

[0195] In certain examples, neighbouring ICs in a stack may couple data and / or power between them using overlapping capacitor plates on each IC, separated by a layer of nonconducting adhesive that also fixes the ICs in place. This has advantages of simplified and lower cost assembly due to the use of NCA, and also provides isolation between the ICs if no conductive interconnections are also present.

[0196] An example of this is shown in Figure 20C. Here, a second IC 700q (which may be a flexible IC) is stacked on a first IC 100q (which may be a flexible IC). The first IC 100q includes a first capacitive plate 160q on a surface facing the second IC 700q. The second IC 700q includes a second capacitive plate 760q on a surface facing the first IC 100q. A NCA is applied between the first and second ICs 100q, 700q, which fixes these ICs in place. The first and second ICs 100q, 700q may therefore be capacitively coupled via the first and second capacitive plates 160q, 760q.

[0197] In certain examples, communications between ICs in a stack may be performed via a RF reader or poller, which may be in or near the stack. Power for one or more of the ICs in the stack may be provided by the reader / poller via inductive (or capacitive) coupling, e.g. of HF antennas. Communications could be bi-directional between an IC and reader, allowing all ICs to indirectly communicate with each other (i.e. via the reader / poller). For example, a temporary stack may be formed in a game application, for example a stack of cards, each having a flexible IC on board, placed on a reader mounted in a board. Alternatively, the reader / poller may provide power for the stacked ICs, which then communicate directly with each other.

[0198] An example of this is shown in Figure 20D. Here, first, second and third flexible ICs 10Or, 700r, 300r are provided power by a RF reader, poller, or power transmission coil 110r.

[0199] Although capacitive coupling has been described above, equivalent functional and design considerations apply to the use of inductive coupling for power and / or data transmission.

[0200] In accordance with certain embodiments of the present disclosure, a first IC 100 or a second IC 700 as discussed above may be provided in isolation of the other one of the first IC 100 and the second IC 700. For example, a first IC and a second IC may be provided at different ends of a structure and then the structure appropriately manipulated / deformed (e.g. bent, folded etc.) to achieve contact and or stacking between the first IC and the second IC. Alternatively, there may be provided only a single IC 400 (which may correspond to a lower IC 100 such as shown in Figures 14A and 14B) with appropriately positioned contacts such that when the IC 400 is appropriately manipulated / deformed (e.g. bent, folded etc.) the contacts come into contact or proximity with one another in order to electrically couple. In another example, the isolated IC 400 may be appropriately manipulated to form contacts with another IC external to the IC 400. These arrangements are described in more detail with respect to Figure 14C.

[0201] Figure 14C shows an example of an IC 400 provided in isolation. IC 400 may include a substrate (e.g., substrate 13) or may be substrate-less (having been formed without or detached from a substrate). The IC 400 in Figure 14C is flexible. In an example, the IC 400 may include one or more contact members 420a, 420b on a second surface 403 opposing a first surface 401 . The first surface 401 may be a surface of the IC 400 to which a substrate is / was attached. It will be appreciated that one or more contact members may alternatively or additionally be provided on the first surface 401 , if desired.

[0202] Where flexible IC 400 includes a plurality of contact members 420a, 420b on the second surface 403, through appropriate deformation of the flexible IC 400, at least one of the plurality of contact members 420a, 420b may be coupled to an entity positioned in a firstdirection relative to the second surface 403 while another at least one of the plurality of contact members 420a, 420b may be coupled to another entity positioned in a second direction (different to the first direction) relative to the second surface 403. For example, referring to Figure 14C, through appropriate bending of the IC 400, two contact members 420a face in a first direction while two contact members 420b face in a second direction different to the first direction. Although the first and second directions are illustrated to be substantially opposite in Figure 14C, it will be appreciated that this is merely a non-limiting example.

[0203] In other words, the flexible IC 400 may advantageously allow for connections to be established in different directions relative to the flexible IC 400 despite contact members only being provided on one surface of the flexible IC 400.

[0204] In accordance with certain embodiments, a flexible IC may be provided as an ‘origami flexible IC’. Such an origami flexible IC is to fix within a specific application space and / or to stack with one or more specific ICs. Such a flexible IC may be non-rectangular and / or may be folded to achieve these aims. IC 400 such as that illustrated in Figure 14C may be used as such an origami flexible IC.

[0205] Figure 15A illustrates an example of a component 110d covered by ICs 100d, 700d, thereby effectively encapsulating (i.e., at least partially surrounding or enclosing) the component 110d. Similar considerations as given here for Figure 15A may be taken for Figures 17E, 17F and 17G (discussed later) with the first entity 20j, 20k, 20I and / or the second entity 30j, 30k, 30I being regarded as similar to component 100d, and vice versa.

[0206] In Figure 15A, a component 110d (i.e. an external device) is stacked on a first IC 100d, and a second IC 700d is stacked on the component 110d. The component 110d is thereby at least partially, substantially or fully encapsulated between the first IC 100d and the second IC 700d. Further, an adhesive or glue 111d may be provided between the first and second ICs 100d, 700d, for example around the component 110d. That is, the space between the first and second ICs 100d, 700d may be sealed and a stacked IC structure is provided.

[0207] Component 110d may be a battery, a sensor, an antenna, another IC or any other suitable component, such as any of those given as examples of the external IC structure or second IC. The component 110d may be flexible, or it may be rigid. The first and second ICs 100d, 700d may be flexible or rigid.

[0208] Where Figure 15A shows two ICs 100d, 700d being used to substantially encapsulate the component 110, an alternative embodiment illustrated in Figure 15B uses a (single) flexible IC to partially, substantially, or fully encapsulate the component 110d,which may be a rigid IC, a flexible IC, or any other electronic component. Here, flexible IC 100d is deformed around the component 110d, and then glue 111d is applied to form a sealed assembly. The glue may for example also act as the mechanical coupler, although any other form of mechanical coupling described herein may be used. That is, the space between / within the folded IC 100d is sealed. Furthermore, as an alternative to glue, any suitable passivation material may be used, such as a polymer for example. The stacked structure (e.g. stacked IC structure) is thus being formed from the IC 100d and the external structure 110d. As for all examples of the stacked structure in the present disclosure, communication between the structures (e.g. ICs), if required, may be implemented via conductive coupling, capacitive coupling, and / or inductive coupling.

[0209] Optionally, such shaped stacking may be improved by introducing strain in one or more layers of the flexible IC, causing it to curl. This may be achieved by any suitable means, for example by thermal curing of one or more layers of the flexible IC causing it to shrink, so as to induce a curl in the flexible IC once it has been removed from its carrier.

[0210] In a further example, such an arrangement may be used to provide a sensor probe, e.g. in which a flexible IC is wrapped around a sensor to which it is electrically connected. The flexible IC may perform amplification, analogue-to-digital conversion, data processing, etc., whilst simultaneously packaging the sensor in a protective passivation. Optionally, one or more further ICs may be stacked with the flexible IC wrapped around the sensor, each further IC providing additional functionality.

[0211] Figure 16 illustrates two stacked ICs 100e, 700e in a ‘daisy-chain’ arrangement. This arrangement may provide top-side and bottom-side contact members for coupling, despite each IC 100e, 700e having contact members on only one side. The first and second ICs 100e, 700e may be electrically coupled via contact members 120e-2 and 710e-2, while contact members 120e-1 and 710e-1 are available for coupling with other entities such as other ICs, components or external circuits.

[0212] In certain examples, such a daisy-chain arrangement may be curled to provide wrap-around stacking, overlapping stacking and / or heterogeneous crystalline I flexible IC stacks, among many geometric possibilities. Some example daisy-chain arrangements are illustrated in Figures 17A, 17B, 17C, 17D and 17E, described below.

[0213] Figures 17A, 17B, 17C, 17D, 17E and 17F schematically illustrate example stacked IC structures according to certain embodiments of the present disclosure, for example one or more of those described previous.

[0214] In Figure 17A, first and second ICs 10Of, 700f may be considered to be stacked, with the first IC 10Of being flexible and being wrapped around the second IC 700f.

[0215] For example, the second IC 700f may have been stacked on a part of the first IC 10Of (in accordance with one of the examples described above, for instance). Mechanical coupling between these parts may then occur (although it will be appreciated that this may happen later in the formation process). Subsequently, another part of the first IC 10Of (e.g., a part on which the stacked second IC 10Of does not overlap) may be moved to bend or fold the first IC 10Of around the second IC 700f to at least partially encapsulate the second IC 700f. The deformed first IC 10Of may therefore partially, substantially, or fully encapsulate the second IC 700f.

[0216] As illustrated, the first and second ICs 10Of, 700f may include contact members on at least some of the opposing surfaces. The first IC 10Of may include contact members for coupling with the second IC 700f only on one surface (e.g., analogous to contact members 120 on second surface 103 of first IC 100, described above), while the second IC 700f may include contact members on both surfaces (e.g., analogous to contact members 710, 220 on first surface 701 and second surface 703 of second IC 700, described above). Through the deformation, the contact members on the single surface of the first IC 100f may be brought close to or into contact with the contact members on both surfaces / sides of the second IC 700f. The contact members may then be electrically coupled to one another (for example, using a conductive adhesive between the respective contact members. However, alternative forms of coupling (e.g. capacitive and inductive) may also be used in 17A and 17B, 17C, 17D, 17E and 17F. With respect to the method of Figure 13, the method may for example further include folding the first IC to encapsulate the second IC such that each of the plurality of contact members provided at on the second surface of the first IC are proximate one or more contact members provided on the first surface or the second surface of the second IC.

[0217] Although the above describes stacking a second IC 700f on the first IC 10Of before deforming the first IC 10Of, it will be appreciated that the arrangement shown in Figure 17A may be obtained by other means. For example, it could be considered that the first IC 10Of may have been wrapped around the second IC 700f, resulting in the stacked IC arrangement. In other words, the first IC 10Of may be deformed prior to being mechanically coupled to the second IC 700f (i.e. , provided around the second IC 700f).

[0218] In Figure 17B, first and second ICs 100g, 700g may be considered to be stacked, with the first IC 100g being flexible and again being wrapped around the second IC 700g. Additionally, the second IC 700g is flexible and deformed, with the first IC 100g being deformed around the bent second IC 700g.

[0219] As illustrated, the first and second ICs 100g, 700g may include contact members. The first IC 100g includes contact members only on one surface (e.g., analogous to contactmembers 120 on second surface 103 of first IC 100, described above), while the second IC 700g also includes contact members on only one surface (e.g., analogous to contact members 710 on first surface 701 of second IC 700, described above).

[0220] A part of the second IC 700g may have been stacked on a part of the first IC 100g (in accordance with one of the examples described above, for instance). Mechanical coupling between these parts may then occur (although it will be appreciated that this may happen later in the formation process). Subsequently, another part of the second IC 700g (e.g., a part which does not overlap with the first IC 100g) may have been moved so as to bend or deform the second IC 700g such that some of the contact members face in a different direction to the other contact members. In this case, these sets of contact members face in substantially opposite directions.

[0221] Another part of the first IC 100g (e.g., a part which does not overlap with the stacked second IC 700g) may be moved so as to bend or deform the first IC 10e around the deformed second IC 700g. The first IC 100g may therefore at least partially encapsulate the second IC 700g, with the contact members of the one surface of the first IC 100g being brought close to or into contact with the contact members of the one surface of the second IC 700g. Respective sets of contact members may then be electrically coupled to one another (for example, using a conductive adhesive between the respective contact members).

[0222] Although the above describes stacking a second IC 700g on the first IC 100g, deforming the second IC 700g and then deforming the first IC 100g, it will be appreciated that the arrangement shown in Figure 17B may be obtained by other means. For example, as an alternative, the second IC 700g may be provided and deformed, and then the first IC 100g is provided above or below the second IC 700g and deformed to wrap around the second IC 700g, with mechanical coupling being performed after.

[0223] In Figure 17C, first and second ICs 100h, 700h may be considered to be stacked, with the first IC 100h being flexible and again being wrapped around a part of the second IC 700h, and also with the second IC 700h being flexible and being wrapped around a part of the first IC 100h.

[0224] A first part of the second IC 700h may have been stacked on a first part of the first IC 100h (in accordance with one of the examples described above, for instance). Mechanical coupling between these parts may then have occurred (although it will be appreciated that this may happen later in the formation process). Subsequently, a second part of the first IC 100h (e.g., a part which does not overlap with the stacked part of the second IC 700h) may be moved so as to deform the first IC 100h around the stacked first part of the second IC 700h. Subsequently, a second part of the second IC 700h (e.g., a part which does not overlap with the first IC 100h) may be moved so as to deform the second IC 700h aroundthe first part of the first IC 100h. Accordingly, the first part of the first IC 100h is at least partially encapsulated by the second IC 700h, while the first part of the second IC is at least partially encapsulated by the first IC 100h.

[0225] The first and second ICs 100h, 700h are shown to include contact members on a single surface only, with the contact members on the at least partly surrounded part of the first IC 100h facing contact members on the second IC 700h. Other contact members of the first IC 100h are facing in an external direction, for coupling to another entity. Of course, this arrangement of contact members is only exemplary, and other arrangements may be implemented as desired. With the respective contact members on the first and second IC 100h, 700h brought closer or into contact with each other through the deforming, they may then be electrically coupled.

[0226] It will also be appreciated that the arrangement shown in Figure 17C may be constructed in other ways; such as performing the various deformations and couplings in a different order.

[0227] With respect to the method of Figure 13 and the forming the structures described with respect to Figures 17B and 17C, the method of Figure 13 may for example further comprise folding the first IC and folding the second IC to at least partially encapsulate the second IC with the first IC such that the one or more contact members provided at the second surface of the first IC is proximate to one or more of the plurality of contact members provided at the first surface of the second IC.

[0228] In Figure 17D, three ICs 10Oi, 700i, 300i are shown. In this example, the second IC 700i is not stacked on the first IC 10Oi, while the third IC 300i is stacked on both first and second ICs 100i, 700i.

[0229] It will be appreciated that this arrangement may be achieved in various ways. For example, the first IC 10Oi may be provided, a part of the third IC 300i may be coupled with a part of the first IC, and a part of the second IC 700i may be coupled with another part of the third IC 300i. As indicated, different contact members of the third IC 300i are electrically coupled with contact members of the first IC 10Oi or contact members of the second IC 700i. Through this, for example, an electrical connection may be made between first and second ICs 100i, 700i. The first and second ICs 100i, 700i may also each have a free (i.e., uncoupled) contact member on a part not overlapped by the third IC 300i, which may be of use in electrically coupling to another entity (such as a further IC or an external circuit (not shown). This may be regarded as a further example of a daisy-chain arrangement.

[0230] In another example, the first IC 10Oi may be provided and the second IC 700i may be provided. The third IC 300i is then coupled with the first and second ICs 10Oi, 700i in any order.

[0231] In yet another example, the third IC 300i may be provided, and the first and second ICs 10Oi, 700i are then coupled to the third IC 300i (in any order).

[0232] In Figure 17E, two ICs 100j, 700j are shown in a similar arrangement to that of Figure 17C. In Figure 17E however, the first IC 100j is also deformed around a first entity 20j, which may be another IC, a component, an external circuit etc. That is, the first entity 20j is partially surrounded by the first IC 100. Also shown is that the second IC 700j is also deformed around a second entity 30j, which may be another IC, a component, an external circuit etc. That is, the second entity 30j is partially surrounded by the second IC 700j.

[0233] The first and second ICs 100j, 700j may be electrically coupled through contact members at the parts of each located between the first entity 20j and the second entity 30j (i.e. , in the terms of Figure 17C, at the first part of the first IC 10Oj and the first part of the second IC 700j).

[0234] The first IC 10Oj may be electrically coupled with the first entity 20j; for example, via corresponding contact members included on / in the first IC 10Oj and the first entity 20j. The second IC 700j may be electrically coupled with the second entity 30j; for example, via corresponding contact members included on / in the second IC 700j and the second entity 30j.

[0235] It will appreciated that only one of the first entity 20j and the second entity 30j may be provided, as desired.

[0236] In another example, shown in Figure 17F, a similar arrangement to that of Figure 17E could be achieved through use of a single IC which, as well as being bent, is appropriately twisted / folded / rolled (as suggested in Figure 14C). IC 100k is shown with a twist 170k. IC 100k includes contact members on only a single surface; however, due to the twist 170k, the IC 100k couples with and at least partially encapsulates first entity 20k and couples with and at least partially encapsulates second entity 30k; where, if the IC 100k were not twisted, the same arrangement may not be feasible. IC 100k therefore at least partially encapsulates both first and second entities 20k, 30k. It will be appreciated that the areas around each entity, within the deformed IC 100k, may be sealed to create a sealed around each entity.

[0237] In Figure 17G, a single IC 1001 is shown deformed around a first entity 201 and a second entity 301. Each of the first entity 201 and the second entity 301 may be another IC, stacked IC structure, a component, an external circuit etc.

[0238] It will be appreciated that the arrangement of Figure 17G may be achieved in various ways. For example, the IC 1001 may be provided, one of the first entity 201 or the second entity 301 may be electrically coupled to a part of the IC 1001, another part of the IC 1001 (e.g., a part not overlapped by the one of the first entity 201 or the second entity 301) may be moved or repositioned to deform / bend the IC 1001 to at least partly surround the one of the first entity 201 or the second entity 301, the other one of the first entity 201 or the second entity 301 may then be electrically coupled to the other part of the IC 1001. In another example, the IC 1001 may be provided, both first and second entities 201, 301 may be stacked on the IC 1001, and the IC 1001 is then deformed to provide the illustrated arrangement. It will be appreciated that other degrees of deformation are possible, such as a deformation of the IC 1001 which results in the first and second entities 201, 301 being substantially perpendicular to one another (where in Figure 17G the first and second entities 20I, 30I may be regarded as substantially parallel to one another).

[0239] For the above examples described in Figures 17A to 17F, it will be appreciated that various modifications may be made, as desired. For example, contact members for providing an electrical coupling between an IC (or a part thereof) and another entity such as another IC or an external circuit (or a part thereof) may be replaced with capacitive plates in the respective IC and entity, to provide electrical coupling in a different manner. Alternatively, inductive coupling may be used for power, data and signal transfer between stacked ICs. Furthermore, in each example, it may be envisaged that one or more of the different entities are mechanically coupled (if not explicitly stated). For instance, mechanical coupling may be between corresponding contact members, or between parts of the surfaces of the different entities, or through the provision / application of a suitable adhesive between the two entities to bond them together.

[0240] Figure 18 illustrates an example of a flexible IC 100m used as an ‘active ribbon cable’ or interposer. The flexible IC 100m is used to connect a passive component 20m (e.g., keys of a keyboard) with embedded analogue and / or digital circuitry 30m. The flexible IC 100m includes contact elements 110m, 120m, for coupling with said external entities.

[0241] Figure 19 illustrates certain embodiments of the present disclosure in which a number of flexible ICs 100n, 700n, 300n are stacked on a surface 40n in layers. Each of the flexible ICs 100n 700n, 300n may contribute certain functionality in the combined system (such an arrangement may allow for ‘mixing and matching’ of functionality). Optionally, one or more of the flexible ICs 100n, 700n, 300n may have a thin substrate or no substrate. Regarding the latter option, for example, a flexible IC may be laminated onto a temporary substrate to assist in assembly, that temporary substrate being removed to leave the flexible IC attached to a stacked IC.

[0242] With regards to a ‘mix and match’ type arrangement, components (each formed in a standardised flexible IC) may be combined into a system (a ‘mix and match system’), which may allow modular systems to be efficiently formed. This mixing and matching can be used in any of the disclosed approaches and structures, for example, the structures of Figures 14A and 14B. Such versatile mixing of components is complex with silicon ICs, at least in part due to the packaging requirements of silicon ICs. Some examples of mix and match systems in accordance with embodiments of the present disclosure are as follows:• A range of ‘standard’ (i.e. high volume) flexible ICs may provide ‘core’ functions such as an analogue-to-digital converter (ADC), processing, logic, memory, input / output (I / O) and other essential functions I IP blocks. Additional custom or standard ICs may then be stacked with the ‘standard’ flexible ICs to form IC structures will customisable functionality.• ICs may have a universal or standardised stacking interface in order to enable a wider range of ICs to be stacked.• ICs manufactured using different processes and / or materials may be stacked due to the increased versatility of flexible ICs compared to silicon ICs.• High-density memory flexible ICs may be stacked into the system if required by a specific application; such memory flexible ICs may be scaled along standard lines, e.g. 1MB, 512GB, etc., and may feature a range of speeds, writabilities, etc.• Custom sensor flexible IC s may each / all be matched - and vertically stacked - with one or more standard flexible ICs.Any of the above may lead to a layering of flexible IC functionality. For example, referring to the arrangement illustrated in Figure 19, it may also be considered that each flexible IC 100n, 700n, 300n may include a sub-system or block (e.g., memory, processor, communications circuitry etc.) that combines with sub-systems or blocks of one or more of the other flexible ICs 100n, 700n, 300n, thereby providing a ‘complete’ (e.g. self-contained) system. To give a further non-limiting example, flexible IC 100n may include a sensor, flexible IC 700n may include a processor, and flexible IC 300n may include communication circuitry. All of the flexible ICs 100n, 700n, 300n may be self-adhesive; for instance, each flexible IC may be regarded as a ‘sticker’. Flexible IC 100n is therefore appropriately applied as a sticker to surface 40n (e.g., making electrical contact with elements on surface 40n). Flexible IC 700n is then appropriately applied as a sticker to flexible IC 100n and flexible IC 300n is then appropriately applied as a sticker to flexible IC 700n, with electrical contact being established through the stack as desired, thereby building-up the desired system.

[0243] Certain embodiments in accordance with the present disclosure may have a number of different applications. Some examples are as follows:

[0244] Certain examples provide driver flexible ICs for arrays, e.g. driver flexible ICs laminated to the rear side of a display array, enabling reduced bezel dimensions. The driver flexible ICs are made in a process optimised for their requirements (e.g. a ‘logic process’), rather than those of the array, leading to a higher yield than methods in which the drivers are formed in the same process as the array. Other examples might include fan-out multiplexers for display or memory arrays.

[0245] In certain other examples, flexible ICs made using different processes may be stacked to provide additional capabilities, or a more economic solution, than a single (flexible) IC:• In one example, a UHF RFID IC is composed of a UHF antenna and Schottky diode rectifier on one flexible IC stacked with digital logic circuits in a second flexible IC. This may enable a high speed, high efficiency rectification circuit to be produced in a process optimised for that purpose, so that the process for manufacturing digital logic circuits does not have to be compromised.• In another example, a combination of a ‘standard’ logic flexible IC with a power flexible IC. The latter may enable higher voltage and / or higher current circuits to be produced, for example DC-DC converters.

[0246] In certain other examples, flexible ICs in accordance with one or more of the above arrangements / s may be used in sensing applications. For example:• Some examples are seen in the arrangements of Figures 14A, 14B, 17E, 17F and 17G.• In other examples, a sensor device may be stacked onto a flexible IC to provide a more application-ready composite component. The flexible IC may provide functionality to the sensor such as amplification, analogue-to-digital conversion, data processing, data transmission and / or reception, power provision, etc.• In other examples, for analyte sensing applications the substrate of a flexible IC may include one or more voids into which the analyte can enter, aided by the flexible nature of the substrate. The flexible IC and a stacked sensor (e.g., a sensor stacked on the flexible IC, or a sensor included in another IC stacked on the flexible IC ) can then combine to perform the analysis.

[0247] In certain other examples, flexible ICs in accordance with one or more of the above arrangements / s may be used in applications related to micro electro-mechanical system (MEMS). For examples:• Broadly, a MEMs device could be laminated or otherwise attached onto a flexible I C, in a manner similar to that described above for sensors applications.• In other examples, two flexible ICs may be stacked in a manner that creates between them a void, membrane, drum, resonant cavity or other commonly used in MEMS devices. Active circuits and / or passive devices in one or both flexible ICs may interact with the stacked to provide sensing, signal generation, actuation or other transducer functions.• In yet other examples, flexible ICs may be fabricated on a substrate having auxetic properties, such as a liquid crystal elastomer, which may also be used to form an upper passivation layer. Alternatively such a material may be stacked onto a flexible IC. Such auxetic stacks may enable sensing of strain or pressure.

[0248] In certain other examples, flexible ICs in accordance with one or more of the above arrangements / s may be used in mix and match systems such as described above (noting the examples described above following the description of the embodiment of Figure 18).

[0249] In certain other examples, flexible ICs in accordance with one or more of the above arrangements / s may be used as ‘glue logic flexible ICs’. Herein, a flexible IC with configurable gates and / or connections may be stacked with one or more other ICs to provide a universal interface. The flexible ICs connection can be made to match any types of IC, while its circuits provide functions such as interconnection (signal routing), current and / or voltage level shifting, and / or other interfacing functions. Such an interfacing flexible IC may aid system design when combining ICs that do not have standardised connections. For example, a flexible IC may be stacked on a PCB or rigid IC, with another flexible IC or another rigid IC stacked on the flexible IC. The flexible ICs connections can be tailored to match those of the lower PCB or rigid IC and those of the upper other flexible IC or other rigid IC.

[0250] The above description provides various examples and embodiments falling under the scope of the present disclosure, including both methods (such as methods of forming a stacked IC and methods of manufacturing an IC) and apparatus (such as individual ICs and stacked ICs). A number of applications for and advantages of stacked ICs and individual flexible ICs have been provided or may be derived, where an application of an individual flexible IC may lie in it being applicable to another IC so as to form a stack. Further, it will be understood that these examples and embodiments may benefit from the use of flexible ICsinstead of, or at least in addition to, rigid ICs (such as silicon ICs); with the benefits of such flexibility being particularly apparent in the examples of Figures 17A to 17G.

[0251] Throughout the description and claims of this specification, the words “comprise” and “contain” and variations of them mean “including but not limited to”, and they are not intended to (and do not) exclude other components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

[0252] As used herein, the terms "A, B or C" or "at least one of A, B and / or C", or the like, may include all possible combinations of A, B and C. It will be understood that when an element (e.g., a first element) is referred to as being (operatively or communicatively) "coupled with / to” or "connected with / to” another element (e.g., a second element), it can be coupled or connected with / to the other element directly or via one or more other elements.

[0253] Features, integers, characteristics, or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and / or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

[0254] The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

CLAIMS1. A method for forming a stacked electronic structure (70), the method comprising: providing a first integrated circuit (IC) (100) on a carrier (200), the first IC (100) having a first surface (101) and a second surface (103), wherein the first surface (101) of the first IC is proximal to an upper surface of the carrier and the second surface (103) of the first IC (100) opposing the first surface (101) of the first IC (100); and contacting a second IC (700) with the first IC (100) and mechanically coupling the second IC (700) with the first IC (100) to form a stacked electronic structure, wherein at least a portion of a first surface (701) of the second IC (700) is arranged to contact at least a portion of the second surface (103) of the first IC (100), and wherein the second IC (700) has a second surface (703) opposing the first surface (701) of the second IC (700); and separating the stacked electronic structure from the carrier (200); wherein the first IC (100) is a flexible IC.

2. The method according to claim 1 , wherein the second surface (103) of the first IC (100) and the first surface (701) of the second IC (700) are the same size or a different size.

3. The method according to claim 1 or claim 2, wherein both the first IC (100) and the second IC (700) are flexible ICs.

4. The method according to any preceding claim, wherein the step of providing a first IC (100) on the carrier (200) comprises manufacturing the first IC (100) on the carrier.

5. The method according to claim 4, wherein manufacturing the first IC (100) on the carrier (200) comprises manufacturing a plurality of flexible ICs on a flexible IC wafer and singulating the wafer to form the first IC (100).

6. The method according to any preceding claim, wherein the step of providing the first IC (100) on the carrier (200) comprises: depositing a polymer layer (202) on the carrier (200); and forming a component layer (206) on the polymer layer (202).

7. The method according to any of claims 1 to 5, wherein the step of providing the first IC on the carrier comprises: depositing a first polymer layer (502) on the carrier (500); depositing a second polymer layer (504) on the first polymer layer (502), wherein the second polymer layer comprises the first surface of the first IC; and forming a component layer (508) on the second polymer layer (504); wherein the step of separating the stacked electronic structure from the carrier (500) comprises detaching the second polymer layer (502) from the first polymer layer (504) to separate the first IC from the first polymer layer (504) and the carrier (500).

8. The method according to claim 7, wherein the second polymer layer (502) has a thickness of between 5pm and 0.01 m.

9. The method according to claim 7 or claim 8, further comprising the step of: depositing a barrier layer (506) on the second polymer layer (502); and forming the component layer (508) on the barrier layer (506).

10. The method according to any of claims 1 to 3, wherein the step of providing the first IC on the carrier comprises: depositing a barrier layer (802) on the carrier (800); and forming a component layer (804) on the barrier layer (802).

11. The method according to claim 9 or claim 10, wherein the barrier layer (802) has a thickness of between 5pm and 0.001pm.

12. The method according to claim 10 or 11, wherein the step of separating the stacked electronic structure from the carrier (800) comprises detaching the barrier layer (802) from the carrier (800) to separate the first IC from the carrier (800), wherein the surface of the barrier layer (802) proximal to the carrier is the first surface of the first IC.

13. The method according to claim 10 or 11, wherein the step of separating the stacked electronic structure from the carrier (800) comprises detaching the component layer (804) from the barrier layer (802) to separate the first IC from the barrier layer (802) and the carrier (800), wherein the surface of the component layer proximal to the carrier is the first surface of the first IC.

14. The method according to any claims 1 to 6, and claims 10 to 12, wherein a release layer is disposed between the carrier and the first surface of the first IC for aiding separation of the stacked electronic structure from the carrier.

15. The method according to any preceding claim, wherein the stacked IC structure is separated from the carrier after the second IC is mechanically coupled to the first IC.

16. The method according to any of preceding claim, further comprising the step of electrically coupling the first IC to the second IC.

17. The method according to any preceding claim, wherein one, or both, of the first IC and the second IC comprise one or more contact members.

18. The method according to claim 16 or claim 17, wherein the first IC (100) comprises one or more contact members (120) proximal to the second surface (103) of the first IC (100), and the second IC (700) comprises one or more contact members (710) proximal to the first surface (701) of the second IC; and wherein one or more of the contact members (120) proximal to the second surface (103) of the first IC (100) are configured to electrically couple with one or more of the contact members (710) proximal to the first surface (701) of the second IC (700) to electrically couple the first IC and the second IC.

19. The method according to any of claims 16 to 18, wherein one or more of: the first IC comprises one or more contact members proximal to the first and / or second surface of the first IC, said one or more contact members being configured to electrically and / or mechanically couple to a first external circuit; andthe second IC comprises one or more contact members proximal to the first and / or second surface (701, 703) of the second IC structure, said one or more contact members being configured to electrically and / or mechanically couple to a second external circuit.

20. The method according to any of claims 16 to 19 , wherein the first IC and the second IC are electrically coupled by one or more of: conductive coupling, capacitive coupling and inductive coupling.

21. The method according to claim 20, wherein the contact members of the first IC and the second IC configured to electrically couple have an insulating layer therebetween.

22. The method according to claim 19 where the first IC (100) and / or the second IC (700) comprises a contact member proximal to their respective first surface and a contact member proximal to their respective second surface, and a via (750) connecting the contact member proximal to their respective first surface and the contact member proximal to their respective second surface.

23. The method according to any preceding claim, comprising: providing a third IC (300) on the second IC (700), wherein a first surface (301) of the third IC (300) is configured to contact the second surface (703) of the second IC (700); and mechanically coupling the third IC (300) with the second IC (700).

24. The method according to claim 23, wherein at least one via (750) is provided through one or more of the first IC, the second IC and the third IC.

25. The method of claim 24, wherein a via is provided through the second IC (700) to electrically connect the first IC (100) and the third IC (300), and the via is not electrically connected to electronic components of the second IC (700) so as to operationally skip the second IC (700).

26. The method according to any previous claim, wherein the first IC (100) has an irregular shape.

27. The method according to any previous claim, wherein one or more external devices are encapsulated between the first IC (100) and the second IC (700).

28. The method according to any of claims 1 to 27, comprising: folding the first IC such that one or more external devices and / or the second IC is encapsulated by the folded first IC.

29. The method according to claim 28, comprising: sealing a space between the folded first IC and the at least one external device and / or the second IC encapsulated by the folded first IC.

30. The method according to claim 28 or 29, wherein folding the first IC comprises thermal treatment of one or more of the layers of the first IC to induce a curl in the first IC upon removal from the carrier.

31. The method according to any of claims 27 to 30, wherein the at least one external device comprises at least one of a further IC, an antenna, a sensor, a display device, a light emitting diode (LED), an LED circuit or LED driver, a microLED, a microLED circuit or microLED driver, an organic light-emitting diode (OLED), an OLED circuit or an OLED driver, a photovoltaic (PV) cell, or a PV device or PV circuit, a capacitor, a capacitor circuit or capacitor driver, a super-capacitor, a super-capacitor circuit or super-capacitor driver, or piezoelectric actuator, and a battery.

32. The method according to any of claims 1 to 17, wherein the first IC comprises a plurality of contact members provided on the second surface; wherein the second IC comprises one or more contact members provided on the first surface of the second IC and one or more contact members provided on the second surface of the second IC; and wherein the method comprises:folding the first IC to encapsulate the second IC such that each of the plurality of contact members provided on the second surface of the first IC are proximate one or more contact members provided on the first surface or the second surface of the second IC .

33. The method according to any of claims 1 to 17, wherein the first IC comprises one or more contact members provided on the second surface; wherein the second IC comprises a plurality of contact members provided on the first surface of the second IC; and wherein the method comprises: folding the first IC and folding the second IC to at least partially encapsulate the second IC with the first IC such that the one or more contact members provided at the second surface of the first IC is proximate to one or more of the plurality of contact members provided at the first surface of the second IC.

34. The method according to any previous claim, comprising: depositing an adhesive on at least a portion of the second surface of the first IC such that at least part of the first surface of the second IC contacts the adhesive to mechanically and / or electrically couple the first IC and the second IC.

35. The method according to claim 34, wherein depositing the adhesive includes patterning the adhesive.

36. The method according to claim 34 or 35, wherein the at least a portion of the second surface of the first IC and the at least a portion of the first surface of the second IC comprise one or more contact members and the adhesive is a conductive adhesive.

37. The method according to any previous claim, wherein the second IC is mechanically coupled to the first IC through an adhesive applied to the first surface of the second IC, the first surface of the second IC being in contact with the second surface of the first IC.

38. The method according to any preceding claim, comprising:providing an adhesive on the first surface of the first IC; and attaching the first IC to an external object by contacting the adhesive on the first surface of the first IC to a surface of the external object.

39. The method according to claim 37 or claim 38 when dependent on one of claims 23 or 24, wherein the third IC is mechanically coupled to the second IC through an adhesive applied to the first surface of the third IC, the first surface of the third IC being in contact with the second surface of the second IC.

40. The method according to any preceding claim, wherein the ICs of the stacked electronic structure include at least one data bus (50o) connecting each of the ICs to one another.

41. The method according to any preceding claim, wherein the stacked electronic structure provides a self-contained electronic system and each of the ICs provide a subsystem of the electronic system.

42. A stacked electronic structure comprising a first integrated circuit (IC) and a second IC, wherein the first IC is a flexible IC and is folded to surround at least a portion of the second IC such that a first portion of a surface of the first IC opposes a first portion of a surface of the second IC, and wherein the first portion of a surface of the first IC includes a first contact member configured to electrically couple to a first contact member included in the first portion of a surface of the second IC.

43. The stacked electronic structure of claim 42, wherein the second IC is a flexible IC and is folded.

44. The stacked electronic structure of claim 42 or 43, wherein all contact members of the first IC configured to electrically couple to contact members of the second IC are provided on a same surface of the first IC.

45. The stacked electronic structure of any of claims 42 to 44, wherein all contact members of the second IC configured to electrically couple to contact members of the first IC are provided on a same surface of the second IC.

46. The stacked electronic structure of any of claims 42 to 45, wherein the first IC includes a second portion of a surface that opposes a second portion of a surface of the second IC, and the second portion of a surface of the first IC includes a second contact member configured to electrically couple to a second contact member included in a second portion of a surface of the second IC, and wherein the first and second portions of the first IC are folded with respect to one another.

47. The stacked electronic structure of claim 46, wherein the first and second portions of the second IC are folded with respect to each other.

48. The stacked electronic structure of any of claims 42 to 47, wherein the first IC and the second IC are mechanically coupled.

49. The stacked electronic structure of any of claims 42 to 48, wherein at least one of the first IC and the second IC at least partially encapsulates an external device.

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