Semiconductor device and method for driving same

Abstract

The present invention provides a novel semiconductor device and a method for driving the same. The semiconductor device comprises: m lines WL (where m is an integer equal to or greater than 2) to which a potential L or a potential WLH is supplied; m lines PL to which a potential H or a potential COM is supplied; n lines BL (where n is an integer equal to or greater than 2) to which a potential H or the potential COM is supplied; and a plurality of memory cells arranged in a matrix of m rows and n columns, each memory cell including an oxide semiconductor-containing transistor and a ferroelectric capacitor, wherein when reading out data from the memory cells connected to the i-th line WL (where i is equal to or greater than 1 and less than m), the potential WLH is supplied to the i-th line WL and the potential L, which is lower than the potential COM, is supplied to the lines WL other than the i-th line WL.

Description

Semiconductor device and driving method thereof

[0001] One embodiment of the present invention relates to a semiconductor device and a driving method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as shown in Non-Patent Documents 1 and 2, research and development of memories using ferroelectrics is being actively carried out. For next-generation ferroelectric memories, ferroelectric HfO ２ Research on Hf-based materials (Non-Patent Document 3), ０．５ Zr０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 4), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 5), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 6).

[0006] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011N. Ramaswamy, et al. , “NVDRAM: A 32Gb Dual Layer 3D Stacked Non-volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI “Workloads”, IEDM 2023Zhen Fan, et al. , "Ferroelectric HfO2-based materials for next-generation ferroelectric memories," JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016; Jun Okuno, et al., "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2," VLSI 2020; Akira Toriumi, "Ferroelectricity of HfO2 thin films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. Francois, et al., "Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications," IEDM 2019. Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology (AIST) Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0007] An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, or a memory device.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a novel transistor, a novel semiconductor device, or a novel memory device.

[0008] It should be noted that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims.

[0009] (1) One embodiment of the present invention is a semiconductor device including a first element layer, a second element layer on the first element layer, and a third element layer on the second element layer, the first element layer including a driver circuit and a selection circuit, the second element layer including a plurality of first memory cells, the third element layer including a plurality of second memory cells, the driver circuit including a first transistor including silicon in a channel formation region, each of the plurality of first memory cells including a first capacitor whose dielectric is a paraelectric and a second transistor whose channel formation region includes an oxide semiconductor, each of the plurality of second memory cells including a second capacitor whose dielectric is a ferroelectric and a third transistor whose channel formation region includes an oxide semiconductor, the second transistor including a region overlapping with the first capacitor, and the third transistor including a region overlapping with the second capacitor,

[0010] In addition, in (1), the first element layer preferably includes single crystal silicon.

[0011] (2) One embodiment of the present invention includes m (m is an integer of 2 or more) wirings WL to which a potential L or a potential WLH is supplied, m wirings PL to which a potential H or a potential COM is supplied, n (n is an integer of 2 or more) wirings BL to which a potential H or a potential COM is supplied, and a plurality of memory cells arranged in a matrix of m rows and n columns, each of the plurality of memory cells including a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed and a capacitor whose dielectric is a ferroelectric, and a first terminal of the transistor in each of the plurality of memory cells is electrically connected to any one of the n wirings BL. a second terminal of the transistor is electrically connected to a first terminal of the capacitor, a gate of the transistor is electrically connected to any one of m wirings WL, the second terminal of the capacitor is electrically connected to any one of m wirings PL, a potential WLH is higher than a potential H, the potential H is higher than a potential COM, and a potential L is lower than a potential COM; when reading data from a memory cell connected to the i-th wiring WL (i is 1 or more and less than m), a potential WLH is supplied to the i-th wiring WL, and a potential L is supplied to wirings WL other than the i-th wiring WL.

[0012] In (2), when writing data to a memory cell connected to the i-th wiring WL, it is preferable that a potential WLH is supplied to the i-th wiring WL and a potential L is supplied to wirings WL other than the i-th wiring. It is preferable that the m wirings WL are arranged parallel to or approximately parallel to the m wirings PL, and it is preferable that the n wirings BL are arranged so as to intersect with the m wirings WL.

[0013] In the above (1) and (2), the oxide semiconductor preferably contains indium, the oxide semiconductor preferably has crystallinity, and the ferroelectric preferably contains hafnium and zirconium.

[0014] One embodiment of the present invention can provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. One embodiment of the present invention can provide a highly reliable transistor, a semiconductor device, or a memory device. One embodiment of the present invention can provide a semiconductor device or a memory device with low power consumption. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with favorable electrical characteristics. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with high on-state current. One embodiment of the present invention can provide a novel transistor, a novel semiconductor device, or a novel memory device.

[0015] The description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0016] FIG. 1 is a circuit diagram of a semiconductor device. FIG. 2 is a circuit diagram of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating the Id-Vg characteristics of a transistor. FIG. 4A is a diagram illustrating an example of the hysteresis characteristics of a ferroelectric. FIGS. 4B and 4C are diagrams illustrating the remanent polarization of a ferroelectric capacitor. FIG. 5 is a timing chart illustrating an example of the operation of a semiconductor device. FIGS. 6A and 6B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIG. 7 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIGS. 8A and 8B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIG. 9 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 10 is a timing chart illustrating an example of the operation of a semiconductor device. FIGS. 11A and 11B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIGS. 12A and 12B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIGS. 13A and 13B are circuit diagrams illustrating an example of the operation of a semiconductor device. FIG. 14 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 15 is a plan view illustrating an example of the configuration of a semiconductor device. FIGS. 16A to 16C are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIGS. 17A to 17C are perspective views illustrating an example of the configuration of a semiconductor device. FIGS. 18A and 18B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 19A is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 19B and 19C are perspective views illustrating an example of the configuration of a semiconductor device. FIG. 20A is a perspective view illustrating an example of the configuration of a semiconductor device. FIG. 20B is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 20C and 20D are circuit diagrams of a semiconductor device. FIGS. 21A and 21B are block diagrams illustrating an example of the configuration of a semiconductor device. FIG. 22 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 23 is a block diagram illustrating a CPU. FIGS. 24A and 24B are perspective views of a semiconductor device. FIGS. 25A and 25B are perspective views of a semiconductor device. FIG. 26 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 27A and 27B are examples of the configuration of electronic components. FIGS. 28A to 28C are examples of the configuration of a mainframe computer. Fig. 29A is a configuration example of space equipment, and Fig. 29B is a configuration example of a storage system.30A and 30B are diagrams illustrating the carrier concentration dependence of Hall mobility, and Fig. 30C is a cross-sectional view illustrating an indium oxide film.

[0017] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0018] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0019] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0020] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in plan views, perspective views, etc.

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0022] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0023] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0024] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0025] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0026] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0027] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0028] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0029] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0030] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a supplied voltage.

[0031] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal of the transistor", and the other of the source or the drain of the transistor may be referred to as a "second terminal of the transistor".

[0032] In this specification, "parallel" refers to a state in which two straight lines are arranged at a relative angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at a relative angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at a relative angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at a relative angle of 60° or more and 120° or less.

[0033] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0034] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0035] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in an electrically conductive state (a state in which electricity can be passed), and the "off state" of a transistor means that the source and drain of the transistor are in an electrically non-conductive state (a state that can be considered to be electrically disconnected).

[0036] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0037] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS.

[0038] In addition, in drawings and the like, to clearly show the potential of wirings, electrodes, etc., "H" indicating a potential H or "L" indicating a potential L may be added adjacent to the wirings, electrodes, etc. Furthermore, "H" or "L" may be enclosed in a box next to wirings, electrodes, etc. where a potential change has occurred. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor. Furthermore, an arrow may be added to indicate the direction of current flow.

[0039] In this specification, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0040] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0041] Generally, "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator. In addition, in this specification, one electrode of a capacitance element may be referred to as a "first terminal of the capacitance element." In addition, the other electrode of the capacitance element may be referred to as a "second terminal of the capacitance element."

[0042] In this specification and the like, a transistor using a metal oxide (also referred to as an "oxide semiconductor") that functions as a semiconductor in a semiconductor layer and a transistor having a metal oxide in a channel formation region may be referred to as an "OS transistor." Also, a transistor having silicon in a channel formation region may be referred to as a "Si transistor."

[0043] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0045] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0046] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0047] Unless otherwise specified, in this specification and the like, off-state current refers to a current that flows between the source and drain of a transistor when the transistor is in an off state (also referred to as a "non-conducting state" or "cut-off state"). Unless otherwise specified, the off state refers to a state in which the voltage between the gate and the source of an n-channel transistor is lower than a threshold voltage (also referred to as "Vth") (or higher than Vth in a p-channel transistor).

[0048] In this specification and the like, the threshold voltage of a transistor refers to a gate voltage (Vg) at which a channel is considered to be formed in the transistor. Specifically, the threshold voltage of a transistor refers to the Vg at which a tangent with a maximum slope intersects with the horizontal axis where Id is 0 A in a curve plotted with the gate voltage on the horizontal axis (Vg axis) and the square root of the drain current (Id) on the vertical axis. For example, an n-channel transistor having a threshold voltage of 0 V or more can be considered a normally-off transistor. Furthermore, an n-channel transistor having a threshold voltage of less than 0 V can be considered a normally-on transistor.

[0049] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0050] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., vertical directions.

[0051] Furthermore, in this specification, when the same symbol is used for multiple elements, and when it is particularly necessary to distinguish between them, the symbol may be accompanied by an identifying symbol such as "_1", "_2", "[n]", or "[m, n]".

[0052] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to drawings.

[0053] <Configuration Example of Semiconductor Device> Fig. 1 shows a circuit diagram of a semiconductor device 10 functioning as a memory cell. Fig. 1 shows a memory cell array 100 including a plurality of semiconductor devices 10 arranged in m rows and n columns (m and n are each an integer of 2 or greater).

[0054] In this specification and the like, the semiconductor device 10 arranged in the first row and first column will be referred to as semiconductor device 10[1,1]. The semiconductor device 10 arranged in the mth row and first column will be referred to as semiconductor device 10[m,1]. The semiconductor device 10 arranged in the first row and nth column will be referred to as semiconductor device 10[1,n]. The semiconductor device 10 arranged in the mth row and nth column will be referred to as semiconductor device 10[m,n].

[0055] The memory cell array 100 has m wirings WL, m wirings PL, and n wirings BL. The wirings WL and PL extend in the row direction (e.g., X direction), and the wirings BL extend in the column direction (e.g., Y direction). The wirings WL function as word lines, and the wirings BL function as bit lines. The wirings PL function as power supply lines.

[0056] In this specification and the like, the first wiring WL, the first wiring PL, and the first wiring BL are referred to as wiring WL[1], wiring PL[1], and wiring BL[1], respectively. The second wiring WL, the second wiring PL, and the second wiring BL are referred to as wiring WL[2], wiring PL[2], and wiring BL[2], respectively. The m-th wiring PL and the m-th wiring BL are referred to as wiring WL[m] and wiring PL[m], respectively. The n-th wiring BL is referred to as wiring BL[n].

[0057] Each of the semiconductor devices 10 arranged in the first row is connected to the wiring WL[1] and the wiring PL[1]. Each of the semiconductor devices 10 arranged in the first column is connected to the wiring BL[1].

[0058] Furthermore, each of the n wirings BL is connected to each of the n sense amplifiers 50. Specifically, the wiring BL[1], which is the first wiring BL, is connected to the sense amplifier 50[1], which is the first sense amplifier 50. The wiring BL[2], which is the second wiring BL, is connected to the sense amplifier 50[2], which is the second sense amplifier 50. The wiring BL[n], which is the nth wiring BL, is connected to the sense amplifier 50[n], which is the nth sense amplifier 50.

[0059] The sense amplifier 50 has a function of detecting a change in the potential of the wiring BL and outputting a potential corresponding to data stored in the semiconductor device 10 to the output terminal OUT and the wiring BL. In this specification and the like, the output terminal OUT of the sense amplifier 50[1] is referred to as the output terminal OUT[1]. The output terminal OUT of the sense amplifier 50[2] is referred to as the output terminal OUT[2]. The output terminal OUT of the sense amplifier 50[n] is referred to as the output terminal OUT[n].

[0060] The semiconductor device 10 has a transistor 20 and a capacitance element 30. Fig. 2 shows a circuit diagram of a semiconductor device 10[i,j], which is the semiconductor device 10 arranged in the i-th row and j-th column (i is an integer of 1 to m, and j is an integer of 1 to n). In Fig. 2, the transistor 20 and capacitance element 30 included in the semiconductor device 10[i,j] are respectively represented as transistor 20[i,j] and capacitance element 30[i,j]. When referring to an arbitrary semiconductor device 10, the descriptions semiconductor device 10 and semiconductor device 10[i,j] are synonymous.

[0061] The gate of the transistor 20[i,j] is connected to the wiring WL[i]. One of the source or drain of the transistor 20[i,j] is connected to the wiring BL[j], and the other of the source or drain is connected to one electrode of the capacitor 30[i,j]. The other electrode of the capacitor 30[i,j] is connected to the wiring PL[i]. The wiring BL[j] is connected to the sense amplifier 50[j]. In FIG. 2, the output terminal OUT of the sense amplifier 50[j] is referred to as the output terminal OUT[j].

[0062] A region where the other of the source or the drain of the transistor 20 and one electrode of the capacitor 30 are connected and always at the same potential is referred to as a node ND. In FIG. 2, the node ND included in the semiconductor device 10[i, j] is referred to as a node ND[i, j].

[0063] When referring to an arbitrary semiconductor device 10, the semiconductor device 10 and the semiconductor device 10[i,j] are synonymous. When referring to an arbitrary wiring WL, the wiring WL[i] and the wiring WL are synonymous. When referring to an arbitrary wiring BL, the wiring BL[i] and the wiring BL are synonymous. When referring to an arbitrary wiring PL, the wiring PL[i] and the wiring PL are synonymous. When referring to an arbitrary node ND, the node ND[i,j] and the node ND are synonymous. When referring to an arbitrary sense amplifier 50, the sense amplifier 50[j] and the sense amplifier 50 are synonymous. When referring to an arbitrary output terminal OUT, the output terminal OUT[j] and the output terminal OUT are synonymous.

[0064] In the semiconductor device 10 according to one embodiment of the present invention, an OS transistor is used as the transistor 20. Furthermore, a capacitor (also referred to as a "ferroelectric capacitor") using a material that can have ferroelectricity as a dielectric (also referred to as a "ferroelectric") is used as the capacitor 30.

[0065] The band gap of the oxide semiconductor used in the OS transistor is 2 eV or more, and therefore the off-state current is significantly small. The off-state current of the OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less or 1yA (1 x 10 −２４ The off-state current value of a Si transistor (a transistor including silicon in a semiconductor layer in which a channel is formed) per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) More than 1pA (1×10 −１２ Therefore, it can be said that the off-state current of an OS transistor is about three to twelve orders of magnitude lower than that of a Si transistor.

[0066] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A semiconductor device including an OS transistor has stable operation and high reliability even in a high-temperature environment.

[0067] In addition, an OS transistor has a high withstand voltage between the source and the drain. By using an OS transistor as a transistor included in a semiconductor device, the operation is stable even when the transistor size is reduced, and a highly reliable semiconductor device can be realized.

[0068] Here, the Id-Vg characteristic, which is one of the electrical characteristics of a transistor, will be described. FIGS. 3A and 3B show an example of the Id-Vg characteristic, which is one of the electrical characteristics of a transistor. The Id-Vg characteristic shows the change in drain current (Id) with respect to the change in gate voltage (Vg) when the drain voltage is constant. The horizontal axis of FIGS. 3A and 3B represents Vg on a linear scale. The vertical axis of FIGS. 3A and 3B represents Id on a logarithmic scale.

[0069] 3A shows the Id-Vg characteristics of an OS transistor (OS-FET), and FIG. 3B shows the Id-Vg characteristics of a Si transistor (Si-FET). Note that both FIG. 3A and FIG. 3B show the Id-Vg characteristics of an n-channel transistor.

[0070] To turn off an n-channel transistor, Vg needs to be equal to or lower than the threshold voltage. In particular, to turn off a normally-on n-channel transistor, Vg needs to be negative. Furthermore, the off-state current of the transistor 20 needs to be sufficiently small to retain data written to the semiconductor device 10. In an n-channel transistor, Vg is preferably negative to sufficiently reduce the off-state current.

[0071] However, when Vg of a Si transistor is set too negative, the off-state current tends to increase (see FIG. 3B). On the other hand, when Vg of an OS transistor is set too negative, the off-state current does not increase easily (see FIG. 3A). Therefore, even if the OS transistor is a normally-on transistor, it is easy to turn off the transistor.

[0072] Furthermore, an OS transistor has a larger voltage range M of Vg required to keep its off-state current equal to or less than a certain value than a Si transistor. That is, by using an OS transistor as the transistor 20, the semiconductor device 10 can be resistant to noise, can retain data for a long period of time, and can have higher reliability.

[0073] Furthermore, paraelectrics have the property that when a voltage is applied, the random polarization direction aligns in a certain direction, and returns to disorder when the voltage application is stopped. Ferroelectrics have the property that when a voltage is applied, the polarization aligns in a certain direction, and the polarization remains aligned even after the voltage application is stopped. Furthermore, when the voltage is reversed, the polarization is reversed. The semiconductor device 10 according to one aspect of the present invention can function as a nonvolatile memory element by applying the properties of a ferroelectric. A nonvolatile memory element using a ferroelectric is sometimes called a "ferroelectric memory." The semiconductor device 10 according to one aspect of the present invention functions as a ferroelectric memory. The semiconductor device 10 according to one aspect of the present invention can function as a memory cell for FeRAM.

[0074] Furthermore, depending on the configuration of the ferroelectric capacitor, a relatively large voltage may need to be applied when reversing polarization. As described above, OS transistors have a high withstand voltage between the source and drain, making them suitable for use as transistors in the semiconductor device 10 including a ferroelectric capacitor. By using OS transistors, it is possible to stably supply the voltage required for reversing polarization even when the transistor size is reduced. Therefore, by using OS transistors, a semiconductor device with stable operation and high reliability can be realized. Furthermore, by using OS transistors, miniaturization and high integration of semiconductor devices become easier.

[0075] Furthermore, depending on the composition of the ferroelectric, the leakage current may be larger than that of a paraelectric. Therefore, when a Si transistor is used as the transistor 20, the power consumption of the semiconductor device 10 may be increased due to the leakage current between the wiring BL and the wiring PL. When an OS transistor is used as the transistor 20, the leakage current between the wiring BL and the wiring PL is reduced, and the power consumption of the semiconductor device 10 can be reduced.

[0076] Furthermore, as the number of semiconductor devices 10 connected to the wiring BL increases, the potential change of the wiring BL decreases due to the leakage current, which tends to reduce the accuracy of data reading. By using an OS transistor as the transistor 20, the leakage current can be reduced and the accuracy of data reading can be improved. Therefore, the reliability of the semiconductor device 10 can be improved.

[0077] Furthermore, by using an OS transistor as the transistor 20, the accuracy of reading data is less likely to decrease even when the number of semiconductor devices 10 connected to the wiring BL is increased. Therefore, a semiconductor device with stable operation and high reliability can be realized. Furthermore, miniaturization and high integration of the semiconductor device can be easily achieved.

[0078] <Example of Operation of Semiconductor Device> Next, a description will be given of an example of operation of the semiconductor device 10. First, the hysteresis characteristics of a ferroelectric material will be described.

[0079] [Hysteresis Characteristics of Ferroelectrics] Ferroelectrics have hysteresis characteristics. FIG. 4A is a diagram showing an example of the hysteresis characteristics of a ferroelectric. The hysteresis characteristics of a ferroelectric can be measured using a ferroelectric capacitor. In FIG. 4A, the horizontal axis represents the voltage (electric field) applied to the ferroelectric. This voltage is the potential difference between one electrode and the other electrode of the ferroelectric capacitor. The electric field strength can be calculated by dividing this potential difference by the thickness of the ferroelectric.

[0080] In Figure 4A, the vertical axis represents the polarization of the ferroelectric. When the polarization is positive, it indicates that the positive charge in the ferroelectric is biased toward one electrode of the capacitance element, and the negative charge is biased toward the other electrode of the capacitance element. On the other hand, when the polarization is negative, it indicates that the negative charge in the ferroelectric is biased toward one electrode of the capacitance element, and the positive charge is biased toward the other electrode of the capacitance element.

[0081] Furthermore, the polarization shown on the vertical axis of the graph in Figure 4A may be positive when negative charges are biased toward one electrode side of the capacitance element and positive charges are biased toward the other electrode side of the capacitance element, and may be negative when positive charges are biased toward one electrode side of the capacitance element and negative charges are biased toward the other electrode side of the capacitance element.

[0082] 4A, the hysteresis characteristics of a ferroelectric material can be expressed by a curve 51 and a curve 52. The voltages at the intersections of the curves 51 and 52 are referred to as the saturated polarization voltage +VSP (also referred to as "+VSP") and the saturated polarization voltage -VSP (also referred to as "-VSP"). It can be said that +VSP and -VSP have opposite polarities.

[0083] When a voltage equal to or less than -VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is increased, the polarization of the ferroelectric changes according to curve 51. On the other hand, when a voltage equal to or greater than +VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is decreased, the polarization of the ferroelectric changes according to curve 52. Note that +VSP may be referred to as a "positive saturation polarization voltage" or a "first saturation polarization voltage." Furthermore, -VSP may be referred to as a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0084] When the polarization of a ferroelectric changes according to curve 51, the voltage at which the polarization becomes 0 is referred to as coercive voltage +Vc. Furthermore, when the polarization of a ferroelectric changes according to curve 52, the voltage at which the polarization becomes 0 is referred to as coercive voltage -Vc. The values ​​of +Vc and -Vc are between +VSP and -VSP. Note that +Vc may be referred to as a "positive coercive voltage" or "first coercive voltage," and -Vc may be referred to as a "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0085] Furthermore, when no voltage is applied to the ferroelectric (when the voltage is 0 V), the maximum value of polarization is denoted as "residual polarization +Pr" or "residual polarization Pr1," and the minimum value is denoted as "residual polarization -Pr" or "residual polarization Pr2." The capacitance value of the ferroelectric capacitor according to the present embodiment and the like is assumed to be larger when the remnant polarization of the dielectric is -Pr than when the remnant polarization is +Pr.

[0086] The absolute value of the difference between the remanent polarization +Pr and the remanent polarization -Pr is referred to as "remanent polarization 2Pr." The larger the remanent polarization 2Pr, the larger the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. The larger the remanent polarization 2Pr, the more preferable it is.

[0087] Fig. 4B is a schematic diagram showing the case where the remanent polarization of the capacitance element 30, which is a ferroelectric capacitor, is -Pr. Fig. 4C is a schematic diagram showing the case where the remanent polarization of the capacitance element 30, which is a ferroelectric capacitor, is +Pr. Figs. 4B and 4C schematically show the polarization of the dielectric of the capacitance element 30. In Figs. 4B and 4C, the direction of polarization is indicated by arrows.

[0088] Examples of ferroelectrics include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of ferroelectrics include materials obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close thereto. Examples of ferroelectrics include materials obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of element J2 atoms can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or close thereto. Furthermore, lead titanate (PbTiO Ｘ(X is a real number greater than 0), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or piezoelectric ceramics having a perovskite structure such as barium titanate (BST), strontium titanate (BFO), or barium titanate can also be used.

[0089] As a ferroelectric material, aluminum scandium nitride (Al １−ａ Sc ａ N ｂ (where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1. Hereinafter, this may be referred to simply as "AlScN"), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used. Ferroelectrics include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Ferroelectrics include materials obtained by adding element M3 to the above-mentioned metal nitrides. The element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately. Since the above metal nitride contains at least a Group 13 element and nitrogen, which is a Group 15 element, the metal nitride may be referred to as a Group 13-15 ferroelectric, a Group 13 nitride ferroelectric, etc.

[0090] As a ferroelectric material, SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0091] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, etc. may be used.

[0092] Furthermore, the ferroelectric may be, for example, a mixture or compound of multiple materials selected from the materials listed above. For example, the ferroelectric may have a layered structure of multiple materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. For this reason, in this specification, the term ferroelectric is used to refer not only to materials that exhibit ferroelectricity, but also to materials that can have ferroelectricity.

[0093] Metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Representative examples of metal oxides containing hafnium and zirconium include HfZrO Ｘ Also, HfZrO Ｘ It is also possible to use a metal oxide in which Y (yttrium) is added to HfZrO. Ｘ By adding Y (yttrium) to the above, the ferroelectricity can be enhanced.

[0094] In this specification and the like, a ferroelectric may be referred to as a "ferroelectric material." A layer of a ferroelectric material may be referred to as a "ferroelectric layer." A device having a ferroelectric layer may be referred to as a "ferroelectric device."

[0095] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals with an orthorhombic crystalline structure is preferred because it manifests ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0096] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0097] As described above, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even when it is a thin film of a few nanometers, and is therefore preferable for the insulating layer 250. The film thickness of the insulating layer 250 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).

[0098] Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in a small area, making them preferable for the insulating layer 250. For example, the ferroelectric layer can exhibit ferroelectricity even when its area (occupied area) in a plan view is 100 μm or less, 10 μm or less, 1 μm or less, or 0.1 μm or less. Furthermore, the ferroelectric layer may exhibit ferroelectricity even when its area is 10,000 nm or less, or 1,000 nm or less. By using a ferroelectric layer with a small area, the occupied area of ​​the semiconductor device 10 can be reduced.

[0099] [Write Operation] An operation of writing binary data of data "0" or "1" to the semiconductor device 10 functioning as a memory cell will be described. In the present embodiment and the like, the polarization of the capacitive element 30 is set to +Pr when writing data "0", and the polarization of the capacitive element 30 is set to -Pr when writing data "1". Figure 5 is a timing chart illustrating an example of an operation of writing data to the semiconductor device 10. Figures 6A and 6B are circuit diagrams illustrating the operation of writing data.

[0100] First, an operation of writing data "1" to the semiconductor device 10 will be described. In a period T11, a potential WLH is supplied to the wiring WL, a potential H is supplied to the wiring BL, and a potential COM is supplied to the wiring PL (see FIGS. 5 and 6A). Then, the potential H is supplied to one electrode (node ​​ND) of the capacitor 30, and the potential COM is supplied to the other electrode of the capacitor 30.

[0101] The potential H is higher than the potential COM, and the potential L is lower than the potential COM. The potential WLH is higher than the potential H plus the threshold voltage of the transistor 20. Therefore, the potential WLH is a potential that reliably turns on the transistor 20. The potential difference between the potential H and the potential COM is a potential difference (voltage) that is equal to or greater than the absolute values ​​of +VSP and −VSP. If the potential COM is a reference potential (e.g., 0 V), the potential H and the potential WLH are positive potentials, and the potential L is negative potential.

[0102] When the potential H is supplied to the node ND and the potential COM is supplied to the wiring PL, +VSP is applied to the capacitor 30 .

[0103] In period T12, a potential COM is supplied to the wiring BL (see FIGS. 5 and 6B). As a result, the voltage applied to the capacitor 30 becomes 0 V, and the residual electrode becomes +Pr. In period T13, a potential L is supplied to the wiring WL, turning off the transistor 20 (see FIG. 7). In this way, data "1" can be written to the semiconductor device 10.

[0104] Next, an operation of writing data "0" to the semiconductor device 10 will be described. In a period T14, a potential WLH is supplied to the wiring WL, a potential COM is supplied to the wiring BL, and a potential H is supplied to the wiring PL (see FIGS. 5 and 8A). Then, the potential COM is supplied to one electrode (node ​​ND) of the capacitor 30, and the potential H is supplied to the other electrode of the capacitor 30.

[0105] When the potential COM is supplied to the node ND and the potential H is supplied to the wiring PL, −VSP is applied to the capacitor 30 .

[0106] In period T15, a potential COM is supplied to the wiring PL (see FIGS. 5 and 8B). As a result, the voltage applied to the capacitor 30 becomes 0 V, and the residual electrode becomes −Pr. In period T16, a potential L is supplied to the wiring WL, turning off the transistor 20 (see FIG. 9). In this way, data “0” can be written to the semiconductor device 10.

[0107] By turning off the transistor 20 in the periods T13 and T15, the node ND is in an electrically floating state (also referred to as a "floating state"). Therefore, after writing data and before turning off the transistor 20, it is important to set the node ND and the wiring PL to the same potential.

[0108] For example, consider a case where the transistor 20 is turned off while the potential of the node ND is at the potential COM and the potential of the wiring PL is at the potential H (period T14, see FIG. 8A). After this, when the potential of the wiring PL is lowered from the potential H to the potential COM, the potential of the floating node ND, which is capacitively coupled via the capacitor 30, also drops. When the potential of the node ND drops, the node ND becomes the source of the transistor 20, and the transistor 20 may be unintentionally turned on. This may cause data written to the semiconductor device 10 to be corrupted.

[0109] After writing data, the node ND and the wiring PL are set to the same potential before turning off the transistor 20, whereby corruption of data written in the semiconductor device 10 can be prevented and the reliability of the semiconductor device 10 can be improved.

[0110] [Read Operation] Next, a read operation of data stored in the semiconductor device 10 functioning as a memory cell will be described. Fig. 10 is a timing chart for describing a read operation of data stored in the semiconductor device 10. Note that Fig. 10 shows an enlarged view of the potential change of the wiring BL during the period T22. Figs. 11A and 11B are circuit diagrams for describing the data read operation.

[0111] In the period T21, the wiring BL is precharged to a potential H. Specifically, the potential H is supplied to the wiring BL, and then the wiring BL is set in a floating state at the potential H (see FIGS. 10 and 11A).

[0112] In the period T22, a potential WLH is supplied to the wiring WL to turn on the transistor 20. Then, the wiring BL and the node ND are connected through the channel formation region of the transistor 20. When the wiring BL and the node ND are connected, a current flows in the channel formation region of the transistor 20 according to the capacitance value of the capacitor 30. That is, the potential of the wiring BL, which is in a floating state, changes according to the capacitance value of the capacitor 30.

[0113] For example, when data "1" is written to the semiconductor device 10, the potential of the wiring BL changes from potential H to potential V1. When data "0" is written to the semiconductor device 10, the potential of the wiring BL changes from potential H to potential V0. In FIG. 10, the potential change of the wiring BL when data "1" is written to the semiconductor device 10 is indicated by a solid line, and the potential change of the wiring BL when data "0" is written is indicated by a dashed line.

[0114] When data "1" is written in the semiconductor device 10, the remanent polarization of the capacitive element 30 is +Pr, and when data "0" is written, the remanent polarization of the capacitive element 30 is -Pr. Therefore, as described above, the capacitance value of the capacitive element 30 when data "0" is written is larger than the capacitance value of the capacitive element 30 when data "1" is written. Therefore, the potential V0 is lower than the potential V1 (see FIGS. 10 and 11B).

[0115] As described above, the wiring BL is connected to the sense amplifier 50 (see FIGS. 1 and 2). The sense amplifier 50 detects whether the potential of the wiring BL has changed to a potential V1 or a potential V0 and outputs the detection result to the output terminal OUT and the wiring BL. For example, the sense amplifier 50 compares the potential of the wiring BL with a reference potential. If the potential of the wiring BL is higher than the reference potential (if the potential of the wiring BL is V1), the sense amplifier 50 outputs a potential H to the output terminal OUT and the wiring BL. If the potential of the wiring BL is lower than the reference potential (if the potential of the wiring BL is V0), the sense amplifier 50 outputs a potential COM to the output terminal OUT and the wiring BL (see FIGS. 10 and 12A). During the period T22, the transistor 20 is on, and therefore the potential of the node ND also changes in the same way as the wiring BL.

[0116] Note that if the data held by the semiconductor device 10 is "0", when potential H is supplied to the wiring BL in period T22, potential H is also supplied to the node ND, and the polarization of the capacitor 30 is reversed. That is, in the semiconductor device 10, "destructive read" is performed, in which the data held during data read is destroyed. If the data held by the semiconductor device 10 is "1", the polarization of the capacitor 30 is not reversed. Therefore, if the data held by the semiconductor device 10 is "1", the data is not destroyed.

[0117] Next, in the period T23, the destroyed data "0" is written back. Specifically, in the period T23, a potential H is supplied to the wiring PL (see FIGS. 10 and 12B). If the data held in the semiconductor device 10 is "1," the potential of the node ND becomes the potential H in the period T22, and therefore both electrodes of the capacitor 30 have the same potential. Therefore, polarization reversal does not occur.

[0118] If the data held in the semiconductor device 10 is "0", the potential of the node ND becomes the potential COM in the period T22. Therefore, when the potential H is supplied to the wiring PL in the period T23, the polarization of the capacitor 30 is reversed. In this manner, the data "0" can be written back.

[0119] In the period T24, a potential H is supplied to the wiring BL. Then, the voltage applied to the capacitor 30 becomes 0 V (see FIGS. 10 and 13A).

[0120] In a period T25, the potential L is supplied to the wiring WL. When the potential L is supplied to the wiring WL, the transistor 20 is turned off and the node ND is brought into a floating state (see FIGS. 10 and 13B).

[0121] In the period T26, the potential COM is supplied to the wiring BL and the wiring PL (see FIGS. 10 and 14). When the potential of the wiring PL changes from the potential H to the potential COM, the potential of the node ND also changes to the potential COM.

[0122] In this way, it is possible to read and write back data stored in the semiconductor device 10. Furthermore, reading and writing back data stored in the semiconductor device 10 can be performed for each row of the memory cell array 100. In other words, it can be performed for each of the multiple semiconductor devices 10 connected to one wiring WL.

[0123] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0124] Embodiment 2 In this embodiment, a structural example of a transistor and a capacitor that can be used in the semiconductor device 10 will be described with reference to the drawings.

[0125] Fig. 15 is a plan view showing an example of a memory cell array 100 including a plurality of semiconductor devices 10. Fig. 15 shows the memory cell array 100 having nine semiconductor devices 10 arranged in a matrix of three rows and three columns. Note that some elements are omitted from the plan view of Fig. 15 for clarity.

[0126] Fig. 16A is a cross-sectional view taken along dashed dotted lines A1-A2 shown in Fig. 15. Fig. 16B is a cross-sectional view taken along dashed dotted lines A3-A4 shown in Fig. 15. Fig. 16C is a cross-sectional view taken along dashed dotted lines B1-B2 shown in Fig. 15.

[0127] 17A, 17B, and 17C are perspective views illustrating an example of a semiconductor device according to one embodiment of the present invention. Parts of the configuration illustrated in FIG. 17A are illustrated in FIGS. 17B and 17C. FIG. 17B includes an example cross-sectional configuration taken along dashed line A1-A2 in FIG. 15. Furthermore, FIG. 17C includes an example cross-sectional configuration taken along dashed line B1-B2 in FIG. 15.

[0128] The semiconductor device 10 shown in Figures 15, 16A to 16C, and 17A to 17C has an insulating layer 180 on a substrate (not shown), a conductive layer 110 on the insulating layer 180, a capacitance element 30 and an insulating layer 160 on the conductive layer 110, an insulating layer 280 on the insulating layer 160, a transistor 20 on the capacitance element 30, an insulating layer 285 on the transistor 20, and a conductive layer 245 on the transistor 20 and on the insulating layer 285.

[0129] The conductive layer 110 extends in the Y direction and functions as a wiring PL. The conductive layer 245 extends in the X direction and functions as a wiring BL. The insulating layer 180, the insulating layer 160, the insulating layer 280, and the insulating layer 285 function as interlayer films.

[0130] The nine semiconductor devices 10 included in the memory cell array 100 shown in FIG. 15 are provided in regions where the conductive layer 110, the conductive layer 245, and a conductive layer 260 (described later) overlap each other.

[0131] [Capacitor 30] The capacitor 30 includes a conductive layer 115 over the conductive layer 110, an insulating layer 121 over the conductive layer 115 and the insulating layer 160, and a conductive layer 120 located over the insulating layer 121 and having a region overlapping with the conductive layer 115. Note that an insulating layer 280 is provided over the insulating layer 121 and the conductive layer 120.

[0132] The conductive layer 115 functions as one of a pair of electrodes of the capacitor 30. The conductive layer 120 functions as the other of the pair of electrodes of the capacitor 30. Furthermore, the insulating layer 121 functions as a dielectric of the capacitor 30. As described above, the capacitor 30 constitutes a MIM (Metal-Insulator-Metal) capacitor. The conductive layer 115 is also called a "lower electrode," and the conductive layer 120 is also called an "upper electrode."

[0133] 15 , 16A to 16C and 17A to 17C , an opening 190 is provided in the insulating layer 160, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed within the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 within the opening 190, and a region in contact with the side surface of the insulating layer 160 within the opening 190. The insulating layer 121 and the conductive layer 120 are disposed so that at least a portion thereof is located within the opening 190.

[0134] The conductive layer 120 has a region inside the opening 190 that faces the conductive layer 115 with the insulating layer 121 sandwiched therebetween. Therefore, the capacitive element 30 is configured such that the upper electrode and the lower electrode face each other with a dielectric sandwiched between them not only on the bottom surface but also on the side surfaces within the opening 190. This allows the capacitance per unit area to be greater than, for example, when the capacitive element 30 is a planar capacitor. The capacitance of the capacitive element 30 can be increased as the depth of the opening 190 is increased. Increasing the capacitance per unit area of ​​the capacitive element 30 in this way stabilizes the read operation of the semiconductor device. Furthermore, miniaturization and high integration of semiconductor devices can be promoted.

[0135] 16A and 16C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the semiconductor device can be achieved.

[0136] A conductive layer 115 and an insulating layer 121 are stacked along the sidewall of the opening 190 and the upper surface (bottom surface of the recess) of the conductive layer 110. A conductive layer 120 is also provided so as to fill the opening 190. A capacitance element 30 having such a configuration can be called a trench-type capacitance or a trench capacitance.

[0137] [Transistor 20] The transistor 20 includes a conductive layer 120, a conductive layer 240 over an insulating layer 280, a metal oxide layer 230 over the conductive layer 120 and the conductive layer 240, an insulating layer 250 over the metal oxide layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is provided over the conductive layer 120.

[0138] The metal oxide layer 230 functions as a semiconductor layer of the transistor 20. The conductive layer 260 functions as a gate electrode of the transistor 20. The insulating layer 250 functions as a gate insulating layer of the transistor 20. The conductive layer 120 functions as one of a source electrode and a drain electrode of the transistor 20. The conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor 20. Here, the conductive layer 260 is provided to extend in the Y direction. The conductive layer 260 functions as a wiring WL.

[0139] 15 , 16A to 16C, and 17A to 17C, the insulating layer 280 has a groove 290 that partially reaches the conductive layer 120. The groove 290 extends in a direction parallel to the extension direction of the conductive layer 260. That is, the groove 290 extends in the Y direction, similar to the conductive layer 260. As described above, the conductive layer 245 extends in the X direction. As a result, the conductive layer 245 intersects with the groove 290 and the conductive layer 260 in a planar view, for example, perpendicularly or substantially perpendicularly to them.

[0140] In this specification and the like, a groove can be rephrased as a slit or a trench. A groove portion can be rephrased as a slit portion or a trench portion. A groove portion can be rephrased as a slit or a trench.

[0141] At least a portion of the components of the transistor 20 is disposed within the groove 290. Specifically, the metal oxide layer 230, the insulating layer 250, and the conductive layer 260 are each disposed such that at least a portion thereof is located within the groove 290. The transistors 20 included in the semiconductor devices 10 in the same column have regions located within the same groove 290.

[0142] Each transistor 20 has two conductive layers 240 that are arranged to face each other across a groove 290 in plan view. One conductive layer 240 is shared between two transistors 20 adjacent in the X direction. This allows the other of the sources and drains of the two transistors 20 to be connected.

[0143] The metal oxide layer 230 has a region in contact with the upper surface of the conductive layer 120 within the groove 290, a region in contact with the side surface of the conductive layer 240, a region in contact with the side surface of the groove 290, and a region in contact with the upper surface of the conductive layer 240 outside the groove 290. Note that, although Fig. 16A shows an example in which the metal oxide layer 230 is shared by multiple transistors 20 adjacent in the X direction, it is also possible to separate the metal oxide layer 230 between the transistors 20. In other words, it is possible to provide the metal oxide layer in an island shape.

[0144] The insulating layer 250 is provided in the groove 290 so as to cover the metal oxide layer 230. The insulating layer 250 has a recess at a position overlapping the groove 290. Note that although an example in which the insulating layer 250 is shared by all the transistors 20 is shown in FIGS. 16A and 16C , it is also possible that the insulating layer 250 is not shared between the transistors 20 adjacent to each other in the X direction, for example. For example, the insulating layer 250 can be processed so that its shape in plan view is the same as or approximately the same as the conductive layer 260.

[0145] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the groove 290 that faces the metal oxide layer 230 with the insulating layer 250 sandwiched therebetween.

[0146] As described above, the metal oxide layer 230 is provided in the groove 290. In addition, the transistor 20 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 120) is located on the bottom and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located on the top, so that current flows in the vertical direction. In other words, a channel is formed along the sidewall of the groove 290.

[0147] The above configuration allows the channel formation region, source region, and drain region to be formed in the groove 290. This allows the transistor 20 to occupy a smaller area than a planar transistor in which the channel formation region, source region, and drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

[0148] 15 , 16A to 16C and 17A to 17C , the transistor 20 is provided so as to have an area overlapping with the capacitive element 30. Furthermore, the opening 190 in which part of the structure of the capacitive element 30 is provided has an area overlapping with the groove 290 in which part of the structure of the transistor 20 is provided. This allows the area occupied by the semiconductor device 10 to be reduced compared to, for example, a case in which the opening 190 does not overlap with the groove 290. This allows for miniaturization or high integration of the semiconductor device.

[0149] The insulating layer 285 is located on the conductive layer 260 and the insulating layer 250. The insulating layer 285, the insulating layer 250, and the metal oxide layer 230 have an opening 270 that reaches the conductive layer 240. A conductive layer 244 is provided in the opening 270. For example, the conductive layer 244 is provided so as to fill the opening 270. The conductive layer 244 may have a region in contact with the conductive layer 240 within the opening 270. Note that, for example, when the metal oxide layer 230 and the insulating layer 250 are not shared between multiple transistors 20 adjacent in the X direction, the opening 270 may not be provided in the metal oxide layer 230 and the insulating layer 250.

[0150] The conductive layer 245 is provided on the insulating layer 285 and the conductive layer 244 and can be in contact with the top surface of the conductive layer 244. This allows the conductive layer 245 to be connected to the conductive layer 244. As described above, the conductive layer 244 is connected to the conductive layer 240. As described above, the conductive layer 245 is provided to extend in the X direction. The conductive layer 245 functions as a source wiring or a drain wiring. Specifically, when the conductive layer 240 functions as a source electrode, the conductive layer 245 functions as a source wiring, and when the conductive layer 240 functions as a drain electrode, the conductive layer 245 functions as a drain wiring. By providing the conductive layer 245 to extend in the X direction, the conductive layers 240 of the multiple transistors 20 arranged in the X direction can be connected to each other.

[0151] The conductive layer 245 overlaps with the conductive layer 260 with the insulating layer 285 interposed therebetween. This allows the physical distance between the bit line and the conductive layer 260 to be larger than, for example, when the conductive layer 240 is extended in the Y direction as a bit line without providing the conductive layer 245. Therefore, the parasitic capacitance generated between the bit line and the conductive layer 260 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device that operates at high speed. Note that the height of the top surface of the conductive layer 244 and the height of the top surface of the insulating layer 285 are preferably aligned or approximately aligned.

[0152] FIG. 18A is an enlarged view of the transistor 20 shown in FIG. 16A.

[0153] The channel length of the transistor 20 is the distance between the source region and the drain region in the metal oxide layer 230. In Fig. 18A, the channel length L of the transistor 20 is indicated by a double-headed arrow. The channel length L is the distance between the end of the region where the metal oxide layer 230 and the conductive layer 240 contact each other and the end of the region where the metal oxide layer 230 and the conductive layer 120 contact each other in a cross-sectional view.

[0154] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 20 can be set by, for example, the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 20 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 20, thereby improving the frequency characteristics.

[0155] Note that the channel length of the transistor 20 is determined by the film thickness of the insulating layer 280 and the like. Therefore, the channel length does not affect the area occupied by the transistor 20, for example, the area of ​​the transistor 20 in a plan view. By setting the channel length of the transistor 20 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the groove 290 and the like.

[0156] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0157] 18A shows an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. Also, an example in which the conductive layer 120 has a two-layer structure of a conductive layer 120_1 and a conductive layer 120_2 over the conductive layer 120_1. Furthermore, an example in which the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1 is shown.

[0158] 18A illustrates a configuration in which the upper surface of the conductive layer 120 has a recess. Specifically, the upper surface of the conductive layer 120_2 has a recess. The bottom surface of the recess corresponds to the bottom surface of the recess of the conductive layer 120_2. The side surface of the recess corresponds to the side surface of the recess of the conductive layer 120_2.

[0159] The recess of the conductive layer 120_2 is provided at a position overlapping the groove 290. Here, the bottom of the groove 290 includes the bottom surface of the recess of the conductive layer 120_2. The sidewall of the groove 290 includes the side surface of the recess of the conductive layer 120_2 and the side surface of the insulating layer 280.

[0160] By providing a recess in a position where the conductive layer 120_2 overlaps with the groove 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the groove 290 can be made lower than the height of the top surface of the conductive layer 120_2 that is in contact with the insulating layer 280, compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is formed. Note that the surface used as the reference is not limited to the surface on which the transistor is formed. For example, the top surface of a substrate on which the semiconductor device is provided can also be used as the reference.

[0161] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the channel formation region of the metal oxide layer 230. This can improve the electrical characteristics of the transistor 20. In addition, a gate electric field can be easily applied to a region of the metal oxide layer 230 in contact with the conductive layer 120_2. This can increase the on-state current of the transistor 20. Furthermore, regardless of whether the conductive layer 120 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 20 can be improved.

[0162] 18A , for example, shows an example in which the opening 270 is provided not only in the insulating layer 285, the insulating layer 250, and the metal oxide layer 230, but also in the conductive layer 240_2. Also, for example, FIG. 18A shows an example in which the opening 270 reaches the conductive layer 240_1. In this case, the conductive layer 244 can have a region in contact with the top surface of the conductive layer 240_1 and the side surface of the conductive layer 240_2. By having the conductive layer 244 in contact with the top surface of the conductive layer 240, the contact resistance between the conductive layer 240 and the conductive layer 244 can be reduced, even if, for example, the contact resistance per unit area between the conductive layer 240_2 and the conductive layer 244 is greater than the contact resistance per unit area between the conductive layer 240_1 and the conductive layer 244. Furthermore, by having the conductive layer 244 in contact with the side surface of the conductive layer 240_2, the contact area between the conductive layer 240 and the conductive layer 244 can be increased compared to when the conductive layer 244 is in contact only with the top surface of the conductive layer 240. This can reduce the contact resistance between the conductive layer 240 and the conductive layer 244. Note that the conductive layer 240_2 does not necessarily have to have the opening 270. In this case, the opening 270 reaches the top surface of the conductive layer 240_2. When the conductive layer 240_2 does not have the opening 270, the opening 270 can be formed more easily than when the conductive layer 240_2 has the opening 270.

[0163] 18A , the opening 270 includes an opening in the insulating layer 285, an opening in the insulating layer 250, an opening in the metal oxide layer 230, and an opening in the conductive layer 240_2. Note that the shape and size of the opening 270 in a plan view may differ depending on the layer. Furthermore, when the shape of the opening 270 in a plan view is circular, the openings in each layer may or may not be concentric.

[0164] 18B is an enlarged view of the capacitive element 30 shown in FIG. 16A. For example, FIG. 18B illustrates a configuration in which the upper surface of the conductive layer 110 has a recess. The recess is provided at a position overlapping the opening 190. Here, the bottom of the opening 190 includes the bottom surface of the recess in the conductive layer 110. Furthermore, the sidewall of the opening 190 includes the side surface of the recess in the conductive layer 110 and the side surface of the insulating layer 160.

[0165] By providing a recess in the conductive layer 110 at a position overlapping the opening 190, the contact area between the conductive layer 110 and the conductive layer 115 can be increased compared to when the recess is not provided, and therefore the contact resistance between the conductive layer 110 and the conductive layer 115 can be reduced.

[0166] The conductive layer 115 has a region 101 with curved corners within the recess of the conductive layer 110. This allows for more suppression of electric field concentration in the insulating layer 121 near the region 101 than when the region 101 has a corner. Furthermore, the end 103 of the conductive layer 115 is located at a lower height from the reference plane than the top surface of the insulating layer 160. This allows for more suppression of electric field concentration in the insulating layer 121 near the end 103 than when the end 103 is located on the insulating layer 160. As described above, suppressing electric field concentration in the insulating layer 121 prevents dielectric breakdown of the insulating layer 121, thereby providing a highly reliable semiconductor device. For example, FIG. 18B shows an example in which the region 102 between the top surface of the insulating layer 160 and the side surface of the opening 190 has a curved portion.

[0167] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment can have a single-layer structure or a stacked structure of two or more layers.

[0168] [Metal Oxide Layer] As described above, the metal oxide layer 230 has a channel formation region. The metal oxide layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The metal oxide layer 230 can have a single-layer structure or a stacked structure of two or more layers.

[0169] The crystallinity of the semiconductor material used for the metal oxide layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0170] The transistor 20 preferably includes a metal oxide functioning as a semiconductor (also referred to as an "oxide semiconductor") in the metal oxide layer 230 including a channel formation region. When a metal oxide functioning as a semiconductor is used for the metal oxide layer 230, the transistor 20 can be referred to as an OS transistor.

[0171] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0172] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. ＯThe source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0173] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the metal oxide layer 230, the off-state current of the transistor 20 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0174] For example, examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide (In oxide, indium oxide). Examples of the metal oxide include zinc oxide (Zn oxide, zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0175] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0176] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0177] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0178] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0179] Note that a semiconductor device according to one embodiment of the present invention can also include a transistor whose channel formation region includes another semiconductor material, such as a semiconductor made of a single element or a compound semiconductor.

[0180] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0181] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. Impurities can be included as dopants in these semiconductor materials.

[0182] In addition, the semiconductor device of this embodiment mode can also use a transistor in which a layer material functioning as a semiconductor is used for a channel formation region. Note that the layer material will be described in detail in Embodiment Mode 5.

[0183] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 180, insulating layer 160, insulating layer 121, insulating layer 280, insulating layer 250, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film can also be used for the insulating layer of the semiconductor device.

[0184] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0185] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0186] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0187] It is preferable to use the above-mentioned material having a high relative dielectric constant for the insulating layer 121. By using a material having a high relative dielectric constant for the insulating layer 121, the insulating layer 121 can be made thick enough to suppress leakage current and the capacitance of the capacitive element 30 can be sufficiently ensured.

[0188] Furthermore, the insulating layer 121 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a layered structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 121 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 121 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 121 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element 30 can be suppressed.

[0189] Furthermore, by using the above-mentioned material capable of having ferroelectricity for the insulating layer 121, the capacitive element 30 can function as a ferroelectric memory.

[0190] A transistor using a metal oxide for a semiconductor layer in which a channel is formed can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0191] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also included are nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Also included are nitride oxides such as silicon nitride oxide.

[0192] Furthermore, an insulating layer such as a gate insulating layer that is in contact with a metal oxide layer or that is provided near the metal oxide layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is located in contact with or near the metal oxide layer, oxygen vacancies in the metal oxide layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0193] An insulating layer provided in contact with or near a metal oxide layer is preferably a barrier insulating layer against hydrogen, since the insulating layer has a barrier property against hydrogen, which can suppress diffusion of hydrogen into the metal oxide layer.

[0194] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0195] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure can be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0196] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0197] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0198] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0199] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that makes the corresponding substance less permeable, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0200] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0201] Examples of materials for the barrier insulating layer against oxygen include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0202] The insulating layer 180, the insulating layer 160, the insulating layer 280, and the insulating layer 285 function as interlayer films, and therefore, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer films, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 180, the insulating layer 160, the insulating layer 280, and the insulating layer 285.

[0203] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the metal oxide layer 230.

[0204] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not use hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a portion of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the metal oxide layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0205] Since the thickness of the insulating layer 280 on the conductive layer 120 affects the channel length of the transistor 20 , the thickness of the insulating layer 280 is set appropriately according to the design value of the channel length of the transistor 20 .

[0206] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 250. When the insulating layer 250 provided on the metal oxide layer 230 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen contained in the conductive layer 260 into the metal oxide layer 230. For example, a silicon nitride film has a high barrier property against hydrogen and is therefore suitable as the insulating layer 250.

[0207] Furthermore, since the insulating layer 250 is in contact with the metal oxide layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the metal oxide layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the metal oxide layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0208] Furthermore, it is preferable to use an insulating layer having a region containing excess oxygen as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the metal oxide layer 230, thereby reducing oxygen vacancies in the metal oxide layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable as the insulating layer 250 because it has a structure that is stable against heat.

[0209] For example, FIG. 16A shows an example in which the insulating layer 250 has a single-layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the metal oxide layer 230 and a function of suppressing diffusion of hydrogen into the metal oxide layer 230.

[0210] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the metal oxide layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the metal oxide layer 230 can be reduced and diffusion of hydrogen into the metal oxide layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0211] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the metal oxide layer 230 can be reduced, and diffusion of hydrogen into the metal oxide layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0212] Furthermore, for example, the insulating layer 250 may have a third insulating layer between the metal oxide layer 230 and the first insulating layer. In other words, the insulating layer 250 may have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0213] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the metal oxide layer 230, oxygen can be supplied to the metal oxide layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, it is possible to suppress a decrease in the amount of oxygen supplied from the third insulating layer to the metal oxide layer 230.

[0214] Furthermore, for example, the insulating layer 250 may have a fourth insulating layer between the metal oxide layer 230 and the third insulating layer. In other words, the insulating layer 250 may have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0215] It is preferable to use an insulating layer having a barrier property against oxygen as the fourth insulating layer. Note that the same configuration as that of the layers used in the three-layer structure described above can be applied to the first to third insulating layers. The fourth insulating layer is a layer in contact with the metal oxide layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the metal oxide layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 20.

[0216] For example, an aluminum oxide film may be used as the fourth insulating layer. Since an aluminum oxide film has a function of capturing or fixing hydrogen, it is suitable as the fourth insulating layer in contact with the metal oxide layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the metal oxide layer 230 side.

[0217] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the "S value"), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0218] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0219] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are set to 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0220] It is also possible to configure the insulating layer 250 having a four-layer structure without providing the second insulating layer. For example, it is possible to use an insulating layer having a barrier property against oxygen as the fourth insulating layer, an insulating layer made of a material with a low relative dielectric constant as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer. Specifically, it is possible to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the metal oxide layer 230 side.

[0221] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0222] [Conductive Layer] The conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 240, conductive layer 260, conductive layer 244, conductive layer 245, etc.) included in the semiconductor device preferably include a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above-mentioned metal element, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element, a nitride of the alloy or an oxide of the alloy can be used. For example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0223] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide, also referred to as “ITO”), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as “ITSO”), indium zinc oxide (In—Zn oxide, also referred to as “IZO” (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0224] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0225] In addition, it is possible to use a plurality of stacked conductive layers formed from the above materials. For example, a stacked structure combining the above-mentioned material containing a metal element and a conductive material containing oxygen can be used. In addition, a stacked structure combining the above-mentioned material containing a metal element and a conductive material containing nitrogen can be used. In addition, a stacked structure combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can be used.

[0226] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0227] A conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as the wiring PL.

[0228] The conductive layer 115 is preferably formed using a single layer or a stacked layer of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride, ITSO, or the like can be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten can be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and then a second titanium nitride is stacked on the tungsten can be used. With such a structure, when an oxide is used for the insulating layer 121, the insulating layer 121 can suppress oxidation of the conductive layer 115. Furthermore, when an oxide is used for the insulating layer 160, the insulating layer 160 can suppress oxidation of the conductive layer 115.

[0229] The conductive layer 120 and the conductive layer 240 are each conductive layers in contact with the metal oxide layer 230. Therefore, for the conductive layer 120 and the conductive layer 240, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an "oxide conductor"), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120 and the conductive layer 240.

[0230] By using a conductive material containing oxygen for the conductive layer 120, the conductive layer 120 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, it is preferable to use, for example, ITO, ITSO, In—Zn oxide, or the like for each of the conductive layer 120 and the conductive layer 240.

[0231] When the conductive layer 120 and the conductive layer 240 each have a stacked structure, the contact resistance between the conductive layer 120 and the metal oxide layer 230 and between the conductive layer 240 and the metal oxide layer 230 can be reduced by using a conductive material containing oxygen in the layer of the stacked structure that has the largest contact area with the metal oxide layer 230.

[0232] For example, the conductive layer 120 shown in FIG. 18A has a two-layer structure including a conductive layer 120_1 and a conductive layer 120_2 over the conductive layer 120_1. In this case, for example, a conductive material containing oxygen is preferably used for the conductive layer 120_2. Furthermore, a material having higher conductivity than the conductive layer 120_2 is preferably used for the conductive layer 120_1. Specifically, an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) is preferably used for the conductive layer 120_2, and tungsten is preferably used for the conductive layer 120_1. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like can be used for the conductive layer 120_1. By using an oxide conductor for the conductive layer 120_2 that is mainly in contact with the metal oxide layer 230, the contact resistance with the metal oxide layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 120, the conductivity of the conductive layer 120 can be increased.

[0233] Note that a conductive material containing oxygen can be used for the conductive layer 120_1, and a material having higher conductivity than the conductive layer 120_1 can be used for the conductive layer 120_2. In this case, the material with higher conductivity is used for the layer of the conductive layer 120 that is closest to the channel formation region of the metal oxide layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 20 can be increased.

[0234] For example, the conductive layer 240 shown in FIG. 18A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, a conductive material containing oxygen is preferably used for the conductive layer 240_2. Furthermore, a material having higher conductivity than the conductive layer 240_2 is preferably used for the conductive layer 240_1. Specifically, an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) is preferably used for the conductive layer 240_2, and tungsten is preferably used for the conductive layer 240_1. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like can be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the metal oxide layer 230, the contact resistance with the metal oxide layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of each conductive layer 240 can be increased.

[0235] Note that the conductive layer 240_1 may be formed using a conductive material containing oxygen, and the conductive layer 240_2 may be formed using a material having higher conductivity than the conductive layer 240_1. In this case, an oxide conductor is used for the conductive layer 240 that is closest to the channel formation region of the metal oxide layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 20 can be increased.

[0236] The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 260. As described above, examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0237] The conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive layer 260 may contain the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.). Alternatively, one or more materials selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0238] 18A shows an example in which the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. By using a conductive material having a function of suppressing oxygen diffusion as the conductive layer 260_1, for example, release of oxygen from the metal oxide layer 230 can be suppressed, and formation of oxygen vacancies in the metal oxide layer 230 can be suppressed.

[0239] Furthermore, by using a conductive material that is resistant to oxidation as the conductive layer 260_1, it is possible to prevent the conductive layer 260_1 from being oxidized and its conductivity from being reduced due to, for example, the release of oxygen from the metal oxide layer 230 or the release of oxygen from the insulating layer 250.

[0240] The material used for the conductive layer 260_2 preferably has higher conductivity than the material used for the conductive layer 260_1, for example. In addition, by increasing the thickness of the conductive layer 260_2, the current flowing through the conductive layer 260_2 can be increased.

[0241] By using a deposition method with high coverage for the conductive layer 260_1, the conductive layer 260_1 can be suitably formed along the sidewall of the groove 290.

[0242] The conductive layer 260_1 can be, for example, a conductive material containing nitrogen, a conductive material containing oxygen, or the like. Alternatively, the conductive layer 260_1 can be, for example, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.

[0243] For example, a conductive material containing the above-mentioned metal element and nitrogen can be used as the conductive layer 260_1, such as tantalum nitride, titanium nitride, ruthenium nitride, a nitride containing molybdenum, a nitride containing tungsten, titanium, and aluminum, or a nitride containing tantalum and aluminum.

[0244] Furthermore, for example, a conductive material containing the above-mentioned metal element and oxygen can be used as the conductive layer 260_1, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.

[0245] In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon can be used. Indium gallium zinc oxide containing nitrogen can also be used.

[0246] Furthermore, as the conductive layer 260_1, a material containing titanium, tantalum, ruthenium, or one or more selected from these metal elements is preferable because it is a conductive material that is resistant to oxidation, a conductive material that has the function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen.

[0247] The conductive layer 260_2 can be formed using, for example, any of the above metal elements, alloys containing the above metal elements, alloys of a combination of the above metal elements, etc. For example, tungsten can be used.

[0248] The conductive layer 260_1 can further have a stacked structure. The conductive layer 260_2 can further have a stacked structure. When the conductive layer 260_1 has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260_1 can be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention can be stacked. When the conductive layer 260_2 has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260_2 can be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention can be stacked.

[0249] The conductive layer 244 and the conductive layer 245 can be formed using a material that can be used for the conductive layer 240. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 244 and the conductive layer 245. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0250] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of other substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements can be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0251] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0252] Embodiment 3 In this embodiment, a semiconductor device 900A according to one embodiment of the present invention will be described. The semiconductor device 900A includes a plurality of semiconductor devices 10 according to one embodiment of the present invention and functions as a memory device.

[0253] Fig. 19A shows a block diagram illustrating a configuration example of a semiconductor device 900A. Figs. 19B and 19C are schematic perspective views of the semiconductor device 900A. The semiconductor device 900A shown in Fig. 19A has a drive circuit 910 and a memory cell array 100. The memory cell array 100 has a plurality of semiconductor devices 10. Fig. 19A shows an example in which the memory cell array 100 has a plurality of semiconductor devices 10 arranged in a matrix. The semiconductor devices 10 function as memory cells.

[0254] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0255] In the semiconductor device 900A, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0256] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0257] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900 A. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900 A. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0258] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0259] The peripheral circuit 911 is a circuit for writing and reading data to and from the semiconductor device 10. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927. The sense amplifier 927 corresponds to, for example, the sense amplifier 50 described in the above embodiment.

[0260] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the semiconductor device 10, the function of reading data from the semiconductor device 10, the function of holding the read data, etc.

[0261] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the semiconductor device 10. The data (Dout) read from the semiconductor device 10 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900A. The data output from the output circuit 926 is a signal RDA.

[0262] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply potential of the semiconductor device 900A is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 19A, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0263] 19B , the semiconductor device 900A can be configured such that a drive circuit 910 is provided in the element layer 70, a memory cell array 100 is provided in the element layer 80, and the element layer 80 is stacked on the element layer 70. For example, a single-crystal silicon substrate is used as the element layer 70, and the drive circuit 910 is formed on the silicon substrate. By forming the channel formation region of the Si transistor included in the drive circuit 910 on the silicon substrate, a Si transistor having a single-crystal semiconductor in the channel formation region and having a high operating speed can be formed.

[0264] For example, an SOI (Silicon on Insulator) substrate or the like can be used as the element layer 70. Examples of SOI substrates that can be used include SIMOX (Separation by Implanted Oxygen) substrates formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that occur in the surface layer, Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, and ELTRAN method (registered trademark: Epitaxial Layer Transfer). Si transistors fabricated using SOI substrates have reduced parasitic capacitance and can achieve high-speed operation.

[0265] Furthermore, because OS transistors are thin film transistors, they can easily be provided as the element layer 80 overlapping the element layer 70. In addition, as described above, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in characteristics. Therefore, even if the memory cell array 100 including OS transistors is provided overlapping the driver circuit 910 including Si transistors, it is less susceptible to the heat generated by the driver circuit 910. This improves the reliability of the semiconductor device 900A.

[0266] 19C , it is possible to provide a plurality of element layers 80 including memory cell arrays 100 stacked on an element layer 70 including a driver circuit 910. FIG. 19C shows an example in which k (k is an integer of 2 or more) element layers 80 are stacked on the element layer 70. In FIG. 19C , the first element layer 80 provided on the element layer 70 is shown as element layer 80[1], and the kth element layer 80 is shown as element layer 80[k]. Furthermore, the memory cell array 100 provided in the element layer 80[k] is shown as memory cell array 100[k].

[0267] By stacking the element layer 70 including the driver circuit 910 and the element layer 80 including the memory cell array 100, the signal propagation distance between the driver circuit 910 and the memory cell array 100 can be shortened. Therefore, the parasitic resistance and parasitic capacitance between the driver circuit 910 and the memory cell array 100 are reduced, and power consumption and signal delay can be reduced. Furthermore, the semiconductor device 900A can be miniaturized. Furthermore, the memory capacity per unit area can be increased.

[0268] 20A to 20D show a configuration example of a semiconductor device 900B, which is a modified example of the semiconductor device 900A. Fig. 20A is a schematic perspective view of the semiconductor device 900B. Fig. 20B is a block diagram illustrating the configuration of the semiconductor device 900B. Fig. 20C is a circuit diagram of a semiconductor device 10 functioning as a memory cell. Fig. 20D is a circuit diagram of a semiconductor device 15 functioning as a memory cell.

[0269] The semiconductor device 900B has a configuration including an element layer 75 between an element layer 70 and an element layer 80. The element layer 75 has a memory cell array 200. The memory cell array 200 has a plurality of semiconductor devices 15 that function as memory cells. A memory cell having a different configuration from that of the semiconductor device 10 can be used as the semiconductor device 15. For example, a memory cell for a DRAM including a transistor 21 and a capacitor 31 can be used as the semiconductor device 15 ( FIG. 20D ).

[0270] In the semiconductor device 15 functioning as a DRAM memory cell, a paraelectric material is used as the dielectric constituting the capacitive element 31, rather than a ferroelectric material. By using a paraelectric material as the dielectric constituting the capacitive element 31, a memory cell with faster data write and read speeds than the semiconductor device 10 can be realized. A capacitive element using a paraelectric material as the dielectric is sometimes called a "paraelectric capacitor." Furthermore, it is preferable to use an OS transistor similar to the transistor 20 as the transistor 21 constituting the semiconductor device 15 functioning as a DRAM memory cell. Since an OS transistor has a low off-state current, the refresh frequency of the semiconductor device 15 can be reduced. Therefore, the power consumption of the semiconductor device 15 can be reduced.

[0271] The wiring BL provided in each of the element layers 75 and 80 is connected to the drive circuit 910 via the wiring GBL. Note that the semiconductor device 10 functioning as a memory cell of an FeRAM and the semiconductor device 15 functioning as a memory cell of a DRAM have different data writing and reading methods. For this reason, the wiring BL and wiring GBL connected to the semiconductor device 15 are preferably connected to the drive circuit 910 via the switching circuit 60.

[0272] The switching circuit 60 has a function of selecting whether to connect the driver circuit 910 to the wiring BL of the element layer 75 or to connect the driver circuit 910 to the wiring BL of the element layer 80. For example, when data is written and read relatively frequently, the driver circuit 910 can be connected to the element layer 75 (DRAM) which has a faster operating speed than the element layer 80 (FeRAM).

[0273] Furthermore, when the frequency of writing and reading data is relatively low and data is to be held for a long period of time, it is possible to connect to the element layer 80 (FeRAM) which can hold data for a longer period of time than the element layer 75 (DRAM).

[0274] By combining memory cells of different storage methods as in the semiconductor device 900B, it is possible to improve the operating speed, reduce power consumption, and improve the data retention period.

[0275] 21A , it is preferable to provide a switch 61 for each of the wirings BL included in the element layer 75 and the element layer 80, and to connect the wirings BL and GBL via the switch 61. By connecting only the wiring BL of the layer from which data is read or written to the wiring GBL, the parasitic capacitance of the wirings BL and GBL is reduced, and signal delay is reduced. Therefore, the operating speed of the semiconductor device 900B can be increased. Furthermore, the power consumption of the semiconductor device 900B can be reduced.

[0276] 21B , a selection circuit SEL can be provided in the element layer 70. In a semiconductor device 900B shown in FIG. 21B , the driver circuit 910 and the selection circuit SEL are connected via wiring GBL, and each of the wirings BL included in the element layer 75 and the element layer 80 is connected to the wiring GBL via the selection circuit SEL. That is, each of the wirings BL included in the element layer 75 and the element layer 80 is connected to the wiring GBL via the driver circuit 910.

[0277] The selection circuit SEL has a function of connecting only the wiring BL of the layer from which data is read or written to the wiring GBL. Only the wiring BL selected by the selection circuit SEL is connected to the driver circuit 910 via the wiring GBL. This reduces the parasitic capacitance of the wiring BL and the wiring GBL, thereby reducing signal delay. This can increase the operating speed of the semiconductor device 900B. Furthermore, the power consumption of the semiconductor device 900B can be reduced.

[0278] Although the selection circuit SEL can be provided in the element layer 75 or the element layer 80, it is preferable to provide it near the driver circuit 910 in order to enhance the effect of improving signal delay. Therefore, it is preferable to provide the selection circuit SEL in the element layer 70. Furthermore, for example, when a single-crystal silicon substrate is used as the element layer 70, providing the selection circuit SEL in the element layer 70 can realize a selection circuit SEL with a high operating speed.

[0279] Fig. 22 shows an example of a cross-sectional structure of a portion of the semiconductor device 900B. Fig. 22 illustrates a transistor 400 as an example of a transistor included in the element layer 70. Fig. 22 also illustrates a semiconductor device 15 included in the element layer 75 and a semiconductor device 10 included in the element layer 80.

[0280] The transistor 400 is provided over a substrate 371 and includes a conductive layer 376 that functions as a gate electrode, an insulating layer 375 that functions as a gate insulating layer, a semiconductor region 373 that is part of the substrate 371, and low-resistance regions 374a and 374b that are part of the substrate 371 and function as source and drain regions. The transistor 400 can be either a p-channel transistor or an n-channel transistor. The substrate 371 can be, for example, a single-crystal silicon substrate.

[0281] In the transistor 400, a semiconductor region 373 (a part of the substrate 371) where a channel is formed has a convex shape. A conductive layer 376 is provided to cover the side and top surfaces of the semiconductor region 373 with an insulating layer 375 interposed therebetween. Note that the conductive layer 376 may be formed using a material that adjusts the work function. Such a transistor is also called a Fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may also be provided. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape can also be formed by processing an SOI (Silicon on Insulator) substrate.

[0282] The driver circuit 910 includes a plurality of transistors 400. Note that the transistor 400 can be used not only as a transistor included in the driver circuit 910 but also as a transistor included in the selection circuit SEL or the like. Note that the transistor 400 shown in FIG. 22 is an example and is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration or the driving method.

[0283] The element layer 70 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, wiring and plugs may be integrated. That is, there may be cases where a part of the conductive layer functions as wiring and where a part of the conductive layer functions as plugs.

[0284] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 392 and the like are embedded in the insulating layer 390 and the insulating layer 391. A conductive layer 395, a conductive layer 397, and the like are embedded in the insulating layer 393 and the insulating layer 394. The conductive layer 392 and the conductive layer 395 function as contact plugs or wirings.

[0285] In addition, the insulating layer functioning as an interlayer film can also function as a planarizing film that covers the uneven shape below it. For example, by performing CMP treatment or the like on the top surface of the insulating layer 391 to improve the planarity, the insulating layer 391 can function as a planarizing film.

[0286] 22, an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 385, a conductive layer 386, and a conductive layer 397 are formed in the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 385, the conductive layer 386, and the conductive layer 397 function as contact plugs or wirings.

[0287] Moreover, an insulating layer 180 of the element layer 75 is provided on the insulating layer 384. The element layer 75 includes a capacitor 31 using a paraelectric material as a dielectric and a transistor 21, and is provided with a semiconductor device 15 that functions as a memory cell. In FIG. 22 , the insulating layer that functions as the dielectric of the capacitor 31 is shown as an insulating layer 121a. Furthermore, in the semiconductor device 15, the transistor 21 is provided overlapping the capacitor 31. In the semiconductor device 15, the capacitor 31 and the transistor 21 have overlapping regions. By providing the capacitor 31 and the transistor 21 overlapping each other, the area occupied by the semiconductor device 15 can be reduced.

[0288] The element layer 80 includes a capacitor 30 using a ferroelectric material as a dielectric and a transistor 20, and is provided with a semiconductor device 10 that functions as a memory cell. In the semiconductor device 10, the transistor 20 is provided overlapping the capacitor 30. In the semiconductor device 10, the capacitor 30 and the transistor 20 have overlapping regions. By providing the capacitor 30 and the transistor 20 overlapping each other, the area occupied by the semiconductor device 10 can be reduced.

[0289] The semiconductor device 10 and the semiconductor device 15 are connected to any one of a plurality of transistors 400 via a conductive layer (not shown).

[0290] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0291] Embodiment 4 In this embodiment, an example of a processing unit that can include a semiconductor device according to one embodiment of the present invention will be described.

[0292] Fig. 23 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in Fig. 23 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0293] The arithmetic device 960 shown in FIG. 23 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0294] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0295] As will be described later, a memory cell array 920 can be provided by stacking it on the arithmetic unit 960. The memory cell array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory cell array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0296] It is also possible to use only the memory cell array 920 as a cache without providing the cache 999 .

[0297] The arithmetic device 960 shown in FIG. 23 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 23 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0298] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0299] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0300] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0301] 23, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 996 can be stopped.

[0302] The memory cell array 920 and the arithmetic device 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 24A and 24B. The semiconductor device 970A has a layer 930 on which a memory cell array is provided, on an arithmetic device 960. The layer 930 is provided with a memory cell array 920L1, a memory cell array 920L2, and a memory cell array 920L3. The arithmetic device 960 and each memory cell array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in FIG. 24B.

[0303] By overlapping the layer 930 having the memory cell array and the arithmetic device 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, the short connection distance can reduce power consumption.

[0304] As a method for stacking the layer 930 having the memory cell array and the arithmetic device 960, a method (also called "monolithic stacking") in which the layer 930 having the memory cell array is stacked directly on the arithmetic device 960 can be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and connection is made using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) can be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0305] Here, the arithmetic device 960 does not have a cache 999, and the memory cell arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory cell array 920L1 can be used as an L1 cache (also referred to as a "level 1 cache"), the memory cell array 920L2 can be used as an L2 cache (also referred to as a "level 2 cache"), and the memory cell array 920L3 can be used as an L3 cache (also referred to as a "level 3 cache"). Of the three memory cell arrays, the memory cell array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory cell array 920L1 has the smallest capacity and the highest access frequency.

[0306] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory cell array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0307] 24B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory cell array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory cell array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory cell array 920L3 via a connection electrode 940L3.

[0308] Although the number of memory cell arrays functioning as a cache is three in this example, the number of memory cell arrays may be one or two, or may be four or more.

[0309] When the memory cell array 920L1 is used as a cache, the drive circuit 910L1 can function as part of the cache interface 989, and it is also possible to configure the drive circuit 910L1 to be connected to the cache interface 989. Similarly, the drive circuits 910L2 and 910L3 can also function as part of the cache interface 989, or be configured to be connected thereto.

[0310] Whether the memory cell array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. Based on a signal supplied from the arithmetic device 960, the control circuit 912 can make some of the plurality of semiconductor devices 10 or the plurality of semiconductor devices 15 included in the semiconductor device 900 (semiconductor device 900A or semiconductor device 900B) function as RAM.

[0311] The semiconductor device 900 can cause some of the semiconductor devices 10 or 15 functioning as memory cells to function as cache, and the other parts to function as main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

[0312] It is also possible to provide a layer 930 having one memory cell array 920 overlapping the arithmetic device 960. Fig. 25A shows a perspective view of a semiconductor device 970B.

[0313] In the semiconductor device 970B, one memory cell array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 25A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0314] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0315] Furthermore, a plurality of memory cell arrays can be stacked. Figure 25B shows a perspective view of a semiconductor device 970C.

[0316] The semiconductor device 970C includes a layer 930L1 having a memory cell array 920L1, a layer 930L2 having a memory cell array 920L2 on top of that, and a layer 930L3 having a memory cell array 920L3 on top of that. The memory cell array 920L1, which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory cell array 920L3, which is farthest from the arithmetic device 960, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory cell array to be increased, thereby further improving processing power.

[0317] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0318] Embodiment 5 In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0319] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 26 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 26, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0320] In FIG. 26 , from the top layer of the triangle, memories integrated as registers into arithmetic processing devices such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an NPU (Neural Processing Unit), cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs (Dynamic Random Access Memory), and storage memories such as 3D NANDs and HDDs (Hard Disk Drives) are shown.

[0321] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0322] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0323] The memory device according to one embodiment of the present invention can function as a DRAM.

[0324] 26 illustrates only up to the L3 cache as a cache memory, but the present invention is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0325] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0326] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0327] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0328] The memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits by using OS transistors. Furthermore, the use of OS transistors allows monolithic stacking with peripheral circuits. Therefore, this has advantages in terms of data access with peripheral circuits. Furthermore, the degree of integration can be increased by stacking with peripheral circuits. Furthermore, the use of OS transistors enables the memory device of one embodiment of the present invention to retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

[0329] Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed of rewriting, can be increased in some cases.

[0330] Furthermore, since the memory device of one embodiment of the present invention includes a capacitor including a ferroelectric material, data can be retained for a long time. Therefore, when the memory device is used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0331] The storage device of one embodiment of the present invention can be used for the Target2 area and the Target1 area shown in Figure 26. In particular, it is suitable for the Target1 area.

[0332] 26, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC mentioned above.

[0333] By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, compared to a configuration using a DRAM. Therefore, the storage device of one embodiment of the present invention is suitable for Target 1.

[0334] Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention is particularly suitable for Target1_1, which is an area of ​​Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the integration degree of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

[0335] Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and is therefore suitable for Target1_2, which is rewritten more frequently than Target1. By applying the storage device of one embodiment of the present invention to Target1_2, the computational efficiency of the storage device can be improved and power consumption can be reduced.

[0336] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called "High Performance Computers (HPCs)"), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be suppressed.

[0337] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0338] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0339] Embodiment 6 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0340] [Electronic Component] FIG. 27A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 27A has semiconductor device 710 inside mold 711. FIG. 27A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0341] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0342] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called "memory bandwidth").

[0343] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0344] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a "wafer") and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a "silicon wafer") may be called a silicon die.

[0345] 27B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0346] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0347] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0348] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0349] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0350] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0351] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. It is also possible to create a composite structure that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0352] It is also preferable to provide a heat sink (heat sink) overlapping the electronic component 730. By providing a heat sink, it is possible to reduce a performance degradation due to heat generated by the electronic component 730 itself. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0353] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 27B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 can also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0354] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0355] 28A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 is sometimes called a supercomputer.

[0356] 28B shows a perspective view of an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0357] Fig. 28C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629, etc., which are mounted on the board 5622. Note that Fig. 28C illustrates components other than electronic components 5626, 5627, and 5628.

[0358] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0359] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0360] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0361] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0362] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0363] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0364] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0365] Fig. 29A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 29A shows a planet 6804 in space as an example.

[0366] 29A , a battery management system (also referred to as a “BMS”) or a battery control circuit is provided for the secondary battery 6805. The use of an OS transistor in the BMS or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0367] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0368] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0369] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0370] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has higher reliability than a Si transistor in an environment where radiation may be incident.

[0371] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0372] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0373] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0374] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0375] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0376] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0377] Fig. 29B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 29B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0378] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 are connected to each other via a network.

[0379] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0380] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0381] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.

[0382] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0383] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0384] Embodiment 7 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0385] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0386] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0387] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 30A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 30B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0388] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 30B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 30A (see Non-Patent Document 7). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 30A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 30A.

[0389] 30A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0390] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0391] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0392] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0393] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 30A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0394] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0395] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0396] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0397] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0398] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0399] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0400] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0401] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0402] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0403] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 30C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0404] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0405] Furthermore, as shown in FIG. 30C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses from the outside into the indium oxide film permeates the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0406] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0407] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0408]

[0409] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0410] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0411] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0412] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0413] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0414] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0415] 10: semiconductor device, 15: semiconductor device, 20: transistor, 30: capacitor, 31: capacitor, 50: sense amplifier, 51: curve, 52: curve, 60: switching circuit, 61: switch, 70: element layer, 75: element layer, 80: element layer, 100: memory cell array, 101: region, 102: region, 103: end, 110: conductive layer, 115: conductive layer, 120: conductive layer, 121: insulating layer, 160: insulating layer, 180: insulating layer, 190: opening, 200: memory cell array, 230: metal oxide layer, 240: conductive layer, 244: conductive layer, 245: conductive layer, 250: insulating layer Edge layer, 260: conductive layer, 270: opening, 280: insulating layer, 285: insulating layer, 290: groove, 371: substrate, 373: semiconductor region, 375: insulating layer, 376: conductive layer, 382: insulating layer, 384: insulating layer, 385: conductive layer, 386: conductive layer, 390: insulating layer, 391: insulating layer, 392: conductive layer, 393: insulating layer, 394: insulating layer, 395: conductive layer, 396: insulating layer, 397: conductive layer, 400: transistor, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: Wire, 715: Drive circuit layer, 716: Memory layer, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 900: Semiconductor device, 910: Drive circuit, 911: Peripheral circuit, 912: Control circuit, 915: Peripheral circuit, 920: Memory cell array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 928: Voltage generation circuit, 930: Layer, 931: PSW, 932: PSW, 941: Row decoder, 942: Column decoder, 960: Arithmetic device 989: cache interface, 990: board, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component,5628: Electronic components, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6000: Storage system, 6001: Host, 6002: Storage control circuit, 6003: Storage, 6800: Artificial satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device,

Claims

a first element layer; and a second device layer on the first device layer; a third device layer on the second device layer; the first element layer includes a drive circuit and a selection circuit; the second element layer includes a plurality of first memory cells; the third element layer includes a plurality of second memory cells; the drive circuit includes a first transistor including silicon in a channel formation region; Each of the plurality of first memory cells a first capacitance element whose dielectric is a paraelectric; and a second transistor whose channel formation region includes an oxide semiconductor; Each of the plurality of second memory cells a second capacitance element whose dielectric is a ferroelectric; and a third transistor whose channel formation region includes an oxide semiconductor; the second transistor has a region overlapping the first capacitive element, the third transistor has a region overlapping the second capacitive element, The selection circuit a connection between the drive circuit and the plurality of first memory cells; The semiconductor device has a function of switching the connection between the driver circuit and the plurality of second memory cells. 　 In claim 1, The semiconductor device, wherein the oxide semiconductor contains indium.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor has crystallinity. 　 In claim 1 or claim 2, The semiconductor device wherein the ferroelectric material contains hafnium and zirconium. 　 In claim 1 or claim 2, The first element layer is a semiconductor device including single crystal silicon. m (m is an integer of 2 or more) wirings WL to which a potential L or a potential WLH is supplied; m wirings PL to which a potential H or a potential COM is supplied; n (n is an integer of 2 or more) wirings BL to which the potential H or the potential COM is supplied; a plurality of memory cells arranged in a matrix of m rows and n columns; each of the plurality of memory cells includes a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed, and a capacitor element whose dielectric is a ferroelectric; In each of the plurality of memory cells, a first terminal of the transistor is electrically connected to any one of the n wirings BL; a second terminal of the transistor electrically connected to a first terminal of the capacitance element; The gate of the transistor is electrically connected to any one of the m wirings WL, a second terminal of the capacitance element is electrically connected to any one of the m wirings PL; The potential WLH is a potential higher than the potential H, The potential H is higher than the potential COM, The potential L is lower than the potential COM, When reading data from the memory cell connected to an i-th wiring WL (i is 1 or more and less than m), the potential WLH is supplied to the i-th wiring WL, A method for driving a semiconductor device in which the potential L is supplied to wirings WL other than the i-th wiring. In claim 6, When writing data to the memory cell connected to the i-th wiring WL, the potential WLH is supplied to the i-th wiring WL, A method for driving a semiconductor device in which the potential L is supplied to wirings WL other than the i-th wiring. 　 In claim 6 or claim 7, The m wirings WL are arranged parallel or substantially parallel to the m wirings PL, A method for driving a semiconductor device in which the n wirings BL are arranged to intersect with the m wirings WL. 　 In claim 6 or claim 7, A method for driving a semiconductor device, wherein the oxide semiconductor contains indium.

8. The method for driving a semiconductor device according to claim 6, wherein the oxide semiconductor has crystallinity. 　 In claim 6 or claim 7, A method for driving a semiconductor device, wherein the ferroelectric material contains hafnium and zirconium.

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