Storage device

Abstract

Provided is a storage device with a reduced occupied area. Provided is a storage device capable of accurately reading data. Provided is a storage device which can be easily manufactured. In this storage device, a first plurality of transistors have a portion positioned in a first opening of an insulating layer, a second plurality of transistors have a portion positioned in a second opening of the insulating layer, and a plate line of a first plurality of capacitive elements and a plate line of a second plurality of capacitive elements are spaced apart. The first plurality of capacitive elements and the second plurality of capacitive elements include a material capable of having ferroelectricity. One among the source and the drain of one of the first plurality of transistors is connected to one of the first plurality of capacitive elements, and the other is connected to a bit line. One among the source and the drain of one of the second plurality of transistors is connected to one of the second plurality of capacitive elements, and the other is connected to the bit line.

Description

storage device

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Research and development of memories using ferroelectrics is actively underway (Non-Patent Document 1). In addition, for the next generation of ferroelectric memories, ferroelectric HfO ２ Research on Hf-based materials (Non-Patent Document 2), ０．５ Zr ０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 5).

[0004] A ferroelectric capacitor is an example of a memory or circuit element that uses a ferroelectric material. A ferroelectric capacitor is a type of capacitance element in which a ferroelectric insulating material is sandwiched between a pair of electrodes, and is capable of retaining data by utilizing the hysteresis characteristics of the remanent polarization of the ferroelectric insulating material. This allows data to be retained even without the application of voltage, and therefore the realization of a non-volatile memory (FeRAM) using a ferroelectric capacitor is expected.

[0005] In particular, Patent Documents 1 and 2 disclose a circuit configuration that retains data in a ferroelectric capacitor even when the power supply voltage to a flip-flop circuit is cut off. This circuit configuration makes it possible to back up the data retained in the flip-flop circuit to the ferroelectric capacitor, and to stop the flip-flop circuit.

[0006] Republished Patent Publication No. 03-044953 Japanese Patent Application Laid-Open No. 2013-124290

[0007] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al. , “Ferroelectric HfO2-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016Jun Okuno, et al. , "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2", VLSI 2020. Akira Toriumi, "Ferroelectricity of HfO2 thin films", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. T. Francois, et al. , "Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications," IEDM 2019. Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology (AIST) Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] An object of one embodiment of the present invention is to provide a memory device with a reduced occupation area. Another object of one embodiment of the present invention is to provide a memory device from which data can be accurately read. Another object of one embodiment of the present invention is to provide a memory device that can be easily manufactured. Another object of one embodiment of the present invention is to provide a semiconductor device with a reduced occupation area. Another object of one embodiment of the present invention is to provide a semiconductor device from which data can be accurately read. Another object of one embodiment of the present invention is to provide a semiconductor device that can be easily manufactured. Another object of one embodiment of the present invention is to provide an electronic device including the above-described memory device. Another object of one embodiment of the present invention is to provide a novel memory device, a novel semiconductor device, or a novel electronic device.

[0009] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems. Therefore, one embodiment of the present invention does not necessarily solve all of the above problem and other problems.

[0010] One embodiment of the present invention provides a transistor including a first transistor, a second transistor, a first capacitor, a second capacitor, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line, wherein the first transistor, the second transistor, and the second insulating layer are each located over the first insulating layer, the third insulating layer is located over the first transistor and the second transistor, the first capacitor, the second capacitor, and the bit line are each located over the third insulating layer, and the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer, a portion of the first transistor being located in the first opening, and a portion of the second transistor being located in the second opening, and the first transistor has a first electrode functioning as one of a source electrode and a drain electrode and a second electrode functioning as the other. the second transistor has a first electrode functioning as one of a source electrode and a drain electrode and a third electrode functioning as the other, the first electrode being connected to a bit line; the first capacitor has a fifth electrode having a columnar shape, a fourth insulating layer covering at least a part of a side surface of the columnar fifth electrode, and a sixth electrode; the second capacitor has a seventh electrode having a columnar shape, a fifth insulating layer covering at least a part of a side surface of the columnar seventh electrode, and an eighth electrode; the fourth insulating layer has a portion located between the fifth electrode and the sixth electrode, and the fifth insulating layer has a portion located between the seventh electrode and the eighth electrode; the fourth insulating layer and the fifth insulating layer contain a material that can have ferroelectricity; the second electrode is connected to the fifth electrode of the first capacitor, and the third electrode is connected to the seventh electrode of the second capacitor.

[0011] In the above aspect, it is preferable that the semiconductor device has a first plug, a second plug, and a third plug, the first plug to the third plug each having a portion provided in the third insulating layer, the first electrode to the third electrode each being located on the second insulating layer, the first electrode being connected to the bit line via the first plug, the second electrode being connected to the fifth electrode of the first capacitance element via the third plug, and the third electrode being connected to the seventh electrode of the second capacitance element via the third plug.

[0012] In the above aspect, it is preferable that the semiconductor layer is shared by the first transistor and the second transistor, the first transistor has a first gate line, the second transistor has a second gate line, the semiconductor layer has a first portion in contact with a first side surface of the first opening, a second portion in contact with an upper surface of the first insulating layer in the first opening, a third portion in contact with the second side surface of the first opening, a fourth portion in contact with the third side surface of the second opening, a fifth portion in contact with the upper surface of the first insulating layer in the second opening, and a sixth portion in contact with the fourth side surface of the second opening, and the first portion and the third portion are arranged with the first gate line sandwiched therebetween, and the fourth portion and the sixth portion are arranged with the second gate line sandwiched therebetween.

[0013] In the above embodiment, the semiconductor layer preferably includes a metal oxide, and the metal oxide preferably contains indium.

[0014] Alternatively, one embodiment of the present invention includes a first plurality of transistors, a second plurality of transistors, a first plurality of capacitors, a second plurality of capacitors, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line, wherein the first plurality of transistors, the second plurality of transistors, and the second insulating layer are each located on the first insulating layer, the third insulating layer is located on the first plurality of transistors and the second plurality of transistors, the first plurality of capacitors, the second plurality of capacitors, and the bit line are each located on the third insulating layer, the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer, each of the first plurality of transistors has a portion located within the first opening, and each of the second plurality of transistors has a portion located within the second opening, the first plurality of capacitors have a first plate line provided in common to the first plurality of capacitors, and the second plurality of capacitors a second plate line shared by a second plurality of capacitance elements, the first plate line and the second plate line being spaced apart; the first transistor being one of the first plurality of transistors, one of a source and a drain of which is connected to a bit line and the other of which is connected to one of the first plurality of capacitance elements; the second transistor being one of the second plurality of transistors, one of a source and a drain of which is connected to the bit line and the other of which is connected to one of the second plurality of capacitance elements; each of the first plurality of capacitance elements having a fifth electrode having a columnar shape; each of the second plurality of capacitance elements having a sixth electrode having a columnar shape; each of the first plurality of capacitance elements having a fourth insulating layer sandwiched between the fifth electrode and the first plate line; each of the second plurality of capacitance elements having a fifth insulating layer sandwiched between the sixth electrode and the second plate line;

[0015] In the above aspect, it is preferable that each of the first plurality of transistors has a first semiconductor layer, and in the first opening, the first semiconductor layers of the first plurality of transistors are arranged in order along the first direction, each of the second plurality of transistors has a second semiconductor layer, and in the second opening, the second semiconductor layers of the second plurality of transistors are arranged in order along the second direction, and the bit line extends in a third direction, and each of the first direction and the second direction intersects with the third direction.

[0016] In the above aspect, it is preferable that the first plurality of transistors have a first gate line shared by the first plurality of transistors, and the first semiconductor layer in each of the first plurality of transistors has a first portion in contact with the first side surface of the first opening, a second portion in contact with the top surface of the first insulating layer in the first opening, and a third portion in contact with the second side surface of the first opening, with the first portion and the third portion being arranged with the first gate line sandwiched between them, and the second plurality of transistors have a second gate line shared by the second plurality of transistors, and the second semiconductor layer in each of the second plurality of transistors has a fourth portion in contact with the third side surface of the second opening, a fifth portion in contact with the top surface of the first insulating layer in the second opening, and a sixth portion in contact with the fourth side surface of the second opening, with the fourth portion and the sixth portion being arranged with the second gate line sandwiched between them.

[0017] According to one embodiment of the present invention, a semiconductor device with a reduced occupation area can be provided. According to one embodiment of the present invention, a semiconductor device from which data can be accurately read can be provided. According to one embodiment of the present invention, a semiconductor device that can be easily manufactured can be provided. According to one embodiment of the present invention, a semiconductor device with a reduced occupation area can be provided. According to one embodiment of the present invention, a semiconductor device from which data can be accurately read can be provided. According to one embodiment of the present invention, a semiconductor device that can be easily manufactured can be provided. According to one embodiment of the present invention, an electronic device including the above-described memory device can be provided. According to one embodiment of the present invention, a novel memory device, a novel semiconductor device, or a novel electronic device can be provided.

[0018] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above.

[0019] FIG. 1A is a top view showing a structural example of a memory device. FIG. 1B is a perspective view showing a structural example of a memory device. FIG. 1C is a cross-sectional view showing a structural example of a memory device. FIG. 1D is a top view showing a structural example of a memory device. FIG. 2A is a top view showing a structural example of a memory device. FIG. 2B is a cross-sectional view showing a structural example of a memory device. FIG. 2C is a perspective view showing a structural example of a memory device. FIG. 2D is a cross-sectional view showing a structural example of a memory device. FIG. 3A is a top view showing a structural example of a memory device. FIGS. 3B and 3C are cross-sectional views showing a structural example of a memory device. FIG. 4A is a top view showing a structural example of a memory device. FIG. 4B is a cross-sectional view showing a structural example of a memory device. FIG. 4C is a top view showing a structural example of a memory device. FIGS. 4D and 4E are cross-sectional views showing a structural example of a memory device. FIGS. 5A to 5E are cross-sectional views showing an example method for manufacturing a memory device. FIG. 6 is a cross-sectional view showing a structural example of a memory device. FIG. 7A is a cross-sectional view showing a structural example of a memory device. FIG. 7B is a top view showing a structural example of a memory device. FIG. 8 is a cross-sectional view showing a structural example of a memory device. FIG. 9 is a cross-sectional view showing a structural example of a memory device. FIG. 10 is a cross-sectional view showing an example of the configuration of a memory device. FIG. 11 is a cross-sectional view showing an example of the configuration of a memory device. FIG. 12 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 13 is a diagram explaining an example of the circuit configuration of a memory cell array and a memory cell. FIG. 14A is a graph showing an example of hysteresis characteristics, and FIG. 14B is a timing chart showing an example of a method for driving a memory cell. FIG. 15 is a conceptual diagram explaining the hierarchy of a memory device. FIG. 16A is a block diagram showing an example of the configuration of a semiconductor device, and FIG. 16B is a schematic perspective view showing an example of the configuration of a semiconductor device. FIGS. 17A to 17E are diagrams showing an example of a memory device. FIGS. 18A to 18D are diagrams showing an example of an electronic component. FIGS. 19A and 19B are diagrams showing an example of an electronic device, and FIGS. 19C to 19E are diagrams showing an example of a mainframe computer. FIG. 20A is a diagram showing an example of space equipment. FIG. 20B is a diagram showing an example of a storage system applicable to a data center. FIGS. 21A and 21B are diagrams explaining the carrier concentration dependence of Hall mobility. FIG. 21C is a cross-sectional view illustrating an indium oxide film.22A1 to 22A7 and 22B1 to 22B6 are diagrams for explaining electrical connections.

[0020] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, a memory device, a display device, a light-emitting device, a computing device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0021] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0022] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0023] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 22A1 and 22A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 22A3 , when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0024] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 22A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 22A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0025] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 22A6 and 22A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 22A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 22A6 and 22A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0026] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0027] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 22B1, 22B2, and 22B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 22B4 and 22B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 22B6. ​​Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0028] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0029] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Furthermore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0030] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, or the gate capacitance of a transistor. The terms "capacitive element" and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the term "capacitive element" or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0031] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or the drain" and "the other of the source or the drain" are sometimes interchangeable. In addition, "one of the source or the drain" may be interchangeable with "first terminal" or "first electrode," and "the other of the source or the drain" may be interchangeable with "second terminal" or "second electrode." Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this specification, one of the gate or the backgate of the transistor may be referred to as a first gate, and the other of the gate or the backgate of the transistor may be referred to as a second gate. Furthermore, the terms "gate" and "back gate" may be interchangeable for the same transistor. When a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc. in this specification.

[0032] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0033] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor element, this includes two or more resistor elements connected in series. For example, when a circuit diagram shows one capacitor element, this includes two or more capacitor elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0034] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal, a wiring, or the like can also be referred to as a node.

[0035] Furthermore, in this specification, the term "selector" may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the term "selector" may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the term "selector" may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the term "selector" may refer to a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the term "selector" may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, the selector may refer to an analog multiplexer or an analog demultiplexer.

[0036] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0037] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0038] In addition, in this specification, the term "high potential" can be appropriately replaced with "high level potential." In addition, in this specification, the term "low potential" can be appropriately replaced with "low level potential."

[0039] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0040] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0041] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0042] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0043] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0044] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

[0045] Furthermore, the terms "electrode," "wiring," and "terminal" used herein do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0046] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0047] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0048] In this specification, the term "impurities in a semiconductor" refers to, for example, a substance other than the main component constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following problems: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity.

[0049] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling a current.

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0052] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0053] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0054] In addition, the content (part or all of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (part or all of the content) described in that embodiment and another content (part or all of the content) described in one or more other embodiments.

[0055] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0056] Furthermore, a figure (part or all) described in one embodiment can be combined with another part of that figure, another figure (part or all) described in that embodiment, and at least one figure (part or all) described in one or more other embodiments to form even more figures.

[0057] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0058] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0059] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences, etc. may be included.

[0060] Embodiment 1 In this embodiment, a memory device which is a semiconductor device of one embodiment of the present invention will be described.

[0061] [Configuration Example 1] Fig. 1A shows a schematic top view of a memory device having two memory cells 15. Fig. 1B shows a perspective view corresponding to the schematic top view of Fig. 1A, Fig. 1C shows schematic cross-sectional views taken along lines A1-A2, A2-A3, and A3-A4 shown in Fig. 1A, and Fig. 1D shows a schematic top view taken along chain double-dashed line B1-B2 shown in Fig. 1C.

[0062] 1A, two memory cells 15 are arranged side by side along the direction in which the semiconductor layer 21 extends. The semiconductor layer 21 is provided across the two memory cells 15.

[0063] The memory cell 15 includes a transistor 20 and a capacitor 30 thereon. The capacitor 30 can be provided over the transistor 20.

[0064] The memory cell 15 is a memory circuit having one transistor and one capacitance element, and has a DRAM (Dynamic Random Access Memory) configuration. Furthermore, by using a material that can have ferroelectricity as the dielectric of the capacitance element, the capacitance element can be made into a ferroelectric capacitor, and the memory cell 15 can have a FeRAM (Ferroelectric Random Access Memory) configuration.

[0065] The transistor 20 and the capacitor 30 are provided over an insulating layer 11 provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer. A portion of the transistor 20 is located in an opening provided in the insulating layer 43.

[0066] The transistor 20 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, and a conductive layer 25a functioning as one of a source electrode and a drain electrode, and a conductive layer 25b functioning as the other. The conductive layer 25a is connected to the conductive layer 24, and the conductive layer 25b is connected to the capacitor 30. The conductive layer 25a can be shared by two adjacent memory cells 15.

[0067] The conductive layer 23 is disposed in the opening of the insulating layer 43. The semiconductor layer 21 has a portion located in the opening of the insulating layer 43, and faces the conductive layer 23 at this portion with the insulating layer 22 sandwiched therebetween.

[0068] The conductive layer 25a and the conductive layer 25b are located on the insulating layer 43, and are arranged with the conductive layer 23 sandwiched between them in a plan view.

[0069] Two memory cells are provided in one island-shaped semiconductor layer 21, and the two memory cells are connected to the same conductive layer 24. The transistors 20 of the two memory cells share a conductive layer 25a, and are provided with separate conductive layers 25b. Two conductive layers 23 are arranged perpendicular to the conductive layer 24, with one conductive layer 25a sandwiched between them. Two conductive layers 25b are arranged, each sandwiching one of the conductive layers 23 between them.

[0070] The integration density of the memory device can be increased by configuring two transistors 20 provided in one island-shaped semiconductor layer 21 to share the conductive layer 25a. On the other hand, the semiconductor layers 21 are provided separately in memory cells connected to different bit lines. This reduces noise, leakage, etc. between memory cells and increases the reliability of the memory device.

[0071] The capacitor 30 includes a conductive layer 51 that functions as a lower electrode, a conductive layer 53 that functions as an upper electrode, and an insulating layer 52 that is disposed between the conductive layer 51 and the upper electrode and functions as a dielectric. The conductive layer 51 has a columnar shape.

[0072] In this specification, a columnar body refers to a structure having a shape with a high aspect ratio in a cross-sectional view. For example, in the cross-sectional view of FIG. 1C , the aspect ratio of the conductive layer 51 refers to the ratio of the length M of the conductive layer 51 in the A2-A3 direction (which can also be referred to as the width M of the conductive layer 51) to the length K of the conductive layer 51 in a direction perpendicular or approximately perpendicular to the surface on which it is formed (e.g., one or both of the conductive layer 46 b and the insulating layer 46). The aspect ratio of the conductive layer 51 is preferably as large as possible without causing the conductive layer 51 to collapse during the fabrication process of the capacitive element 30. In other words, the height K of the conductive layer 51 is preferably greater than the width M of the conductive layer 51, provided that the conductive layer 51 does not collapse. Note that although the cross-sectional view of FIG. 1C has been described above as an example, the height H of the conductive layer 51 is preferably greater than the width L of the conductive layer 51, provided that the conductive layer 51 does not collapse, even in cross-sectional views other than those of FIG. 1C .

[0073] In this specification, the term "columnar body" may be interchangeably referred to as "pillar." The columnar body or pillar may have a tapered shape. In this specification, the columnar body or pillar having a tapered shape may be referred to as a truncated cone.

[0074] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the film surface underlying the structure. The angle between the inclined side surface and the substrate surface or the film surface is referred to as the taper angle. In this specification, a tapered shape having a taper angle greater than 0 degrees and less than 90 degrees is referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90 degrees and less than 180 degrees is referred to as a reverse taper shape.

[0075] 1C and 1D , the insulating layer 52 covers the side surfaces of the columnar shape of the conductive layer 51. The conductive layer 53 has a portion facing the side surface of the conductive layer 51 with the insulating layer 52 sandwiched therebetween. Fig. 1D shows an example in which the conductive layer 51 is circular in plan view, the insulating layer 52 and the conductive layer 53 have high film thickness uniformity, and the outlines (also referred to as peripheries) of each layer in plan view, more specifically, the outer outlines thereof, are circular.

[0076] 2A shows a schematic top view of a memory device 10. The memory device 10 shown in FIG. 2A has a plurality of memory cells 15 shown in FIG. 1A. In FIG. 2A, the plurality of memory cells 15 are arranged in a matrix. Note that a conductive layer 53 overlaps a conductive layer 51, but in order to make the conductive layer 51 easier to see, the conductive layer 51 is shown here by a solid line instead of a dotted line.

[0077] 2B shows schematic cross-sectional views taken along the cutting lines A5-A6, A6-A7, and A7-A8 shown in FIG. 2A, and FIG. 2C shows a perspective view corresponding to a partial region of FIG. 2A.

[0078] The memory device 10 has a configuration in which multiple memory cells 15 are arranged along a line 99 that forms an angle θ with the X-axis and along a line that is perpendicular to the Z-axis and perpendicular to the line 99. In the plan view shown in FIG. 2A and other figures, the semiconductor layer 21 has a region extending in a strip shape along the line 99. FIG. 2A shows an example in which θ is 27°. θ can be, for example, 30° or an angle close to that. Reducing θ can sometimes increase the integration density of the memory device. On the other hand, θ is preferably large enough so that the region where the conductive layer 51 of the capacitance element 30 is formed does not overlap with the conductive layer 24 functioning as a bit line. θ can be, for example, 10° to 35°. In the memory device 10, the conductive layer 24 functioning as a bit line and the conductive layer 23 functioning as a word line are preferably arranged to intersect. In the memory device 10, the conductive layer 24 functioning as a bit line extends in the X-direction, and the conductive layer 23 functioning as a word line extends in the Y-direction.

[0079] The conductive layer 23 can function as a gate line shared by a plurality of transistors 20 arranged in sequence in the Y direction. The conductive layer 23 can function as a gate electrode in each of the plurality of shared transistors 20.

[0080] 2A , in the region surrounded by a dashed square line, memory cells 15 are arranged in a matrix, and conductive layers 24 extend in the X direction to a region 80 on the left side (the negative side of the X coordinate). In region 80 shown in FIG. 2A , conductive layers 24 may be connected to, for example, peripheral circuits of memory cells 15. Region 80 will be described later with reference to FIG. 12 .

[0081] The memory cell 15, the transistor 20, and the capacitor 30 can be applied to the memory cell MC or the memory cell 1480, the transistor M9, and the capacitor Cfe, respectively, in Embodiment 2. The conductive layer 24 and the conductive layer 23 can be applied to the wiring BL and the wiring WL, respectively.

[0082] In a transistor according to one embodiment of the present invention, a semiconductor layer is formed along the side surfaces and bottom surface of a slit-shaped opening provided in an insulating layer, and a gate insulating layer and a gate electrode are formed in this order over the semiconductor layer. By deepening the opening, the channel length can be increased without increasing the area of ​​the transistor in a plan view.

[0083] 1A to 2C, a slit-shaped opening is provided in the insulating layer 43, and the longitudinal direction of the slit coincides with the Y direction. It can also be expressed as a slit-shaped opening extending in the Y direction being provided in the insulating layer 43. It can also be expressed as the opening of the insulating layer 43 having a region extending in a band shape in a plan view.

[0084] A plurality of semiconductor layers 21 are provided in the slit along the Y direction. For example, each of the plurality of semiconductor layers 21 is included in a different transistor 20. The plurality of semiconductor layers 21 are arranged in order along the Y direction.

[0085] The conductive layer 23 is provided to extend in the Y direction within an opening extending in the Y direction. The slit-shaped opening of the insulating layer 43 has a first side surface and a second side surface facing each other with the conductive layer 23 sandwiched therebetween. The first side surface and the second side surface each extend in the Y direction.

[0086] By making the upper surface of the conductive layer 23 lower than the upper surface of the insulating layer 22 outside the opening by planarization treatment using polishing or etch-back treatment using dry etching, the conductive layer 23 can be processed without using a photomask or the like. The upper surface of the conductive layer 23 may be higher than the lower surfaces of the conductive layers 25 a and 25 b, for example. The transistor 20 shown in FIG. 1C and other figures illustrates an example in which the upper surface of the conductive layer 23 is lower than the upper surfaces of the conductive layers 25 a and 25 b.

[0087] In the transistor 20, a current path is formed in the semiconductor layer 21 in the following order: a portion in contact with one of the conductive layers 25a and 25b, a portion in contact with one of the first side surface and the second side surface, a portion in contact with the top surface of the insulating layer 11, a portion in contact with the other of the first side surface and the second side surface, and a portion in contact with the other of the conductive layers 25a and 25b.

[0088] An insulating layer 44 is provided to cover the transistor 20. An insulating layer 45 is provided over the insulating layer 44. An insulating layer 46 and a conductive layer 24 are provided over the insulating layer 45. An insulating layer 46 is provided over the insulating layer 45 and the conductive layer 24. An insulating layer 47 and an insulating layer 48 are provided in this order over the insulating layer 46.

[0089] The conductive layer 25a and the conductive layer 24 are connected via a conductive layer 88a. The conductive layer 88a is formed so as to be embedded in the insulating layer 45, the insulating layer 44, and the semiconductor layer 21, and can function as a plug.

[0090] The capacitance element 30 is provided on the insulating layer 46 .

[0091] The conductive layer 51 of the capacitor 30 is connected to the conductive layer 25b of the transistor 20 via the conductive layer 46b and the conductive layer 88b. The conductive layer 88b is formed so as to be embedded in the insulating layer 46, the insulating layer 45, the insulating layer 44, and the semiconductor layer 21, and can function as a plug. The conductive layer 46b is formed on the insulating layer 46 and the conductive layer 88b. The conductive layer 46b has a portion overlapping with the conductive layer 51 and a portion overlapping with the conductive layer 88b.

[0092] 1A to 1C and 2A to 2D, the conductive layer 51 overlaps the conductive layer 23 in plan view. This allows a configuration in which the direction in which the multiple capacitance elements 30 are provided and the direction in which the conductive layer 23 extends to coincide, as shown in FIGS.

[0093] The conductive layer 51 has a portion buried in the insulating layer 47 and a portion buried in the insulating layer 48. The conductive layer 51 also has a columnar portion protruding above the insulating layer 48. While FIGS. 1A to 2C and other figures illustrate examples in which the conductive layer 51 has a columnar shape and the bottom shape of the column is circular, the bottom shape is not limited to a circle and can be an ellipse, a rectangle with rounded corners, or the like. The contour shape of the conductive layer 51 in a planar view may be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. The channel width can be increased by forming the conductive layer 51 into a concave polygon, such as a star-shaped polygon, with at least one interior angle exceeding 180°. Other shapes include a polygon with rounded corners and a closed curve combining straight and curved lines.

[0094] In the memory device 10 shown in FIGS. 2A to 2D, the conductive layer 53 may be shared by two adjacent capacitor elements 30.

[0095] FIG. 2D shows a modified example of the capacitance element shown in FIG. 2B, in which a conductive layer 53 is formed to fill the region between the conductive layers 51, and the upper surface of the conductive layer 53 is provided to be approximately flat.

[0096] 7A is a modified example of FIG. 1C , showing an example in which the upper portion of the conductive layer 51 is rounded. In FIG. 7A , the conductive layer 51 has rounded corners at the upper portion in a cross-sectional view. The rounded shape can alleviate the electric field concentration between the conductive layer 51 and the conductive layer 53. Alleviating the electric field concentration can suppress short circuits in the capacitive element 30, thereby improving the reliability of the memory device 10.

[0097] 1D and 2A, the conductive layer 53 of the capacitance element 30 has a columnar appearance, and the conductive layer 51 and the insulating layer 52 are disposed inside the columnar appearance. As shown in Fig. 2A, the conductive layer 53 has a shape in which adjacent circles overlap each other in a plan view. It can also be expressed that the conductive layers 53 of the two capacitance elements 30 overlap and are connected.

[0098] By connecting the conductive layers 53 of adjacent capacitor elements 30, it is possible to arrange a plurality of memory cells 15 at high density. The conductive layers 53 can function as wiring. Since the length of the wiring can be shortened, it may be possible to reduce the wiring resistance.

[0099] In plan view, the conductive layer 53 has a shape in which adjacent circles overlap each other, and the adjacent circles are aligned along the Y direction. Note that in Fig. 2A, in the capacitive elements 30 aligned in the Y direction, one adjacent capacitive element is connected to the conductive layer 53, and the other adjacent capacitive element is separated by the conductive layer 53. Here, as shown in Figs. 3A and 3B, by disposing a dummy pattern capacitive element (hereinafter referred to as capacitive element dm) between the two separated conductive layers 53, the conductive layer 53 can be extended in the Y direction.

[0100] For example, the conductive layer 51 is provided separately for each of the plurality of capacitor elements 30. The insulating layer 52 can be shared by the plurality of capacitor elements 30. Alternatively, the insulating layer 52 can be provided separately for each of the plurality of capacitor elements 30.

[0101] 3A shows a schematic top view of the memory device 10, and FIG. 3B shows a schematic cross-sectional view taken along the line A9-A10. Note that although a conductive layer 53 overlaps the conductive layer 51, in FIG. 3B the conductive layer 51 is shown by a solid line instead of a dotted line to make the conductive layer 51 easier to see.

[0102] 3A, the conductive layer 53 has a shape in which adjacent circles overlap each other and multiple circles are arranged along the Y direction. For this reason, the conductive layer 53 is sometimes referred to as a beaded wiring. The memory device 10 shown in FIG. 3A has multiple beaded wirings that extend in the Y direction, and the multiple wirings are arranged in order in the X direction.

[0103] The conductive layer 53 has a region that functions as a wiring, for example, a wiring PL that will be described in Embodiment 2 later.

[0104] In particular, when the capacitive element 30 of the memory device 10 is a ferroelectric capacitor, the conductive layer 53 (wiring PL) functions as a plate line for transmitting a predetermined signal when writing data to or reading data from the memory cell 15.

[0105] When the memory device 10 is a DRAM instead of an FeRAM, the conductive layer 53 (wiring PL) preferably has a function as wiring for applying a fixed potential.

[0106] Since the conductive layer 53 functions as one of the multiple wirings PL, adjacent wirings need to be electrically isolated from each other. In the memory device 10 shown in Figure 3A, adjacent bead-shaped wirings in the X direction are spaced apart, and can be suitably used as electrically isolated wirings.

[0107] The wiring is configured to connect the conductive layers 53 of adjacent capacitance elements 30, and in the conductive layers 53, in regions sandwiched between the conductive layers 51 between the plurality of capacitance elements 30, the conductive layers 53 are provided so as to fill in the spaces between the conductive layers 51, thereby making it possible to increase the thickness of the conductive layers 53 in the height direction (Z direction). By making the conductive layers 53 thicker, it is possible to reduce the wiring resistance.

[0108] Furthermore, since the conductive layer 53 can function as a plate line, the manufacturing process can be simplified compared to when a separate plate line is provided.

[0109] Furthermore, for example, when a plate line is provided separately in a layer above or below the capacitance element 30, the plate line and the conductive layer 53 of the capacitance element can be connected using a plug or the like. In this case, when the plug is provided on the upper surface of the conductive layer 53, depending on the thickness of the conductive layer 53, there is a concern that the plug may penetrate the insulating layer 52 below the conductive layer 53, causing a short circuit between the plug and the conductive layer 51. If the plug is positioned so as not to overlap the conductive layer 51 in a plan view in order to avoid a short circuit, there is a concern that this may lead to an increase in the circuit area.

[0110] In the memory device 10 shown in FIGS. 3A and 3B, the conductive layer 53 functions as a plate line, thereby realizing circuit integration and improving the reliability of the memory device.

[0111] 3C shows a modification of FIG. 3B. In the structure shown in FIG. 3C, the conductive layer 53 has a portion facing the side surface of the conductive layer 51 with the insulating layer 52 sandwiched therebetween, and does not cover the top surface of the conductive layer 51. When a planarization treatment by polishing is used in forming the conductive layer 53, the structure shown in FIG. 3C may be obtained.

[0112] By using a low resistance material for the conductive layer 53, the wiring resistance can be reduced.

[0113] The capacitance element dm functioning as a dummy pattern has a conductive layer 51, similar to the capacitance element 30. An insulating layer 52 is provided on the conductive layer 51 of the capacitance element dm, and a conductive layer 53 is provided on the insulating layer 52. In the capacitance element dm, similar to the capacitance element 30, the conductive layer 53 has a portion facing the side surface of the conductive layer 51 and a portion facing the top surface of the conductive layer 51, with the insulating layer 52 sandwiched therebetween.

[0114] In addition, in the capacitor dm, the conductive layer 51 is not connected to the conductive layer 25b of the transistor 20 and is in a floating state. Therefore, a plug for connection to the conductive layer 25b does not need to be provided under the conductive layer 51. Unlike the capacitor 30, the capacitor dm does not retain data because one of the pair of electrodes is in a floating state.

[0115] 7B, in order to make it easier to see the memory cells 15 corresponding to the respective conductive layers 23 and 24 in the top view shown in FIG. 2A, numbers are assigned to the conductive layers 23, 24, and memory cells 15, and they are represented as conductive layer 23[x], conductive layer 24[y], and memory cell 15[y,x]. Memory cell 15[y,x] is the memory cell 15 connected to conductive layer 23[x] and conductive layer 24[y]. x and y are each a positive integer.

[0116] 7B shows four sequentially arranged conductive layers 23, namely, conductive layer 23[1], conductive layer 23[2], conductive layer 23[3], and conductive layer 23[4], and three sequentially arranged conductive layers 24, namely, conductive layer 24[1], conductive layer 24[2], and conductive layer 24[3]. Also, FIG. 7B shows memory cell 15[y, x], where x=1 to 4 and y=1 to 3.

[0117] 7B shows memory cell 15[1,2], memory cell 15[2,2], and memory cell 15[3,2] as memory cells 15 connected to conductive layer 23[2]. By providing capacitance element dm between capacitance element 30 of memory cell 15[2,2] and capacitance element 30 of memory cell 15[3,2], conductive layers 53 in memory cell 15[1,2], memory cell 15[2,2], and memory cell 15[3,2] can be connected in a rosary shape and used as a common plate line.

[0118] Furthermore, in memory cell 15[1,1], memory cell 15[2,1], and memory cell 15[3,1] connected to conductive layer 23[1], by providing a capacitance element dm between the capacitance element 30 of memory cell 15[1,1] and the capacitance element 30 of memory cell 15[2,1], the conductive layers 53 in memory cell 15[1,1], memory cell 15[2,1], and memory cell 15[3,1] can be connected in a rosary shape and used as a common plate line.

[0119] Furthermore, in memory cell 15[1,3], memory cell 15[2,3], and memory cell 15[3,3] connected to conductive layer 23[3], by providing a capacitance element dm between the capacitance element 30 of memory cell 15[1,3] and the capacitance element 30 of memory cell 15[2,3], the conductive layers 53 in memory cell 15[1,3], memory cell 15[2,3], and memory cell 15[3,3] can be connected in a rosary shape and used as a common plate line.

[0120] Furthermore, in memory cell 15[1,4], memory cell 15[2,4], and memory cell 15[3,4] connected to conductive layer 23[4], by providing a capacitance element dm between the capacitance element 30 of memory cell 15[2,4] and the capacitance element 30 of memory cell 15[3,4], the conductive layers 53 in memory cell 15[1,4], memory cell 15[2,4], and memory cell 15[3,4] can be connected in a rosary shape and used as a common plate line.

[0121] 1A to 2C and 7B, etc., in the transistors 20 of two memory cells 15 (e.g., memory cell 15[1,1] and memory cell 15[1,2] shown in FIG. 7B) that share a semiconductor layer 21, the conductive layer 25a connected to the conductive layer 24 via the conductive layer 88a is shared as shown in FIG. 1C. On the other hand, the conductive layer 25b is provided separately for each memory cell 15.

[0122] In the transistor 20, the semiconductor layer 21 has a portion in contact with the side surface of the insulating layer 43 and a portion in contact with the top surface of the insulating layer 11. The side surface of the insulating layer 43 is preferably perpendicular to the top surface of the insulating layer 11. Note that the side surface of the insulating layer 43 is not necessarily strictly perpendicular to the top surface of the insulating layer 11. If the side surface of the insulating layer 43 is inclined with respect to the Z direction, the semiconductor layer 21 is also provided at an inclination along the side surface. The semiconductor layer 21 also has portions in contact with the side surfaces of the conductive layer 25a and the conductive layer 25b, and these portions can function as one and the other of the source and drain regions of the transistor. Furthermore, the vicinity of the portion of the semiconductor layer 21 in contact with the side surface of the conductive layer 25a may also function as one of the source and drain regions. Similarly, the vicinity of the portion in contact with the side surface of the conductive layer 25b may also function as the other of the source and drain regions. In the semiconductor layer 21, the region sandwiched between the source and drain regions functions as a channel formation region. For example, in the semiconductor layer 21, at least a part of the region in contact with the side surface of the insulating layer 43 functions as a channel formation region.

[0123] The semiconductor layer 21 has a portion that is provided along the side of the insulating layer 43 and whose surface (either or both of the surface of the semiconductor layer 21 on the insulating layer 43 side or the surface of the insulating layer 22 side) is perpendicular or approximately perpendicular to the upper surface of the insulating layer 11, and a portion that is provided along the upper surface of the insulating layer 11 and whose surface (the surface of the semiconductor layer 21 on the insulating layer 11 side or the surface of the insulating layer 22 side) is parallel or approximately parallel to the upper surface of the insulating layer 11.

[0124] In the memory device 10, the insulating layer 43 has two side surfaces (hereinafter referred to as a first side surface and a second side surface) that face each other with the conductive layer 23 sandwiched therebetween. The semiconductor layer 21 has a portion that contacts the first side surface and a portion that contacts the second side surface. The portion that contacts the first side surface and the portion that contacts the second side surface are arranged with the gate electrode sandwiched therebetween.

[0125] The channel formation region of the transistor 20 is provided along the side surface of an opening provided in the insulating layer 43. In the cross-sectional view shown in FIG. 1C etc., the semiconductor layer 21 can also be expressed as having a U-shape. In the semiconductor layer 21, current flows along the U-shape. In the transistor 20, the channel length direction has not only a horizontal portion but also a vertical portion. Therefore, the occupied area can be reduced compared to a so-called planar type transistor in which semiconductors are arranged on a flat surface.

[0126] Furthermore, in the transistor 20, the conductive layers 25a and 25b and the channel formation region can be provided at different heights. That is, the source electrode and the drain electrode can be provided at different heights from the channel formation region. Therefore, it can be considered that this structure is easy to suppress the short channel effect. Furthermore, even when the channel length is increased to a degree that the short channel effect can be sufficiently suppressed, an increase in the area occupied by the transistor 20 can be suppressed.

[0127] When a metal oxide is used as the semiconductor layer 21, the semiconductor layer 21 can be easily formed on the side surface of the opening provided in the insulating layer 43 by a thin-film method. By configuring the semiconductor layers of adjacent transistors to be insulated by the insulating layer 43, noise, leakage, and the like between adjacent transistors can be made extremely small. Therefore, even when miniaturization is performed and the degree of integration is increased, a highly reliable memory device can be realized.

[0128] Furthermore, the channel length of the transistor 20 can be precisely controlled by the thickness of the insulating layer 43, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 43, a transistor with an extremely short channel length can be fabricated. For example, a transistor with a channel length of 10 nm to 2 μm, or 10 nm to 1 μm, or 10 nm to 500 nm, or 10 nm to 300 nm, or 10 nm to 200 nm, or 10 nm to 100 nm, or 15 nm to 100 nm, or 20 nm to 100 nm, or 20 nm to 50 nm can be fabricated. Therefore, a transistor with an extremely short channel length that could not be achieved using a mass-production exposure tool can be realized. Furthermore, a transistor with a channel length of less than 20 nm can be fabricated without using the extremely expensive exposure tool used in cutting-edge LSI technology.

[0129] The conductive layers 25a1 and 25b1 of the transistor 20 are preferably made of a conductive material having lower resistance than the conductive layers 25a2 and 25b2, and particularly preferably contain a metal material. The conductive layers 25a2 and 25b2 are preferably made of a conductive metal oxide (oxide conductor).

[0130] The use of a conductive metal oxide for the conductive layers 25a2 and 25b2 in contact with the semiconductor layer 21 containing a metal oxide is preferable because the contact resistance between them can be reduced and the load on the wiring can be reduced. In particular, a configuration in which the conductive layers 25a2 and 25b2 contain the same metal element as the metal element contained in the semiconductor layer 21 is preferable because the contact resistance can be further reduced. Furthermore, by using a metal material having a lower resistance than the conductive layers 25a2 and 25b2 for the conductive layers 25a1 and 25b1, it is possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

[0131] In the memory device 10, the insulating layers 44, 46, and 47 function as interlayer insulating films. For the insulating layers 44, 46, and 47, inorganic insulating materials such as silicon oxide and silicon oxynitride can be used. For the insulating layers 45 and 48, it is preferable to use an insulating film having barrier properties against hydrogen. This can prevent hydrogen from diffusing from above the insulating layers 45 and 48 toward the semiconductor layer 21. For the insulating layers 45 and 48, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film.

[0132] Configuration Example 2 FIG. 4A shows a schematic top view of the storage device 10, and FIG. 4B shows a schematic cross-sectional view taken along the cutting lines A11-A12 and A12-A13 shown in FIG. 4A.

[0133] In the memory device 10 shown in FIG. 4A , compared to FIG. 2A , adjacent capacitance elements 30 in the Y direction are arranged with a gap between them. Furthermore, adjacent capacitance elements 30 in the X direction with a single conductive layer 23 sandwiched therebetween are arranged so that their Y coordinates are offset. Therefore, the configuration shown in FIG. 4A can increase the packing rate of the capacitance elements 30. This may allow the integration density of the memory device 10 to be increased.

[0134] 4A , the conductive layer 51 of the capacitance element 30 is shifted to a position closer to the conductive layer 24 than the position of the conductive layer 25 b, so that the conductive layer 51 may have a portion that overlaps with the conductive layer 24 in a plan view.

[0135] 4C shows a configuration in which the conductive layers 53 that are spaced apart from one another in the plurality of capacitance elements 30 arranged side by side in the Y direction in FIG. 4A are connected together. The conductive layers 53 are shared by the plurality of capacitance elements 30 arranged side by side in the Y direction and can function as wiring extending in the Y direction.

[0136] Fig. 4D is a schematic cross-sectional view taken along the line A14-A15 shown in Fig. 4C. Note that Fig. 4C omits the configuration below the insulating layer 46. The conductive layer 53 is shared by a plurality of capacitive elements 30 arranged in the Y direction.

[0137] Fig. 4E shows a modification of Fig. 4D. Fig. 4D shows an example in which the thickness of conductive layer 53 is approximately the same in the portion covering the side surface of conductive layer 51 and the portion covering the top surface, whereas Fig. 4E shows an example in which conductive layer 53 is formed so as to be embedded in the region between conductive layers 51, and the top end is approximately flat.

[0138] 4D, for example, when removing portions between patterns of the conductive layer 53, the conductive film in the portions to be removed is thin and therefore easy to remove. On the other hand, in the configuration shown in FIG. 4E, for example, the conductive layer 53 is thick and therefore the wiring resistance of the conductive layer 53 can be reduced.

[0139] [Manufacturing Method Example] An example of a manufacturing method of a memory device according to one embodiment of the present invention will be described below, taking the memory device 10 illustrated in FIG. 2B as an example.

[0140] The thin films (insulating films, semiconductor films, conductive films, etc.) constituting the memory device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD (TCVD) method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0141] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up the memory device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0142] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is suitable for film formation using an insulating target. DC sputtering is mainly used for forming metal conductive films. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0143] CVD methods can be classified into PECVD, TCVD, photo-CVD (photo-CVD) using light, etc. They can also be further classified into metal CVD (MCVD) and MOCVD depending on the source gas used.

[0144] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0145] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0146] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0147] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the raw material gases. For example, in the CVD method, by changing the flow rate ratio of the raw material gases while forming a film, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers, since no time is required for transportation or pressure adjustment. Therefore, the productivity of memory devices can be improved in some cases.

[0148] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0149] The thin film constituting the memory device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0150] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0151] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0152] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0153] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0154] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0155] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0156] Subsequently, an insulating film to be the insulating layer 43 is formed over the insulating layer 11. The insulating film is preferably an oxide film that contains a large amount of oxygen so that oxygen is released by heating and that contains a small amount of hydrogen.

[0157] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating film can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0158] Subsequently, a conductive film that will become the conductive layer 25 a and the conductive layer 25 b is formed on the insulating film that will become the insulating layer 43 .

[0159] Next, slit-shaped openings are formed in the conductive film that will become the conductive layers 25 a and 25 b. Subsequently, the insulating film that will become the insulating layer 43 is formed by forming slit-shaped openings in the insulating film that will become the insulating layer 43 using the conductive layer having the openings as a mask.

[0160] When processing the insulating layer 43, it is preferable to process it by anisotropic dry etching so that the side surfaces are approximately vertical. Depending on the processing conditions, the side surfaces of the insulating layer 43 may be inclined with respect to the direction perpendicular to the surface on which the insulating layer 43 is formed, resulting in a tapered shape.

[0161] Next, a semiconductor film that will become the semiconductor layer 21 is formed to cover the conductive layer provided with the slit-shaped openings and the insulating layer 43 .

[0162] The semiconductor film can be a metal oxide (oxide semiconductor) film having semiconductor properties, which can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0163] Next, unnecessary portions of the semiconductor film that will become the semiconductor layer 21 are removed by etching to form the semiconductor layer 21. Subsequently, unnecessary portions of the conductive layer below the semiconductor layer 21 are removed by etching to form conductive layers 25a and 25b ( FIG. 5A ). Note that although the conductive layer 25a is not shown in the cross sections shown in FIGS. 5A to 5E , the conductive layer 25a can be formed by referring to the method for forming the conductive layer 25b.

[0164] Next, an insulating layer 22 is formed, followed by forming a conductive layer 23 so as to fill the slit-shaped openings of the insulating layer 43 (FIG. 5B).

[0165] Next, insulating layers 44 and 45 are formed in this order on the conductive layer 23 and the insulating layer 22. Subsequently, openings are provided in the insulating layer 45, the insulating layer 44, and the semiconductor layer 21, and a conductive layer 88a is formed to fill the openings. Note that the conductive layer 88a is not shown here.

[0166] Next, the conductive layer 24 is formed on the insulating layer 45. Subsequently, the insulating layer 46 is formed on the insulating layer 45 and the conductive layer 24.

[0167] Next, openings are formed in the insulating layer 46, the insulating layer 45, the insulating layer 44 and the semiconductor layer 21, and the conductive layer 88b is formed to fill the openings.

[0168] Next, conductive layer 46b is formed on insulating layer 46 and conductive layer 88b. Subsequently, insulating layers 47, 48, and 79 are formed in this order on conductive layer 46b and insulating layer 46. Here, insulating layer 79 is an insulating layer that is removed after conductive layer 51 is formed. Therefore, insulating layer 79 may be called a sacrificial layer.

[0169] Next, openings reaching the conductive layer 46b are formed in the insulating layer 79, the insulating layer 48, and the insulating layer 47. Subsequently, a conductive layer is embedded in the openings to form the conductive layer 51 (FIG. 5C).

[0170] Next, the insulating layer 79 is removed by etching. Here, by using an insulating layer having a relatively low etching rate under the etching conditions for the insulating layer 79 as the insulating layer 48, the insulating layer 48 can function as an etching stopper for the insulating layer 79.

[0171] Subsequently, an insulating layer 52 is formed so as to cover the side surfaces and upper surface of the conductive layer 51 and the upper surface of the insulating layer 48. Subsequently, a conductive film 53f that will become the conductive layer 53 is formed on the insulating layer 52 (FIG. 5D).

[0172] Next, part of the conductive film 53f is removed to form the conductive layer 53, and the memory device of one embodiment of the present invention can be manufactured (FIG. 5E).

[0173] [Configuration Example 3] In the memory device 10, a layer in which a functional circuit is provided can be stacked on a layer in which the memory cells 15 are provided. The functional circuit can include, for example, a driver circuit for driving the memory cells 15, as well as an arithmetic circuit, a power supply circuit, etc. The driver circuit can include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This can reduce the footprint of the semiconductor chip including the memory device 10 and can shorten the wiring length compared to when the functional circuit and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0174] 6 shows an example in which a transistor 90 constituting a functional circuit is disposed below the insulating layer 11. In this example, one of the source electrode and the drain electrode of the transistor 90 is connected to a conductive layer 24 functioning as a bit line. FIG. 6 corresponds to the region 80 shown in FIG. 2A and is a schematic cross-sectional view taken along the cutting line C1-C2.

[0175] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. The substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate.

[0176] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95a and 95b functioning as source and drain regions. The transistor 90 may be either a p-channel type or an n-channel type. An element isolation layer 98 is provided on the substrate 91 between two adjacent transistors 90.

[0177] The transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 6, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the X direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0178] An insulating layer 85 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 85, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 11 is provided covering the conductive layer 81 and the insulating layer 87. A plug 82 is provided inside an opening provided in the insulating layer 85 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A plug 83 is provided inside an opening provided in the insulating layer 43 and the insulating layer 11, and the plug 83 connects the conductive layer 25c to the conductive layer 81. A conductive layer 88c is provided inside an opening provided in the insulating layer 44 and the insulating layer 45. The conductive layer 25c is connected to the conductive layer 24 via the conductive layer 88c.

[0179] The conductive layer 25c includes a conductive layer 25c1 and a conductive layer 25c2 over the conductive layer 25c1. The conductive layers 25a1 and 25a2 can be referred to for materials, structures, and the like that can be used for the conductive layers 25c1 and 25c2, respectively.

[0180] Note that although an example of providing a conductive layer 81 as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also called a multilayer wiring layer) can be used between the layer in which the transistor 90 is provided and the layer in which the memory cell 15 is provided.

[0181] The above is a description of an example of the configuration of the storage device.

[0182] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0183] <Insulating Layer> For the insulating layer 52, for example, a material that functions as a dielectric can be used. As the dielectric, for example, a high dielectric constant (high-k) material can be preferably used. Specifically, for example, for the insulating layer 52, a high dielectric constant material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used. Alternatively, as another example, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably to use hafnium oxide having an amorphous structure. Furthermore, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３By using a high dielectric constant material for the dielectric of the capacitance element 30, the capacitance value can be increased, and the voltage written to the capacitance element 30 can be held for a long period of time.

[0184] Furthermore, a material that can have ferroelectricity can be used for the insulating layer 52. Furthermore, by using a material that can have ferroelectricity for the insulating layer 52, the capacitive element 30 can be a ferroelectric capacitor.

[0185] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and hafnium zirconium oxide (HfZrO Ｘ (where X is a real number greater than 0), and the element J is added to hafnium oxide. １ (Element J here １ refers to one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr), and zirconium oxide is doped with element J. ２ (Element J here ２ Examples of materials that can have ferroelectricity include materials to which one or more elements selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr) are added. Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above may be used. Incidentally, hafnium oxide, zirconium oxide, zirconium hafnium oxide, and hafnium oxide containing element J may be used. １The crystal structure (characteristics) of a material to which an ion beam is added may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material that can have ferroelectricity.

[0186] Among these, materials having hafnium oxide or materials having hafnium oxide and zirconium oxide are preferred as materials capable of exhibiting ferroelectricity, since they can exhibit ferroelectricity even in thin films of a few nanometers. This allows the process of fabricating a ferroelectric capacitor to be shortened. In this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.

[0187] When the insulating layer 52 is formed by the ALD method using a material containing hafnium oxide and zirconium oxide, for example, tetrakis(ethylmethylamido)hafnium (TEMAHf) or hafnium tetrachloride can be used as a precursor containing hafnium. Also, tetrakis(ethylmethylamido)zirconium (TEMAZr) or zirconium tetrachloride can be used as a precursor containing zirconium. Also, H ２ O and O ３ However, the oxidizing agent is not limited to these. For example, O ２ , O ３ , N ２ O, NO ２ , H ２ O and H ２ O ２ It can include one or more selected from the following.

[0188] The insulating layer 52 may have a single layer structure or a multilayer structure. In particular, when the insulating layer 52 has a multilayer structure, each insulating layer included in the insulating layer 52 may be made of, for example, one or both of the high-k material and the material that may have ferroelectricity.

[0189] The thickness of the insulating layer 52 is preferably 1 nm or more and 30 nm or less, more preferably 2 nm or more and 20 nm or less, and even more preferably 3 nm or more and 15 nm or less.

[0190] Furthermore, unlike paraelectric materials, ferroelectric materials maintain their internal dielectric polarization even when no voltage is applied (sometimes called remanent polarization). Because the dielectric polarization is maintained, using a ferroelectric capacitor for the capacitive element 30 suppresses degradation of data stored in the memory cells 15. This reduces the number of refresh operations for the memory cells 15, thereby reducing the power consumption of the storage device 10.

[0191] The insulating layer 22 functions as a gate insulating layer of the transistor. The insulating layer 22 can be made of an insulating material including a high-k material.

[0192] Furthermore, it is preferable to use a laminate of insulating materials made of high-k materials as the insulating layer 22, and it is preferable to use a laminate structure of a high-k material and a material having a higher dielectric strength than the high-k material.

[0193] Furthermore, the insulating layer 22 may be made of a material exhibiting ferroelectricity.

[0194] The insulating layer 22 may have an insulating film that has the function of capturing or fixing hydrogen. The insulating layer 22 may also have an insulating film that has a barrier property against hydrogen. By suppressing the diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, a highly reliable transistor can be realized.

[0195] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0196] As the insulating film having a barrier property against hydrogen, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like is preferably used.

[0197] The insulating layer 22 may also have an insulating film that releases oxygen when heated.

[0198] The insulating layer 22 may have an insulating film having a barrier property against oxygen. As the insulating film having a barrier property against oxygen, an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, or the like is preferably used. As the insulating film having a barrier property against oxygen and hydrogen, an aluminum oxide film, a silicon nitride film, a hafnium oxide film, or the like is preferably used.

[0199] Furthermore, the insulating layer 22 may have an insulating film that has barrier properties against hydrogen.

[0200] Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21 .

[0201] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0202] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0203] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0204] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include hafnium aluminate. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0205] The insulating layer 11, the insulating layer 43, the insulating layer 46, and the insulating layer 47 can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not required as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 20 can be stabilized.

[0206] The insulating layer 43 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The insulating layer 43 can be an oxide insulating film that can be used for the gate insulating layer.

[0207] For example, an insulating film having a barrier property against hydrogen, an insulating film having a function of capturing or fixing hydrogen, etc. can be used as the insulating layer 45 and the insulating layer 48. This makes it possible to prevent hydrogen from diffusing from above the insulating layer 45 or the insulating layer 48 toward the semiconductor layer 21.

[0208] <Conductive Layer> For the conductive layer, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, an alloy containing two or more selected from the above-mentioned metal elements, or an alloy combining two or more selected from the above-mentioned metal elements. For the conductive layer, it is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0209] Using a material with high electrical conductivity (a material with low electrical resistance) can reduce the power consumption of the memory device 10. Furthermore, using a material with high electrical conductivity (a material with low electrical resistance) can reduce the amount of electric heat generated, thereby reducing the thermal effect on the transistor 20.

[0210] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0211] The conductive layer 25a and the conductive layer 25b are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 25a or the conductive layer 25b in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 25a or the conductive layer 25b and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 25a or the conductive layer 25b in contact with the semiconductor layer 21.

[0212] For the conductive layer 25a2 and the conductive layer 25b2 in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0213] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0214] For example, the conductive layer 25a2 and the conductive layer 25b2 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0215] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0216] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layer 25a and the conductive layer 25b.

[0217] The conductive layer 51 functions as one electrode of the capacitor 30 , and the conductive layer 53 functions as the other electrode of the capacitor 30 .

[0218] Various conductive materials can be used for each of the conductive layer 51 and the conductive layer 53. For example, the above-mentioned materials applicable to a conductive layer can be used.

[0219] Each of the conductive layer 51 and the conductive layer 53 may have a single layer structure or a stacked layer structure.

[0220] The conductive layer 51 has, for example, a columnar shape. Therefore, when a laminated structure is applied to the conductive layer 51, for example, the conductive layer 51 can have a configuration including a first layer that serves as a core and a second layer and subsequent layers that surround the core.

[0221] It is preferable to use, for example, titanium nitride as the conductive layer 51 and the conductive layer 53. Furthermore, when the conductive layer has a laminated structure, for example, by using titanium nitride for the layer on the side in contact with the insulating layer 52, the ferroelectricity of the insulating layer 52 may be more easily exhibited.

[0222] Furthermore, it is preferable to use a material that can be formed using the ALD method for the conductive layer 51. The ALD method has high coverage and is suitable as a method for forming a conductive film in a fine opening with a high aspect ratio.

[0223] The conductive layer 53 can also function as a wiring layer. Therefore, by using a low-resistance material for the conductive layer 53, the wiring resistance can be reduced and the operating speed of the memory device can be increased.

[0224] The resistance of the conductive layer 53 can be suitably reduced by using a metal such as tungsten or ruthenium for the conductive layer 53. Alternatively, for example, these metals can be stacked with titanium nitride. As an example, titanium nitride can be used as the first layer (here, the layer in contact with the insulating layer 52), and tungsten can be used as the second layer on the titanium nitride.

[0225] The conductive layer 53, the conductive layer 23, the conductive layer 25a, and the conductive layer 25b also function as wirings, and therefore, it is preferable to use a stack of low-resistance conductive materials. For example, the low-resistance conductive material that can be used for the conductive layer 23 described above can also be used for the upper layer of the conductive layer 25a and the conductive layer 25b.

[0226] The conductive layer 24 can function as a wiring. The conductive material that can be used for the conductive layer 23, the conductive layer 25a, and the conductive layer 25b can be used for the conductive layer 24. In particular, it is preferable to use a conductive material with low resistance.

[0227] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0228] As the metal oxide that can be used for the semiconductor layer 21, an In oxide is preferably used. Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or a metalloid element having a high bond energy with oxygen, such as a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred.

[0229] Indium oxide is preferably used for the semiconductor layer. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer, the transistor can have a large on-state current and high frequency characteristics.

[0230] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0231] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0232] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 21A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 21B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0233] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 21B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 21A (see Non-Patent Document 6). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 21A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 21A.

[0234] 21A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0235] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0236] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0237] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable to include an element that is common to the source electrode and drain electrode of a transistor. Examples of such elements include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0238] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 21A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0239] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0240] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 21B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 21A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0241] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0242] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0243] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0244] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0245] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0246] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0247] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0248] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0249] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0250] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0251] The indium oxide film in the channel formation region may contain elements that can maintain a low carrier concentration, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such elements include gallium, aluminum, scandium, yttrium, and lanthanides (lanthanum, neodymium, samarium, erbium, ytterbium, etc.). These elements exist primarily as trivalent cations in oxides, and therefore can maintain a low carrier concentration in indium oxide.

[0252] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0253] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 21C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0254] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0255] Furthermore, as shown in FIG. 21C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0256] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0257] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0258]

[0259] A layer (hereinafter referred to as a seed layer) in contact with at least a portion of the crystalline indium oxide film is preferably made of a material containing crystals with a small difference in lattice constant (also referred to as lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0260] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L１ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0261] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0262] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0263] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0264] In a crystalline film, for example, crystal grains can be confirmed in a high-resolution transmission electron microscope (TEM) image. In addition, in a crystalline film, for example, crystal grain boundaries can sometimes be confirmed in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film.

[0265] The content of the first element in the semiconductor layer is preferably low. Furthermore, the concentration of the first element in the semiconductor layer is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. The concentration of the first element in the semiconductor layer is preferably, for example, 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0266] Furthermore, by using a precursor that has been distilled one or more times during deposition of the semiconductor layer, the concentration of the first element in the semiconductor layer can be set to 0.01 atomic % (100 ppm) or less, 0.0001% (1 ppm) or less, or 0.00001% (0.1 ppm or 100 ppb) or less. That is, the content (purity) of indium excluding oxygen in the semiconductor layer can be set to 99.99 atomic % or more (4N), 99.9999 atomic % or more (6N), or 99.99999 atomic % or more (7N).

[0267] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer, the crystallinity of the semiconductor layer can be improved.

[0268] When a semiconductor layer contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. Note that the same phenomenon as when a semiconductor layer contains zinc atoms may occur.

[0269] The concentration of the first element can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), or inductively coupled plasma optical emission spectroscopy (ICP-AES). The evaluation can be performed using plasma-atomic emission spectroscopy or the like.

[0270] The metal oxide functioning as a semiconductor preferably has a band gap of 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap for the semiconductor layer, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0271] In a transistor using a metal oxide for a semiconductor layer, the off-state current value per 1 μm of channel width at room temperature is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ It is possible to make it less than A / μm.

[0272] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be increased. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

[0273] The semiconductor layer may be a single layer or may have a stacked structure of two or more layers. For example, when the semiconductor layer has a two-layer structure of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path (channel). In other words, the first semiconductor layer has a channel formation region on the surface on the second semiconductor layer side and in the vicinity thereof.

[0274] The above-described structure can reduce carriers trapped at the interface of the first semiconductor layer and its vicinity. Furthermore, the channel can be located away from the surface of the gate insulating layer, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0275] Examples of metal oxides that can be used for the second semiconductor layer include In—Ga oxide, In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), In—Al—Zn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, indium titanium zinc oxide (In—Ti—Zn oxide), ITSO, etc. Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), aluminum tin oxide (Al—Sn oxide), etc. can be used.

[0276] The In-Zn oxide used in the second semiconductor layer can specifically have a composition of In:Zn=1:1 (atomic ratio) or thereabouts, In:Zn=2:1 (atomic ratio) or thereabouts, or In:Zn=4:1 (atomic ratio) or thereabouts. Furthermore, the IGZO used in the second semiconductor layer can specifically have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts, In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or In:Ga:Zn=1:3:4 (atomic ratio) or thereabouts.

[0277] The crystallinity of the metal oxide included in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0278] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0279] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0280] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0281] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0282] The above is a description of the components.

[0283] [Configuration Example 4] Configuration examples of a storage device of one embodiment of the present invention will be described with reference to FIGS.

[0284] The transistor 20 used in the memory cell 15 can be formed using a thin-film method. Therefore, the memory cell 15 including the transistor 20 can be stacked on another functional layer, such as a layer in which a memory cell array is formed or a layer in which a functional circuit is formed. For example, as shown in FIG. 6 , a layer including a memory cell array having a plurality of memory cells 15 can be stacked on a functional circuit provided on a substrate 91. By providing the layer including the memory cell array on the functional circuit, circuit integration can be achieved. Furthermore, by providing the layer including the memory cell array on the functional circuit, the wiring length between the functional circuit and the memory cell array can be shortened, thereby improving data accessibility and reducing power consumption.

[0285] Furthermore, the memory cell arrays can be stacked, which increases the memory density per chip.

[0286] 8 shows an example of laminating a layer 77 in which a memory cell array is provided. A plurality of memory cells 15 are provided in the layer 77, and the plurality of memory cells 15 are arranged in a matrix in a plan view, for example.

[0287] As shown in Fig. 8, the layers 77 can be stacked. Although Fig. 8 shows an example in which two layers 77 are stacked, three or more layers 77 can also be stacked.

[0288] As shown in FIGS. 9 and 10, a layer 77_S may be formed using a transistor 90 formed on a substrate 91 instead of the transistor 20, and a layer 77 may be stacked over the layer 77_S.

[0289] 9 includes a plurality of memory cells 15. Each memory cell 15 includes a transistor 90 and a capacitor 30 provided over the transistor 90. The transistor 90 shown in FIG. 6 can be used as the transistor 90.

[0290] Although FIG. 8 shows an example in which one layer 77 is stacked on the layer 77_S, two or more layers of the layer 77 may be stacked.

[0291] FIG. 10 shows an example in which the configuration of the transistor 90 is different from that of FIG.

[0292] 10 has a configuration in which an insulating layer 93 functioning as a gate insulating layer and a conductive layer 94 functioning as a gate electrode are provided in a trench portion formed in a substrate 91. Furthermore, an insulating layer UI1 is formed on the conductive layer 94 in the trench.

[0293] A semiconductor region 92 is formed in the region corresponding to the side surface and bottom surface of the trench portion in the substrate 91. Above the semiconductor region 92, a low resistance region 95a and a low resistance region 95b are formed.

[0294] The transistor 20 shown in FIG. 10 has a semiconductor region 92 that is U-shaped in cross section, and low-resistance regions 95a and 95b that face each other across a trench portion in plan or cross section.

[0295] The insulating layer UI1 functions as an insulating layer to prevent direct contact between the low resistance region 95a and the low resistance region 95b.

[0296] In the memory device of one embodiment of the present invention, the capacitor 30 can be made nonvolatile by using a ferroelectric insulating layer for the insulating layer 52. This allows data to be held for a long time in the memory cell 15. Furthermore, by using a ferroelectric insulating layer for the insulating layer 52, the reliability of the memory cell 15 can be improved in some cases.

[0297] Furthermore, in the memory device of one embodiment of the present invention, by using an OS transistor as the transistor of the memory cell 15, leakage of charge held in the capacitor 30 can be extremely small. Thus, data can be held in the memory cell 15 for a long time.

[0298] 11 differs from FIG. 10 in the configuration of the capacitance elements 30 included in the layer 77. In FIG. 11, the conductive layers 53 of the capacitance elements 30 included in the layer 77 are not provided separately for each capacitance element 30 or for each series of capacitance elements 30 arranged in one direction (for example, the Y direction shown in FIG. 3A ), but are provided in common for the capacitance elements 30 in, for example, an entire block included in the layer 77. When a ferroelectric insulating layer is not used as the insulating layer 52 of the capacitance element 30, for example, the configuration shown in FIG. 11 may be used.

[0299] A configuration in which an insulating layer without ferroelectricity is used for the insulating layer 52 may simplify the manufacturing process of the memory cell 15 and the peripheral circuits, etc. Furthermore, the material used for the insulating layer 52 can be appropriately selected according to the operating speed, process temperature, etc. required for the memory cell 15.

[0300] In the memory device of one embodiment of the present invention, for example, a ferroelectric insulating layer can be used for the insulating layer 52 of the capacitor used in the layer 77_S, and an insulating layer that is less ferroelectric than the layer 77_S can be used for the insulating layer 52 of the capacitor used in the layer 77. Alternatively, a ferroelectric insulating layer can be used for the layer 77_S, and an OS transistor can be used as the transistor in the layer 77.

[0301] Since a plurality of layers 77 can be stacked, the memory capacity can be increased, and therefore the memory can be suitably used as a large-capacity memory.

[0302] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0303] Embodiment 2 In this embodiment, structural examples of a memory device which is a semiconductor device of one embodiment of the present invention and a peripheral circuit included in the memory device will be described with reference to FIGS. 12 to 14B.

[0304] 12 shows an example of the configuration of a memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0305] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is connected to the memory cell of the memory cell array 1470. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, a plate line driver circuit, etc., and can select the row to access.

[0306] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside as power supply voltages. Control signals (CE, WEN, RES), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0307] The control logic circuit 1460 processes control signals (CE, WEN, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WEN is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0308] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0309] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

[0310] FIG. 13 shows an example of the configuration of the memory cell array 1470 and memory cells MC.

[0311] The memory cell array 1470 shown in Fig. 13 has memory cells 1480 arranged in a matrix of m / 2 rows and n columns (m is an even number greater than or equal to 1, and n is an integer greater than or equal to 1). The memory cells 1480 shown in Fig. 13 are storage circuits applicable to the memory cells MC described above, and are an example of the circuit configuration of a memory cell using a ferroelectric capacitor. Fig. 13 also shows a row circuit 1420 and a column circuit 1430.

[0312] 13, a memory cell 1480 includes a transistor M9 and a capacitance element Cfe. In the memory cell 1480, the transistor M9 can correspond to the transistor 20 described in the first embodiment, and the capacitance element Cfe can correspond to the capacitance element 30 described in the first embodiment.

[0313] In the memory cell array 1470 of FIG. 13, m memory cells 1480 are connected to one wiring BL.

[0314] In the following description, attention is focused on one of the memory cells 1480 shown in FIG.

[0315] One of the source and drain of the transistor M9 is connected to a wiring BL (e.g., one of the wirings BL[1] to BL[n]). The other of the source and drain of the transistor M9 is connected to one of a pair of electrodes of a capacitor Cfe. The gate of the transistor M9 is connected to a wiring WL (e.g., one of the wirings WL[1] to WL[m]). The other of the pair of electrodes of the capacitor Cfe is connected to a wiring PL (e.g., one of the wirings PL[1] to PL[m]).

[0316] The wiring WL functions as a word line, and can control switching between an on state and an off state of the transistor M9 by applying a potential to the wiring WL as a selection signal or a non-selection signal. For example, the transistor M9 can be turned on by setting a selection signal applied to the wiring WL to a high potential (H), and the transistor M9 can be turned off by setting a non-selection signal applied to the wiring WL to a low potential (L). The wiring WL is connected to a word line driver circuit included in the row circuit 1420, and the word line driver circuit can apply a selection signal or a non-selection signal to the wiring WL.

[0317] The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to a data signal applied to the wiring BL is applied to one of a pair of electrodes of the capacitor Cfe. The wiring BL is connected to a bit line driver circuit included in the column circuit 1430. The bit line driver circuit has a function of generating a data signal to be written to the memory cell MC. The bit line driver circuit also has a function of reading data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read using the sense amplifier.

[0318] The wiring PL has the function as a plate line. A predetermined potential applied to the wiring PL is supplied to the other of the pair of electrodes of the capacitive element Cfe. The wiring PL is connected to a plate line driver circuit included in the row circuit 1420, and the plate line driver circuit is a circuit that can apply the potential to the wiring PL during, for example, a write operation or a read operation.

[0319] The capacitive element Cfe has a material that can have ferroelectricity as a dielectric layer between two electrodes. By using a ferroelectric layer that can be thinned as the dielectric layer of the capacitive element and combining it with a miniaturized transistor, a high-integration memory device can be obtained. Hereinafter, the dielectric layer included in the capacitive element Cfe is referred to as a ferroelectric layer.

[0320] The ferroelectric layer included in the capacitive element Cfe has hysteresis characteristics. FIG. 14A is a graph showing an example of the hysteresis characteristics. In FIG. 14A, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one of the pair of electrodes of the capacitive element Cfe and the potential of the other of the pair of electrodes of the capacitive element Cfe.

[0321] Also, in FIG. 14A, the vertical axis represents the polarization of the ferroelectric layer. When the value is positive, it indicates that positive charges are biased to one side of the pair of electrodes of the capacitive element Cfe and negative charges are biased to the other electrode side of the pair of electrodes of the capacitive element Cfe. On the other hand, when the polarization has a negative value, it indicates that positive charges are biased to the other side of the pair of electrodes of the capacitive element Cfe and negative charges are biased to one side of the pair of electrodes of the capacitive element Cfe.

[0322] Note that the voltage shown on the horizontal axis of the graph in FIG. 14A may be the difference between the potential of the other electrode of the pair of electrodes of the capacitive element Cfe and the potential of one electrode of the pair of electrodes of the capacitive element Cfe. Also, the polarization shown on the vertical axis of the graph in FIG. 14A may be set to a positive value when positive charges are biased to the other electrode side of the pair of electrodes of the capacitive element Cfe and negative charges are biased to one electrode side of the pair of electrodes of the capacitive element Cfe, and set to a negative value when positive charges are biased to one electrode side of the pair of electrodes of the capacitive element Cfe and negative charges are biased to the other electrode side of the pair of electrodes of the capacitive element Cfe.

[0323] 14A, the hysteresis characteristic of the ferroelectric layer can be expressed by a curve 61 and a curve 62. The voltages at the intersections of the curve 61 and the curve 62 are defined as VSP and −VSP. It can be said that VSP and −VSP have opposite polarities.

[0324] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 61. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can each be referred to as saturation polarization voltages. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Also, while FIG. 14A shows a case where the absolute values ​​of the first and second saturation polarization voltages are equal, the absolute values ​​of the two may be different.

[0325] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 61 and the polarization of the ferroelectric layer is zero. Furthermore, −Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 62 and the polarization of the ferroelectric layer is zero. Vc and −Vc can be referred to as coercive voltages, respectively. The values ​​of Vc and −Vc can be referred to as values ​​between −VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and −Vc may be referred to as the second coercive voltage. Although FIG. 14A shows that the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, their absolute values ​​may be different.

[0326] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "remanent polarization Pr" and the minimum value is called "remanent polarization -Pr". Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "remanent polarization 2Pr".

[0327] As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed by the difference between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe. Also, as described above, the other of the pair of electrodes of the capacitance element Cfe is connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be controlled.

[0328] 13 , an example of a method for driving the memory cell 1480 will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitor Cfe is the difference (potential difference) between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes (wiring PL) of the capacitor Cfe. Furthermore, the transistor M9 is an n-channel transistor.

[0329] 14B is a timing chart showing an example of a method for driving the memory cell 1480. FIG. 14B shows an example of writing and reading binary digital data to the memory cell 1480. Specifically, FIG. 14B shows an example of writing data “1” to the memory cell 1480 from time T01 to time T02, reading and rewriting from time T03 to time T05, reading from time T11 to time T13 and writing data “0” to the memory cell 1480, reading and rewriting from time T14 to time T16, and reading from time T17 to time T19 and writing data “1” to the memory cell 1480.

[0330] A reference potential Vref is supplied to the sense amplifier electrically connected to the wiring BL. In the read operation shown in Figure 14B, when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0331] Between time T01 and time T02, the word line driver circuit applies a high potential to the wiring WL as a selection signal. This turns on transistor M9. Also, the potential of wiring BL is set to Vw. Because transistor M9 is on, the potential of one of the pair of electrodes of capacitance element Cfe becomes Vw. Furthermore, GND is applied to wiring PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to memory cell 1480. Therefore, the period from time T01 to time T02 can be said to be a period during which a write operation is performed.

[0332] Here, Vw is preferably equal to or greater than VSP, for example. Although GND is a ground potential in this specification, it is not necessarily the ground potential as long as the memory cell 1480 can be driven to satisfy the spirit of one embodiment of the present invention. For example, if the absolute values ​​of the first and second saturation polarization voltages are different and the absolute values ​​of the first and second coercive voltages are different, GND can be a potential other than ground.

[0333] Between time T02 and time T03, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Between time T01 and time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be made equal to or higher than VSP, and therefore, between time T02 and time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 62 shown in FIG. 14A. As a result, between time T02 and time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

[0334] After applying GND to both the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal, thereby turning off the transistor M9. This completes the write operation, and data "1" is stored in the memory cell 1480. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage -Vc.

[0335] Between time T03 and time T04, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. Furthermore, the plate line driver circuit applies Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" between time T01 and time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, a current flows through the line BL, and the potential of the line BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in the memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may also be higher than Vw, for example.

[0336] Since the above read is a destructive read, the data "1" held in memory cell 1480 is lost. Therefore, from time T04 to time T05, Vw is applied to the wiring BL by the bit line driver circuit, and GND is applied to the wiring PL by the plate line driver circuit. This rewrites the data "1" to memory cell 1480. Therefore, the period from time T04 to time T05 can be said to be the period during which the rewrite operation is performed.

[0337] From time T05 to time T11, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. Then, the word line driver circuit applies a low potential as a non-selection signal to the wiring WL. This completes the rewrite operation, and data "1" is held in the memory cell 1480.

[0338] Between time T11 and time T12, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Also, the plate line driver circuit applies a potential Vw to the wiring PL. Since data "1" is stored in the memory cell 1480, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the memory cell 1480 is read. Therefore, the period from time T11 to time T12 can be said to be a period during which a read operation is performed.

[0339] Between time T12 and time T13, the bit line driver circuit applies GND to the wiring BL. Since the transistor M9 is in the on state, the potential of one of the pair of electrodes of the capacitance element Cfe becomes GND. In addition, the plate line driver circuit applies a potential Vw to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." This allows data "0" to be written to the memory cell 1480. Therefore, the period from time T12 to time T13 can be said to be a period during which a write operation is performed.

[0340] Between time T13 and time T14, GND is applied to the line BL by the bit line driver circuit, and GND is applied to the line PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe between time T12 and time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe between time T13 and time T14 changes according to the curve 61 shown in FIG. 14A. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe between time T13 and time T14.

[0341] After applying GND to the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal, thereby turning off the transistor M9. This completes the write operation, and data "0" is stored in the memory cell 1480. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0342] Between time T14 and time T15, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on the transistor M9. The plate line driver circuit also applies a potential Vw to the line PL. By setting the potential of the line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" between time T12 and time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Specifically, the potential of the line BL is equal to or lower than Vref. Therefore, the bit line driver circuit can read the data "0" stored in the memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0343] From time T15 to time T16, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies a potential Vw to the wiring PL, thereby rewriting data "0" to the memory cell 1480. Therefore, the period from time T15 to time T16 can be said to be a period during which a rewrite operation is performed.

[0344] Between time T16 and time T17, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. After that, the word line driver circuit applies a low potential as a non-selection signal to the wiring WL. This completes the rewrite operation, and data "0" is held in the memory cell 1480.

[0345] Between time T17 and time T18, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Furthermore, the plate line driver circuit applies a potential Vw to the wiring PL. Since data "0" is stored in the memory cell 1480, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the memory cell 1480 is read out. Therefore, the period from time T17 to time T18 can be considered a period during which a read operation is performed.

[0346] Between time T18 and time T19, the bit line driver circuit applies a potential Vw to the wiring BL. Because the transistor M9 is on, the potential of one electrode of the capacitance element Cfe becomes Vw. In addition, the plate line driver circuit applies a potential GND to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to the memory cell 1480. Therefore, the period from time T18 to time T19 can be said to be the period during which the write operation is performed.

[0347] After time T19, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-selection signal. This completes the write operation, and data "1" is stored in the memory cell 1480.

[0348] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0349] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, so power consumption can be reduced.

[0350] In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 １０ or more, preferably 1×10 １２ or more, more preferably 1×10 １５ The FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0351] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of one day or more, preferably ten days or more, more preferably one year or more, and even more preferably ten years or more in a temperature environment of 150°C or 200°C.

[0352] The FE memory can also be applied to cache memories and registers of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc. By combining the FE memory with the cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0353] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0354] Embodiment 3 In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 15 . A transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor are used in a memory device of one embodiment of the present invention. Since the off-state current of an OS transistor is extremely small, a memory device including an OS transistor has excellent retention characteristics and can function as a nonvolatile memory.

[0355] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 15 shows a conceptual diagram illustrating the hierarchy of memory devices used in semiconductor devices. In Figure 15, the conceptual diagram illustrating the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0356] In FIG. 15 , from the top layer of the triangle, memories integrated as registers in arithmetic processing devices such as a CPU, GPU, and NPU (Neural Processing Unit), cache memory (sometimes simply referred to as cache, and typically L1, L2, and L3 caches), main memory such as DRAM, and storage memory such as 3D NAND and hard disk (also called HDD: Hard Disk Drive) are shown.

[0357] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0358] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0359] The memory device of one embodiment of the present invention can be used as a DRAM.

[0360] 15 illustrates only up to the L3 cache, but the cache memory is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0361] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0362] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0363] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0364] The memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits by using OS transistors. Furthermore, the use of OS transistors allows monolithic stacking with peripheral circuits. Therefore, this has advantages in terms of data access with peripheral circuits. Furthermore, the degree of integration can be increased by stacking with peripheral circuits. Furthermore, the use of OS transistors enables the memory device of one embodiment of the present invention to retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

[0365] Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed of rewriting, can be increased in some cases.

[0366] Furthermore, since the memory device of one embodiment of the present invention includes a capacitor including a ferroelectric material, data can be retained for a long time. Therefore, when the memory device is used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0367] The storage device of one embodiment of the present invention can be used for the Target2 region and the Target1 region shown in Figure 15. In particular, the storage device can be suitably used for the Target1 region.

[0368] 15, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC described above.

[0369] By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, compared to a configuration using a DRAM. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target 1.

[0370] Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the degree of integration of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

[0371] Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and therefore can be suitably used for Target1_2, which is rewritten more frequently than Target1. By applying the storage device of one embodiment of the present invention to Target1_2, the calculation efficiency of the storage device can be improved and power consumption can be reduced.

[0372] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be suppressed.

[0373] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0374] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0375] 16A and 16B , an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0376] As shown in FIG. 16A , the chip 1200 includes a CPU 1211 , a GPU 1212 , one or more analog arithmetic units 1213 , one or more memory controllers 1214 , one or more interfaces 1215 , and one or more network circuits 1216 .

[0377] 16B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the package substrate 1201 opposite the first surface, which is connected to a motherboard 1203.

[0378] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 and the flash memory 1222 may be replaced with the storage device 10 described in the first embodiment.

[0379] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the storage device 10 described above. The GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing or multiply-and-accumulate operations.

[0380] Furthermore, since the CPU 1211 and GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0381] The analog calculation unit 1213 has one or both of an AD (analog-digital) conversion circuit and a DA (digital-analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0382] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0383] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0384] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0385] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0386] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204 .

[0387] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit included in the GPU 1212 enables calculations such as deep neural networks (DNNs), which are AI models. Representative examples of AI models include convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0388] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0389] Embodiment 5 In this embodiment, an application example of a semiconductor device using a storage device according to one embodiment of the present invention will be described. The storage device 10 described in the previous embodiment can be applied to various removable storage devices such as a memory card (e.g., an SD card), a USB memory, and an SSD (Solid State Drive) as a cache memory or a main memory. Several configuration examples of removable storage devices are schematically shown in FIGS. 17A to 17E . The semiconductor device according to one embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0390] 17A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1105 or the like.

[0391] FIG. 17B is a schematic diagram of the appearance of an SD card, and FIG. 17C is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1114 or the like.

[0392] FIG. 17D is a schematic diagram of the appearance of an SSD, and FIG. 17E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1154 or the like.

[0393] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0394] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0395] [Electronic Component] Fig. 18A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 18A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that Fig. 18A omits some parts in order to show the inside of electronic component 700.

[0396] The substrate 701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0397] Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered with mold 711, and another portion of lead frame 712 is exposed to the outside of mold 711. In particular, lead frame 712 exposed to the outside of mold 711 functions as, for example, a terminal for mounting electronic component 700 on a printed circuit board.

[0398] Within mold 711, electrode pads 713 are provided on lead frame 712, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on a printed circuit board, for example, by contacting lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0399] Next, the semiconductor device 710 will be described. For example, as shown in FIG. 18B , the semiconductor device 710 has a drive circuit layer 715 and a memory layer 716. The memory layer 716 can be configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. Configurations other than the monolithic stacked configuration include a configuration in which a plurality of memory layers 716 are stacked using through-electrode technology (e.g., TSV (Through Silicon Via)) and Cu-Cu direct bonding technology. By stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0400] Furthermore, the semiconductor device 710 has a configuration in which multiple memory cell arrays are stacked, which can improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange.

[0401] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0402] Next, Fig. 18C shows a modified example of electronic component 700. Electronic component 700A shown in Fig. 18C differs from electronic component 700 in that it does not use lead frame 712, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

[0403] 18C shows an example in which electrodes 733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, substrate 701 is provided with through-hole vias, and conductive layers 732 that function as wiring are provided in these vias. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below substrate 701 so as to be in contact with them below conductive layer 732.

[0404] Furthermore, the electrodes 733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0405] Further, the electronic component 700A can be mounted on other substrates using various mounting methods, not limited to BGAs and PGAs. Examples of mounting methods include, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0406] Further, the electronic component of one aspect of the present invention may be in the form of a SiP (System in Package) or an MCM (Multi Chip Module). For example, in the electronic component 700C shown in FIG. 18D, an interposer 731 is provided on a package substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0407] In the electronic component 700C of FIG. 18D, as an example, an example of using the semiconductor device 710 as a high bandwidth memory (HBM: High Bandwidth Memory) is shown. For example, the semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0408] Similar to the substrate 701, the package substrate 734 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can use, for example, a silicon interposer or a resin interposer.

[0409] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0410] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0411] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0412] Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 700C so that the heat sink overlaps the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[0413] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 19A . The electronic device 6500 shown in FIG. 19A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6500 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in, for example, the display portion 6502, the control device 6509, or the like.

[0414] 19B is an information terminal that can be used as a notebook computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6600 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in the display portion 6615, the control device 6616, or the like.

[0415] The semiconductor device of one embodiment of the present invention is preferably provided in the electronic devices 6500 and 6600 because power consumption can be reduced.

[0416] 19C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 19C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0417] The computer 5620 can have the configuration shown in the perspective view in Fig. 19D, for example. In Fig. 19D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0418] A PC card 5621 shown in Figure 19E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 19E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0419] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0420] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0421] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0422] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 700 can be used as the semiconductor device 5627.

[0423] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wirings of the board 5622. For example, the semiconductor device 5628 can be a memory device which is a semiconductor device of one embodiment of the present invention. For example, the electronic component 700 described above can be used for the semiconductor device 5628.

[0424] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0425] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0426] Fig. 20A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 20A, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0427] Although not shown in FIG. 20A, the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit.

[0428] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0429] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0430] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0431] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably formed using a semiconductor device which is one embodiment of the present invention.

[0432] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0433] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0434] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0435] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0436] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0437] Fig. 20B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 20B has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0438] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0439] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0440] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0441] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0442] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0443] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0444] ADDR: address signal, BL[1]: wiring, BL[n]: wiring, BL: wiring, CE: control signal, Cfe: capacitance element, dm: capacitance element, GND: potential, MC: memory cell, PL: wiring, Pr: remanent polarization, RDATA: data signal, RES: control signal, TrP: transistor, TrQ: transistor, Vw: potential, WDATA: data signal, WEN: control signal, WL: wiring, 10: memory device, 11: insulating layer, 15: memory cell, 20: transistor, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 24: conductive layer, 25a: conductive layer, 25b: conductive layer, 2 5c: conductive layer, 30: capacitance element, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 46b: conductive layer, 47: insulating layer, 48: insulating layer, 51: conductive layer, 52: insulating layer, 53: conductive layer, 53f: conductive film, 61: curve, 62: curve, 79: insulating layer, 80: region, 81: conductive layer, 82: plug, 83: plug, 85: insulating layer, 86: insulating layer, 87: insulating layer, 88a: conductive layer, 88b: conductive layer, 88c: conductive layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 98: element Child separation layer, 99: line, 700: electronic component, 700A: electronic component, 700C: electronic component, 701: substrate, 710: semiconductor device, 711: mold, 712: lead frame, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 731: interposer, 732: conductive layer, 733: electrode, 734: package substrate, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD Card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface,1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1480: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 650 3: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network,

Claims

a first transistor, a second transistor, a first capacitance element, a second capacitance element, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line; the first transistor, the second transistor, and the second insulating layer are each located on the first insulating layer; the third insulating layer is located on the first transistor and the second transistor; the first capacitance element, the second capacitance element, and the bit line are each located on the third insulating layer; the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer; the first transistor has a portion located within the first opening; the second transistor has a portion located within the second opening; the first transistor has a first electrode functioning as one of a source electrode and a drain electrode, and a second electrode functioning as the other of the source electrode and the drain electrode; the second transistor has the first electrode functioning as one of a source electrode and a drain electrode, and a third electrode functioning as the other of the first electrode and the drain electrode; the first electrode is connected to the bit line; the first capacitance element includes a fifth electrode having a columnar shape, a fourth insulating layer covering at least a part of a side surface of the columnar shape of the fifth electrode, and a sixth electrode; the second capacitance element includes a seventh electrode having a columnar shape, a fifth insulating layer covering at least a part of a side surface of the columnar shape of the seventh electrode, and an eighth electrode; the fourth insulating layer has a portion located between the fifth electrode and the sixth electrode, the fifth insulating layer has a portion located between the seventh electrode and the eighth electrode, the fourth insulating layer and the fifth insulating layer contain a material that may have ferroelectric properties, the second electrode is connected to the fifth electrode of the first capacitance element; The third electrode is connected to the seventh electrode of the second capacitance element. 　 In claim 1, a first plug, a second plug, and a third plug; each of the first plug to the third plug has a portion provided in the third insulating layer; the first electrode to the third electrode are each located on the second insulating layer; the first electrode is connected to the bit line via the first plug; the second electrode is connected to the fifth electrode of the first capacitance element via the third plug; the third electrode is connected to the seventh electrode of the second capacitive element via the third plug. 　 In claim 2, a semiconductor layer shared by the first transistor and the second transistor; the first transistor has a first gate line; the second transistor has a second gate line; the semiconductor layer has a first portion in contact with a first side surface of the first opening, a second portion in contact with an upper surface of the first insulating layer within the first opening, a third portion in contact with the second side surface of the first opening, a fourth portion in contact with the third side surface of the second opening, a fifth portion in contact with the upper surface of the first insulating layer within the second opening, and a sixth portion in contact with the fourth side surface of the second opening; the first portion and the third portion are disposed with the first gate line interposed therebetween, The fourth portion and the sixth portion are disposed with the second gate line interposed therebetween. 　 In claim 3, the semiconductor layer comprises a metal oxide; The memory device, wherein the metal oxide includes indium. 　 a first plurality of transistors, a second plurality of transistors, a first plurality of capacitance elements, a second plurality of capacitance elements, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line; the first plurality of transistors, the second plurality of transistors, and the second insulating layer are each located on the first insulating layer; the third insulating layer is located on the first plurality of transistors and on the second plurality of transistors; the first plurality of capacitive elements, the second plurality of capacitive elements, and the bit lines are each located on the third insulating layer; the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer; each of the first plurality of transistors has a portion located within the first opening; each of the second plurality of transistors has a portion located within the second opening; the first plurality of capacitive elements have a first plate line provided in common to the first plurality of capacitive elements; the second plurality of capacitive elements have a second plate line provided in common to the second plurality of capacitive elements; the first plate line and the second plate line are spaced apart from each other, a first transistor, which is one of the first plurality of transistors, has one of a source and a drain connected to the bit line and the other connected to one of the first plurality of capacitance elements; a second transistor, which is one of the second plurality of transistors, has one of a source and a drain connected to the bit line and the other connected to one of the second plurality of capacitance elements; each of the first plurality of capacitance elements has a fifth electrode having a columnar shape; each of the second plurality of capacitance elements has a sixth electrode having a columnar shape; each of the first plurality of capacitive elements has a fourth insulating layer sandwiched between the fifth electrode and the first plate line; each of the second plurality of capacitive elements has a fifth insulating layer sandwiched between the sixth electrode and the second plate line; The fourth insulating layer and the fifth insulating layer include a material that can have ferroelectric properties. 　 In claim 5, each of the first plurality of transistors has a first semiconductor layer; In the first opening, the first semiconductor layers of the first plurality of transistors are arranged in order along a first direction, each of the second plurality of transistors has a second semiconductor layer; In the second opening, the second semiconductor layers of the second plurality of transistors are arranged in order along a second direction, the bit lines extend in a third direction; The storage device, wherein the first direction and the second direction each intersect with the third direction. 　 In claim 6, the first plurality of transistors have a first gate line shared by the first plurality of transistors; In each of the first plurality of transistors, the first semiconductor layer has a first portion in contact with a first side surface of the first opening, a second portion in contact with an upper surface of the first insulating layer within the first opening, and a third portion in contact with a second side surface of the first opening; the first portion and the third portion are disposed with the first gate line interposed therebetween, the second plurality of transistors have a second gate line provided in common with the second plurality of transistors; In each of the second plurality of transistors, the second semiconductor layer has a fourth portion in contact with a third side surface of the second opening, a fifth portion in contact with an upper surface of the first insulating layer within the second opening, and a sixth portion in contact with the fourth side surface of the second opening; The fourth portion and the sixth portion are disposed with the second gate line interposed therebetween.

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