Electronic device

Abstract

Provided is a novel electronic device. The electronic device comprises a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer is provided with a drive circuit unit and an arithmetic circuit unit. The second layer is provided with a first pixel circuit unit, a second pixel circuit unit, and a storage circuit unit. The third layer is provided with a light-receiving element and a light-emitting element. The storage circuit unit has a function of holding a weight value set by a current signal of an analog value, and a function of performing a product-sum operation of the weight value and an input value. The arithmetic circuit unit has a function of performing arithmetic processing based on a neural network by using an output current output from the storage circuit unit with a signal obtained by light reception as the input value, and a function of outputting a signal for controlling the drive circuit unit in accordance with the arithmetic processing.

Description

electronic equipment

[0001] FIELD OF THE INVENTION One embodiment of the present invention relates to an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, head-mounted display (HMD) type electronic devices suitable for applications such as virtual reality (VR), augmented reality (AR), etc. HMDs can display images 360 degrees around the observer in response to the user's head movement, line of sight, or operation, allowing the user to experience a high level of immersion and realism.

[0004] The display device provided in the HMD is configured to be magnified and viewed via optical components or the like. In this case, there is a risk that the inclusion of optical components may increase the size of the housing, or that the user may easily see the pixels and perceive a strong sense of graininess, so the display device is required to have high resolution and / or be compact. In addition, in order to provide a more advanced user experience in an HMD-type electronic device, it is desirable to have a configuration that incorporates not only a display function but also a sensing function. For example, Patent Document 1 discloses a configuration in which a display device provided in an HMD has a sensing function in addition to a display function.

[0005] International Publication No. 2022 / 180481

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] In HMD-type electronic devices, if the display unit of the display device also has a sensing function for acquiring information about the user's eyes, the provision of a light-receiving element may impair the resolution of the display unit. Alternatively, if the sensing function for acquiring information about the eyes is located separately from the display unit, the acquired information about the eyes may be fragmented. When estimating a user's health condition from fragmented data, computational processing simulating an artificial neural network (hereinafter sometimes referred to as a neural network) is effective, but the computational processing may increase power consumption. Furthermore, due to concerns that prolonged use of HMD-type electronic devices that provide a highly immersive experience may impair a user's health condition, considerations for safety and security, such as continuous monitoring of the user's health condition while wearing the device, are required.

[0008] An object of one embodiment of the present invention is to provide an electronic device having a display device with a sensing function and high resolution.Another object of one embodiment of the present invention is to provide an electronic device having a display device that can reduce power consumption associated with arithmetic processing.Another object of one embodiment of the present invention is to provide a novel electronic device in which consideration is given to safety, security, and the like.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention is an electronic device including a housing and a display device. The housing has a function of placing the display device at and / or around the eye of a user. The display device is provided with a first layer, a second layer, and a third layer stacked in this order. The first layer is provided with a driver circuit unit and an arithmetic circuit unit. The second layer is provided with a first pixel circuit unit, a second pixel circuit unit, and a memory circuit unit. The third layer is provided with a light-receiving element and a light-emitting element. The light-emitting element is provided in a display portion of the display device. The light-receiving element is provided in a region outside the display portion. The first pixel circuit unit has a function of controlling the light-emitting element. The second pixel circuit unit has a function of controlling the light-receiving element. The memory circuit unit has a function of holding a weight value set by a current signal of an analog value and a function of performing a product-sum operation on the weight value and an input value. The arithmetic circuit unit has a function of performing arithmetic processing based on a neural network using an output current output from the memory circuit unit using a signal obtained by light reception as an input value, and a function of outputting a signal to control the driver circuit unit in accordance with the arithmetic processing.

[0011] In one embodiment of the present invention, the electronic device preferably includes a first transistor having a semiconductor layer including silicon in a channel formation region, and a second transistor having a semiconductor layer including metal oxide in a channel formation region.

[0012] In one embodiment of the present invention, the electronic device is preferably an oxide containing In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0013] In one embodiment of the present invention, the metal oxide is indium oxide.

[0014] In one aspect of the present invention, the electronic device is preferably one in which the light-receiving element is an organic photodiode and the light-emitting element is an organic electroluminescence element.

[0015] In one aspect of the present invention, the electronic device preferably includes a housing including a mounting portion and an optical member.

[0016] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0017] According to one embodiment of the present invention, an electronic device having a display device with a sensing function and excellent resolution can be provided. Alternatively, according to another embodiment of the present invention, an electronic device having a display device capable of reducing power consumption associated with arithmetic processing can be provided. Alternatively, according to another embodiment of the present invention, a novel electronic device in which consideration is given to safety, security, and the like can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0019] FIGS. 1A to 1C are diagrams illustrating exemplary configurations of a display device and an electronic device. FIGS. 2A to 2D are diagrams illustrating exemplary configurations of a display device. FIGS. 3A and 3B are diagrams illustrating exemplary configurations of a display device. FIGS. 4A and 4B are diagrams illustrating exemplary configurations of a display device. FIGS. 5A and 5B are diagrams illustrating exemplary configurations of a display device. FIG. 6 is a diagram illustrating an exemplary configuration of a display device. FIGS. 7A and 7B are diagrams illustrating an exemplary configuration of a display device. FIG. 8 is a diagram illustrating an exemplary configuration of a display device. FIGS. 9A and 9B are diagrams illustrating an exemplary configuration of a display device. FIGS. 10A and 10B are diagrams illustrating an exemplary configuration of a display device. FIG. 11 is a diagram illustrating an exemplary configuration of a display device. FIGS. 12A to 12C are diagrams illustrating an exemplary configuration of a display device. FIGS. 13A to 13D are diagrams illustrating an exemplary configuration of a display device. FIGS. 14A to 14C are diagrams illustrating an exemplary configuration of a display device. FIG. 15 is a diagram illustrating an exemplary configuration of a display device. FIGS. 16A and 16B are diagrams illustrating an exemplary configuration of a display device. FIGS. 17A and 17B are diagrams illustrating an example of the configuration of a display device. FIGS. 18A to 18D are diagrams illustrating an example of the configuration of a display device. FIGS. 19A to 19D are diagrams illustrating an example of the configuration of a display device. FIGS. 20A to 20D are diagrams illustrating an example of the configuration of a display device. FIGS. 21A and 21B are diagrams illustrating an example of the configuration of a display device. FIGS. 22A and 22B are diagrams illustrating an example of the configuration of a display device. FIGS. 23A to 23D are diagrams illustrating an example of the configuration of a display device. FIGS. 24A to 24D are diagrams illustrating an example of the configuration of a display device. FIG. 25 is a diagram illustrating an example of the configuration of a display device. FIG. 26 is a diagram illustrating an example of the configuration of a display device. FIGS. 27A to 27C are diagrams illustrating an example of the configuration of a display device. FIGS. 28A and 28B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 28C is a cross-sectional view illustrating an indium oxide film. FIGS. 29A and 29B are diagrams illustrating an example of the configuration of a display device. 30A and 30B are diagrams illustrating an example of the configuration of a display device.

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0021] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] Embodiment 1 In this embodiment, an electronic device according to one embodiment of the present invention will be described. The electronic device according to one embodiment of the present invention can be suitably used as a wearable electronic device for VR and AR applications.

[0024] 1A is a perspective view of an electronic device 100. The electronic device 100 is a wearable electronic device, and a goggle-type electronic device is shown as an example.

[0025] 1A includes a pair of display devices 10_L and 10_R in a housing 101. Also, FIG. 1A illustrates an eye 102 (eyeball) of a user wearing the electronic device 100.

[0026] The housing 101 has a function of disposing the pair of display devices 10_L and 10_R in positions where they can capture an image of the user's eye 102 and / or the area around the eye 102. For example, as shown in Fig. 1A , the pair of display devices 10_L and 10_R are disposed in the housing 101 in positions that overlap with the eye 102. The housing 101 is equipped with an acceleration sensor such as a gyro sensor, and can detect the orientation of the user's head and display an image according to that orientation.

[0027] In this specification, for example, when describing matters common to the display devices 10_L and 10_R, or when there is no need to distinguish between them, the display device may simply be referred to as "display device 10."

[0028] FIG. 1B is a perspective schematic diagram of a display device 10 applicable to the display devices 10_L and 10_R shown in FIG. 1A.

[0029] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display unit 13 and a light receiving unit 14 provided between the substrate 11 and the substrate 12.

[0030] The display section 13 is an area that displays an image in the display device 10. The display section 13 is provided with light-emitting elements 61 whose light intensity is controlled by pixel circuits.

[0031] The light receiving section 14 is an area that captures an image of the periphery of the display device 10. The light receiving section 14 is provided with a light receiving element 62 that outputs a current (photocurrent) according to the intensity of light. The light receiving element 62 is an element that converts light energy into electrical energy, and is sometimes called a photoelectric conversion element.

[0032] In this specification and the like, the term “element” may be replaced with “device.” For example, a display element, a light-emitting element, and a light-receiving element may be replaced with a display device, a light-emitting device, and a light-receiving device.

[0033] The display device 10 receives and outputs various signals and power supply potentials from the outside via the terminal unit 15, and can display images in the display unit 13 and capture images in the light-receiving unit 14. A plurality of layers are provided between the substrate 11 and the substrate 12, and each layer is provided with transistors for circuit operation as well as the above-mentioned light-receiving elements 62 and light-emitting elements 61. The layer in which the transistors are provided is provided with a pixel circuit unit (also referred to as a first pixel circuit unit) that has the function of controlling the light-emitting elements 61, a pixel circuit unit (also referred to as a second pixel circuit unit) that has the function of controlling the light-receiving elements 62, a drive circuit unit that has the function of controlling each pixel circuit unit, an arithmetic circuit unit that has the function of arithmetic processing signals generated by the light-receiving elements 62, a memory circuit unit that stores data for arithmetic operations performed by the arithmetic circuit unit, and the like.

[0034] Note that controlling the light-emitting element means controlling the pixel circuit of the first pixel circuit unit to pass a current corresponding to image data through the light-emitting element to control light emission, and controlling the light-receiving element means controlling the pixel circuit of the second pixel circuit unit to control the output of a signal corresponding to a current flowing through the light-receiving element upon receiving light.

[0035] 1C is a schematic diagram illustrating a case where a display device 10 including a display unit 13 and a light receiving unit 14 is provided in a position close to a user's eye 102. In FIG. 1C, the display unit 13 and the light receiving unit 14 are arranged such that the display unit 13 is arranged between the light receiving units 14.

[0036] The user's eye 102 can visually recognize the image by the light 13A emitted from the light emitting element 61 in the display unit 13. The light 13A may include light such as infrared light in addition to visible light.

[0037] Furthermore, the reflected light 14A from the user's eye 102 and / or its periphery is converted into an electrical signal by the light receiving element 62 in the light receiving unit 14. The information acquired by the light receiving unit 14 can be image data of the eyeball (or the state of the pupil) for gaze detection and / or image data of movement around the eyeball (for example, the eyelid, between the eyebrows, inner corner of the eye, outer corner of the eye, etc.).

[0038] <Examples of Arrangement of Display Unit and Light Receiving Unit> FIGS. 2A to 2D are schematic diagrams for explaining examples of arrangement of the display unit 13 and the light receiving unit 14 shown in FIGS. 1B and 1C.

[0039] The example shown in FIG. 2A illustrates a configuration in which the display unit 13 area and the light receiving unit 14 area are located at different positions. In FIG. 2A, the light receiving unit 14 is configured to be arranged in a line in contact with both edges of the display unit 13. If an image of an eyelid movement, such as blinking, is to be captured, it can be detected by the line-shaped light receiving unit 14. By detecting eyelid movement in this manner, an inference operation based on the presence or absence of blinking can be performed in the arithmetic circuit connected to the light receiving unit 14. Note that the light receiving unit 14, which can be arranged in a line, can also be configured to be arranged in a line in contact with one edge of the display unit 13, as shown in FIG. 2B.

[0040] 2C illustrates an example in which the light receiving units 14 are arranged to surround the display unit 13. In FIG. 2C , the light receiving units 14 are arranged in a ring shape around the outside of the display unit 13. In this ring-shaped configuration, the light receiving units 14 can detect movement around the eyeball, such as the eyelids, between the eyebrows, inner corners of the eyes, and outer corners of the eyes. Therefore, for example, an arithmetic circuit connected to the light receiving units 14 can infer the gaze direction without capturing images of the eyeball movement. In this way, the electronic device of one embodiment of the present invention can infer the user's condition even if only fragmentary information about the area around the eyes is acquired.

[0041] The light receiving unit 14, which can be provided in an annular shape, is preferably provided around the display unit 13, which is larger than the eye 102, as shown in FIG. ＤThe diagonal dimension of the display device 10 is set to 0.1 inches or more and 5 inches or less, preferably 0.5 inches or more and 3 inches or less, further preferably 1 inch or more and 2 inches or less, more preferably 1.3 inches or more and 1.7 inches or less, and even more preferably 1.5 inches or more and 1.6 inches or less, thereby enabling a configuration in which a display unit 13 according to the size of the eye 102 and a light receiving unit 14 according to the size of the eye 102 are provided. With this configuration, when the display device 10 is brought close to the user's eye 102, information about the user's eye 102 and its surroundings can be obtained by the light receiving unit 14, and the field of view of the image displayed on the display unit 13 can be increased.

[0042] 2A to 2D, the display unit 13 area and the light receiving unit 14 area are configured to be in different positions. That is, the light emitting element 61 and the light receiving element 62 are configured to be arranged in different locations. This configuration allows the layout density of the light emitting element 61 and the light receiving element 62 to be different. As a result, the light receiving unit 14 can be arranged without impairing the resolution of the display unit 13. In addition, fragmentary information about the area around the eye can be acquired.

[0043] <Configuration Example of Display Device> The configuration of the display device 10 applicable to the display devices 10_L and 10_R shown in FIGS. 1A and 1B will be described with reference to FIGS. 3A to 7B.

[0044] FIG. 3A is a perspective view that schematically shows the configuration of each layer provided between the substrate 11 and the substrate 12 in the display device 10 shown in FIG. 1B.

[0045] A layer 40 is provided on the substrate 11. As an example, the layer 40 includes a driver circuit section 47 and an arithmetic circuit section 45. The layer 40 includes a transistor 42 (also referred to as a Si transistor) having silicon in a channel formation region 44. As an example, the substrate 11 is a silicon substrate. A silicon substrate is preferable because it has higher thermal conductivity than a glass substrate. The layer 40 may be referred to as a first layer.

[0046] The transistor 42 can be, for example, a transistor having single crystal silicon in its channel formation region. In particular, when a transistor having single crystal silicon in its channel formation region is used as the transistor provided in the layer 40, the on-state current of the transistor can be increased. This is preferable because the circuit included in the layer 40 can be driven at high speed. Furthermore, a Si transistor can be formed by microfabrication so that the channel length is 3 nm to 10 nm. Therefore, it is possible to provide an arithmetic circuit portion 45 and / or a driver circuit portion 47 dedicated to the neural network.

[0047] The drive circuit unit 47 includes, for example, a gate driver circuit, a source driver circuit, etc. The gate driver circuit, the source driver circuit, etc. can be arranged to overlap the display unit 13 and / or the light receiving unit 14. Therefore, compared to when the drive circuit unit 47 and the display unit 13 and / or the light receiving unit 14 are arranged side by side, the width of the non-display area (also called a frame) existing on the periphery of the display unit 13 of the display device 10 can be made extremely narrow, thereby realizing a compact display device 10. Furthermore, when arranged on the periphery of the display unit 13 of the display device 10, the gate driver circuit and the source driver circuit are arranged together on the periphery, but the drive circuit unit 47 can be divided into multiple parts and arranged in the area overlapping with the display unit 13.

[0048] The arithmetic circuit unit 45 has a function of performing arithmetic processing based on a neural network, such as pooling, padding, and stride processing. The arithmetic circuit unit 45 is a circuit having a function of performing arithmetic processing based on a hierarchical neural network, such as a deep neural network (DNN) or a convolutional neural network (CNN). Therefore, even if the input value based on the acquired imaging data is fragmentary information, the arithmetic circuit unit 45 can perform inference processing regarding the health condition of the user wearing the electronic device.

[0049] The arithmetic circuit unit 45 has a function of controlling the execution of a product-sum operation using a minute current corresponding to an analog voltage in the memory circuit unit 59 described below. This configuration reduces power consumption compared to a configuration in which the product-sum operation is performed using a digital signal in the arithmetic circuit unit 45. Note that the memory circuit unit 59 uses the signal obtained by the light-receiving element 62 as an input value and can obtain an output current corresponding to the result of the product-sum operation with the weight value stored in the memory circuit unit. The arithmetic circuit unit 45 can perform arithmetic processing based on a neural network using the obtained output current.

[0050] The arithmetic circuit unit 45 has a function of outputting a signal that controls the drive circuit unit 47 in accordance with the arithmetic processing. For example, the arithmetic circuit unit 45 can output a signal for controlling the stopping of the drive circuit unit 47 or the switching of the image displayed on the display unit in accordance with the output result obtained by the inference processing based on the hierarchical neural network. Therefore, if there is a concern that the user's health may be impaired due to prolonged use of an electronic device that provides a highly immersive experience, a warning can be issued to the user. As a result, the electronic device can be designed with safety, security, and other factors in mind.

[0051] A layer 50 is provided over the layer 40. The layer 50 includes a pixel circuit portion 55 having a pixel circuit 51, a pixel circuit portion 57 having a pixel circuit 56, and a memory circuit portion 59 having a memory circuit 58. The layer 50 includes a transistor 52 (also referred to as an OS transistor) having a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 54. Note that the layer 50 can be stacked over the layer 40. The layer 50 can also be formed over a different substrate and then bonded to the other substrate.

[0052] The transistor 52, which is an OS transistor, preferably has an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region. Such an OS transistor has a characteristic of extremely low off-state current. Therefore, it is preferable to use an OS transistor as a transistor provided in the pixel circuit 51, the pixel circuit 56, and the memory circuit 58, in particular, because analog data, which is the potential of an analog value written in the pixel circuit 51, the pixel circuit 56, and the memory circuit 58, can be held for a long period of time.

[0053] The pixel circuit section 55 has a function of controlling the light emission of the light-emitting element 61. The pixel circuit section 55 is provided with a plurality of pixel circuits 51 that control the light emission of the light-emitting element 61. The pixel circuit section 55 is arranged in a region separate from the pixel circuit section 57 and the memory circuit section 59, so that it is possible to arrange a plurality of pixel circuits 51 at an extremely high density, thereby enabling extremely high pixel definition.

[0054] The pixel circuit unit 57 has a function of controlling the reception of light by the light receiving elements 62. The pixel circuit unit 57 is provided with a plurality of pixel circuits 56 that control the output of signals in response to the reception of light by the light receiving elements 62. The pixel circuit unit 57 is provided with pixel circuits 56 that hold, amplify, and output photocurrents generated by the reception of light by the light receiving elements 62. The pixel circuits 56 are also provided in positions close to the light receiving elements 62. Therefore, even if the current flowing due to the reception of light by the light receiving elements 62 is a small current, it can be amplified and output.

[0055] The memory circuit unit 59 has the function of retaining weight values ​​set by analog current signals and the function of performing product-sum operations between the weight values ​​and input values. The memory circuit unit 59 has a plurality of memory circuits 58 that retain weight values ​​set by analog current signals and perform product-sum operations between the weight values ​​and input values. The memory circuits 58 can be divided into reference cells and operation cells depending on their functions. The memory circuits 58 can retain analog data written in response to minute currents for a long period of time. Furthermore, the memory circuit unit 59 that performs product-sum operations using minute currents can perform operations with excellent operation efficiency.

[0056] A layer 60 is provided on the layer 50. A substrate 12 is provided on the layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. The layer 60 includes a display section 13 having a plurality of light-emitting elements 61 and a light-receiving section 14 having a plurality of light-receiving elements 62. The layer 60 may be laminated on the layer 50. The light-emitting elements 61 may be, for example, organic electroluminescence elements (also referred to as organic EL elements). However, the light-emitting elements 61 are not limited thereto, and may also be, for example, inorganic EL elements made of inorganic materials. Note that "organic EL elements" and "inorganic EL elements" may be collectively referred to as "EL elements." The light-emitting elements 61 may include inorganic compounds such as quantum dots. For example, quantum dots may be used in the light-emitting layer to function as a light-emitting material. The light-receiving elements 62 may be, for example, organic photodiodes.

[0057] As shown in FIG. 3A , the display device 10 of one embodiment of the present invention can have a stacked structure including a light-emitting element 61, a pixel circuit portion 55, and a driver circuit portion 47, thereby enabling an extremely high pixel aperture ratio (effective display area ratio). Furthermore, the pixel circuits 51 can be arranged at extremely high density, enabling extremely high pixel resolution. Because of its extremely high resolution, the display device 10 can be suitably used for VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display portion of the display device 10 is viewed through an optical component such as a lens, the display device 10 has an extremely high-resolution display portion, and therefore, pixels are not visible even when the display portion is enlarged with the lens, enabling a highly immersive display experience.

[0058] As shown in FIG. 3A , the display device 10 of one embodiment of the present invention can have a stacked structure including the light-receiving element 62, the pixel circuit portion 57, the memory circuit portion 59, and the arithmetic circuit portion 45. This allows for efficient arithmetic processing using a minute current output from the light-receiving element 62 as input data. Furthermore, the display device 10 can have the light-receiving portion 14 located close to the display portion 13, allowing the user to view an image with their eye and capture images of the user's eye and / or its surroundings. Furthermore, the memory circuit 58 can retain analog data written in response to a minute current for a long period of time. Furthermore, the memory circuit portion 59, which performs product-sum calculations using a minute current, allows for efficient arithmetic processing.

[0059] 3B shows a block diagram of each component of the layers 40, 50, and 60 in FIG. 3A. The drive circuit section 47 in the layer 40 outputs signals GS and DS (for example, GS is a signal for driving a gate line, and DS is a signal corresponding to image data) for controlling the pixel circuit section 55 in the layer 50. The pixel circuit section 55 in the layer 50 supplies a current I corresponding to image data to a light-emitting element 61 (not shown) in the display section 13 in the layer 60. ＥＬ The light emitting element 61 (not shown) in the display unit 13 in the layer 60 outputs a current I ＥＬ The light is emitted in accordance with the image, and the user can visually recognize the image.

[0060] In the block diagram shown in FIG. 3B, a light receiving element 62 (not shown) in the light receiving unit 14 in the layer 60 detects an electric current I by capturing an image of the user's eye and / or the area around the eye. ＰＳ It outputs the current I ＰＳ is amplified by the pixel circuit section 57 in the layer 50, and the signal S ＤＸ The signal S ＤＸ When the signal S is a current value, it can be input to the memory circuit unit 59. When the signal S is a voltage value, it can be output to the memory circuit unit 59 via, for example, an analog-to-digital converter or the like provided in the layer 40. The memory circuit unit 59 in the layer 50 receives the signal S set by the arithmetic circuit unit 45 in the layer 40. ＤＷ is used as a weight value, and the current I ＰＳBy giving as an input value, the output current I ＭＡＣ to the arithmetic circuit unit 45 in the layer 40. The arithmetic circuit unit 45 in the layer 40 outputs an output signal OD that controls the drive circuit unit 47.

[0061] The memory circuit unit 59 shown in Fig. 3B has the function of performing product-sum calculations and therefore has the function of performing part of the calculation processing of the neural network. Therefore, the memory circuit unit 59 can be made part of the circuit that makes up the calculation circuit unit 45. Fig. 4A shows an example configuration of the calculation circuit unit 45 in the block diagram shown in Fig. 3B, which includes the memory circuit unit 59 and the peripheral circuit PERI. The peripheral circuit PERI has the function of exchanging various signals for performing product-sum calculations with the memory circuit unit 59, and of performing calculation processing of signals obtained by the product-sum calculation processing.

[0062] 4A illustrates an output signal OD that is output by performing inference processing based on the neural network NN of the arithmetic circuit unit 45. The arithmetic circuit unit 45 in the layer 40 performs inference processing based on the neural network, and can output an output signal OD that controls the drive circuit unit 47 in accordance with the inference processing.

[0063] An example of inference processing in the neural network NN will be described with reference to Fig. 4B. The arithmetic circuit unit 45 capable of arithmetic processing based on the neural network NN captures an image of the user's eye 102 and its surroundings with the light receiving element 62 of the light receiving unit 14, amplifies the minute current flowing through the light receiving element 62 with the pixel circuit unit 57, and outputs a signal (signal S ＤＸ ) is used as an input value. The arithmetic circuit unit 45 having the memory circuit unit 59 performs a product-sum operation using the input value obtained by imaging and the weight value held in the memory circuit unit 59, thereby executing arithmetic processing based on a neural network.

[0064] The inference processing obtained by the arithmetic circuit unit 45 determines, for example, warning level 1 to level 10. The drive circuit unit 47 is controlled by an output signal OD corresponding to the determination. For example, if warning level 9 (the second highest level of danger) is determined, it is determined that the health of the user using the electronic device is in danger, and the drive circuit unit 47 is controlled to display a warning image on the display unit 13 as the output signal OD. Furthermore, if warning level 10 (the highest level of danger) is determined, it is determined that the health of the user using the electronic device is in danger, and the drive circuit unit 47 is controlled to stop outputting the signal.

[0065] 4A and 4B, the minute current flowing through the light receiving element 62 can be used as an input value to the memory circuit unit 59. In this case, the signal S ＤＸ is the current I ＰＳ can be used (I ＰＳ = S ＤＸ 5A and 5B, the pixel circuit section 57 can be omitted.

[0066] FIG. 6 is a flowchart showing the inference process performed by the arithmetic circuit unit 45 using the product-sum operation in the memory circuit unit 59.

[0067] The arithmetic circuit unit 45 outputs the signal S ＤＷ By applying the weighting factor, a current corresponding to the weighting factor can be passed through the memory circuit unit 59, and the weighting factor can be stored (step S31).

[0068] The current Ips obtained by the light receiving element 62 is converted into a signal S corresponding to the input value via the pixel circuit section 57. ＤＸ are input to the memory circuit section 59 (step S32).

[0069] In the memory circuit section 59, an output current I obtained by a product-sum operation of the input value and the weight value is ＭＡＣ Then, a calculation process based on a neural network is performed using the above (step S33).

[0070] Next, a warning level is obtained as a result of the inference process using the neural network. Depending on the warning level, it is determined whether or not a warning is necessary for the user of the electronic device (step S34). If a warning is necessary, such as warning level 9 or higher (YES), the process proceeds to step S35. If a warning is not necessary (NO), the process proceeds to step S32.

[0071] If a warning is necessary, the arithmetic circuit unit 45 outputs an output signal OD to the drive circuit unit 47, and executes processing such as displaying a warning screen and stopping the drive circuit unit (step S35).

[0072] The arithmetic circuit unit 45 can output a signal for controlling the stopping of the drive circuit unit 47 or the switching of the image displayed on the display unit, depending on the output result obtained by the inference process based on the neural network. Therefore, if there is a concern that the user's health may be impaired due to prolonged use of an electronic device that provides a highly immersive experience, a warning can be issued to the user. As a result, the electronic device can be designed with safety and security in mind.

[0073] The layer 50 provided over the layer 40 can have a structure of two or more layers. For example, as in a display device 10A illustrated in FIG. 7A , layers 50_1 and 50_2 including a transistor 52 that is an OS transistor can be provided. In FIG. 7A , the layer 50_1 includes a pixel circuit portion 55 including a pixel circuit 51 and a pixel circuit portion 57 including a pixel circuit 56, and the layer 50_2 includes a memory circuit portion 59 including a memory circuit 58. This configuration can increase the area in which the pixel circuit 51, the pixel circuit 56, and the memory circuit 58 can be provided.

[0074] 7B shows a block diagram of each component included in the layer 40, the layer 50_1, the layer 50_2, and the layer 60 in FIG. 7A, similar to FIG. 3B. As shown in FIG. 7B, the driver circuit portion 47 in the layer 40 and the pixel circuit portion 55 in the layer 50_1 are connected via the layer 50_2. Note that providing a layer for providing wiring between the layer 40 and the layer 50_1 and between the layer 50_1 and the layer 50_2 is preferable because it facilitates circuit connection between different layers.

[0075] 7B , the light receiving portion 14 in the layer 60 and the memory circuit in the layer 50_2 are connected via the layer 50_1 having the pixel circuit portion 57. Note that it is preferable to provide a layer for providing wiring between the layer 60 and the layer 50_1 and between the layer 50_1 and the layer 50_2, since this facilitates the connection of circuits between different layers.

[0076] As described above, a display device according to one embodiment of the present invention can have a stacked structure including a light-emitting portion, a pixel circuit portion that controls the light-emitting portion, and a driver circuit portion that controls the pixel circuit portion. The driver circuit portion, which is a peripheral circuit, can be arranged to overlap with the pixel circuit portion, and the width of the frame can be made extremely narrow, resulting in a display device that is small and lightweight. Therefore, the electronic device according to one embodiment of the present invention can be an electronic device with excellent wearability.

[0077] In addition, by stacking the circuits in the display device of one embodiment of the present invention, wiring connecting the circuits can be shortened, thereby making the display device lightweight. Furthermore, the display device of one embodiment of the present invention can have a display portion with improved pixel resolution. Therefore, an electronic device including the display device can have excellent display quality.

[0078] Furthermore, a display device according to one embodiment of the present invention can have a stacked structure including a light-receiving portion, a memory circuit portion that receives an input value corresponding to a current flowing through the light-receiving portion, and an arithmetic circuit portion that provides a weight value to the memory circuit portion. Since the light-receiving portion can be closely spaced from the memory circuit portion and the arithmetic circuit portion, a minute current output from the light-receiving portion can be used as an input value to the memory circuit portion. The arithmetic circuit portion and the memory circuit portion can perform arithmetic processing with excellent arithmetic efficiency.

[0079] Furthermore, in an electronic device including a display device according to one embodiment of the present invention, a light-receiving unit can be disposed close to a display unit, allowing a user to view an image and capture an image of the user's eye and / or its surroundings. Furthermore, a cell array in the display device can retain analog data written in response to a minute current for a long period of time. An arithmetic circuit that performs a product-sum operation using a minute current can perform an operation with excellent arithmetic efficiency.

[0080] <Configuration Example of Memory Circuit> A memory circuit 58 included in a memory circuit portion 59 included in the display device 10 applicable to the display devices 10_L and 10_R shown in FIGS. 1A and 1B will be described. FIG. 8 is a diagram for explaining the memory circuit 58.

[0081] The memory circuit 58 includes a reference cell 21 and an arithmetic cell 31. The reference cell 21 includes a transistor 22, a transistor 23, a transistor 24, and a capacitor 25. The arithmetic cell 31 includes a transistor 32, a transistor 33, a transistor 34, and a capacitor 35. The transistors and capacitors included in the reference cell 21 and the arithmetic cell 31 are connected to at least one of a wiring WSL, a wiring XCL, a wiring VBL, a wiring WCL, and a wiring that applies a ground potential, as shown in FIG.

[0082] The reference cell 21 has a function of causing a set current to flow when writing data and when reading data, thereby executing a calculation operation in the calculation cell 31. Specifically, when writing data, the reference cell 21 causes a reference current to flow, thereby maintaining a reference voltage within the reference cell 21, and then, when reading data, causes a current corresponding to input data (X) given to the calculation cell 31 to flow through the reference cell 21, thereby controlling the current flowing through the calculation cell 31. Note that the reference cell 21 may also be simply referred to as a cell.

[0083] Next, the connections within the reference cell 21 will be described.

[0084] A gate of the transistor 22 is connected to a wiring WSL. One of a source or a drain of the transistor 22 is connected to one of a source or a drain of the transistor 23 and a wiring XCL. The other of the source or the drain of the transistor 22 is connected to a gate of the transistor 24 and one electrode of the capacitor 25. When writing data, the transistor 22 is turned on to write a reference voltage to a holding node (the gate of the transistor 24) in the reference cell 21, and is turned off to hold the reference voltage in the reference cell 21.

[0085] The gate of the transistor 23 is connected to the wiring VBL. The back gate of the transistor 23 is connected to the other of the source and the drain of the transistor 24. The one of the source and the drain of the transistor 23 is connected to the one of the source and the drain of the transistor 22 and the wiring XCL. The other of the source and the drain of the transistor 23 is connected to the one of the source and the drain of the transistor 24. The transistor 23 sets the potential of the one of the source and the drain of the transistor 24 to a potential corresponding to the potential of the gate of the transistor 23.

[0086] The gate of the transistor 24 is connected to the other of the source and drain of the transistor 22 and one electrode of the capacitor 25. Note that a node to which the gate of the transistor 24, the other of the source and drain of the transistor 22, and one electrode of the capacitor 25 are connected is also referred to as a retention node. The retention node can be set to a potential corresponding to a current flowing through the transistor 24. The backgate of the transistor 24 is connected to the other of the source and drain of the transistor 24. The other of the source and drain of the transistor 24 is connected to a wiring that applies a low power supply potential (e.g., ground potential). The wiring that applies the ground potential functions as a wiring for flowing a current between the source and drain of the transistor 24. The other of the source and drain of the transistor 24 is connected to the backgate of the transistor 23 and the backgate of the transistor 24. A fixed potential is applied to the backgate of the transistor 23 and the backgate of the transistor 24, thereby stabilizing the transistor characteristics of the transistors 23 and 24. The transistor 24 flows an output current corresponding to the gate potential of the transistor 24 to the other of the source and drain.

[0087] One electrode of the capacitor 25 is connected to the other of the source and the drain of the transistor 22 and the gate of the transistor 24. The other electrode of the capacitor 25 is connected to the wiring XCL. When one electrode of the capacitor 25 is in an electrically floating state, the potential of the one electrode of the capacitor 25 changes in response to a change in the potential of the other electrode.

[0088] When writing data, the arithmetic cell 31 has the function of passing a current corresponding to the weight data (W) held in the arithmetic cell 31, thereby holding a voltage corresponding to the current. When reading data, the arithmetic cell 31 has the function of passing a current corresponding to the calculation of the weight data and input data, by boosting the voltage held when writing data according to the current flowing through the reference cell 21. The weight data may be referred to as first data, and the input data may be referred to as second data. The arithmetic cell 31 may also be simply referred to as a cell. The weight data may be, for example, data (weight data) corresponding to weight parameters used in product-sum calculations of an artificial neural network.

[0089] Next, the connections within the processing cell 31 will be described.

[0090] A gate of the transistor 32 is connected to a wiring WSL. One of a source or a drain of the transistor 32 is connected to one of a source or a drain of the transistor 33 and a wiring WCL. The other of the source or the drain of the transistor 32 is connected to a gate of the transistor 34 and one electrode of the capacitor 35. The transistor 32 is turned on when writing data to write a voltage corresponding to the weight data into the arithmetic cell 31, and turned off to hold the voltage corresponding to the weight data in the arithmetic cell 31.

[0091] The gate of the transistor 33 is connected to the wiring VBL. The back gate of the transistor 33 is connected to the other of the source and the drain of the transistor 34. The one of the source and the drain of the transistor 33 is connected to the one of the source and the drain of the transistor 32 and the wiring WCL. The other of the source and the drain of the transistor 33 is connected to the one of the source and the drain of the transistor 34. The transistor 33 sets the potential of the one of the source and the drain of the transistor 34 to a potential corresponding to the potential of the gate of the transistor 33.

[0092] The gate of the transistor 34 is connected to the other of the source and drain of the transistor 32 and one electrode of the capacitor 35. Note that a node to which the gate of the transistor 34, the other of the source and drain of the transistor 32, and the one electrode of the capacitor 35 are connected is also referred to as a retention node. The backgate of the transistor 34 is connected to the other of the source and drain of the transistor 34. The other of the source and drain of the transistor 34 is connected to a wiring that applies a low power supply potential (e.g., ground potential). The wiring that applies the ground potential functions as a wiring for flowing current between the source and drain of the transistor 34. The other of the source and drain of the transistor 34 is connected to the backgate of the transistor 33 and the backgate of the transistor 34. A fixed potential is applied to the backgate of the transistor 33 and the backgate of the transistor 34, thereby stabilizing the transistor characteristics of the transistors 33 and 34. The transistor 34 flows an output current to the other of the source and drain according to the gate potential of the transistor 34.

[0093] One electrode of the capacitor 35 is connected to the other of the source and the drain of the transistor 32 and the gate of the transistor 34. The other electrode of the capacitor 35 is connected to the wiring XCL. When one electrode of the capacitor 35 is in an electrically floating state, the potential of the one electrode of the capacitor 35 changes in response to a change in the potential of the other electrode.

[0094] Next, the transistors included in the reference cell 21 and the operation cell 31 will be described.

[0095] Unless otherwise specified, the transistors 24 and 34 operate in the subthreshold region. The drain current Id of a transistor operating in the subthreshold region can be expressed by the following equation (1).

[0096]

[0097] In formula (1), I ０ is V ｇ =V ｔｈ The drain current when ｇis the gate voltage, V ｔｈ is the threshold voltage, η is a coefficient determined by the device structure, etc., and k Ｂ is the Boltzmann constant, and T is temperature. As shown in equation (1), the drain current Id of a transistor operating in the subthreshold region does not depend on the drain voltage. The current flowing through transistor 24 and transistor 34 is the amount of current flowing when operating in the subthreshold region. The current in the subthreshold region of transistor 24 and transistor 34 can reduce the influence of variations in drain voltage. This can improve the accuracy of data obtained by calculation.

[0098] In this specification and elsewhere, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes the regions that can be considered as the regions described above.

[0099] The drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with gate voltage, regardless of drain voltage. Circuit operation using the subthreshold current can reduce the effect of drain voltage variations.

[0100] When the transistor 32 and the transistor 22 are turned off, they have a function of holding potentials of the gates of the transistors 24 and 34. Specifically, they have a function of holding potentials according to data applied to the gate of the transistor 34 through the transistor 32. As an example, the transistors 32 and 22 are preferably OS transistors.

[0101] As described above, an OS transistor has an extremely small current flowing between its source and drain in an off state, that is, a very small leakage current. By using OS transistors as the transistors 32 and 22, the leakage current of the transistors 32 and 22 can be suppressed, thereby reducing the power consumption of the memory circuit 58. Specifically, fluctuations in the potentials held at the gates of the transistors 24 and 34 can be significantly reduced, thereby reducing the number of refresh operations for the potentials. Furthermore, reducing the number of refresh operations can reduce the power consumption of the memory circuit 58. Furthermore, by significantly reducing the leakage current from the retention node to the wiring WCL or XCL, the cell can retain the potential of the retention node for a long time.

[0102] When the gate voltage of an OS transistor is lower than the threshold voltage of the transistor, −２０ Less than A, 1 x 10 −２２ Less than A or 1 x 10 −２４ An extremely small drain current per 1 μm of channel width, such as less than 1.0×10 A, can flow. −８ A or less, 1.0×10 −１２ A or less, or 1.0 x 10 −１５ A or less per 1 μm of channel width can flow. Therefore, the OS transistor can flow subthreshold currents of different magnitudes in the range of gate voltages in which it operates in the subthreshold region. That is, the OS transistor can operate in a wide range of gate voltages in the subthreshold region. Specifically, when the threshold voltage of the OS transistor is V ｔｈ In the subthreshold region, (V ｔｈ -1.0V) or more V ｔｈ Below, or (V ｔｈ -0.5V) or more V ｔｈ The circuit can operate using gate voltages in the following voltage ranges:

[0103] On the other hand, Si transistors have a large off-state current and operate in a narrow range of gate voltages in the subthreshold region. When using a subthreshold current, an OS transistor can operate in a circuit over a wider range of gate voltages than a Si transistor.

[0104] Next, the wiring WSL, the wiring XCL, the wiring VBL, and the wiring WCL connected to the reference cell 21 and the processing cell 31 will be described.

[0105] The wiring WSL receives a signal that controls the on / off of the transistor 22 and the transistor 32, which function as switches. The wiring WSL functions as a write word line when writing data to the reference cell 21 and the calculation cell 31. Data is written to the reference cell 21 and the calculation cell 31 by applying a current or voltage corresponding to the data to be written to the wiring XCL or the wiring WCL. The data is written by turning on the transistor 22 and the transistor 32. In this case, the wiring WCL is set to an H level (high-level potential). Furthermore, in the reference cell 21 and the calculation cell 31, the transistor 22 and the transistor 32 are controlled to be turned off, thereby holding the data in the reference cell 21 and the calculation cell 31. In this case, the wiring WCL is set to an L level (low-level potential).

[0106] The wiring WCL supplies a current amount (weight current or current I Ｗｕｔ ) or a function of applying a voltage Vd for causing a current to flow in accordance with the potential held in the processing cell.

[0107] The wiring XCL supplies a current amount (reference current or current I) corresponding to the reference data to the reference cell 21 and the operation cell 31. Ｘｕｔ ), or the amount of current (input current or current I Ｘ ) has the function of flowing.

[0108] The wiring VBL is a wiring to which a constant potential Vb is applied. The constant potential Vb is a potential for fixing the potentials of the drain terminals of the transistors 24 and 34 in the reference cell 21 and the calculation cell 31. By applying the constant potential Vb to the gates of the transistors 23 and 33, it is possible to stabilize the transistor characteristics, such as the threshold voltages of the transistors 24 and 34, in response to fluctuations in the potential of the wiring WCL.

[0109] In particular, when transistor 34 and transistor 24 are short-channel transistors with short channel lengths, the threshold voltage decreases due to drain-induced barrier lowering (DIBL), causing the drain current to depend on the drain voltage. Therefore, it is effective to apply a constant potential Vb to the gates of transistors 23 and 33 to reduce changes in the drain voltage of transistors 24 and 34. This configuration can improve the accuracy of data obtained by calculation.

[0110] Next, a configuration including a plurality of reference cells 21 and calculation cells 31 in Fig. 8 will be described with reference to Fig. 9A and Fig. 9B. Fig. 9A shows an outline of the operation when writing data, and Fig. 9B shows an outline of the operation when reading data.

[0111] 9A and 9B, a reference cell section 20 includes a plurality of cells 21_1 to 21_m (corresponding to the reference cell 21 in FIG. 8), and an arithmetic cell section 30 includes a plurality of arithmetic cells 31_1,1 to 31_m,n (corresponding to the arithmetic cell 31 in FIG. 8). Also, in FIGS. 9A and 9B, a plurality of wirings XCL are illustrated as wirings XCL_1 to XCL_m. Also, in FIGS. 9A and 9B, a plurality of wirings WCL are illustrated as wirings WCL_1 to WCL_n. Note that both m and n are natural numbers.

[0112] 9A and 9B, the reference cell unit 20 and the calculation cell unit 30 have n+1 cells arranged in a matrix in the row direction and m cells in the column direction. The reference cell unit 20 and the calculation cell unit 30 only need to have two or more cells arranged in a matrix in the row direction and one or more cells arranged in a matrix in the column direction.

[0113] 9A and 9B, the reference cell 21 and the operation cell 31 are shown in a simplified form for the sake of explanation. Ｐ corresponds to the other electrode of the capacitance element 25 in FIG. Ｗ corresponds to a terminal to which one of the source or drain of the transistor 22 and one of the source or drain of the transistor 23 in FIG. 8 are connected. Ｐ corresponds to the other electrode of the capacitance element 35 in FIG. Ｘ corresponds to a terminal to which one of the source or drain of the transistor 32 and one of the source or drain of the transistor 33 in FIG. 8 are connected.

[0114] In the data write operation shown in FIG. 9A, a current I Ｘｕｔ The current given to each row is the normalized current I Ｘｕｔ and are equal. Current I Ｘｕｔ corresponds to the amount of current (reference current) corresponding to the reference data. Since the arithmetic cells 31 in each row are connected via capacitance, no current flows through them. The reference cells 21 operate to maintain a voltage corresponding to the current flowing through them.

[0115] In the data write operation shown in FIG. 9A, a current I Ｗ１ ~I Ｗｎ (I Ｗ The current given to each column is the normalized current I Ｗｕｔ corresponds to the current amount obtained by multiplying the weight data w by Ｗ = w × I Ｗｕｔ ). current I Ｗ１ ~I Ｗｎmay be different for each column.

[0116] In the data read operation shown in FIG. 9B, a current I Ｘ１ ~I Ｘｍ (I ｘ ) is applied to each row. Ｘ１ ~I Ｘｍ is the normalized current I Ｘｕｔ corresponds to the current amount obtained by multiplying the input data x (I Ｘ = x x I Ｘｕｔ ). current I Ｘ１ ~I Ｘｍ The current I Ｘｕｔ is the current I Ｗｕｔ is preferably equal to

[0117] In the data read operation shown in FIG. 9B, the current I Ｘ１ ~I Ｘｍ The voltage held in the reference cell 21 is boosted by the voltage Vd. The voltages of the wirings XCL_1 to XCL_m are also boosted in response to this boost, so that the voltage held in the arithmetic cell 31 is boosted by the capacitive coupling of the capacitor 35. Then, the potential of the wirings WCL_1 to WCL_n is set to the voltage Vd. At this time, the current I ｒ is the current value (I ｗ ) and the current value (I ｘ ) and the product of (current I ｒ１１ ~I ｒｍｎ The current I ｒ１１ ~I ｒｍ By estimating the sum of the input data and the weight data, it is possible to output data equivalent to the result of the sum of the products of the input data and the weight data.

[0118] It is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors 32 to 34 included in each cell of the arithmetic cell unit 30 are equal to each other. It is also preferable that the sizes of the transistors 22 to 24 included in each cell of the reference cell unit 20 are equal to each other. It is also preferable that the sizes of the transistors 22 and 32 are equal to each other. It is also preferable that the sizes of the transistors 23 and 33 are equal to each other. It is also preferable that the sizes of the transistors 24 and 34 are equal to each other.

[0119] By making the transistors equal in size, the electrical characteristics of the respective transistors can be made substantially equal. Therefore, by making the size of the transistor 32 included in each of the cells 31_1,1 through 31_m,n equal, making the size of the transistor 33 included in each of the cells 31_1,1 through 31_m,n equal, and making the size of the transistor 34 included in each of the cells 31_1,1 through 31_m,n equal, each of the cells 31_1,1 through 31_m,n can perform substantially the same operation under the same conditions. Here, the same conditions refer to, for example, input potentials to the source, drain, gate, etc. of the transistor 32, input potentials to the source, drain, gate, etc. of the transistor 33, input potentials to the source, drain, gate, etc. of the transistor 34, and voltages held in each of the cells 31_1,1 through 31_m,n. Furthermore, by making the sizes of the transistors 22 included in each of the cells 21_1 to 21_m equal, making the sizes of the transistors 23 included in each of the cells 21_1 to 21_m equal, and making the sizes of the transistors 24 included in each of the cells 21_1 to 21_m equal, for example, the cells 21_1 to 21_m can perform substantially the same operation and achieve substantially the same results. The cells 21_1 to 21_m can perform substantially the same operation under the same conditions. The same conditions here refer to, for example, input potentials to the source, drain, gate, etc. of the transistor 22, input potentials to the source, drain, gate, etc. of the transistor 23, input potentials to the source, drain, gate, etc. of the transistor 24, and voltages held in each of the cells 21_1 to 21_m.

[0120] The operations of the reference cell 21 and the operation cell 31 during data writing will be described with reference to FIG. 10A.

[0121] The wiring WSL is set to H level, and the transistors 22 and 32 are set to ON state. A current I corresponding to the reference current flows through the wiring XCL. Ｘｕｔ In addition, a current I Ｗ The current IＷ is the current I normalized to the weight data w Ｗｕｔ The current multiplied by (in the figure, I ｗ =wI Ｗｕｔ ) is equivalent to

[0122] In the reference cell 21, the transistor 22 is turned on. The potential of the retention node, which is the gate of the transistor 24, is set to a value that causes the transistor 24 to flow a current I Ｘｕｔ is the potential at which ｇ１ As a result, the transistor 24 flows a current I Ｘｕｔ In this specification and the like, such an operation is referred to as "the current flowing between the source and drain of the transistor 24 of the reference cell 21 is I Ｘｕｔ This is sometimes referred to as "setting (programming)" or "setting to the

[0123] In the operation cell 31, the transistor 32 is turned on. The potential of the holding node, which is the gate of the transistor 34, is set to a value that causes the transistor 34 to flow a current I Ｗ is the potential at which ｇ２ As a result, the current flowing between the source and drain of the transistor 34 of the processing cell 31 is expressed as I ｗ Set to.

[0124] The current I supplied to the reference cell 21 through the line XCL when writing data Ｘｕｔ can be expressed by equation (2).

[0125]

[0126] In formula (2), V ｇ１ is the potential of the retention node, which is the gate of transistor 24. In equation (2), V ｔｈ１ ' is the threshold voltage of transistor 24;

[0127] When writing data, the current I is supplied to the processing cell 31 via the wiring WCL. Ｗ can be expressed by equation (3).

[0128]

[0129] In formula (3), V ｇ２is the potential of the retention node, which is the gate of transistor 34. In equation (3), V ｔｈ１ is the threshold voltage of transistor 34. Current I ｗ is the weight data w and the normalized current I Ｗｕｔ It can be expressed as a product of

[0130] The constant potential Vb applied to the wiring VBL is V ｔｈ２ Let Vb be the threshold voltage of the transistor 33 and Vth2' be the threshold voltage of the transistor 23, then Vb > Vth2' and Vb > Vth2. With this configuration, the drain voltage of the transistor 24 can be set to (Vb - Vth2). Therefore, the drain voltage of the transistor 34 can also be set to (Vb - Vth2'). In other words, the drain voltages of the transistors 24 and 34 can be set to potentials that do not depend on the potentials of the wirings WCL and XCL. Therefore, a decrease in the threshold voltages of the transistors 34 and 24 due to DIBL can be suppressed, and the accuracy of data obtained by calculation can be improved.

[0131] The operations of the reference cell 21 and the calculation cell 31 during data read will be described with reference to FIG. 10B . Note that a period during which a set current is held can be provided between the time when data is written and the time when data is read. During the period during which the set current is held, the transistors 22 and 32 are turned off (OFF). By configuring the transistors 22 and 32 as OS transistors, the potential of the holding node corresponding to the set current can be held.

[0132] In the reference cell 21, the wiring WSL is set to the L level, and the transistor 22 is set to the OFF state. A current I ｘ The current I Ｘ is the current I normalized to the input data x ｘｕｔ The current multiplied by (in the figure, I Ｘ = xIx ｕｔ The potential of the retention node, which is the gate of transistor 24, drives transistor 24 with a current I Ｘ By playing Vｇ１ +Δ, and the potential of the wiring XCL also fluctuates accordingly.

[0133] In the arithmetic cell 31, the wiring WSL is set to an L level, and the transistor 32 is turned off. Therefore, the storage node of the arithmetic cell 31 is in an electrically floating state. The potential V ｇ２ fluctuates, and V ｇ１ +Δ. The potential of the storage node of the operation cell 31 becomes V ｇ２ +Δ, the transistor 34 of the arithmetic cell 31 receives a current I ｒ is playing.

[0134] A current I is applied to the reference cell 21 through the wiring WSL when reading data. Ｘ can be expressed by equation (4). ｇ１ +Δ is the current I Ｘ is a change in potential at the holding node of the reference cell 21 due to the flow of

[0135]

[0136] In equation (4), Δ can be expressed by the input data x shown in equation (5).

[0137]

[0138] From equations (4) and (5), the current I Ｘ is the input data x and the normalized current I Ｘｕｔ It can be expressed as a product of

[0139] When reading data, the wiring WCL is connected to a voltage V ｄ Then, the potential of the storage node of the arithmetic cell 31 is set to V ｇ２ +Δ, the current I flowing through the transistor 34 of the arithmetic cell 31 ｒ can be expressed by equation (6).

[0140]

[0141] I in Equation (3), Equation (5) and Equation (6)ｒ can be estimated as a current equivalent to the product of the weight data w and the input data x. The currents flowing through the arithmetic cells 31 in each row can be added together, so that by outputting the current flowing through the wiring WCL to the outside, it is possible to output a signal corresponding to the calculation result of the sum-of-products calculation process according to the weight data w and the input data x.

[0142] 11 shows a configuration example of a memory circuit unit 59 that performs a product-sum operation on first data (weight data) and second data (input data), and its peripheral circuits (circuits WCS, XCS, WSD, SWS1, SWS2, and conversion circuits ITRZ_1 to ITRZ_n). The memory circuit unit 59 shown in FIG. 11 is a circuit that performs a product-sum operation on first data corresponding to the potential held in each cell and input second data. Note that the first data and the second data may be, for example, analog data or multi-valued data (discrete data).

[0143] The peripheral circuits, such as the circuit WCS, the circuit XCS, the circuit WSD, and the conversion circuit ITRZ (conversion circuits ITRZ_1 to ITRZ_n), correspond to the peripheral circuit PERI described in FIG. 4A. Each of the above-mentioned peripheral circuits is provided in the layer 40. Therefore, it is possible to provide them so as to have an overlapping area with the memory circuit unit 59 provided in the layer 50, and the connection distance (wiring length) between the peripheral circuits and the memory circuit unit 59 can be extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. In addition, power consumption can be reduced. Furthermore, miniaturization and weight reduction can be achieved.

[0144] The memory circuit unit 59 includes cells 31_1,1 to 31_m,n and cells 21_1 to 21_m. For example, like the calculation cell 31 described above, each of cells 31_1,1 to 31_m,n includes a transistor 32, a transistor 33, a transistor 34, and a capacitor 35. For example, like the reference cell 21 described in the above embodiment, each of cells 21_1 to 21_m includes a transistor 22, a transistor 23, a transistor 24, and a capacitor 25. In the following description, the above-described "one of the source or the drain" may be referred to as a "first terminal," and the above-described "other of the source or the drain" may be referred to as a "second terminal." In the following description, the above-described "one electrode" of a capacitor may be referred to as a "first terminal," and the above-described "other electrode" may be referred to as a "second terminal."

[0145] 11 , in cell 31_1,1, the connection point between the first terminal of transistor 32, the gate of transistor 34, and the first terminal of capacitor 35 is designated as node NN_11. Similarly, in FIG. 11 , similar connection points are designated as nodes NN_1n, NN_m1, and NN_mn in cells 31_1,n, 31_m,1, and 31_m,n. Similarly, in FIG. 11 , similar connection points are designated as nodes NN_ref1 and NNref_m in cells 21_1 and 21_m. Note that nodes NN_11 to NN_mn and nodes NNref_1 to NNref_m function as retention nodes for the respective cells.

[0146] The circuit SWS1 includes, for example, transistors F3_1 to F3_n. A first terminal of the transistor F3_1 is connected to the wiring WCL_1, a second terminal of the transistor F3_1 is connected to the circuit WCS, and a gate of the transistor F3_1 is connected to the wiring SWL1. A first terminal of the transistor F3_n is connected to the wiring WCL_n, a second terminal of the transistor F3_n is connected to the circuit WCS, and a gate of the transistor F3_n is connected to the wiring SWL1.

[0147] Each of the transistors F3_1 to F3_n can be, for example, a transistor that can be used as a transistor included in the memory circuit portion 59. In particular, each of the transistors F3_1 to F3_n is preferably an OS transistor.

[0148] The circuit SWS1 functions as a circuit that switches the connection state between the circuit WCS and each of the wirings WCL_1 to WCL_n.

[0149] The circuit SWS2 includes, for example, transistors F4_1 to F4_n. A first terminal of the transistor F4_1 is connected to the wiring WCL_1, a second terminal of the transistor F4_1 is connected to the input terminal of the conversion circuit ITRZ_1, and a gate of the transistor F4_1 is connected to the wiring SWL2. A first terminal of the transistor F4_n is connected to the wiring WCL_n, a second terminal of the transistor F4_n is connected to the input terminal of the conversion circuit ITRZ_n, and a gate of the transistor F4_n is connected to the wiring SWL2.

[0150] Each of the transistors F4_1 to F4_n can be, for example, a transistor that can be used as a transistor included in the memory circuit portion 59. In particular, each of the transistors F4_1 to F4_n is preferably an OS transistor.

[0151] The circuit SWS2 functions as a circuit that switches the connection state between the wiring WCL_1 and the conversion circuit ITRZ_1 and between the wiring WCL_n and the conversion circuit ITRZ_n.

[0152] The circuit WCS has a function of supplying data to be stored in each cell of the memory circuit portion 59 .

[0153] The circuit XCS is connected to the wirings XCL_1 to XCL_m. The circuit XCS has a function of supplying a current of an amount corresponding to reference data or second data, which will be described later, to each of the cells 21_1 and 21_m included in the memory circuit portion 59.

[0154] The circuit WSD is connected to the wirings WSL_1 to WSL_m. When writing first data to the cells 31_1,1 to 31_m,n, the circuit WSD has a function of selecting a row of the memory circuit portion 59 to which the first data is to be written by supplying a predetermined signal to the wirings WSL_1 to WSL_m. That is, the wirings WSL_1 to WSL_m function as write word lines.

[0155] The circuit WSD is connected to, for example, a wiring SWL1 and a wiring SWL2. The circuit WSD has a function of switching the connection state between the circuit WCS and the memory circuit portion 59 by supplying a predetermined signal to the wiring SWL1, and a function of switching the connection state between the conversion circuits ITRZ_1 to ITRZ_n and the memory circuit portion 59 by supplying a predetermined signal to the wiring SWL2.

[0156] Each of the conversion circuits ITRZ_1 to ITRZ_n has an input terminal and an output terminal, for example. For example, the output terminal of the conversion circuit ITRZ_1 is connected to the wiring OL_1, and the output terminal of the conversion circuit ITRZ_n is connected to the wiring OL_n.

[0157] Each of the conversion circuits ITRZ_1 to ITRZ_n has a function of converting a current input to an input terminal into a voltage corresponding to the amount of the current and outputting the voltage from an output terminal. The voltage can be, for example, an analog voltage or a digital voltage. Each of the conversion circuits ITRZ_1 to ITRZ_n may include a function-based arithmetic circuit. In this case, for example, the arithmetic circuit may perform a function calculation using the converted voltage and output the calculation result to the wirings OL_1 to OL_n.

[0158] In particular, when performing calculations on a hierarchical neural network, the above-mentioned functions may be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like.

[0159] <<Circuit WCS, Circuit XCS>> Here, specific examples of the circuit WCS and the circuit XCS will be described.

[0160] First, the circuit WCS will be described. Fig. 12A is a block diagram showing an example of the circuit WCS. Note that Fig. 12A also shows a circuit SWS1, a transistor F3, a wiring SWL1, and a wiring WCL in order to show connections between the circuit WCS and peripheral circuits. The transistor F3 is any one of the transistors F3_1 to F3_n shown in Fig. 11, and the wiring WCL is any one of the wirings WCL_1 to WCL_n shown in Fig. 11.

[0161] 12A includes a switch SWW, as an example. A first terminal of the switch SWW is connected to a second terminal of the transistor F3, and the second terminal of the switch SWW is connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0162] The switch SWW can be, for example, an electrical switch such as an analog switch or a transistor. When a transistor is used as the switch SWW, the transistor can be, for example, a transistor that can be used in the memory circuit portion 59. In addition to an electrical switch, a mechanical switch may also be used.

[0163] 12A has a plurality of current sources CS. Ｋ value) (K is an integer of 1 or more) as a current. In this case, the circuit WCS has a function of outputting the first data of Ｋ The circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-th bit as a current. Ｋ−１There are individual ones.

[0164] 12A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to the second terminal of the transistor F3 of the circuit SWS1. The terminal T2 of one current source CS is connected to the wiring DW_1, and the terminals T2 of the two current sources CS are connected to the wiring DW_2. Ｋ−１ The terminals T2 of the current sources CS are each connected to the wiring DW_K.

[0165] The multiple current sources CS included in the circuit WCS each have the same current I Ｗｕｔ The current I Ｗｕｔ is the normalized current I Ｗｕｔ In reality, during the manufacturing process of a display device, an error may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the current I output from each of the terminals T1 of the multiple current sources CS may be Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the current I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCS is Ｗｕｔ The following explanation will be given assuming that there is no error.

[0166] The wirings DW_1 to DW_K receive a current I from the connected current source CS. Ｗｕｔ Specifically, for example, when a high-level potential is applied to the wiring DW_1, the current source CS connected to the wiring DW_1 outputs a constant current I Ｗｕｔ flows to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW_1, the current source CS connected to the wiring DW_1 flows as follows: Ｗｕｔ Do not output.

[0167] The current flowing from one current source CS connected to wiring DW_1 corresponds to the value of the first bit, the current flowing from two current sources CS connected to wiring DW_2 corresponds to the value of the second bit, and the current flowing from K current sources CS connected to wiring DW_K corresponds to the value of the Kth bit.

[0168] 12A illustrates the circuit WCS when K is an integer equal to or greater than 3, but when K is 1, the circuit WCS in FIG. 12A may be configured without the current source CS connected to the wirings DW_2 to DW_K. When K is 2, the circuit WCS in FIG. 12A may be configured without the current source CS connected to the wirings DW_3 to DW_K.

[0169] Next, a specific example of the configuration of the current source CS will be described.

[0170] The current source CS1 shown in FIG. 13A is a circuit that can be applied to the current source CS included in the circuit WCS in FIG. 12A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0171] A first terminal of the transistor Tr1 is connected to the wiring VDDL, and a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is connected to the terminal T1, and a gate of the transistor Tr2 is connected to the terminal T2. The terminal T2 is also connected to the wiring DW.

[0172] The wiring DW is any one of the wirings DW_1 to DW_K in FIG. 12A.

[0173] The wiring VDDL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential.

[0174] When the constant voltage applied by the wiring VDDL is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region current range flows between the first terminal and the second terminal of the transistor Tr1. Note that this current is the same as the above-mentioned I Ｗｕｔ , or I described below Ｘｕｔ is equivalent to

[0175] The transistor Tr2 functions as a switching element. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0176] Note that a circuit applicable to the current source CS included in the circuit WCS of FIG. 12A is not limited to the current source CS1 of FIG. 13A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 13B. In the current source CS2 shown in FIG. 13B, the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0177] Further, for example, the current source CS1 is configured such that the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected. However, between the back gate and the second terminal of the transistor Tr2, a configuration may be adopted in which a voltage is held by a capacitor. Such a configuration example is shown in FIG. 13C. The current source CS3 shown in FIG. 13C includes a transistor Tr3 and a capacitor element C6 in addition to the transistor Tr1 and the transistor Tr2. The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are connected via the capacitor element C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are connected. Also, the current source CS3 is configured such that the second terminal of the transistor Tr3 is connected to the wiring VTL and the gate of the transistor Tr3 is connected to the wiring VWL. By applying a high-level potential to the wiring VWL to turn on the transistor Tr3, the conduction state can be established between the wiring VTL and the back gate of the transistor Tr1. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by the capacitor element C6. That is, by determining the voltage applied from the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor element C6.

[0178] Further, for example, as a circuit applicable to the current source CS included in the circuit WCS of FIG. 12A, the current source CS4 shown in FIG. 13D may be used. The current source CS4 is configured such that in the current source CS3 of FIG. 13C, the back gate of the transistor Tr2 is connected not to the second terminal of the transistor Tr2 but to the wiring VTHL. That is, similar to the current source CS2 of FIG. 13B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential applied by the wiring VTHL.

[0179] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0180] 12A includes the current sources CS1 to CS4 shown in FIGS. 13A to 13D , which enable the circuit WCS to output a current corresponding to the K-bit first data. The amount of the current can be, for example, a current flowing between the first terminal and the second terminal of the transistor 34 within a range in which the transistor 34 operates in the subthreshold region.

[0181] 12B may be used as the circuit WCS in FIG. 12A. In the circuit WCS in FIG. 12B, the current source CS in FIG. 13A is connected to each of the wirings DW_1 to DW_K. When the channel width of the transistor Tr1_1 is w_1, the channel width of the transistor Tr1_2 is w_2, and the channel width of the transistor Tr1_K is w_K, the ratio of the channel widths is w_1:w_2:w_K=1:2:2. Ｋ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCS shown in FIG. 12B can output a current corresponding to the K-bit first data, similar to the circuit WCS in FIG. 12A.

[0182] Note that the transistor Tr1 (including transistors Tr1_1 to Tr2_K), the transistor Tr2 (including transistors Tr2_1 to Tr2_K), and the transistor Tr3 can be, for example, a transistor that can be used as a transistor included in the memory circuit portion 59. In particular, OS transistors are preferably used as the transistor Tr1 (including transistors Tr1_1 to Tr2_K), the transistor Tr2 (including transistors Tr2_1 to Tr2_K), and the transistor Tr3.

[0183] Next, a specific example of the circuit XCS will be described.

[0184] 12C is a block diagram showing an example of a circuit XCS. Note that in order to show the connection of the circuit WCS to peripheral circuits, a wiring XCL is also illustrated in FIG. 12C. The wiring XCL is any one of the wirings XCL_1 to XCL_m in FIG. 11.

[0185] 12C includes, as an example, a switch SWX. A first terminal of the switch SWX is connected to the wiring XCL and a plurality of current sources CS, and a second terminal of the switch SWX is connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL. The initialization potential may be a ground potential (GND), a low-level potential, a high-level potential, or the like. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0186] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0187] The circuit configuration of the circuit XCS in Fig. 12C can be made almost the same as that of the circuit WCS in Fig. 12A. Specifically, the circuit XCS has a function of outputting reference data as a current and a function of outputting L bits (2 Ｌand a function of outputting second data of a value (L is an integer of 1 or more) as a current. In this case, the circuit XCS has a function of outputting second data of a value (L is an integer of 1 or more) as a current. Ｌ The circuit XCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the Lth bit as a current. Ｌ−１ There are individual ones.

[0188] Incidentally, the reference data output as a current by the circuit XCS can be, for example, information in which the value of the first bit is "1" and the values ​​of the second and subsequent bits are "0".

[0189] In FIG. 12C, the terminal T2 of one current source CS is connected to the wiring DX_1, and the terminals T2 of two current sources CS are each connected to the wiring DX_2. Ｌ−１ The terminals T2 of the current sources CS are each connected to the line DX_L.

[0190] The multiple current sources CS of the circuit XCS are each supplied with the same constant current I Ｘｕｔ from the terminal T1. The wirings DX_1 to DX_L are connected to the current source CS and output I Ｘｕｔ That is, the circuit XCS has a function of causing a current corresponding to L bits of information transmitted from the wirings DX_1 to DX_L to flow to the wiring XCL.

[0191] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCS, the current I output from each of the terminals T1 of the multiple current sources CS Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCS is Ｘｕｔ The following explanation will be given assuming that there is no error.

[0192] 13A to 13D can be applied as the current source CS of the circuit XCS, similar to the current source CS of the circuit WCS. In this case, the wiring DW shown in FIGS. 13A to 13D can be replaced with the wiring DX. This allows the circuit XCS to pass a current in the subthreshold current range through the wiring XCL as reference data or L-bit second data.

[0193] 12C can have the same circuit configuration as the circuit WCS shown in Fig. 12B. In this case, the circuit WCS shown in Fig. 12B can be replaced with the circuit XCS, the wiring DW_1 with the wiring DX_1, the wiring DW_2 with the wiring DX_2, the wiring DW_K with the wiring DX_L, the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0194] <<Conversion Circuits ITRZ_1 to ITRZ_n>> Here, specific examples of circuits that can be applied to the conversion circuits ITRZ_1 to ITRZ_n in FIG. 11 will be described.

[0195] The conversion circuit ITRZ1 shown in Figure 14A is an example of a circuit that can be applied to the conversion circuits ITRZ_1 to ITRZ_n in Figure 11. Note that Figure 14A also illustrates a circuit SWS2, a wiring WCL, a wiring SWL2, and a transistor F4 to show connections to peripheral circuits of the conversion circuit ITRZ1. The wiring WCL is any one of the wirings WCL_1 to WCL_n in Figure 11, and the transistor F4 is any one of the transistors F4_1 to F4_n in Figure 11.

[0196] 14A is connected to the wiring WCL via a transistor F4. The conversion circuit ITRZ1 is also connected to the wiring OL. The conversion circuit ITRZ1 has a function of converting a current flowing from the conversion circuit ITRZ1 to the wiring WCL or a current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. In other words, the conversion circuit ITRZ1 has a current-voltage conversion circuit.

[0197] The conversion circuit ITRZ1 in FIG. 14A includes, for example, a resistor R5 and an operational amplifier OP1.

[0198] The inverting input terminal of the operational amplifier OP1 is connected to the first terminal of the resistor R5 and the second terminal of the transistor F4, the non-inverting input terminal of the operational amplifier OP1 is connected to the wiring VRL, and the output terminal of the operational amplifier OP1 is connected to the second terminal of the resistor R5 and the wiring OL.

[0199] The wiring VRL functions as a wiring that applies a constant voltage, which may be, for example, a ground potential (GND) or a low-level potential.

[0200] By configuring the conversion circuit ITRZ1 as shown in FIG. 14A, the current flowing from the wiring WCL to the conversion circuit ITRZ1 via the transistor F4, or the current flowing from the conversion circuit ITRZ1 to the wiring WCL via the transistor F4, can be converted into an analog voltage and output to the wiring OL.

[0201] In particular, by setting the constant voltage provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, and therefore the analog voltage output to the wiring OL can be a voltage based on the ground potential (GND).

[0202] Furthermore, while the conversion circuit ITRZ1 in FIG. 14A is configured to output an analog voltage, the circuit configuration applicable to the conversion circuits ITRZ_1 to ITRZ_n in FIG. 11 is not limited to this. For example, the conversion circuit ITRZ1 may be configured to include an analog-to-digital conversion circuit ADC, as shown in FIG. 14B. Specifically, the conversion circuit ITRZ2 in FIG. 14B is configured such that the input terminal of the analog-to-digital conversion circuit ADC is connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is connected to the wiring OL. With this configuration, the conversion circuit ITRZ2 in FIG. 14B can output a digital signal to the wiring OL.

[0203] Furthermore, in the conversion circuit ITRZ2, when the digital signal output to the wiring OL is 1 bit (binary), the conversion circuit ITRZ2 may be replaced with a conversion circuit ITRZ3 shown in FIG. 14C. The conversion circuit ITRZ3 in FIG. 14C is configured by adding a comparator CMP1 to the conversion circuit ITRZ1 in FIG. 14A. Specifically, the conversion circuit ITRZ3 is configured such that a first input terminal of the comparator CMP1 is connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, a second input terminal of the comparator CMP1 is connected to a wiring VRL2, and an output terminal of the comparator CMP1 is connected to a wiring OL. The wiring VRL2 functions as a wiring that provides a potential to be compared with the potential of the first terminal of the comparator CMP1. With this configuration, the conversion circuit ITRZ3 in FIG. 14C can output a low-level potential or a high-level potential (a binary digital signal) to the wiring OL depending on the magnitude of the voltage converted from the current flowing between the source and drain of the transistor F4 by the current-voltage conversion circuit and the voltage applied by the wiring VRL2.

[0204] 11 are not limited to the conversion circuits ITRZ1 to ITRZ3 shown in FIGS. 14A to 14C. For example, it is preferable to have a circuit that performs a function-based operation as the operation of the hierarchical neural network. Examples of the function-based operation include a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function.

[0205] <Example of Operation of the Product-Sum Operation Array> Next, an example of operation of the product-sum operation array will be described.

[0206] 15 shows a timing chart of an operation example of the memory circuit unit 59 in FIG. 11. The timing chart in FIG. 15 shows fluctuations in the potentials of the wiring SWL1, the wiring SWL2, the wiring WSL_i (i is an integer of 1 to m-1), the wiring WSL_i+1, the wiring XCL_i, the wiring XCL_i+1, the node NN_i,j (j is an integer of 1 to n-1), the node NN_i+1,j, the node NNref_i, and the node NNref_i+1 between time T11 and time T23 and in the vicinity thereof. Furthermore, the timing chart in FIG. 15 shows fluctuations in the potentials of the wiring SWL1, the wiring SWL2, the wiring WSL_i (i is an integer of 1 to m-1), the wiring WSL_i+1, the wiring XCL_i, the wiring XCL_i+1, the node NN_i,j (j is an integer of 1 to n-1), the node NN_i+1,j, the node NNref_i, and the node NNref_i+1 between time T11 and time T23 and in the vicinity thereof. ３４ _i,j and the current I flowing between the first terminal and the second terminal of the transistors 23 and 24 included in the cell 21_i. ２４ _i and a current I flowing between the first terminal and the second terminal of the transistors 33 and 34 included in the cell 31_i+1,j. ３４ _i+1,j and a current I flowing between the first terminal and the second terminal of the transistors 23 and 24 included in the cell 21_i+1. ２４ _i+1 and the respective variations are also shown.

[0207] It is to be noted that the circuit WCS in FIG. 11 is the circuit WCS in FIG. 12A, and the circuit XCS in FIG. 11 is the circuit XCS in FIG. 12C.

[0208] In this operation example, the source potentials of the transistors 24 and 34 are set to the ground potential GND. Before time T11, the potentials of the nodes NN_i,j, NN_i+1,j, NNref_i, and NNref_i+1 are set to the ground potential GND as an initial setting. Specifically, for example, by setting the initialization potential of the wiring VINIL1 in FIG. 12A to the ground potential GND and turning on the switch SWW, the transistor F3, and the transistors 32 included in the cells 31_i,j and 31_i+1,j, the potentials of the nodes NN_i,j and NN_i+1,j can be set to the ground potential GND. Furthermore, for example, by setting the initialization potential of the wiring VINIL2 in Figure 12C to the ground potential GND and turning on the switch SWX and the respective transistors 22 included in the cells 31_i,j and 31_i+1,j, the potentials of the nodes NNref_i,j and NNref_i+1,j can be set to the ground potential GND.

[0209] In this operation example, the gate potential of transistors 23 and 33 is set to a constant potential Vb. By setting the gate potential of transistors 23 and 33 to the constant potential Vb, the first terminals of transistors 23 and 33 can be set to a voltage Vb-Vth, which is lower than the constant potential Vb by the threshold voltage. This makes it possible to suppress an increase in the second terminals (drain sides) of transistors 24 and 34.

[0210] <<From Time T11 to Time T12>> From time T11 to time T12, a high-level potential (denoted as High in FIG. 15) is applied to the wiring SWL1, and a low-level potential (denoted as Low in FIG. 15) is applied to the wiring SWL2. As a result, the high-level potential is applied to the gates of the transistors F3_1 to F3_n, turning on the transistors F3_1 to F3_n, and the low-level potential is applied to the gates of the transistors F4_1 to F4_n, turning off the transistors F4_1 to F4_n.

[0211] Furthermore, between time T11 and time T12, a low-level potential is applied to the wirings WSL_i and WSL_i+1. As a result, a low-level potential is applied to the gates of the transistors 32 included in the cells 31_i,1 to 31_i,n in the i-th row of the memory circuit unit 59 and the gates of the transistors 22 included in the cell 21_i, turning off the transistors 32 and 22. Furthermore, a low-level potential is applied to the gates of the transistors 32 included in the cells 31_i+1,1 to 31_i+1,n in the i+1-th row of the memory circuit unit 59 and the gates of the transistors 22 included in the cell 21_i+1, turning off the transistors 32 and 22.

[0212] 12C corresponds to the wiring XCL_i and the wiring XCL_i+1, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0213] 12A corresponds to the wirings WCL_1 to WCL_K, the first data is not input to the wirings DW_1 to DW_K. Also, between time T11 and time T12, when the wiring WCL in FIG. 12A corresponds to the wirings WCL_1 to WCL_K, the first data is not input to the wirings DW_1 to DW_K. Also, when the wiring XCL in FIG. 12C corresponds to the wirings XCL_1 to XCL_K, the second data is not input to the wirings DX_1 to DX_L. Here, in the circuit WCS in FIG. 12A, a low-level potential is input to the wirings DW_1 to DW_K, and in the circuit XCS in FIG. 12C, a low-level potential is input to the wirings DX_1 to DX_L.

[0214] Furthermore, between time T11 and time T12, no current flows through the wiring WCL_j, the wiring XCL_i, and the wiring XCL_i+1. ３４ _i, j, I２４ _i, I ３４ _i+1, j, I ２４ _i+1 becomes 0.

[0215] <<From Time T12 to Time T13>> A high-level potential is applied to the wiring WSL_i from time T12 to time T13. As a result, a high-level potential is applied to the gate of the transistor 32 included in the cells 31_i,1 to 31_i,n in the i-th row of the memory circuit portion 59 and the gate of the transistor 22 included in the cell 21_i, so that the transistors 32 and 22 are turned on. Furthermore, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i from time T12 to time T13. As a result, the transistors 32 included in the cells 31_1,1 to 31_m,n other than the i-th row of the memory circuit portion 59 and the transistors 22 included in the cells 21_1 to 21_m other than the i-th row of the memory circuit portion 59 are turned off.

[0216] Furthermore, the ground potential GND continues to be applied to the wirings XCL_1 to XCL_m from before time T12.

[0217] <<From Time T13 to Time T14>> During the period from time T13 to time T14, a current I is supplied as first data from the circuit WCS to the memory circuit unit 59 via the transistor F3_j. ０ Specifically, when the wiring WCL illustrated in FIG. 12A is the wiring WCL_j, a signal corresponding to the first data is input to each of the wirings DW_1 to DW_K, and a current I flows from the circuit WCS to the second terminal of the transistor F3_j. ０ That is, the value of the K-bit signal input as the first data is α_i,j (α_i,j is set to 0 or more and 2 or less). Ｋ -1 or less), then I ０ _i,j=α_i,j×I Ｗｕｔ (In the figure, "x" is shown as "*").

[0218] When α_i,j is 0, I ０_i,j = 0, so strictly speaking, no current flows from the circuit WCS to the memory circuit unit 59 through the transistor F3_j. However, in this specification and the like, there may be descriptions such as "a current of I ０ _i,j flows".

[0219] Between time T13 and time T14, the connection between the first terminal of the transistor 32 included in the cell 31_i,j in the i-th row of the memory circuit unit 59 and the wiring WCL_j is in a conductive state, and the connection between the first terminal of the transistor 32 included in the cells 31_1,j to 31_m,j other than the i-th row of the memory circuit unit 59 and the wiring WCL_j is in a non-conductive state. Therefore, a current amount I ０ _i,j flows from the wiring WCL_j to the cell 3l_i,j.

[0220] By the way, the transistor 32 included in the cell 31_i,j is turned on. In the transistor 34, the gate-source voltage becomes V ｇ _i,j - GND, and the current I ０ _i,j is set as the current flowing between the first terminal and the second terminal of the transistor 34.

[0221] Also, between time T13 and time T14, a current I ｒｅｆ０ flows from the circuit XCS to the wiring XCL_i as reference data. Specifically, when the wiring XCL shown in FIG. 12C is the wiring XCL_i, a high-level potential is input to the wiring DX_1, and low-level potentials are input to each of the wirings DX_2 to DX_K, and a current I ｒｅｆ０ flows from the circuit XCS to the wiring XCL_i. That is, I ｒｅｆ０ = I Ｘｕｔ holds.

[0222] Between time T13 and time T14, since the connection between the first terminal of the transistor 22 included in the cell 21_i and the wiring XCL_i is in a conductive state, a current I ｒｅｆ０ flows from the wiring XCL_i to the cell 21_i.

[0223] As in the cell 31_i,j, the transistor 22 included in the cell 21_i is turned on. In the transistor 24, the gate-source voltage is V ｇｍ _i-GND, and the current flowing between the first terminal and the second terminal of the transistor 24 is the current I ｒｅｆ０ is set.

[0224] <<From Time T14 to Time T15>> A low-level potential is applied to the wiring WSL_i from time T14 to time T15. As a result, the low-level potential is applied to the gates of the transistors 32 included in the cells 31_i,1 to 31_i,n in the i-th row of the memory circuit portion 59 and the gates of the transistors 22 included in the cell 21_i, so that the transistors 32 and 22 are turned off.

[0225] When the transistor 32 included in the cell 31_i,j is turned off, the capacitor 35 receives a potential difference V ｇ _i, j-V ｇｍ When the transistor 32 included in the cell 21_i is turned off, the capacitor 25 holds 0, which is the difference between the potential of the gate of the transistor 24 (node ​​NNref_i) and the potential of the wiring XCL_i.

[0226] 12C is the wiring XCL_i, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0227] Therefore, the potentials of nodes NN_i,1 to NN_i,n change due to capacitive coupling by the capacitive element 35 included in each of cells 31_i,1 to 31_i,n in the i-th row, and the potential of node NNref_i changes due to capacitive coupling by the capacitive element 25 included in cell 21_i.

[0228] The amount of change in the potential of the nodes NN_i,1 to NN_i,n is calculated by multiplying the amount of change in the potential of the wiring XCL_i by a capacitive coupling coefficient determined by the configuration of each of the cells 31_i,1 to 31_i,n included in the memory circuit portion 59. The capacitive coupling coefficient is calculated based on the capacitance of the capacitive element 35, the gate capacitance of the transistor 34, the parasitic capacitance, and the like. In each of the cells 31_i,1 to 31_i,n, when the capacitive coupling coefficient of the capacitive element 35 is p, the potential of the node NN_i,j of the cell 31_i,j is calculated by multiplying the potential at a point in time between time T14 and time T15 by p(V ｇｍ _i-GND) decreases.

[0229] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to capacitive coupling by the capacitor 25 included in the cell 21_i. When the capacitive coupling coefficient of the capacitor 25 is p, similar to the capacitor 35, the potential of the node NNref_i of the cell 21_i changes from the potential between time T14 and time T15 to p(V ｇｍ 15, p=1 is set as an example. Therefore, the potential of the node NNref_i between time T15 and time T16 becomes GND.

[0230] As a result, the potential of the node NN_i,j of the cell 31_i,j drops, so that the transistor 34 is turned off, and similarly, the potential of the node NNref_i of the cell 21_i drops, so that the transistor 24 is also turned off. ３４ _i, j, I ２４ Each of the _i's will be 0.

[0231] <<From Time T16 to Time T17>> A high-level potential is applied to the wiring WSL_i+1 between time T16 and time T17. As a result, a high-level potential is applied to the gate of the transistor 32 included in cells 31_i+1,1 to 31_i+1,n in the i+1th row of the memory circuit portion 59 and the gate of the transistor 22 included in cell 21_i+1, turning on the transistors 32 and 22. Furthermore, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i+1 between time T16 and time T17. As a result, the transistors 32 included in cells 31_1,1 to 31_m,n other than those in the i+1th row of the memory circuit portion 59 and the transistors 22 included in cells 21_1 to 21_m other than those in the i+1th row of the memory circuit portion 59 are turned off.

[0232] Furthermore, the ground potential GND continues to be applied to the wirings XCL_1 to XCL_m from before time T16.

[0233] <<From Time T17 to Time T18>> During the period from time T17 to time T18, a current I is supplied as first data from the circuit WCS to the memory circuit unit 59 via the transistor F3_j. ０ Specifically, when the wiring WCL illustrated in FIG. 12A is the wiring WCL_j+1, signals corresponding to the first data are input to the wirings DW_1 to DW_K, and a current I flows from the circuit WCS to the second terminal of the transistor F3_j. ０ That is, the value of the K-bit signal input as the first data is α_i+1,j (α_i+1,j is 0 to 2). Ｋ -1 or less.) ０ _i+1,j=α_i+1,j×I Ｗｕｔ (In the figure, "x" is shown as "*").

[0234] When α_i+1,j is 0, I ０ Since j=0, strictly speaking, no current flows from the circuit WCS to the memory circuit unit 59 via the transistor F3_j. However, in this specification, I ０As in the case of i, j = 0, "I ０ _i+1, j=0 current flows."

[0235] At this time, conduction is established between the first terminal of the transistor 32 included in the cell 31_i+1,j in the i+1th row of the memory circuit portion 59 and the wiring WCL_j, and conduction is not established between the first terminal of the transistor 32 included in the cells 31_1,j to 31_m,j other than the cell 31_i+1,j in the i+1th row of the memory circuit portion 59 and the wiring WCL_j. Therefore, a current I flows from the wiring WCL_j to the cell 31_i+1,j. ０ _i+1, j flows.

[0236] Now, suppose that the transistor 32 included in the cell 31_i+1,j is in an on state. In the transistor 34, the gate-source voltage is V ｇ _i+1, j-GND, and the current flowing between the first terminal and the second terminal of the transistor 34 is the current I ０ _i+1, j is set.

[0237] In addition, between time T17 and time T18, the current I ｒｅｆ０ Specifically, similarly to the period from time T13 to time T14, when the wiring XCL in FIG. 12C is the wiring XCL_i+1, a high-level potential is input to the wiring DX_1 and a low-level potential is input to each of the wirings DX_2 to DX_K, and a current I flows from the circuit XCS to the wiring XCL_i+1. ｒｅｆ０ =I Ｘｕｔ is playing.

[0238] Between time T17 and time T18, conduction is established between the first terminal of the transistor 22 included in the cell 21_i+1 and the wiring XCL_i+1, so that a current I flows from the wiring XCL_i+1 to the cell 21_i+1. ｒｅｆ０ is playing.

[0239] As in the case of the cell 31_i+1,j, the transistor 22 included in the cell 21_i+1 is in an on state. In the transistor 24, the gate-source voltage is V ｇｍ_i+1-GND, and the current flowing between the first terminal and the second terminal of the transistor 24 is the current I ｒｅｆ０ is set.

[0240] <<From Time T18 to Time T19>> A low-level potential is applied to the wiring WSL_i+1 from time T18 to time T19. As a result, a low-level potential is applied to the gates of the transistors 32 included in cells 31_i+1,1 to 31_i+1,n in the i+1th row of the memory circuit portion 59 and the gate of the transistor 22 included in cell 21_i+1, so that the transistors 32 and 22 are turned off.

[0241] When the transistor 32 included in the cell 31_i+1,j is turned off, the capacitor 35 receives a potential difference V ｇ _i+1,j-V ｇｍ _i+1 is held. Furthermore, because the transistor 32 included in the cell 21_i+1 is turned off, the capacitor 25 holds 0, which is the difference between the potential of the gate of the transistor 24 (node ​​NNref_i+1) and the potential of the wiring XCL_i+1. Note that the voltage held by the capacitor 25 is a non-zero voltage (here, for example, V ｄｓ In this case, the potential of the node NNref_i+1 is V ｄｓ This can be thought of as the sum of the potentials.

[0242] 12C is the wiring XCL_i+1, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0243] Therefore, the potentials of nodes NN_i,1 to NN_i+1,n change due to capacitive coupling by the capacitive element 35 included in each of cells 31_i+1,1 to 31_i+1,n in the i+1th row, and the potential of node NNref_i+1 changes due to capacitive coupling by the capacitive element 25 included in cell 21_i+1.

[0244] The amount of change in the potential of the nodes NN_i+1,1 to NN_i+1,n is calculated by multiplying the amount of change in the potential of the wiring XCL_i+1 by a capacitive coupling coefficient determined by the configuration of each of the cells 31_i+1,1 to 31_i+1,n included in the memory circuit portion 59. The capacitive coupling coefficient is calculated based on the capacitance of the capacitive element 35, the gate capacitance of the transistor 34, the parasitic capacitance, and the like. When the capacitive coupling coefficient of the capacitive element 35 in each of the cells 31_i+1,1 to 31_i+1,n is set to p, which is the same as the capacitive coupling coefficient of the capacitive element 35 in each of the cells 31_i,1 to 31_i,n, the potential of the node NN_i+1,j of the cell 31_i+1,j is calculated by multiplying the amount of change in the potential of the wiring XCL_i+1 by p(V ｇｍ _i+1-GND) decreases.

[0245] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to capacitive coupling by the capacitor 25 included in the cell 21_i+1. When the capacitive coupling coefficient of the capacitor 25 is p, similar to the capacitor 35, the potential of the node NNref_i+1 of the cell 21_i+1 changes from the potential between time T18 and time T19 to p(V ｇｍ 15, p=1 is set as an example. Therefore, the potential of the node NNref_i+1 becomes GND between time T20 and time T21.

[0246] As a result, the potential of the node NN_i+1,j of the cell 31_i+1,j drops, so that the transistor 34 is turned off. Similarly, the potential of the node NNref_i+1 of the cell 21_i+1 drops, so that the transistor 24 is also turned off. Therefore, between time T19 and time T20, I ３４ _i+1, j, I ２４ Each of _i+1 is 0.

[0247] <<From Time T20 to Time T21>> A low-level potential is applied to the wiring SWL1 from time T20 to time T21. As a result, the low-level potential is applied to the gates of the transistors F3_1 to F3_n, and the transistors F3_1 to F3_n are turned off.

[0248] <<From Time T21 to Time T22>> A high-level potential is applied to the wiring SWL2 from time T21 to time T22. As a result, the high-level potential is applied to the gates of the transistors F4_1 to F4_n, and the transistors F4_1 to F4_n are turned on.

[0249] <<From Time T22 to Time T23>> During the period from time T22 to time T23, a current I is supplied as second data from the circuit XCS to the wiring XCL_i. ｒｅｆ０ x_i times x_iI ｒｅｆ０ Specifically, for example, when the wiring XCL in FIG. 12C is a wiring XCL_i, a high-level potential or a low-level potential is input to each of the wirings DX_1 to DX_K depending on the value of x_i, and a current of x_iI flows from the circuit XCS to the wiring XCL_i. ｒｅｆ０ = x_iI Ｘｕｔ In this operation example, x_i corresponds to the value of the second data. At this time, the potential of the wiring XCL_i is changed from 0 to V ｇｍ _i+ΔV_i.

[0250] When the potential of the wiring XCL_i changes, the potentials of the nodes NN_i,1 to NN_i,n also change due to capacitive coupling by the capacitors 35 included in the cells 31_i,1 to 31_i,n in the i-th row of the memory circuit portion 59. Therefore, the potential of the node NN_i,j of the cell 31_i,j is V ｇ _i,j+pΔV_i.

[0251] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to capacitive coupling by the capacitor 25 included in the cell 21_i. Therefore, the potential of the node NNref_i of the cell 21_i is V ｇｍ _i+pΔV_i.

[0252] Therefore, as explained above, the current flowing between the first terminal and the second terminal of the transistor 34 included in the cell 31_i,j is proportional to the product of the first data w_i,j and the second data x_i.

[0253] In addition, between time T22 and time T23, a current I is supplied as second data from the circuit XCS to the wiring XCL_i+1. ｒｅｆ０ x_i+1I, which is x_i+1 times ｒｅｆ０ Specifically, for example, when the wiring XCL in FIG. 12C is a wiring XCL_i+1, a high-level potential or a low-level potential is input to each of the wirings DX_1 to DX_K depending on the value of x_i+1, and a current of x_i+1I flows from the circuit XCS to the wiring XCL_i+1. ｒｅｆ０ = x_i + 1I Ｘｕｔ In this operation example, x_i+1 corresponds to the value of the second data. At this time, the potential of the wiring XCL_i+1 changes from 0 to V ｇｍ _i+1+ΔV_i+1.

[0254] When the potential of the wiring XCL_i+1 changes, the potentials of the nodes NN_i+1,1 to NN_i+1,n also change due to capacitive coupling by the capacitors 35 included in the cells 31_i+1,1 to 31_i+1,n in the i+1th row of the memory circuit portion 59. Therefore, the potential of the node NN_i+1,j of the cell 31_i+1,j is V ｇ _i+1,j+pΔV_i+1.

[0255] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to capacitive coupling by the capacitor 25 included in the cell 21_i+1. Therefore, the potential of the node NNref_i+1 of the cell 21_i+1 is V ｇｍ _i+1+pΔV_i+1.

[0256] Therefore, as explained above, the current flowing between the first terminal and the second terminal of transistor 34 included in cell 31_i+1,j is proportional to the product of the first data w_i+1,j and the second data x_i+1.

[0257] Therefore, the current output from the conversion circuit ITRZ_j is proportional to the sum of the products of the weighting coefficients w_i,j and w_i+1,j, which are the first data, and the neuron signal values ​​x_i and x_i+1, which are the second data.

[0258] Therefore, even in the case of a memory circuit unit 59 having three or more rows and two or more columns, it is possible to perform the product-sum operation as described above. In this case, the memory circuit unit 59 selects one of the columns as a current I ｒｅｆ０ , and xI ｒｅｆ０ By using a cell that holds a multiply-and-accumulate signal, it is possible to simultaneously execute the multiply-and-accumulate operation for the remaining number of columns among the multiple columns. In other words, by increasing the number of columns arranged on the array, it is possible to provide a semiconductor device that realizes high-speed multiply-and-accumulate operation. As a result, it is possible to provide a computing device with excellent computing performance per unit power.

[0259] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0260] (Embodiment 2) In this embodiment, a configuration example of a driver circuit, a pixel circuit, and a three-dimensional structure of a light-emitting element, a configuration example of a memory circuit, a configuration example of a pixel circuit connected to a light-receiving element, a top schematic view of a light-emitting element and a cross-sectional schematic view thereof, a configuration example of a light-emitting element, a configuration example of a light-emitting element and a light-receiving element, and a configuration example of a cross-sectional view of a display device will be described.

[0261] 16A and 16B show a configuration example of a pixel circuit 51 and a light-emitting element 61 connected to the pixel circuit 51. Fig. 16A is a diagram showing the connection of each element, and Fig. 16B is a diagram schematically showing the hierarchical relationship between a layer 40 including a drive circuit unit 47, a layer 50 including a plurality of transistors included in the pixel circuit 51, and a layer 60 including the light-emitting element 61.

[0262] 16A and 16B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The transistors 52A, 52B, and 52C can be OS transistors. Each of the OS transistors 52A, 52B, and 52C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode can be applied to the back gate electrode.

[0263] The transistor 52B includes a gate electrode connected to the transistor 52A, a first electrode connected to the light-emitting element 61, and a second electrode connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0264] Transistor 52A has a first electrode connected to the gate electrode of transistor 52B, a second electrode connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0265] The transistor 52C includes a first electrode connected to a wiring V0, a ​​second electrode connected to the light-emitting element 61, and a gate electrode that controls the conduction state or non-conduction state based on the potential of a wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the driver circuit unit 47 or the arithmetic circuit unit 45.

[0266] The capacitor 53 includes a conductive film connected to the gate electrode of the transistor 52B and a conductive film connected to the second electrode of the transistor 52C.

[0267] The light-emitting element 61 includes a first electrode connected to the first electrode of the transistor 52B and a second electrode connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0268] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with an image signal applied to the gate electrode of the transistor 52B. Also, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0269] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the arithmetic circuit unit 45 or the like.

[0270] Note that the light-emitting element described in one embodiment of the present invention refers to a self-luminous light-emitting element such as an organic light-emitting diode (OLED). Note that the light-emitting element connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a quantum-dot light-emitting diode (QLED), or a semiconductor laser.

[0271] In the configuration shown as an example in FIG. 16B , the wiring connecting the pixel circuits 51 and the drive circuit unit 47 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, enabling the display device 10 to be driven at high speed. This allows the display device 10 to have a sufficient frame period even if the number of pixel circuits 51 is increased, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 increases the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be 1,000 ppi or more, 5,000 ppi or more, or 7,000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs, in which the display unit is close to the user.

[0272] 16A and 16B may be provided with the arithmetic circuit unit 45, the memory circuit unit 59, and the photodiode PD serving as a light-receiving element, respectively, as described in the above-described embodiment 2. Therefore, the display device 10 may be configured to include an arithmetic circuit and a drive circuit, a pixel circuit and a memory circuit, a light-emitting element and a light-receiving element.

[0273] 17A is a schematic diagram illustrating the connection relationship between the driver circuit unit 47 (including the gate driver circuit GD and the source driver circuit SD) and the pixel circuit 51 shown in FIG. 16B. As described above, in one embodiment of the present invention, the driver circuit unit 47 and the pixel circuit 51 are provided in different layers, and therefore the pixel circuit 51 can be provided above the driver circuit unit 47.

[0274] The drive circuit unit 47 includes a gate driver circuit GD and a source driver circuit SD. The gate driver circuit GD is connected to a pixel circuit 51 provided above via a wiring GL. Note that there may be a plurality of wirings GL, as with the aforementioned wirings GL1 and GL2. The source driver circuit SD is connected to a pixel circuit 51 provided above via a wiring SL.

[0275] By stacking the drive circuit unit 47 and the pixel circuit 51, the connection distance (wiring length) between the drive circuit unit 47 and the pixel circuit 51 can be made extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. In addition, power consumption can be reduced. Furthermore, miniaturization and weight reduction can be achieved. In addition, the integration degree of the pixel circuit 51 can be increased.

[0276] The gate driver circuit GD and the source driver circuit SD do not have to be located in an area overlapping with the pixel circuits 51. For example, as shown in Fig. 17B, it is also possible to provide the gate driver circuit GD in an area overlapping with the pixel circuits 51, and the source driver circuit SD in an area not overlapping with the pixel circuits 51.

[0277] 16A and 16B show an example of the pixel circuit 51 including three transistors in total, but one embodiment of the present invention is not limited thereto. Below, a configuration example of a pixel circuit that can be applied to the pixel circuit 51 will be described.

[0278] 18A illustrates a pixel circuit 51A including a transistor 52A, a transistor 52B, and a capacitor 53. 18A also illustrates a light-emitting element 61 connected to the pixel circuit 51A. A wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM are connected to the pixel circuit 51A.

[0279] The transistor 52A has a gate connected to the wiring GL, one of its source and drain connected to the wiring SL, and the other connected to the gate of the transistor 52B and one electrode of the capacitor C1. The transistor 52B has one of its source and drain connected to the wiring ANO, and the other connected to the anode of the light-emitting element 61. The capacitor C1 has the other electrode connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode connected to the wiring VCOM.

[0280] 18B is configured by adding a transistor 52C to the pixel circuit 51A. A wiring V0 is also connected to the pixel circuit 51B.

[0281] A pixel circuit 51C shown in FIG. 18C is an example in which transistors having a pair of gates are used as the transistors 52A and 52B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 18D is an example in which the same transistors are used in the pixel circuit 51B. This allows the current that can flow through the transistors to be increased. Note that, although transistors having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is connected to the source.

[0282] 19A has a configuration in which a transistor 52D is added to the pixel circuit 51B. In addition, three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines are connected to the pixel circuit 51E.

[0283] The gate of the transistor 52D is connected to a wiring GL3, one of the source and drain of the transistor 52D is connected to the gate of the transistor 52B, and the other is connected to a wiring V0. The gate of the transistor 52A is connected to a wiring GL1, and the gate of the transistor 52C is connected to a wiring GL2.

[0284] By simultaneously turning on the transistors 52C and 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through the light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0285] 19B is an example in which a capacitor 53A is added to the pixel circuit 51E. The capacitor 53A functions as a storage capacitor.

[0286] 19C and 19D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F. Transistors each having a pair of gates connected to each other are applied to the transistor 52A, the transistor 52C, and the transistor 52D, and a transistor each having one gate connected to its source is applied to the transistor 52B.

[0287] 20A to 20D , configuration examples of the memory circuits described in Embodiment 1 will be described. Note that the memory circuits 58A to 58D shown in FIGS. 20A to 20D are memory circuits using OS transistors, and can be roughly classified into NOSRAM (registered trademark) in FIGS. 20A and 20B and DOSRAM (registered trademark) in FIGS. 20C and 20D.

[0288] Note that NOSRAM refers to a gain cell type DRAM in which the write transistor of a memory circuit is configured with an OS transistor. NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. DOSRAM refers to a memory device in which the memory circuit is a 1T1C (one transistor, one capacitor) type cell and the write transistor is a transistor to which an oxide semiconductor is applied. DOSRAM is an abbreviation for Dynamic Oxide Semiconductor Random Access Memory.

[0289] 20A shows an example of a circuit configuration applicable to the memory circuit 58. Here, the memory circuit 58A is a two-transistor (2T) gain cell. The memory circuit 58A includes transistors MW1 and MR1 and a capacitor CS1. The transistor MW1 is a write transistor, and the transistor MR1 is a read transistor. The back gates of the transistors MW1 and MR1 are connected to a wiring BGL.

[0290] Since the read transistor is an OS transistor, the memory circuit 58A does not consume power to retain data, and therefore the memory circuit 58A can be used as a low-power memory circuit that can retain data for a long period of time.

[0291] The memory circuit 58B shown in FIG. 20B is a 3T-type gain cell and includes transistors MW2, MR2, MS2, and a capacitance element CS2. The transistors MW2, MR2, and MS2 are a write transistor, a read transistor, and a select transistor, respectively. The back gates of the transistors MW2, MR2, and MS2 are connected to a wiring BGL. The memory circuit 58B is connected to word lines RWL and WWL, bit lines RBL and WBL, a capacitance line CDL, and a power supply line PL2. For example, a ground potential GND is input to the capacitance line CDL and the power supply line PL2.

[0292] 20C and 20D show examples of a 1T1C (one transistor, one capacitor) type memory circuit. A memory circuit 58C shown in FIG. 20C is connected to a word line WL, a bit line BL, a capacitor line CDL, and a wiring BGL. The memory circuit 58C has a transistor MW3 and a capacitor element CS3. The back gate of the transistor MW3 is connected to the wiring BGL. Also, a memory circuit 58D shown in FIG. 20D illustrates the configuration of a ferroelectric memory using a capacitor element having a ferroelectric material in the capacitor element CS4. For example, HfZrO Ｘ can be used.

[0293] 21A is a circuit diagram illustrating an example of the circuit configuration of a pixel circuit 56 connected to a light-receiving element 62. The pixel circuit 56 includes a transistor 132, a transistor 133, a transistor 134, a transistor 135, and a capacitor 138. Note that the capacitor 138 may not be provided.

[0294] One electrode (cathode) of the light-receiving element 62 is connected to either the source or the drain of a transistor 132. The other of the source or the drain of the transistor 132 is connected to either the source or the drain of a transistor 133. One of the source or the drain of the transistor 133 is connected to one electrode of a capacitor 138. One electrode of the capacitor 138 is connected to the gate of a transistor 134. One of the source or the drain of the transistor 134 is connected to either the source or the drain of a transistor 135.

[0295] Here, a wiring that connects the other of the source and the drain of the transistor 132, one of the source and the drain of the transistor 133, one electrode of the capacitor 138, and the gate of the transistor 134 is referred to as a node FD. The node FD can function as a charge detection portion.

[0296] The other electrode (anode) of the light-receiving element 62 is connected to the wiring 121. The gate of the transistor 132 is connected to the wiring 127. The other of the source or drain of the transistor 133 is connected to the wiring 122. The other of the source or drain of the transistor 134 is connected to the wiring 123. The gate of the transistor 133 is connected to the wiring 126. The gate of the transistor 135 is connected to the wiring 128. The other electrode of the capacitor 138 is connected to a reference potential line such as a GND wiring. The other of the source or drain of the transistor 135 is connected to the wiring 352.

[0297] The wirings 127, 126, and 128 function as signal lines for controlling the on / off state of each transistor. The wiring 352 functions as an output line.

[0298] 21A , the cathode side of the light-receiving element 62 is connected to the transistor 132, and the node FD can be reset to a high potential. Therefore, the wiring 122 has a high potential (a higher potential than the wiring 121).

[0299] 21A shows a configuration in which the cathode side of the light-receiving element 62 is connected to the node FD, but a configuration in which the anode side of the light-receiving element 62 is connected to one of the source and the drain of the transistor 132 may be used. In this case, the node FD is reset to a low potential to operate, and therefore the wiring 122 is set to a low potential (a potential lower than that of the wiring 121).

[0300] The transistor 132 has a function of controlling the potential of the node FD. The transistor 132 is also referred to as a "transfer transistor". The transistor 133 has a function of resetting the potential of the node FD. The transistor 133 is also referred to as a "reset transistor". The transistor 134 functions as a source follower circuit and can output the potential of the node FD as image data to the wiring 352. The transistor 135 has a function of selecting a pixel to output image data. The transistor 134 is also referred to as an "amplification transistor". The transistor 135 is also referred to as a "selection transistor".

[0301] 21B , a plurality of pairs of a light-receiving element 62 and a transistor 132 may be connected to one node FD. In FIG. 21B , the first pair of a light-receiving element 62 and a transistor 132 is shown as a light-receiving element 62_1 and a transistor 132_1. The gate of the transistor 132_1 is connected to a wiring 127_1. The second pair of a light-receiving element 62 and a transistor 132 is shown as a light-receiving element 62_2 and a transistor 132_2. The gate of the transistor 132_2 is connected to a wiring 127_2. The kth pair (k is an integer greater than or equal to 1) of a light-receiving element 62 and a transistor 132 is shown as a light-receiving element 62_k and a transistor 132_k. The gate of the transistor 132_k is connected to a wiring 127_k. By connecting a plurality of pairs of the light-receiving element 62 and the transistor 132 to one node FD, the number of transistors per light-receiving element 62 can be reduced, and the packaging density of the pixel circuit 56 can be increased.

[0302] 22A is a schematic top view illustrating a configuration example in which a light-emitting element and a light-receiving element are arranged in one pixel in a display device 10 according to one embodiment of the present invention. The display device 10 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, a plurality of light-emitting elements 61B that emit blue light, and a plurality of light-receiving elements 62. In FIG. 22A , in order to easily distinguish between the light-emitting elements 61, the light-emitting regions of the light-emitting elements 61 are labeled with R, G, and B. Furthermore, the light-receiving regions of the light-receiving elements 62 are labeled with PD.

[0303] The light-emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 22A shows an example in which the light-emitting elements 61R, 61G, and 61B are arranged in order in the X direction, and the light-receiving elements 62 are arranged locally at the bottom edge. Fig. 22A also shows an example in which the light-emitting elements 61 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in Fig. 22A, a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting element 61R, a sub-pixel having the light-emitting element 61G, and a sub-pixel having the light-emitting element 61B, which are arranged in the X direction.

[0304] As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, it is preferable to use an EL element such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials contained in the EL elements include fluorescent materials (fluorescent materials), phosphorescent materials (phosphorescent materials), inorganic compounds (quantum dot materials, etc.), and materials that exhibit thermally activated delayed fluorescence (TADF materials).

[0305] For example, a pn-type or pin-type photodiode can be used as the light receiving element 62. The light receiving element 62 functions as a photoelectric conversion element that detects light incident on the light receiving element 62 and generates electric charges. The amount of electric charges generated is determined based on the amount of incident light.

[0306] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light receiving element 62. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0307] In one embodiment of the present invention, an organic EL element is used as the light-emitting element 61, and an organic photodiode is used as the light-receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element. Note that the organic EL elements and the organic photodiode are preferably separated from each other by photolithography. This allows the distance between the light-emitting elements and the organic photodiode to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0308] 22A shows a common electrode 81 and a connection electrode 82. Here, the connection electrode 82 is connected to the common electrode 81. The connection electrode 82 is provided outside the display section where the light-emitting elements 61 and the light-receiving elements 62 are arranged. Also in FIG. 22A, the common electrode 81 having an area overlapping with the light-emitting elements 61, the light-receiving elements 62, and the connection electrode 82 is shown by a dashed line.

[0309] The connection electrodes 82 can be provided along the outer periphery of the display unit. For example, they may be provided along one side of the outer periphery of the display unit, or they may be provided over two or more sides of the outer periphery of the display unit. That is, when the top surface of the display unit has a rectangular shape, the top surface of the connection electrodes 82 can have a strip-like, L-shaped, U-shaped (square bracket-shaped), square-shaped, or the like shape.

[0310] Fig. 22B is a schematic top view showing an example of the configuration of the display device 10, which is a modified example of the display device 10 shown in Fig. 22A. The display device 10 shown in Fig. 22B differs from the display device 10 shown in Fig. 22A in that it includes a light-emitting element 61IR that emits infrared light. The light-emitting element 61IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0311] 22B, in addition to the light-emitting elements 61R, 61G, and 61B, a light-emitting element 61IR is arranged in the X direction, and a light-receiving element 62 is arranged below the light-emitting elements 61R, 61G, and 61B. The light-receiving element 62 has a function of detecting infrared light.

[0312] Fig. 23A is a cross-sectional view corresponding to dashed dotted line A1-A2 in Fig. 22A, and Fig. 23B is a cross-sectional view corresponding to dashed dotted line B1-B2 in Fig. 22A. Fig. 23C is a cross-sectional view corresponding to dashed dotted line C1-C2 in Fig. 22A, and Fig. 23D is a cross-sectional view corresponding to dashed dotted line D1-D2 in Fig. 22A. The light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62 are provided on a substrate 83. Furthermore, when the display device 10 includes a light-emitting element 61IR, the light-emitting element 61IR is provided on the substrate 83.

[0313] 23A shows an example of the cross-sectional configuration of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, and FIG.

[0314] The light-emitting element 61R has a pixel electrode 84R, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G has a pixel electrode 84G, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B has a pixel electrode 84B, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a common electrode 81. The light-receiving element 62 has a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

[0315] The common layer 89 functions as an electron injection layer in the light-emitting element 61. On the other hand, the common layer 89 functions as an electron transport layer in the light-receiving element 62. Therefore, the light-receiving element 62 does not need to have the electron transport layer 88PD.

[0316] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be referred to as functional layers.

[0317] The pixel electrode 84, the hole injection layer 85, the hole transport layer 86, the light emitting layer 87, and the electron transport layer 88 can be provided separately for each element. The common layer 89 and the common electrode 81 are provided in common to the light emitting element 61R, the light emitting element 61G, the light emitting element 61B, and the light receiving element 62.

[0318] 23A , the light-emitting element 61 and the light-receiving element 62 may have a hole-blocking layer and an electron-blocking layer. The light-emitting element 61 and the light-receiving element 62 may have a layer containing a bipolar substance (a substance having high electron-transporting and hole-transporting properties) or the like.

[0319] A gap is provided between the common layer 89 and an insulating layer 92, which will be described later. This prevents the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole transport layer 86, and the hole injection layer 85. This prevents short circuits in the light-emitting element 61 and the light-receiving element 62.

[0320] 23A illustrates a configuration in which, from bottom to top, the light-emitting element 61 includes a pixel electrode 84, a hole injection layer 85, a hole transport layer 86, a light-emitting layer 87, an electron transport layer 88, a common layer 89 (electron injection layer), and a common electrode 81, and the light-receiving element 62 includes a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81, but this configuration is not limited to this. For example, the light-emitting element 61 may include, from bottom to top, a pixel electrode, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a common electrode, and the light-receiving element 62 may include, from bottom to top, a pixel electrode, an electron transport layer, a light-receiving layer, a hole transport layer, and a common electrode. In this case, the hole injection layer of the light-emitting element 61 may be used as a common layer, and the common layer may be provided between the hole transport layer of the light-receiving element 62 and the common electrode. In the light-emitting element 61, the electron injection layer can be separated for each element.

[0321] In the following description, the electron transport layer is assumed to be provided above the hole transport layer. However, the following description can also be applied to the case where the electron transport layer is provided below the hole transport layer, for example, by replacing "electrons" with "holes" and "holes" with "electrons."

[0322] The light-emitting layer 87R of the light-emitting element 61R contains a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The light-emitting layer 87G of the light-emitting element 61G contains a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The light-emitting layer 87B of the light-emitting element 61B contains a light-emitting organic compound that emits light having a peak in at least the blue wavelength range. The light-receiving layer 90 of the light-receiving element 62 contains an organic compound that has detection sensitivity in the wavelength range of visible light, for example.

[0323] A conductive film that is translucent to visible light is used for either the pixel electrode 84 or the common electrode 81, and a conductive film that is reflective is used for the other. By making the pixel electrode 84 translucent and the common electrode 81 reflective, the display device 10 can be a bottom-emission type display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 translucent, the display device 10 can be a top-emission type display device. Note that by making both the pixel electrode 84 and the common electrode 81 translucent, the display device 10 can also be a dual-emission type display device.

[0324] An insulating layer 92 is provided to cover the end portions of the pixel electrodes 84R, 84G, 84B, and 84PD. The end portions of the insulating layer 92 are preferably tapered. Note that the insulating layer 92 does not have to be provided if it is not necessary.

[0325] For example, the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, and the hole transport layer 86PD each have a region in contact with the upper surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. In addition, the end of the hole injection layer 85R, the end of the hole injection layer 85G, the end of the hole injection layer 85B, and the end of the hole transport layer 86PD are located on the insulating layer 92.

[0326] 23A , between light-emitting elements 61 emitting light of different colors, a gap is provided, for example, between two light-emitting layers 87. In this manner, it is preferable that light-emitting layer 87R, light-emitting layer 87G, and light-emitting layer 87B are provided so as not to be in contact with each other. This makes it possible to preferably prevent current from flowing through two adjacent light-emitting layers 87, thereby preventing unintended light emission. This can improve the contrast of the display device 10, thereby improving the display quality of the display device 10.

[0327] A protective layer 91 is provided on the common electrode 81. The protective layer 91 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0328] The protective layer 91 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 91 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0329] In this specification and the like, a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen.

[0330] 23C shows an example of a cross-sectional configuration of the display device 10 in the Y direction, specifically showing an example of a cross-sectional configuration of the light-emitting element 61R and the light-receiving element 62. Note that the light-emitting element 61G and the light-emitting element 61B can also be arranged in the Y direction in the same manner as the light-emitting element 61R.

[0331] 23D shows a connection portion 93 where the connection electrode 82 and the common electrode 81 are connected. In the connection portion 93, the common electrode 81 is provided in contact with the connection electrode 82, and a protective layer 91 is provided to cover the common electrode 81. In addition, an insulating layer 92 is provided to cover the end of the connection electrode 82.

[0332] 24A , the light-emitting element has an EL layer 686 between a pair of electrodes (electrode 672 and electrode 688). The EL layer 686 can be formed of a plurality of layers, such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron-injection properties (electron-injection layer) and a layer containing a substance with high electron-transport properties (electron-transport layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole-injection properties (hole-injection layer) and a layer containing a substance with high hole-transport properties (hole-transport layer).

[0333] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 24A is referred to as a single structure in this specification.

[0334] 24B shows a modified example of an EL layer 686 included in the light-emitting element shown in Fig. 24A. Specifically, the light-emitting element shown in Fig. 24B includes a layer 4430-1 on an electrode 672, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and an electrode 688 on the layer 4420-2. For example, when the electrode 672 is an anode and the electrode 688 is a cathode, the layer 4430-1 functions as a hole-injection layer, the layer 4430-2 functions as a hole-transport layer, the layer 4420-1 functions as an electron-transport layer, and the layer 4420-2 functions as an electron-injection layer. 24B , carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0335] Note that a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 24C is also a variation of the single structure.

[0336] 24D, a configuration in which a plurality of light-emitting units (EL layer 686a, EL layer 686b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure in this specification. Note that although the configuration shown in FIG. 24D is referred to as a tandem structure in this specification and the like, this is not limiting, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting element capable of emitting light with high brightness can be obtained.

[0337] 24C and 24D, the layer 4420 and the layer 4430 may have a laminated structure consisting of two or more layers, as shown in FIG. 24B.

[0338] Furthermore, a structure in which each light-emitting element produces a different emission color (here, blue (B), green (G), and red (R)) is sometimes called an SBS (Side By Side) structure.

[0339] Furthermore, when comparing the above-mentioned single structure and tandem structure with the SBS structure, the power consumption can be reduced in the order of the SBS structure, the tandem structure, and the single structure. If it is desired to keep power consumption low, the SBS structure is preferable. On the other hand, the single structure and tandem structure are preferable because their manufacturing processes are simpler than those of the SBS structure, allowing for lower manufacturing costs or higher manufacturing yields.

[0340] The light-emitting color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 686. Furthermore, the color purity can be further improved by providing the light-emitting element with a microcavity structure.

[0341] A light-emitting element that emits white light preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, it is preferable to select light-emitting materials such that the light emitted by the two light-emitting materials has a complementary color relationship. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer have a complementary color relationship, a light-emitting element that emits white light as a whole can be obtained. Furthermore, when white light emission is obtained using three or more light-emitting layers, the light-emitting colors of the three or more light-emitting layers can be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0342] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0343] <Configuration Example of Light-Emitting Element and Light-Receiving Element> A display device according to one embodiment of the present invention is a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed. In this embodiment, a display device including a top-emission light-emitting element and a light-receiving element will be described as an example.

[0344] In this specification and the like, unless otherwise specified, even when describing a configuration having a plurality of elements (e.g., light-emitting elements, light-emitting layers), when describing matters common to each element, the alphabet will be omitted. For example, when describing matters common to light-emitting layer 383R and light-emitting layer 383G, etc., they may be referred to as light-emitting layer 383.

[0345] The display device 380A shown in Figure 25 has a light receiving element 370PD, a light emitting element 370R that emits red (R) light, a light emitting element 370G that emits green (G) light, and a light emitting element 370B that emits blue (B) light.

[0346] Each light-emitting element has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​a light-emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order. The light-emitting element 370R has a light-emitting layer 383R, the light-emitting element 370G has a light-emitting layer 383G, and the light-emitting element 370B has a light-emitting layer 383B. The light-emitting layer 383R contains a light-emitting material that emits red light, the light-emitting layer 383G contains a light-emitting material that emits green light, and the light-emitting layer 383B contains a light-emitting material that emits blue light.

[0347] The light emitting element is an electroluminescent element that emits light toward the common electrode 375 when a voltage is applied between the pixel electrode 371 and the common electrode 375 .

[0348] The light receiving element 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order.

[0349] The light receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

[0350] In this embodiment, in both the light-emitting element and the light-receiving element, the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode. In other words, the light-receiving element is driven by applying a reverse bias between the pixel electrode 371 and the common electrode 375, so that the light incident on the light-receiving element can be detected, an electric charge can be generated, and the electric charge can be extracted as a current.

[0351] In the display device of this embodiment, an organic compound is used for the active layer 373 of the light-receiving element 370PD. The layers of the light-receiving element 370PD other than the active layer 373 can be configured in common with the light-emitting element. Therefore, by simply adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370PD can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element 370PD can be formed on the same substrate. Therefore, the light-receiving element 370PD can be built into the display device without significantly increasing the number of manufacturing steps.

[0352] The display device 380A shows an example in which the light receiving element 370PD and the light emitting element have a common configuration, except that the active layer 373 of the light receiving element 370PD and the light emitting layer 383 of the light emitting element are fabricated separately. However, the configuration of the light receiving element 370PD and the light emitting element is not limited to this. The light receiving element 370PD and the light emitting element may have layers fabricated separately from each other, in addition to the active layer 373 and the light emitting layer 383. It is preferable that the light receiving element 370PD and the light emitting element have one or more layers used in common (common layers). This allows the light receiving element 370PD to be incorporated into the display device without significantly increasing the number of manufacturing steps.

[0353] A conductive film that transmits visible light is used for the electrode from which light is extracted, either the pixel electrode 371 or the common electrode 375. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.

[0354] The light-emitting element included in the display device of this embodiment preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light-emitting element preferably has an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other preferably has an electrode that is reflective to visible light (reflective electrode). When the light-emitting element has a microcavity structure, light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0355] The semi-transmitting / semi-reflective electrode can have a laminated structure of a reflective electrode and an electrode that is transparent to visible light (also called a transparent electrode).

[0356] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the light emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 −２ When the light-emitting element emits near-infrared light (light having a wavelength of 750 nm or more and 1300 nm or less), the transmittance or reflectance of these electrodes for near-infrared light preferably satisfies the above-mentioned numerical range, similar to the transmittance or reflectance for visible light.

[0357] The light-emitting element has at least a light-emitting layer 383. The light-emitting element may further have, in addition to the light-emitting layer 383, a layer containing a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, a substance with high electron-injection properties, an electron-blocking material, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties), or the like.

[0358] For example, the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in common, or the light-emitting element and the light-receiving element may have one or more layers of the hole injection layer, hole transport layer, electron transport layer, and electron injection layer formed differently from each other.

[0359] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound or a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0360] In a light-emitting element, the hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. In a light-receiving element, the hole transport layer is a layer that transports holes generated in the active layer based on incident light to the anode. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 −６ cm ２ A substance having a hole mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0361] In a light-emitting element, the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. In a light-receiving element, the electron transport layer is a layer that transports electrons generated in the active layer based on incident light to the cathode. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a 1×10 −６ cm ２A substance having an electron mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of electron-transporting materials that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0362] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0363] The light-emitting layer 383 is a layer containing a light-emitting substance. The light-emitting layer 383 can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0364] Examples of the light-emitting material include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0365] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0366] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0367] The light-emitting layer 383 may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). One or both of a hole-transporting material and an electron-transporting material may be used as the one or more organic compounds. Furthermore, a bipolar material or a TADF material may be used as the one or more organic compounds.

[0368] The light-emitting layer 383 preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. With this structure, light emission can be efficiently obtained using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from an exciplex to a light-emitting substance (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smooth, allowing light emission to be obtained efficiently. With this structure, high efficiency, low-voltage operation, and a long lifetime of the light-emitting element can be simultaneously achieved.

[0369] As a combination of materials that form an exciplex, it is preferable that the HOMO level (highest occupied molecular orbital level) of the hole transporting material is equal to or higher than the HOMO level of the electron transporting material. It is also preferable that the LUMO level (lowest unoccupied molecular orbital level) of the hole transporting material is equal to or higher than the LUMO level of the electron transporting material. The LUMO level and HOMO level of the material can be derived from the electrochemical properties (reduction potential and oxidation potential) of the material measured by cyclic voltammetry (CV).

[0370] The formation of exciplexes can be confirmed, for example, by comparing the emission spectra of the hole-transporting material, the electron-transporting material, and a mixed film obtained by mixing these materials, and observing the phenomenon in which the emission spectrum of the mixed film is shifted to longer wavelengths than the emission spectra of each material (or has a new peak on the longer wavelength side). Alternatively, it can be confirmed by comparing the transient photoluminescence (PL) of the hole-transporting material, the transient PL of the electron-transporting material, and a mixed film obtained by mixing these materials, and observing differences in transient response, such as the transient PL lifetime of the mixed film having a longer-lifetime component or a larger proportion of delayed components than the transient PL lifetimes of the individual materials. The above-mentioned transient PL may also be interpreted as transient electroluminescence (EL). That is, the formation of exciplexes can also be confirmed by comparing the transient EL of the hole-transporting material, the transient EL of the electron-transporting material, and a mixed film obtained by mixing these materials, and observing the differences in transient response.

[0371] The active layer 373 includes a semiconductor. Examples of the semiconductor include an inorganic semiconductor such as silicon and an organic semiconductor including an organic compound. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer 373 is shown. By using an organic semiconductor, the light-emitting layer 383 and the active layer 373 can be formed by the same method (for example, vacuum deposition), which is preferable because a common manufacturing device can be used.

[0372] The active layer 373 has an n-type semiconductor material, such as fullerene (e.g., C ６０ , C ７０Examples of electron-accepting organic semiconductor materials include fullerene derivatives and the like. Fullerenes have a soccer ball-like shape, and this shape is energetically stable. Fullerenes have deep (low) HOMO and LUMO levels. Because fullerenes have a deep LUMO level, they have extremely high electron-accepting (acceptor) properties. Normally, when π-electron conjugation (resonance) spreads on a plane, as in benzene, electron-donating (donor) properties increase, but fullerenes have a spherical shape, so they have high electron-accepting properties despite the wide spread π-electron conjugation. High electron-accepting properties cause charge separation quickly and efficiently, making them useful as light-receiving elements. C ６０ , C ７０ Both have a wide absorption band in the visible light region, and C ７０ is C ６０ Other fullerene derivatives include [6,6]-Phenyl-C71-butylic acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butylic acid methyl ester (abbreviation: PC60BM), and 1',1",4',4"-Tetrahydro-di[1,4]methanenaphthaleno[1,2:2',3',56,60:2",3"][5,6]fullerene-C60 (abbreviation: ICBA).

[0373] Examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0374] Examples of the p-type semiconductor material of the active layer 373 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0375] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, etc.

[0376] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0377] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0378] For example, the active layer 373 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor, or may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0379] The light-emitting element and the light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element and the light-receiving element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0380] For example, a polymer compound such as poly(3,4-ethylenedioxythiophene) (PEDOT) / poly(styrenesulfonic acid) (PSS) can be used as the hole transport material, and an inorganic compound such as molybdenum oxide or copper iodide (CuI) can be used as the electron transport material.

[0381] Furthermore, a polymer compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c′]dithiophene-1,3-diyl]] polymer (abbreviation: PBDB-T) or a PBDB-T derivative, which functions as a donor, can be used for the active layer 373. For example, a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0382] Furthermore, three or more types of materials may be mixed in the active layer 373. For example, in order to expand the absorption wavelength range, a third material may be mixed in addition to an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low molecular weight compound or a high molecular weight compound.

[0383] 26 is a cross-sectional view illustrating a configuration example of the display device 10. The display device 10 has a stacked structure of a transistor 310 having a channel formed in a substrate 301 and a transistor 320 having a channel formed in a semiconductor layer containing metal oxide.

[0384] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layers 251 and 252 each function as wirings. An insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and the transistor 320 is provided over the insulating layer 332. An insulating layer 265 is provided to cover the transistor 320, and a capacitor 240 is provided over the insulating layer 265. The capacitor 240 and the transistor 320 are connected by a plug 274.

[0385] The transistor 320 can be used as a transistor that forms a pixel circuit or a transistor that forms a memory circuit. The transistor 310 can be used as a transistor that forms a memory circuit, a transistor that forms a driver circuit for driving the pixel circuit, or a transistor that forms an arithmetic circuit. The transistors 310 and 320 can be used as transistors that form various circuits such as arithmetic circuits or memory circuits.

[0386] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0387] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0388] The transistor 320 is a transistor in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0389] The transistor 320 includes a semiconductor layer 321 , an insulating layer 323 , a conductive layer 324 , a pair of conductive layers 325 , an insulating layer 326 , and a conductive layer 327 .

[0390] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. As the insulating layer 332, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0391] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0392] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics. The semiconductor layer 321 preferably includes a metal oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc. An OS transistor using such a metal oxide for a channel formation region has a characteristic of extremely low off-state current. Therefore, an OS transistor is preferably used as a transistor in a pixel circuit because analog data written to the pixel circuit can be retained for a long period of time. Similarly, an OS transistor is preferably used as a transistor in a memory circuit because analog data written to the memory circuit can be retained for a long period of time.

[0393] The pair of conductive layers 325 are provided over and in contact with the semiconductor layer 321 and function as a source electrode and a drain electrode.

[0394] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like to the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be an insulating film similar to the insulating layer 332.

[0395] Openings reaching the semiconductor layer 321 are provided in the insulating layer 328 and the insulating layer 264. Inside the openings, an insulating layer 323 and a conductive layer 324 are buried, which are in contact with side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325 and an upper surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0396] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0397] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0398] The plug 274 connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265 , the insulating layer 329 , and the insulating layer 264 .

[0399] The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0400] The conductive layer 245 is provided over the insulating layer 265 and is buried in the insulating layer 254. The conductive layer 245 is connected to one of the source and drain of the transistor 320 by a plug 274 buried in the insulating layers 328, 264, 329, and 265. The insulating layer 243 is provided to cover the conductive layer 245. The conductive layer 241 is provided in a region overlapping with the conductive layer 245 with the insulating layer 243 interposed therebetween.

[0401] An insulating layer 255 is provided to cover the capacitor 240, and a light-emitting element 61, a light-receiving element 62, and the like are provided on the insulating layer 255. A protective layer 91 is provided on the light-emitting element 61 and the light-receiving element 62, and a substrate 420 is attached to the upper surface of the protective layer 91 with a resin layer 419. A light-transmitting substrate can be used as the substrate 420.

[0402] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are connected to either the source or drain of the transistor 320 by a plug 256 embedded in the insulating layer 255, a conductive layer 245 embedded in the insulating layer 254, and a plug 274 embedded in the insulating layers 328, 264, 329, and 265.

[0403] With this configuration, OS transistors that constitute the pixel circuits and memory circuits can be arranged directly under the light-receiving elements and light-emitting elements, and driver circuits, arithmetic circuits, etc. can also be arranged, making it possible to miniaturize a display device with high performance.

[0404] Note that the transistor 320 may have a different structure.

[0405] Fig. 27A is a plan view of a transistor 752 that can replace transistor 320 or can be added to the configuration of Fig. 26. Fig. 27B is a cross-sectional view corresponding to the portion of dashed dotted line A1-A2 shown in Fig. 27A. Fig. 27C is a cross-sectional view corresponding to the portion of dashed dotted line A3-A4 shown in Fig. 27A.

[0406] 27A to 27C, the direction of the dashed dotted line A1-A2 is the X direction, the direction of the dashed dotted line A3-A4 is the Y direction, and the direction perpendicular to the X and Y directions is the Z direction.

[0407] The transistor 752 shown in FIGS. 27A to 27C includes insulators IS1 to IS3, an insulator GI1, conductors ME1 to ME3, and a semiconductor SC1.

[0408] For example, the insulator IS1 functions as a base film for providing the source, drain, and channel formation regions of the transistor 752 thereover. The insulator IS1 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulator IS1 can be, for example, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating. Alternatively, the insulator IS1 can be, for example, a resin. The material used for the insulator IS1 may be an appropriate combination of the above-mentioned insulating materials.

[0409] The conductor ME1 is a conductor (which may also be referred to as a terminal, a wiring, etc.) that functions as one of the source and the drain of the transistor 752. The conductor ME2 is a conductor (which may also be referred to as a terminal, a wiring, etc.) that functions as the other of the source and the drain of the transistor 752.

[0410] 27A to 27C, the conductor ME1 is provided as a wiring extending in the Y direction, for example, and the conductor ME2 is provided as a wiring extending in the X direction, for example.

[0411] Conductor ME1, conductor ME2, and conductor ME3 are preferably made of, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements. Conductor ME1, conductor ME2, and conductor ME3 are preferably made of, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen. Furthermore, the conductor may be a semiconductor with high electrical conductivity, such as polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0412] Conductive oxides may be used for conductors ME1, ME2, and ME3. Examples of conductive oxides include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide (also referred to as IZO (registered trademark)), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide doped with gallium, and In—Ga—Zn oxide. Conductive oxides containing indium are particularly preferred due to their high conductivity.

[0413] A plurality of conductive films formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. Specific examples of the stacked structure of the conductive film include a stacked structure of indium oxide and a metal film containing ruthenium. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0414] For example, the insulator IS2 functions as an interlayer film separating the source and drain of the transistor 752. The insulating film IS2 can be formed using, for example, a material that can be used for the insulator IS1. When the semiconductor SC1 is a metal oxide that functions as an oxide semiconductor, silicon oxide, silicon oxynitride, or silicon oxide having vacancies is preferably used. These materials can easily form a region containing oxygen that is desorbed by heating and can supply the desorbed oxygen to the metal oxide. As a result, the carrier concentration of the metal oxide at and near the interface of the semiconductor SC1, which is in contact with the insulator IS2, decreases, making the interface and near the interface of the semiconductor SC1 i-type or substantially i-type. Therefore, the interface and near the interface of the semiconductor SC1 can function as a channel formation region in the transistor 752.

[0415] The semiconductor SC1 can be, for example, a metal oxide that functions as an oxide semiconductor. In this case, the transistor 752 is an OS transistor. For example, the metal oxide preferably contains at least indium. Alternatively, it preferably contains indium or zinc. In particular, it preferably contains indium and zinc. Furthermore, it is preferable that the element M is also contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, the element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, the element M preferably contains one or both of gallium and tin.

[0416] More specifically, indium oxide can be suitably used as the metal oxide. Alternatively, the metal oxide can be gallium oxide, zinc oxide, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum Examples of the oxide include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Other examples include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0417] In addition, when the semiconductor SC1 is a metal oxide that functions as an oxide semiconductor, it is preferable to form it by the ALD method. As shown in Figures 27B and 27C, when the semiconductor SC1 is formed in a region having a step, the ALD method can be used to form the semiconductor SC1 with good coverage.

[0418] Furthermore, when a metal oxide that functions as an oxide semiconductor is used for the semiconductor SC1, it is preferable to perform microwave treatment in an oxygen-containing atmosphere during or after the formation of the metal oxide to reduce the impurity concentration in the metal oxide. Examples of impurities include hydrogen and carbon. Furthermore, the microwave treatment may improve the crystallinity of the metal oxide. Here, the microwave treatment refers to a treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves.

[0419] Note that it is preferable to use a crystalline metal oxide layer for the semiconductor SC1. For example, a metal oxide layer having a c-axis-aligned crystalline (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor SC1, the density of defect states in the semiconductor SC1 can be reduced, and a highly reliable display device can be realized.

[0420] For example, indium oxide (In oxide, also referred to as IO) is preferably used for the semiconductor SC1. Alternatively, In—Ga—Zn oxide is preferably used for the semiconductor SC1. In particular, the In—Ga—Zn oxide is more preferably a metal oxide having a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, a composition of 4:2:3 (atomic ratio) or a composition thereabout, or a composition of 3:1:2 (atomic ratio) or a composition thereabout. As another example, In—Zn oxide is preferably used for the semiconductor film SC1A. In particular, the In—Zn oxide is more preferably a metal oxide having a composition of In:Zn=4:1 (atomic ratio) or a composition thereabout.

[0421] The semiconductor SC1 preferably has a stacked structure of multiple oxide layers, each with a different atomic ratio of each metal atom. For example, consider a first metal oxide and a second metal oxide formed on the first metal oxide as the metal oxide. When each metal oxide contains at least indium (In) and an element M, it is preferable that the ratio of the number of atoms of element M contained in the first metal oxide to the number of atoms of all elements constituting the first metal oxide is higher than the ratio of the number of atoms of element M contained in the second metal oxide to the number of atoms of all elements constituting the second metal oxide. Furthermore, it is preferable that the atomic ratio of element M contained in the first metal oxide to In is higher than the atomic ratio of element M contained in the second metal oxide to In.

[0422] Specifically, the first metal oxide may have a composition of In:Ga:Zn=1:3:4 (atomic ratio) or thereabout, a composition of 1:3:2 (atomic ratio) or thereabout, or a composition of 1:1:0.5 (atomic ratio) or thereabout. The second metal oxide may have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabout, a composition of 4:2:3 (atomic ratio) or thereabout, or a composition of 3:1:2 (atomic ratio) or thereabout. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio.

[0423] In this case, the main carrier path is the second metal oxide. By configuring the first metal oxide as described above, the defect state density at the interface between the first metal oxide and the second metal oxide can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor can achieve high on-state current and high frequency characteristics.

[0424] An opening KK1 having a side surface that is approximately perpendicular to the X-Y plane (with a taper angle of 70° or more and 110° or less) is formed in the insulator IS2 in a region where the transistor 752 is provided. A semiconductor SC1 including a channel formation region of the transistor 752 is provided so as to be in contact with the conductors ME1 and ME2 through the opening KK1.

[0425] In addition, in the transistor 752, an insulator GI1 is provided over the semiconductor SC1. Specifically, in a plan view, the insulator GI1 is positioned so as to overlap a channel formation region included in the semiconductor SC1. The insulator GI1 functions as a gate insulating film in the transistor 752.

[0426] The insulator GI1 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use a single layer or a stack of insulators containing so-called high-k materials such as BST. Alternatively, the insulator GI1 may be an insulator with a high dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium (also referred to as hafnium silicate, HfxSiOy (x and y are each arbitrary numbers)), an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. Furthermore, the insulator GI1 may be made of a material that can be used for the insulator IS1. For example, the insulator GI1 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.

[0427] In the transistor 752, the conductor ME3 is provided over the insulator GI1 so as to fill the opening KK1. The conductor ME3 is a conductor (which may also be referred to as a terminal, a wiring, or the like) that functions as a gate of the transistor 752.

[0428] In addition, in FIGS. 27A to 27C, the conductor ME3 is provided as a wiring so as to extend in the Y direction, as an example.

[0429] The insulator IS3 is, for example, a film that functions as an interlayer film. Therefore, the insulator IS3 preferably includes an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0430] The insulator IS3 can be made of, for example, a material that can be used for the insulator IS1.

[0431] 27A to 27C, the conductor ME1 functioning as one of the source and the drain is located below the insulator IS2 that serves as an interlayer film, and the conductor ME2 functioning as the other of the source and the drain is located above the insulator IS2. Therefore, the transistor 752 has a configuration in which the channel formation region is provided along the opening of the insulator IS2.

[0432] The transistor 752 has a source and a drain located at different heights, and a current flows in the semiconductor layer in the height direction. That is, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the transistor 752 can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0433] 27A to 27C , by providing the channel formation region of the transistor along the side surface of the opening in the insulator that functions as an interlayer film, the area occupied by the transistor can be made smaller than when the channel formation region of the transistor is provided along the X-Y plane. Therefore, by forming a circuit using one or both of the transistors 752, the area of ​​the circuit can be made smaller. This can also lead to the miniaturization of a display device including the circuit or the display device itself.

[0434] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0435] Embodiment 3 In this embodiment, an indium oxide film that can be used for the semiconductor SC1 of the transistor included in the display device described in Embodiment 2 will be described.

[0436] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0437] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0438] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 28A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 28B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0439] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 28B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 28A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 28A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 28A.

[0440] 28A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0441] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0442] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0443] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0444] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 28A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0445] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0446] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0447] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0448] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0449] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0450] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0451] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0452] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0453] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0454] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 28C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0455] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0456] Furthermore, as shown in FIG. 28C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0457] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0458] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0459]

[0460] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0461] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0462] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0463] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0464] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0465] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0466] Embodiment 4 In this embodiment, structural examples of electronic devices including a display device according to one embodiment of the present invention will be described.

[0467] FIG. 29A is a perspective view showing the back, bottom, and right side of electronic device 100 described in FIG. 1A of the first embodiment.

[0468] 29A , a housing 101 of an electronic device 100 includes, as an example, a pair of display devices 10_L and 10_R, as well as a mounting portion 106, a buffer member 107, and a pair of lenses 108. The display units 13 of the pair of display devices 10_L and 10_R are each provided at a position inside the housing 101 where they can be viewed through the lenses 108.

[0469] The light receiving units 14 of the pair of display devices 10_L and 10_R are provided at positions where they can acquire information about the user's eye 102 and its surroundings. The acquisition of information about the user's eye 102 and its surroundings by the light receiving units 14 may be performed via a lens 108 inside the housing 101 or may be performed without using the lens 108.

[0470] 29A is provided with an input terminal 109 and an output terminal 110. A cable can be connected to the input terminal 109 for supplying an image signal (image data) from a video output device or the like, or for supplying power for charging a battery provided within the housing 101. The output terminal 110 functions as, for example, an audio output terminal, and can be connected to earphones, headphones, or the like.

[0471] Furthermore, the housing 101 preferably has a mechanism for adjusting the left-right positions of the lens 108 and the display devices 10_L and 10_R so that they are optimally positioned according to the position of the user's eyes. Also, the housing 101 preferably has a mechanism for adjusting the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0472] The cushioning member 107 is a portion that comes into contact with the user's face (forehead, cheeks, etc.). The cushioning member 107 makes close contact with the user's face, preventing light leakage and enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it can come into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels pleasant to the touch and prevents the user from feeling cold when worn in cold seasons. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the attachment portion 106, removable, for easier cleaning or replacement.

[0473] The electronic device of one embodiment of the present invention may further include an earphone 106A. The earphone 106A has a communication unit (not shown) and has a wireless communication function. The earphone 106A can output audio data using the wireless communication function. Note that the earphone 106A may have a vibration mechanism in order to function as a bone conduction earphone.

[0474] 29B, the earphone 106A can be directly connected to the attachment unit 106 or connected by wire. The earphone 106B and the attachment unit 106 may have a magnet. This allows the earphone 106B to be fixed to the attachment unit 106 by magnetic force, which is preferable as it makes storage easier.

[0475] 30A is a perspective view of a glasses-type electronic device 100A, which is another example of a wearable electronic device. The electronic device 100A shown in FIG. 30A includes a pair of display devices 10_L and 10_R in a housing 101.

[0476] The electronic device 100A can project an image displayed on the display unit 13 of the display devices 10_L and 10_R onto the display area 104 of the optical member 103. Furthermore, because the optical member 103 is translucent, the user can see the image displayed in the display area 104 superimposed on a transmitted image visually recognized through the optical member 103. Therefore, the electronic device 100A is an electronic device capable of AR display.

[0477] In addition, although not shown, the housing 101 is provided with a connector to which a wireless receiver or a cable can be connected, and a video signal or the like can be supplied to the housing 101. In addition, by providing the housing 101 with an acceleration sensor such as a gyro sensor, the orientation of the user's head can be detected and an image corresponding to that orientation can be displayed in the display area 104.

[0478] 30B, a method for projecting an image onto display area 104 of electronic device 100A will be described. Display device 10, lens 111, and reflector 112 are provided inside housing 101. In addition, a portion of optical member 103 corresponding to display area 104 has reflecting surface 113 that functions as a half mirror.

[0479] Light 115 emitted from the display device 10 passes through the lens 111 and is reflected by the reflector 112 toward the optical member 103. Inside the optical member 103, the light 115 is repeatedly totally reflected at the end face of the optical member 103 and reaches the reflecting surface 113, whereby an image is projected onto the reflecting surface 113. This allows the user to view both the light 115 reflected by the reflecting surface 113 and the transmitted light 116 that has passed through the optical member 103 (including the reflecting surface 113).

[0480] 30B shows an example in which the reflector 112 and the reflecting surface 113 each have a curved surface. This allows for greater freedom in optical design compared to when these surfaces are flat, and allows for a thinner optical member 103. Note that the reflector 112 and the reflecting surface 113 may also be flat.

[0481] A member having a mirror surface, preferably one with high reflectivity, can be used as the reflector 112. A half mirror utilizing reflection from a metal film may be used as the reflecting surface 113, but the transmittance of the transmitted light 116 can be increased by using a prism utilizing total reflection or the like.

[0482] Here, it is preferable that the housing 101 has a mechanism for adjusting the distance between the lens 111 and the display device 10 or the angle therebetween. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, the lens 111 and / or the display device 10 may be configured to be movable in the optical axis direction.

[0483] Furthermore, it is preferable that the housing 101 has a mechanism that can adjust the angle of the reflector 112. By changing the angle of the reflector 112, it is possible to change the position of the display area 104 where an image is displayed. This makes it possible to position the display area 104 in an optimal position according to the position of the user's eyes.

[0484] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0485] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0486] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0487] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0488] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0489] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0490] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0491] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0492] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0493] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0494] In this specification and the like, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0495] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0496] In this specification, the channel length of a planar transistor refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a plan view of the transistor, or a distance between a source and a drain in a region where a channel is formed.

[0497] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0498] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0499] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0500] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0501] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0502] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0503] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0504] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0505] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0506] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0507] 10: display device, 11: substrate, 12: substrate, 13: display section, 14: light receiving section, 15: terminal section, 20: reference cell section, 21: reference cell, 30: calculation cell section, 31: calculation cell, 40: layer, 42: transistor, 44: channel formation region, 45: calculation circuit section, 47: drive circuit section, 50: layer, 51: pixel circuit, 52: transistor, 54: channel formation region, 55: pixel circuit section, 56: pixel circuit, 57: pixel circuit section, 58: memory circuit, 59: memory circuit section, 60: layer, 61: light emitting element, 62: light receiving element, 100: electronic device, 101: housing, 102: eye, 103: optical member

Claims

The device has a housing and a display device, the housing has a function of placing the display device at and / or around the user's eye, the display device is provided with a first layer, a second layer, and a third layer stacked in this order; the first layer is provided with a drive circuit section and an arithmetic circuit section, the second layer is provided with a first pixel circuit section, a second pixel circuit section, and a memory circuit section; the third layer is provided with a light receiving element and a light emitting element, the light-emitting element is provided in a display unit of the display device, the light receiving element is provided in an area outside the display unit, the first pixel circuit unit has a function of controlling the light-emitting element, the second pixel circuit unit has a function of controlling the light receiving element, the memory circuit unit has a function of holding a weight value set by a current signal of an analog value and a function of performing a product-sum operation of the weight value and an input value; The arithmetic circuit unit has a function of performing arithmetic processing based on a neural network using an output current output from the memory circuit unit as an input value for a signal obtained by receiving light, and a function of outputting a signal for controlling the drive circuit unit in accordance with the arithmetic processing. 　 In claim 1, the first layer includes a first transistor having a semiconductor layer having silicon in a channel formation region; the second layer includes a second transistor having a semiconductor layer having a metal oxide in a channel formation region. 　 In claim 2, The electronic device, wherein the metal oxide is an oxide containing In, an element M (M is Al, Ga, Y, or Sn), and Zn. 　 In claim 2, The electronic device, wherein the metal oxide is indium oxide. 　 In claim 1, the light receiving element is an organic photodiode, The electronic device, wherein the light-emitting element is an organic electroluminescence element. 　 In claim 1, The electronic device, wherein the housing includes a mounting portion and an optical member.

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