Semiconductor device

Abstract

Provided is a semiconductor device which can be driven at high speed. A memory string extends in a direction perpendicular to a substrate surface, and a semiconductor layer includes indium oxide. The memory string includes MONOS-type memory cells, a tunnel layer is provided on a control gate side, and a block layer is provided on the semiconductor layer side. Holes are injected into a charge storage layer from the control gate side during an erasing operation. Additionally, a memory cell can be provided on the memory string. A transistor of the memory cell can be a vertical transistor in which at least a part of each of the semiconductor layer, a gate insulating layer, and a gate electrode is provided in a groove.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

[0003] NAND flash memories are widely used as large-capacity storage devices for computers. In recent years, a technology for increasing the integration density of NAND flash memories by arranging memory cells three-dimensionally has become widespread (see Patent Document 1). In this specification and the like, a NAND flash memory in which memory cells are arranged three-dimensionally is referred to as "3D-NAND."

[0004] While polycrystalline silicon is often used for the body portion of a 3D-NAND memory string, Patent Document 2 discloses an example in which a metal oxide (also called an oxide semiconductor) that functions as a semiconductor is used for the body portion of a memory string. Note that the body portion here refers to a semiconductor layer that functions as the channel or source / drain of a transistor that constitutes the memory string.

[0005] Furthermore, it is known that transistors using metal oxides have extremely low leakage current in an off state. For example, Patent Document 3 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of transistors using metal oxides. Furthermore, Patent Document 4 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using metal oxides.

[0006] Examples of metal oxides that can be used in the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization as the active layer.

[0007] JP 2007-266143 JP 2016-225614 JP 2012-257187 JP 2011-151383

[0008] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] The erase operation of a 3D-NAND is performed by flowing holes into the body portion. As methods for flowing holes into the body portion, Patent Document 1 discloses (1) a method of generating holes by GIDL (Gate Induced Drain Leak), (2) a method of injecting holes from a P-well of a semiconductor substrate, and (3) a method of injecting holes from a contact layer made of p-type polysilicon.

[0010] However, when a metal oxide is used for the body portion, none of the above methods (1) to (3) can be used. For example, method (1) cannot be used because metal oxide has a wider band gap than polysilicon and does not generate GIDL. Furthermore, methods (2) and (3) cannot be used because the energy barrier when injecting holes from p-type polysilicon into the metal oxide is high. Therefore, 3D-NAND cannot perform an erase operation simply by replacing the body portion from polysilicon with metal oxide.

[0011] An object of one embodiment of the present invention is to provide a memory device and a semiconductor device that can be driven at high speed.An object of one embodiment of the present invention is to provide a highly reliable memory device and a semiconductor device.An object of one embodiment of the present invention is to provide a memory device with a large storage capacity.An object of one embodiment of the present invention is to provide a novel memory device and a novel semiconductor device.

[0012] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.

[0013] One embodiment of the present invention is a semiconductor device including a substrate, a structure over the substrate, and a conductive layer. The structure includes a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer. The structure extends in a first direction, and the conductive layer extends in a second direction. The first direction is perpendicular or substantially perpendicular to a top surface of the substrate. The second direction intersects the first direction perpendicular or substantially perpendicular to the first direction. The first insulating layer is adjacent to the semiconductor layer, the second insulating layer is adjacent to the first insulating layer, and the third insulating layer is adjacent to the second insulating layer. At an intersection where the structure and the conductive layer intersect, the semiconductor layer, the first insulating layer, the second insulating layer, and the third insulating layer are concentrically arranged as viewed from the first direction. At the intersection, the conductive layer is adjacent to the third insulating layer. The first insulating layer is thicker than the third insulating layer. The semiconductor layer includes indium oxide.

[0014] Alternatively, in the above aspect, the first insulating layer may function as a blocking layer, the second insulating layer may function as a charge storage layer, and the third insulating layer may function as a tunnel layer.

[0015] Alternatively, one embodiment of the present invention includes a substrate, a structure on the substrate, a first conductive layer, an interlayer insulating film, a capacitor, a transistor, a first insulating layer, a second insulating layer, and a second conductive layer, wherein the structure includes a first semiconductor layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, the capacitor includes a sixth insulating layer, a third conductive layer, and a fourth conductive layer, and the transistor includes a seventh insulating layer, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer, wherein the structure extends in a first direction, the first conductive layer extends in a second direction, and the first the first direction is perpendicular or substantially perpendicular to the upper surface of the substrate, the second direction intersects perpendicular or substantially perpendicular to the first direction, the third insulating layer is adjacent to the first semiconductor layer, the fourth insulating layer is adjacent to the third insulating layer, and the fifth insulating layer is adjacent to the fourth insulating layer, and at an intersection where the structure and the first conductive layer intersect, the first semiconductor layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are concentrically arranged when viewed from the first direction, and at the intersection, the first conductive layer is adjacent to the fifth insulating layer, and the third insulating layer is thicker than the fifth insulating layer, and the interlayer insulating film is formed on the structure and the first conductive layer a third conductive layer located on the interlayer insulating film, a sixth insulating layer located on the third conductive layer, a fourth conductive layer located on the sixth insulating layer, a first insulating layer located on the fourth conductive layer, a fifth conductive layer and the sixth conductive layer located on the first insulating layer, the first insulating layer having a trench having a region overlapping with the fourth conductive layer and overlapping with a region between the fifth conductive layer and the sixth conductive layer, and a second semiconductor layer having a region located within the trench, the second semiconductor layer having a region in contact with the fourth conductive layer, a region in contact with the fifth conductive layer, and a region in contact with the sixth conductive layer. the seventh insulating layer is provided on the second semiconductor layer so as to have a region located within the groove; the seventh conductive layer has a region facing the second semiconductor layer with the seventh insulating layer sandwiched therebetween within the groove; the second insulating layer is located on the fifth to seventh conductive layers; the second conductive layer is located on the second insulating layer; the second conductive layer is electrically connected to the fifth conductive layer and the sixth conductive layer; the groove and the seventh conductive layer extend in a third direction in plan view, the third direction intersecting the first direction perpendicularly or approximately perpendicularly; the second conductive layer extends in a fourth direction in plan view, the fourth direction beingThe semiconductor device is a semiconductor device in which the first semiconductor layer and the second semiconductor layer intersect perpendicularly or approximately perpendicularly to the third direction and contain indium oxide.

[0016] Alternatively, in the above aspect, the semiconductor device may have an eighth conductive layer and a ninth conductive layer, the second insulating layer having a first opening overlapping the fifth conductive layer and a second opening overlapping the sixth conductive layer, the eighth conductive layer having a region located within the first opening, the ninth conductive layer having a region located within the second opening, the eighth conductive layer having a region in contact with the second conductive layer and a region in contact with the fifth conductive layer, and the ninth conductive layer having a region in contact with the second conductive layer and a region in contact with the sixth conductive layer.

[0017] Alternatively, in the above aspect, an eighth insulating layer may be provided, the eighth insulating layer being located between the interlayer insulating film and the first insulating layer, the eighth insulating layer having an opening, and the third conductive layer, the sixth insulating layer, and the fourth conductive layer having regions located within the opening.

[0018] Alternatively, in the above aspect, the third insulating layer may function as a blocking layer, the fourth insulating layer may function as a charge storage layer, and the fifth insulating layer may function as a tunnel layer.

[0019] According to one embodiment of the present invention, a memory device and a semiconductor device capable of high-speed operation can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable memory device and a semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a novel memory device and a novel semiconductor device can be provided.

[0020] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0021] FIG. 1A is a cross-sectional view showing an example of the configuration of a memory string. FIG. 1B is a circuit diagram showing an example of the configuration of a memory string. FIGS. 2A and 2B are cross-sectional views showing an example of the configuration of a memory string. FIGS. 3A and 3B are diagrams explaining the carrier concentration dependence of Hall mobility. FIG. 3C is a cross-sectional view explaining an indium oxide film. FIG. 4 is a cross-sectional view showing an example of the configuration of a memory string. FIGS. 5A and 5B are cross-sectional views showing an example of the configuration of a memory string. FIG. 6 is a cross-sectional view showing an example of the configuration of a memory string. FIGS. 7A and 7B are cross-sectional views showing an example of the configuration of a memory string. FIGS. 8A and 8B are cross-sectional views showing an example of the configuration of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of the configuration of a semiconductor device. FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 12A is a plan view showing an example of the configuration of a semiconductor device. FIG. 12B is a circuit diagram showing an example of the configuration of a memory cell. FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device. FIGS. 14A and 14B are plan views showing an example of the configuration of a semiconductor device. 15A and 15B are plan views showing a configuration example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 18A and 18B are perspective views showing a configuration example of a semiconductor device. FIG. 19 is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 20A and 20B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 21A and 21B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 22 is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 23A and 23B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 24A is a plan view showing a configuration example of a semiconductor device. FIGS. 24B to 24E are cross-sectional views showing a configuration example of a semiconductor device. FIG. 25A is a plan view showing a configuration example of a semiconductor device. FIGS. 25B to 25E are cross-sectional views showing an example of a semiconductor device. FIG. 26A is a circuit diagram showing a configuration example of a memory string. FIG. 26B is a diagram showing an example of Id-Vg characteristics of a transistor. FIG. 27A is a timing chart showing an example of an erase operation of a memory string.FIG. 27B is a circuit diagram showing an example of the operating state of a memory string. FIG. 28A is a cross-sectional view showing an example of the configuration of a memory cell. FIG. 28B is an energy band diagram of a memory cell. FIG. 29A is a timing chart showing an example of a write operation of a memory string. FIG. 29B is a circuit diagram showing an example of the operating state of a memory string. FIG. 30A is a cross-sectional view showing an example of the configuration of a memory cell. FIG. 30B is an energy band diagram of a memory cell. FIG. 31A is a timing chart showing an example of a read operation of a memory string. FIGS. 31B to 31D are circuit diagrams showing an example of the operating state of a memory string. FIG. 32 is a block diagram showing an example of the configuration of a semiconductor device. FIGS. 33A to 33G are diagrams showing an example of the circuit configuration of a memory cell. FIGS. 34A and 34B are perspective views showing an example of the configuration of a semiconductor device. FIG. 35 is a block diagram showing an example of the configuration of a CPU. FIGS. 36A and 36B are perspective views showing an example of the configuration of a semiconductor device. FIGS. 37A and 37B are perspective views showing an example of the configuration of a semiconductor device. FIG. 38 is a conceptual diagram explaining the hierarchy of a memory device. Fig. 39A and Fig. 39B are diagrams showing an example of an electronic component. Figs. 40A to 40C are diagrams showing an example of a mainframe computer. Fig. 40D is a diagram showing an example of space equipment. Fig. 40E is a diagram showing an example of a storage system applicable to a data center.

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0024] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0025] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0026] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0027] In this specification and the like, a transistor having a metal oxide in a channel formation region may be referred to as an OS (oxide semiconductor) transistor, and a transistor having silicon in a channel formation region may be referred to as a Si transistor.

[0028] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0029] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0030] In this specification, the term "content" refers to the ratio of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the content of each of metal elements X, Y, and Z is A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0031] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0033] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0034] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0035] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0036] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0037] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0038] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0039] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that intersect with each other perpendicularly or approximately perpendicularly.

[0040] Furthermore, in this specification and the like, when referring to a "first direction," a "second direction," a "third direction," etc., these directions may be different from one another, or at least two of them may be the same. For example, when referring to a "first direction," a "second direction," a "third direction," and a "fourth direction," the first direction, the second direction, and the third direction may be different from one another, and the fourth direction may be the same as any of the first to third directions.

[0041] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0042] Embodiment 1 In this embodiment, a structural example of a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0043] A semiconductor device according to one embodiment of the present invention includes a memory string. The memory string functions as a 3D-NAND memory device. The memory string includes a transistor. In the semiconductor device according to one embodiment of the present invention, a semiconductor layer of the transistor included in the memory string includes indium oxide.

[0044] In addition, in the semiconductor device of one embodiment of the present invention, a memory cell can be provided over the memory string. The memory cell includes a capacitor and a transistor and functions as a memory device. In the semiconductor device of one embodiment of the present invention, a semiconductor layer of the transistor included in the memory cell contains indium oxide.

[0045] When the semiconductor layer of the transistor contains indium oxide, the on-state current of the transistor can be increased. This can improve the frequency characteristics of the transistor. Therefore, the read and write operations of the memory device can be performed at high speed. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation.

[0046] The transistor included in the memory cell may be a vertical transistor. Specifically, the transistor may be a transistor in which at least a portion of the semiconductor layer, the gate insulating layer, and the gate electrode are provided in a groove. The groove may be provided in an interlayer insulating film, for example, on the capacitor.

[0047] In this specification, a transistor in which the source electrode and the drain electrode are located at different heights and the current flowing through the semiconductor layer has a vertical component is referred to as a vertical transistor. A vertical transistor can have two or more of the source electrode, the semiconductor, and the drain electrode stacked on top of each other. For example, one of the source electrode and the drain electrode of the transistor can be located above the other of the source electrode and the drain electrode of the transistor. As a result, the occupied area can be significantly reduced compared to a planar transistor in which the source electrode and the drain electrode are located at the same height or approximately the same height and the current flowing through the semiconductor layer has a horizontal component. Therefore, semiconductor devices can be miniaturized or highly integrated.

[0048] <Configuration example of memory string> FIG. 1A is a cross-sectional view showing a portion of a memory string 10 as viewed from the Y direction. Note that FIG. 1A also shows a central axis 151 of the memory string 10 extending in the Z direction. FIG. 1B is an equivalent circuit diagram of the memory string 10. FIG. 2A is a cross-sectional view of a portion A1-A2 indicated by a dashed-dotted line in FIG. 1A as viewed from the Z direction. FIG. 2B is a cross-sectional view of a portion B1-B2 indicated by a dashed-dotted line in FIG. 1A as viewed from the Z direction. Note that FIGS. 2A and 2B are also referred to as plan views, and specifically, can be considered to be plan views showing cross-sectional configuration examples between portions A1-A2 indicated by dashed-dotted lines in FIG. 1A and between portions B1-B2 indicated by dashed-dotted lines, respectively.

[0049] The memory string 10 includes a conductive layer 101, m insulating layers 102 (where m is an integer of 2 or more), and n conductive layers 103 (where n is an integer of 2 or more), all arranged on a substrate (not shown). The insulating layers 102 and the conductive layers 103 are alternately stacked on the substrate. In FIG. 1A and other figures, the first insulating layer 102 is referred to as insulating layer 102_1, and the m-th insulating layer 102 is referred to as insulating layer 102_m. Similarly, the first conductive layer 103 is referred to as conductive layer 103_1, and the n-th conductive layer 103 is referred to as conductive layer 103_n. In this embodiment, any insulating layer 102 is simply referred to as an "insulating layer 102." Similarly, any conductive layer 103 is simply referred to as a "conductive layer 103."

[0050] In this specification and the like, the Z direction can be defined as a direction perpendicular to the substrate surface (also referred to as the upper surface of the substrate). Alternatively, the Z direction may be defined as a direction approximately perpendicular to the substrate surface.

[0051] The insulating layer 102 and the conductive layer 103 extend in the Y direction. The memory string 10 has a structure in which the insulating layers 102 and the conductive layers 103 are alternately stacked. For example, in FIG. 1A , an insulating layer 102_1 is provided on the conductive layer 101, and a conductive layer 103_1 is provided on the insulating layer 102_1. Furthermore, an insulating layer 102_m is provided on the conductive layer 103_n.

[0052] The memory string 10 also includes a conductive layer 104, an insulating layer 105, a structure 11, and an insulating layer 121. The structure 11 extends along the Z direction. The structure 11 is provided between the conductive layer 101 and the conductive layer 104, penetrating the insulating layers 102_1 to 102_m and the conductive layers 103_1 to 103_n.

[0053] The structure 11 has a columnar structure including an insulating layer 111, a semiconductor layer 112, an insulating layer 113, an insulating layer 114, and an insulating layer 115. Specifically, the insulating layer 111 extends along a central axis 151, and the semiconductor layer 112 is provided adjacent to a side surface of the insulating layer 111. The insulating layer 113 is provided adjacent to a side surface of the semiconductor layer 112, and the insulating layer 114 is provided adjacent to a side surface of the insulating layer 113. The insulating layer 115 is provided adjacent to a side surface of the insulating layer 114. As shown in FIGS. 2A and 2B , the semiconductor layer 112, the insulating layer 113, the insulating layer 114, and the insulating layer 115 are provided concentrically outside the insulating layer 111. FIGS. 2A and 2B show an example in which the semiconductor layer 112, the insulating layer 113, the insulating layer 114, and the insulating layer 115 are provided concentrically outside the insulating layer 111.

[0054] In this specification and the like, the term "concentric" means that multiple layers are arranged to cover one axis. For example, a concentric circular shape is one embodiment of the concentric shape. For example, in the cross sections shown in FIG. 2A and FIG. 2B , the semiconductor layer 112, the insulating layer 113, the insulating layer 114, and the insulating layer 115 are arranged concentrically from the inside to cover a central axis 151 located within the insulating layer 111.

[0055] The insulating layer 121 is provided to cover side surfaces of the insulating layers 102_1 to 102_m and side surfaces of the conductive layers 103_1 to 103_n. The conductive layer 104 is provided over the structure 11 and the insulating layer 102_m. The conductive layer 101 and the conductive layer 104 are connected to the semiconductor layer 112. The insulating layer 105 is provided over the insulating layer 102_m, the insulating layer 121, and the conductive layer 104. The insulating layer 105 functions as an interlayer insulating film.

[0056] In a direction perpendicular to the Z direction, i.e., a direction parallel or substantially parallel to the substrate surface, a region (intersection) where the structure 11 and the conductive layer 103 overlap functions as a transistor Tr. Therefore, in a direction perpendicular to the Z direction, a region (intersection) where the structure 11 and the conductive layer 103 overlap functions as a memory cell. Note that FIG. 1A shows an enlarged view of the intersection.

[0057] Furthermore, the conductive layer 103 functions as the gate of the transistor Tr. The memory string 10 shown in FIG. 1A has n regions (intersections) where the structures 11 and the conductive layer 103 overlap. Therefore, the memory string 10 shown in FIG. 1A has n transistors Tr. Therefore, the memory string 10 shown in FIG. 1A has n memory cells.

[0058] FIG. 2A corresponds to a cross-sectional view of a transistor Tr in the memory string 10 when viewed from the Z direction.

[0059] 1A, the first transistor Tr counting from the conductive layer 101 side is denoted as a transistor Tr_1, and the nth transistor Tr is denoted as a transistor Tr_n. Note that in this embodiment, any transistor Tr may be simply referred to as a "transistor Tr."

[0060] Generally, a memory cell that stores data by holding charges in a charge storage layer has a stacked structure of a control gate, a block layer, a charge storage layer, a tunnel layer, and a semiconductor layer. Such a memory cell may be called by various names depending on the stacked structure from the control gate to the semiconductor layer. For example, when the control gate, block layer, charge storage layer, tunnel layer, and semiconductor layer are respectively composed of a metal, an oxide, a nitride, an oxide, and a semiconductor, the memory cell is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

[0061] Furthermore, in a MONOS type memory cell, when n-type silicon or p-type silicon is used for the control gate, it is called a SONOS (Silicon Oxide Nitride Oxide Semiconductor) type memory cell.

[0062] Similarly, when tantalum nitride is used for the control gate and aluminum oxide is used for the block layer, the memory cell is called a TANOS (Tantalum Nitride Aluminum Oxide Nitride Oxide Semiconductor) type memory cell.

[0063] When tantalum nitride is used for the control gate and hafnium oxide is used for the block layer, the memory cell is called a THNOS (tantalum nitride hafnium oxide nitride oxide semiconductor) type memory cell.

[0064] The transistor Tr according to one embodiment of the present invention functions as, for example, a MONOS memory cell. The memory string 10 functions as a NAND memory device having n memory cells.

[0065] The conductive layer 103 functions as a control gate. The insulating layer 113 functions as a block layer, the insulating layer 114 functions as a charge storage layer, and the insulating layer 115 functions as a tunnel layer. That is, the tunnel layer is provided on the control gate side, and the block layer is provided on the semiconductor layer side.

[0066] As shown in FIG. 1B, the gate of the transistor Tr is connected to a wiring CG. In FIG. 1B, the wiring CG connected to the gate of the transistor Tr_1 is shown as wiring CG_1. Note that part or all of the conductive layer 103 may function as the wiring CG. Note that the wiring CG is also referred to as a "control gate" or a "control gate wiring."

[0067] Among the transistors Tr_2 to Tr_n-1, the source of one of the adjacent transistors Tr is connected to the drain of the other transistor Tr.

[0068] One of the source or drain of the transistor Tr_1 is connected to a wiring SL, and the other is connected to one of the source or drain of the transistor Tr_2. One of the source or drain of the transistor Tr_n is connected to a wiring BL, and the other is connected to one of the source or drain of the transistor Tr_n-1.

[0069] The insulating layer 114, which functions as a charge storage layer, is made of a material having a smaller band gap than the insulating layers 113 and 115. The thickness of the insulating layer 115 (length in a direction perpendicular to the Z direction; length in the X direction in the example shown in FIG. 1A) is preferably 1 nm or more and 10 nm or less. The thickness of the insulating layer 114 is preferably 5 nm or more and 20 nm or less. The thickness of the insulating layer 113 is preferably 5 nm or more and 50 nm or less. The thickness of the insulating layer 115 is preferably thinner than the insulating layer 113. In other words, the thickness of the insulating layer 113 is preferably thicker than the insulating layer 115.

[0070] For example, silicon oxide can be used for the insulating layers 113 and 115, and silicon nitride can be used for the insulating layer 114. Each of the insulating layers 113 to 115 may be a stack of insulating films. For example, the insulating layer 113 may be a stack of a silicon oxide film and an aluminum oxide film.

[0071] Alternatively, for example, silicon nitride may be used for the insulating layer 113 and the insulating layer 115. In this case, silicon nitride having a higher silicon content than the silicon nitride used for the insulating layer 113 and the insulating layer 115 may be used for the insulating layer 114.

[0072] In the memory string 10 according to one embodiment of the present invention, the semiconductor layer 112 corresponds to the body portion. The semiconductor layer 112 includes a region where a channel of the transistor Tr is formed (also referred to as a channel formation region).

[0073] The semiconductor layer 112 preferably contains indium oxide. In this case, the semiconductor layer 112 contains indium and oxygen. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor Tr. Therefore, when the semiconductor layer 112 contains indium oxide, the on-state current of the transistor Tr can be increased. Therefore, the frequency characteristics of the transistor Tr can be improved. Therefore, the read operation and write operation of the memory device can be performed at high speed. As described above, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation.

[0074] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0075] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 3A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 3B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0076] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 3B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 3A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 3A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 3A.

[0077] 3A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0078] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0079] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0080] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0081] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 3A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0082] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0083] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 3B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the semiconductor will no longer function as a transistor. On the other hand, in indium oxide, as shown in FIG. 3A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0084] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. The normally-off state can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to the state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0085] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0086] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0087] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0088] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0089] In this specification, the term "grain boundary" refers to, for example, a grain boundary formed at the boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a grain boundary formed at the boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution transmission electron microscope (TEM) image, if the crystal orientations of the two crystal grains are the same or approximately the same, the boundary may not be called a grain boundary.

[0090] In a crystalline film, for example, crystal grains can be confirmed in a high-resolution TEM image. In addition, in a crystalline film, for example, crystal grain boundaries can be confirmed in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0091] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter of the circle. The diameter in this case is sometimes called the area-equivalent diameter or the like.

[0092] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered a single-crystal film. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0093] The extension length of the grain boundary in the indium oxide film is preferably 0 nm to 1500 nm, more preferably 0 nm to 1000 nm, and even more preferably 0 nm to 800 nm. When the semiconductor layer 112 includes an indium oxide film having an extension length of the grain boundary in the above range, a configuration in which no crystal grain boundary is observed or the grain boundary component is small can be realized. Note that, unless otherwise specified in this specification, the area of ​​the field of view used to calculate the extension length of the grain boundary is 90 nm square.

[0094] The thickness of the semiconductor layer 112 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, still more preferably 2.5 nm to 20 nm, still more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The semiconductor layer 112 preferably has a region with the above thickness in at least a part thereof. For example, the channel formation region of the semiconductor layer 112 preferably has a region with the above thickness. By setting the thickness of the semiconductor layer 112 within the above range, the crystallinity of the semiconductor layer 112 can be improved. By improving the crystallinity of the semiconductor layer 112, the semiconductor layer 112 can have crystal grains.

[0095] The lower the impurity concentration of the indium oxide film, the more preferable. Impurities in the indium oxide film can be a scattering source of carriers, which can cause a decrease in field-effect mobility. Furthermore, these impurities can also cause an inhibition of crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include gallium, zinc, boron, aluminum, and silicon. The concentrations of these impurities in the indium oxide film are preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Elements that can be contained in the indium oxide film include carbon and hydrogen. Carbon and hydrogen are elements that can be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0096] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 112, the crystallinity of the semiconductor layer 112 can be improved.

[0097] When the semiconductor layer 112 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer 112 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer 112, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. Note that the same phenomenon as when the semiconductor layer 112 contains zinc atoms may occur.

[0098] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0099] Furthermore, impurities contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible reduces the number of crystal nuclei, which can promote the growth of large crystal grains.

[0100] Furthermore, by reducing the impurities in the indium oxide film, impurity scattering can be suppressed. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the impurity concentration in the semiconductor layer 112 in the above preferred range, the field-effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0101] The concentration of impurities in the indium oxide film can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), or the like. The evaluation can be performed using, for example, ion beam spectroscopy (EDX), energy dispersive X-ray spectroscopy (EDX), or inductively coupled plasma atomic emission spectroscopy (ICP-AES).

[0102] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 3C, an indium oxide film (InOＸ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ In some cases, oxygen atoms are released as oxygen vacancies (Vo) in the film. If oxygen vacancies (Vo) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0103] The indium oxide film is formed by heat treatment at a heating temperature of 400° C. for 8 hours, and the oxygen concentration is 1×10 ２０ atoms / cm ３ 2x10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ Furthermore, the indium oxide film can transmit, for example, 1×10 ２０ atoms / cm ３ 2x10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ It is preferable that the following oxygen has the property of diffusing within the crystal grains.

[0104] Oxygen in the indium oxide film diffuses through the crystal grains and grain boundaries, and V present in the crystal grains or grain boundaries is removed. Ｏ Therefore, the normally-on state of the transistor can be suppressed. This means that the negative shift of the threshold voltage of the transistor can be eliminated in principle. As described above, by using an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0105] Furthermore, as shown in FIG. 3C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as mentioned above, reacts with oxygen contained in the film and is released as water molecules.

[0106] The permeability of the membrane to oxygen and hydrogen can be evaluated by calculation using, for example, a method called Nudged Elastic Band (NEB). Specifically, the permeability can be evaluated by calculating the migration barrier of oxygen atoms and hydrogen atoms using the NEB method. The smaller the migration barrier value, the easier it is for the atoms to move (permeate).

[0107] An example of the calculation results is shown in Table 1. ２ O ３ is a crystal model of indium oxide, and IGZO shown in Table 1 is a crystal model of In—Ga—Zn oxide.

[0108]

[0109] From Table 1, the migration barriers of oxygen, hydrogen, and excess oxygen are large in the crystal model of In-Ga-Zn oxide and small in the crystal model of indium oxide. This suggests that oxygen and hydrogen move more easily (permeate more easily) in indium oxide than in In-Ga-Zn oxide. It also suggests that the indium oxide film has higher permeability to oxygen atoms and hydrogen atoms than the In-Ga-Zn oxide film. Therefore, it is presumed that the indium oxide film is a film into which hydrogen and oxygen are easily supplied and from which hydrogen and oxygen are easily discharged. In addition, the V generated in the +GBT (Gate Bias-Temperature) test Ｏ It is expected that this will have the effect of filling the gap with oxygen, thereby enabling the realization of highly reliable transistors.

[0110] The crystallinity of the semiconductor layer 112 can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of these methods may be used for analysis.

[0111] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide with a wide band gap for the semiconductor layer 112, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0112] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide with a small effective mass of electrons for the semiconductor layer of a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0113] A transistor using an indium oxide film is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in the transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0114] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10−１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0115]

[0116] In a transistor using indium oxide for the semiconductor layer 112, the off-state current per 1 μm of the channel width at room temperature is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ It is possible to make it less than A / μm.

[0117] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be increased. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

[0118] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0119] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0120] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0121] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0122] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0123] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0124] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a film containing the crystal or the surface on which the crystal is formed. For example, a crystal with a crystal orientation of <100> is said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is formed.

[0125] The indium oxide film may contain one or more metal elements having a large period number in the periodic table, provided that the film has crystallinity. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction. Therefore, by including a metal element having a large period number in the periodic table, the field-effect mobility of the transistor may be improved. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0126] A NAND storage device including an OS memory is also referred to as an “OS NAND type” or an “OS NAND type storage device.” Furthermore, a 3D-NAND storage device including an OS memory is also referred to as a “3D OS NAND type” or a “3D OS NAND type storage device.” Therefore, the memory string 10 according to one embodiment of the present invention can be said to be a 3D OS NAND type storage device.

[0127] [Variation 1] Fig. 4 shows a cross-sectional view of memory string 10A, which is a variation of memory string 10. Fig. 5A is a cross-sectional view of portion C1-C2 indicated by the dashed-dotted line in Fig. 4, as viewed from the Z direction. Fig. 5B is a cross-sectional view of portion D1-D2 indicated by the dashed-dotted line in Fig. 4, as viewed from the Z direction. Figs. 5A and 5B are also referred to as plan views, and specifically can be considered to be plan views showing example cross-sectional configurations between portion C1-C2 indicated by the dashed-dotted line in Fig. 4 and between portion D1-D2 indicated by the dashed-dotted line, respectively.

[0128] FIG. 5A corresponds to a cross-sectional view of a transistor Tr in the memory string 10A when viewed from the Z direction.

[0129] The memory string 10A has a structure 11A instead of the structure 11. The structure 11A has a structure obtained by removing the insulating layer 114 and the insulating layer 115 from the structure 11. The insulating layer 114 and the insulating layer 115 are provided for each transistor Tr.

[0130] In this embodiment, the insulating layer 114 included in the transistor Tr_1 is referred to as the insulating layer 114_1. The insulating layer 115 included in the transistor Tr_1 is referred to as the insulating layer 115_1. Similarly, the insulating layer 114 included in the transistor Tr_n is referred to as the insulating layer 114_n, and the insulating layer 115 included in the transistor Tr_n is referred to as the insulating layer 115_n. The insulating layer 114 included in any transistor Tr is simply referred to as the "insulating layer 114." Similarly, the insulating layer 115 included in any transistor Tr is simply referred to as the "insulating layer 115."

[0131] In the memory string 10A, the insulating layer 115_1 is provided adjacent to the conductive layer 103_1. The insulating layer 115_1 has a region that overlaps with the structure 11A in a direction perpendicular to the Z direction.

[0132] The insulating layer 115_1 has a region overlapping with a bottom surface of the conductive layer 103_1. The conductive layer 103_1 overlaps with the insulating layer 102_1 through the region.

[0133] The insulating layer 115_1 has a region overlapping with a top surface of the conductive layer 103_1. The conductive layer 103_1 overlaps with the insulating layer 102_2 through the region.

[0134] The insulating layer 114_1 is provided adjacent to the insulating layer 115_1. The insulating layer 114_1 has a region that overlaps with the structure 11A in a direction perpendicular to the Z direction.

[0135] The insulating layer 114_1 has a region that overlaps with a bottom surface of the conductive layer 103 through part of the insulating layer 115_1. The conductive layer 103_1 overlaps with the insulating layer 102_1 through this region.

[0136] The insulating layer 114_1 has a region that overlaps with the top surface of the conductive layer 103 through part of the insulating layer 115_1. The conductive layer 103_1 overlaps with the insulating layer 102_2 through this region.

[0137] Therefore, the cross-sectional view shown in FIG. 5A is the same as the cross-sectional view shown in FIG. 2A, but the cross-sectional view shown in FIG. 5B is different from the cross-sectional view shown in FIG. 2B.

[0138] In the memory string 10, the insulating layer 114 is shared between adjacent transistors Tr, so there is a possibility that the charge stored in the insulating layer 114 may interfere with the adjacent transistors Tr. On the other hand, in the memory string 10A, the insulating layer 114 that functions as a charge storage layer is provided independently for each transistor Tr, so the possibility of interference with adjacent transistors Tr can be reduced. This reduces noise and improves the reliability of data retention. Furthermore, the memory string 10A can more easily retain multi-value information than the memory string 10.

[0139] [Variation 2] Fig. 6 shows a cross-sectional view of memory string 10B, which is a variation of memory string 10A. Fig. 7A is a cross-sectional view of portion E1-E2 indicated by the dashed-dotted line in Fig. 6, viewed from the Z direction. Fig. 7B is a cross-sectional view of portion F1-F2 indicated by the dashed-dotted line in Fig. 6, viewed from the Z direction. Figs. 7A and 7B are also referred to as plan views, and more specifically, can be considered to be plan views showing example cross-sectional configurations between portions E1-E2 indicated by the dashed-dotted line in Fig. 6 and between portions F1-F2 indicated by the dashed-dotted line, respectively.

[0140] FIG. 7A corresponds to a cross-sectional view of a transistor Tr in the memory string 10B when viewed from the Z direction.

[0141] The memory string 10B has a structure 11B instead of the structure 11A. The memory string 10B also has an insulating layer 107 and a conductive layer 108. The other structures are the same as those of the memory string 10A.

[0142] The structure 11B has a configuration in which a conductive layer 106 is added to the structure 11A. The conductive layer 106 extends along a central axis 151. The insulating layer 111 is provided adjacent to the conductive layer 106.

[0143] The insulating layer 107 is provided on the insulating layer 102_m and the insulating layer 121. The conductive layer 108 is provided so as to be embedded in a part of the insulating layer 107. In the memory string 10B, the conductive layer 104 is provided on the insulating layer 107 and the conductive layer 108, and the insulating layer 105 is provided to cover the conductive layer 104.

[0144] The semiconductor layer 112 is connected to the conductive layer 104 through the conductive layer 108. The conductive layer 106 is connected to a wiring (not shown). The conductive layer 106 can function as a back gate of the transistor Tr. The threshold voltage of the transistor Tr can be controlled by controlling the potential supplied to the back gate. This allows, for example, a normally-off transistor to be realized.

[0145] The configuration of the memory string 10B can be used in appropriate combination with the memory string 10.

[0146] <Example of Connection with Peripheral Circuits> The memory string 10 according to one embodiment of the present invention may have peripheral circuits such as a read circuit and a precharge circuit formed below it. In this case, for example, Si transistors are formed on a silicon substrate or the like to form the peripheral circuit, and then the memory string 10 according to one embodiment of the present invention is formed on the peripheral circuit. Figure 8A is a cross-sectional view of a semiconductor device 20A in which the peripheral circuit is formed of planar Si transistors (transistors TrS1P and TrS2P) and the memory string 10 according to one embodiment of the present invention is formed above it. Figure 9A is a cross-sectional view of a semiconductor device 20B in which the peripheral circuit is formed of FIN Si transistors (transistors TrS1F and TrS2F) and the memory string 10 according to one embodiment of the present invention is formed above it.

[0147] In this specification and the like, a semiconductor substrate made of silicon is referred to as a silicon substrate.

[0148] The transistors TrS1P, TrS2P, TrS1F, and TrS2F function as selection transistors, which allow selection of a memory string for reading or writing data.

[0149] Note that the memory string that can be used in the semiconductor device 20A and the semiconductor device 20B is not limited to the memory string 10. Instead of the memory string 10, a memory string 10A or a memory string 10B may be used.

[0150] 8A and 9A , Si transistors (transistors TrS1P, TrS2P, TrS1F, and TrS2F) constituting the peripheral circuit are formed on a substrate 1700. Element isolation layers 1701 are formed between multiple Si transistors. Conductive layers 1712 are formed as the sources and drains of the Si transistors. Conductive layers 1730 are formed to extend in the channel width direction and are connected to other Si transistors or the conductive layers 1712 (not shown).

[0151] The substrate 1700 can be, for example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like.

[0152] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. Alternatively, a semiconductor element may be formed using a substrate and then transferred to another substrate. In FIGS. 8A and 9A, a single crystal silicon wafer is used as the substrate 1700.

[0153] 8A and 9A, two memory strings 10 each having n memory cells are connected via a conductive layer 104. By connecting two memory strings each having n memory cells (transistors Tr), they can function as one memory string having 2n memory cells.

[0154] 8A, the transistor TrS1P is connected to the transistor Tr_1, and the transistor TrS2P is connected to the transistor Tr_2n. In addition, in FIG. 9A, the transistor TrS1F is connected to the transistor Tr_1, and the transistor TrS2F is connected to the transistor Tr_2n.

[0155] 10 shows an equivalent circuit diagram of the semiconductor device 20A and the semiconductor device 20B. In FIG. 10, the transistor TrS_1 corresponds to the transistor TrS1P or the transistor TrS1F. Also, in FIG. 10, the transistor TrS_2 corresponds to the transistor TrS2P or the transistor TrS2F.

[0156] The gate of the transistor TrS_1 is connected to the wiring SEL1. One of the source or drain of the transistor TrS_1 is connected to the wiring SL, and the other is connected to the source or drain of the transistor Tr_1. The gate of the transistor TrS_2 is connected to the wiring SEL2. One of the source or drain of the transistor TrS_2 is connected to the wiring BL, and the other is connected to the source or drain of the transistor Tr_2n.

[0157] 8A and 9A, an insulating layer 1203 is formed to cover the conductive layer 104, the memory string 10, and the like. The insulating layer 1203 is preferably made of an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. By using an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen for the insulating layer 1203, impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The diffusion of the impurities (e.g., impurities) into the memory string 10 can be suppressed.

[0158] Here, the Si transistor will be described in detail. FIG. 8A shows a cross-sectional view of a planar Si transistor (transistor TrS1P and transistor TrS2P) in the channel length direction, and FIG. 8B shows a cross-sectional view of the planar Si transistor in the channel width direction. The Si transistor includes a channel formation region 1793 provided in a well 1792, a low-concentration impurity region 1794, and a high-concentration impurity region 1795 (collectively referred to as impurity regions), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and insulating layers 1798 and 1799 provided on side surfaces of the gate electrode 1790. Note that the conductive region 1796 may be made of a metal silicide or the like.

[0159] 9A shows a cross-sectional view of FIN-type Si transistors (transistors TrS1F and TrS2F) in the channel length direction, and FIG. 9B shows a cross-sectional view of the FIN-type Si transistor in the channel width direction. The Si transistors shown in FIGS. 9A and 9B have a channel formation region 1793 having a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side and top surfaces of the channel formation region 1793. While this embodiment shows a case where a convex portion is formed by processing a part of a semiconductor substrate, a semiconductor layer having a convex shape may also be formed by processing an SOI substrate. Note that the reference symbols shown in FIGS. 9A and 9B are the same as those shown in FIGS. 8A and 8B.

[0160] FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device 20C. The semiconductor device 20C has a layer 13 on a memory string 10. For example, the layer 13 is provided on an insulating layer 105 that functions as an interlayer insulating film. A memory cell 150 is provided in the layer 13. The memory cell 150 has a capacitor 100 and a transistor 200. Two memory cells 150 are shown in FIG. 11. Also, FIG. 11 shows an example in which the transistor 200 is provided on the capacitor 100.

[0161] The memory cells 150 can be considered as one aspect of a memory device. The semiconductor device 20C can be considered as a memory device having the memory strings 10 and the memory cells 150.

[0162] 11, the memory cells 150 are provided so as to have an area overlapping with the memory string 10. This facilitates high integration and realizes a memory device with a large capacity.

[0163] Fig. 12A is a plan view showing an example of the configuration of a memory device in which a plurality of memory cells 150 shown in Fig. 11 are arranged. Fig. 12A shows an example in which 2 × 2 memory cells 150 are arranged in the X direction and the Y direction. The cross-sectional view shown in Fig. 11 includes a cross-sectional view of the dashed dotted line G1-G2 shown in Fig. 12A.

[0164] 12B is a circuit diagram showing a configuration example of 2×2 memory cells 150. As described above, the memory cell 150 includes a transistor 200 and a capacitor 100. One of the source and the drain of the transistor 200 is connected to one of a pair of electrodes of the capacitor 100. The other of the source and the drain of the transistor 200 is connected to a wiring BIL. The gate of the transistor 200 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor 100 is connected to a wiring CAL.

[0165] The memory cell 150 includes a conductive layer 110 on an insulating layer 105, a capacitor 100 on the conductive layer 110, an insulating layer 180 on the conductive layer 110 and on the insulating layer 105, a transistor 200 on the capacitor 100 and on the insulating layer 180, an insulating layer 280 on the insulating layer 180 and on the capacitor 100, an insulating layer 283 on the insulating layer 280 and on the transistor 200, an insulating layer 285 on the insulating layer 283, a conductive layer 244, and a conductive layer 245 on the conductive layer 244 and on the insulating layer 285.

[0166] The insulating layer 180, the insulating layer 280, and the insulating layer 285 function as interlayer insulating films in addition to the insulating layer 105. The conductive layer 110 and the conductive layer 245 have regions that function as wirings.

[0167] The transistor 200 includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, a semiconductor layer 230 over the conductive layer 220 and the conductive layer 240, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. Note that the insulating layer 280 is provided over the conductive layer 220.

[0168] The semiconductor layer 230 can be formed using a material that can be used for the semiconductor layer 112. Specifically, the semiconductor layer 230 can contain indium oxide. Therefore, the transistor 200 is an OS transistor. Because an OS transistor has a low off-state current, its use in a storage device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, thereby sufficiently reducing the power consumption of the storage device. By using the transistor 200 in a storage device, high integration and low power consumption of the storage device can be achieved. Furthermore, particularly when the semiconductor layer 112 contains indium oxide, the on-state current of the transistor 200 can be increased, thereby improving the frequency characteristics of the transistor 200. Therefore, read and write operations of the storage device can be performed at high speed. As described above, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation.

[0169] The conductive layer 260 has a region that functions as a gate electrode of the transistor 200. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200. The conductive layer 220 has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240 has a region that functions as the other of the source electrode and the drain electrode of the transistor 200. The transistor 200 has a plurality of conductive layers 240. For example, one transistor 200 has two conductive layers 240. The plurality of conductive layers 240 are connected to each other through a conductive layer 244 and a conductive layer 245.

[0170] 11 and 12A show an example in which the conductive layer 245 is provided to extend in the X direction. Also, an example in which the conductive layer 260 is provided to extend in the Y direction is shown. Note that the conductive layer 245 may be provided to extend in the Y direction. Also, the conductive layer 260 may be provided to extend in the X direction.

[0171] The insulating layer 280 has a groove 290. At least some of the components of the transistor 200 are disposed in the groove 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed so that at least some of them are located in the groove 290. The groove 290 extends in a direction parallel to the extension direction of the conductive layer 260. That is, the groove 290 extends in the Y direction, similar to the conductive layer 260. As described above, the conductive layer 245 extends in the X direction. As a result, the conductive layer 245 intersects with the groove 290 and the conductive layer 260 in a planar view, for example, perpendicularly or approximately perpendicularly.

[0172] 11 and 12A, a conductive layer 240 can be shared between two adjacent memory cells 150. A conductive layer 245 extending in the X direction can connect multiple conductive layers 240 arranged in the X direction to each other. A conductive layer 260 extending in the Y direction can be shared between multiple memory cells 150 arranged in the Y direction.

[0173] 11 and 12A, the semiconductor layer 230 can be shared between two memory cells 150 adjacent in the X direction. Furthermore, as shown in FIG. 12A, a plurality of semiconductor layers 230 can be provided in one groove 290.

[0174] Here, the wiring BIL corresponds to the conductive layer 245. The wiring WOL corresponds to the conductive layer 260. The wiring CAL corresponds to the conductive layer 110.

[0175] As shown in Figure 12A, it is preferable that the conductive layer 245 is provided extending in the X direction, and the conductive layer 260 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided so as to intersect with each other. In the example shown in Figure 12A, the wiring CAL is provided parallel to the wiring WOL. However, the present invention is not limited to this. For example, the wiring CAL may be provided parallel to the wiring BIL.

[0176] The capacitor 100 has a conductive layer 117 on the conductive layer 110 , an insulating layer 130 on the conductive layer 117 , and a conductive layer 220 on the insulating layer 130 .

[0177] In the capacitor 100, the conductive layer 220 has a region that functions as one of a pair of electrodes (sometimes referred to as an upper electrode). The conductive layer 117 has a region that functions as the other of the pair of electrodes (sometimes referred to as a lower electrode). Furthermore, the insulating layer 130 has a region that functions as a dielectric. In other words, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0178] As shown in FIG. 11 , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. The conductive layer 117 is disposed in the opening 190. Note that the conductive layer 117 has a region in contact with the top surface of the conductive layer 110 in the opening 190 and a region in contact with the side surface of the insulating layer 180 in the opening 190. The insulating layer 130 is disposed so as to be located within the opening 190. The conductive layer 220 is disposed so that at least a portion thereof is located within the opening 190. Note that, as shown in FIG. 11 , the conductive layer 220 is preferably provided so as to fill the opening 190. The films provided within the opening 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 117, the insulating layer 130, and the conductive layer 220 are preferably formed using an ALD method.

[0179] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surfaces within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote miniaturization or high integration of memory devices.

[0180] In plan view, the opening 190 is preferably circular. By using a circular shape, the processing accuracy when forming the opening 190 can be improved, and the opening 190 can be formed with a fine size. In this specification and the like, a circle is not limited to a perfect circle. Although the present embodiment illustrates an example in which the opening 190 is circular in plan view, the present invention is not limited to this. In plan view, the opening 190 can be, for example, a circle or a substantially circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygon with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0181] 11 shows an example in which the side surface of the opening 190 in the insulating layer 180 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 can have a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0182] A conductive layer 117 is provided along the side surface of the opening 190 in the insulating layer 180 and the upper surface of the conductive layer 110. An insulating layer 130 is provided on the conductive layer 117. A conductive layer 220 is provided on the insulating layer 130 so as to fill the opening 190. A capacitor 100 having such a configuration may be referred to as a trench capacitor. Note that the configuration of the capacitor 100 is not limited to this, and for example, a pillar capacitor, a parallel plate capacitor, or the like may also be used.

[0183] The insulating layer 130 is provided on the conductive layer 117. The insulating layer 130 is provided so as to cover the end portion of the conductive layer 117. This can prevent the conductive layer 117 and the conductive layer 220 from shorting out.

[0184] 11 shows an example in which the insulating layer 130 is patterned. As a result, the insulating layer 180, the insulating layer 280, the insulating layer 250, the insulating layer 283, the insulating layer 285, etc. have regions that do not overlap with the insulating layer 130. Therefore, for example, when an opening reaching the conductive layer 110 is provided in the insulating layer to connect the conductive layer 110 to another conductive layer, it is not necessary to provide an opening in the insulating layer 130. This makes it possible to easily form an opening reaching the conductive layer 110.

[0185] 11 shows an example in which the end of the insulating layer 130 coincides or substantially coincides with the end of the conductive layer 220. For example, by processing the insulating layer 130 and the conductive film that will become the conductive layer 220 using the same mask, the end of the insulating layer 130 can coincide or substantially coincides with the end of the conductive layer 220.

[0186] The end of the conductive layer 220 is preferably located outside the end of the conductive layer 117 (on the opposite side to the opening 190). With this configuration, the conductive layer 220 can be embedded in the opening 190. Furthermore, the area of ​​the conductive layer 220 in a plan view can be increased. This makes it easier to form the groove 290 so as to have an area that overlaps with the conductive layer 220.

[0187] By providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of electrical characteristics, can be suppressed.

[0188] As shown in FIG. 11 , the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, a groove 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. With this configuration, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, allowing the memory cells 150 to be arranged at a high density and increasing the storage capacity of the storage device. In other words, the storage device can be highly integrated.

[0189] FIG. 11 illustrates an example in which the width of the opening 190 in the X direction is equal to or approximately equal to the width of the groove 290. The relationship in size between the width of the opening 190 and the width of the groove 290 is not particularly limited. The width of the opening 190 can be smaller than the width of the groove 290. By making the width of the opening 190 in the X direction smaller than the width of the groove 290, the alignment accuracy between the end of the conductive layer 220 and the opening 190 can be reduced, making it relatively easy to process the conductive layer 220. Furthermore, miniaturization or high integration of the memory device can be achieved. Furthermore, the width of the opening 190 can be larger than the width of the groove 290 in the X direction. By making the width of the opening 190 larger than the width of the groove 290 in the X direction, the capacitance of the capacitor 100 can be increased. Note that, for example, as shown in FIG. 11 , the relationship in size between the two widths in a semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0190] 13 is a cross-sectional view showing a configuration example of semiconductor device 20D. Semiconductor device 20D differs from semiconductor device 20C in that the end of insulating layer 130 is located outside the end of conductive layer 220 (on the opposite side from opening 190). For example, semiconductor device 20D can be formed by processing a conductive film that will become conductive layer 220 to form conductive layer 220, and then forming insulating layer 280 without processing insulating layer 130. For example, if an opening that reaches conductive layer 110 can be easily formed in insulating layer 130, the number of manufacturing steps for the semiconductor device can be reduced by configuring insulating layer 130 as shown in FIG. 13.

[0191] <Configuration Example 1 of Semiconductor Device> Fig. 14A is a plan view showing a configuration example of a semiconductor device having a transistor 200. Fig. 14B is a plan view in which some elements are omitted from Fig. 14A. Fig. 15A is a plan view in which some elements are further omitted from Fig. 14B. Fig. 15B is a plan view in which some elements are further omitted from Fig. 15A.

[0192] Fig. 16A is a cross-sectional view taken along dashed dotted lines H1-H2 shown in Fig. 14A to 15B. Fig. 16B is a cross-sectional view taken along dashed dotted lines H3-H4 shown in Fig. 14A to 15B. Fig. 17A is a cross-sectional view taken along dashed dotted lines I1-I2 shown in Fig. 14A to 15B. Fig. 17B is a cross-sectional view taken along dashed dotted lines I3-I4 shown in Fig. 14A to 15B.

[0193] 18A and 18B are perspective views illustrating an example of a semiconductor device according to one embodiment of the present invention, in which a part of the configuration illustrated in FIG.

[0194] Fig. 19 is a cross-sectional view taken along dashed line J1-J2 in Fig. 16A and Fig. 16B. Fig. 19 is also called a plan view, and more specifically, can be said to be a plan view showing an example of the cross-sectional configuration taken along dashed line J1-J2.

[0195] 14A to 19 includes an insulating layer 210, a transistor 200 and an insulating layer 280 on the insulating layer 210, an insulating layer 283 on the transistor 200 and on the insulating layer 280, an insulating layer 285 on the insulating layer 283, a conductive layer 244a, a conductive layer 244b, and a conductive layer 245 on the conductive layer 244a, the conductive layer 244b, and the insulating layer 285. Here, FIG. 14B is a plan view in which the conductive layer 245 is omitted from FIG. 14A.

[0196] The insulating layer 210 may correspond to, for example, the insulating layer 180 shown in Figures 11 and 13. Note that, for example, the insulating layer 130 shown in Figures 11 and 13 may be included in the insulating layer 210. For example, when the insulating layer 210 has a laminated structure of multiple layers, the uppermost layer may be the insulating layer 130.

[0197] 14A to 17B includes a conductive layer 220, conductive layers 240a and 240b on an insulating layer 280, a semiconductor layer 230 on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. FIG. 15A is a plan view in which the conductive layer 260, the conductive layer 244a, and the conductive layer 244b are omitted from FIG. 14B. FIG. 15A is a plan view in which the conductive layer 245, the conductive layer 260, the conductive layer 244a, and the conductive layer 244b are omitted from FIG. 14A. FIG. 15B is a plan view in which the semiconductor layer 230 is omitted from FIG. 15A. 15B is a plan view in which the conductive layer 245, the conductive layer 260, the conductive layer 244a, the conductive layer 244b, and the semiconductor layer 230 are omitted from Fig. 14A. Note that the conductive layer 240a and the conductive layer 240b correspond to the conductive layer 240 shown in Fig. 11 to Fig. 13. The conductive layer 244a and the conductive layer 244b correspond to the conductive layer 244 shown in Fig. 11 to Fig. 13.

[0198] 14A to 15B do not show the insulating layer 210, the insulating layer 250, the insulating layer 283, and the insulating layer 285. Some components may also be omitted in the subsequent plan views.

[0199] 14A to 17B show examples in which the conductive layer 220, the conductive layer 240a, and the conductive layer 240b are provided in an island shape. The conductive layer 220, the conductive layer 240a, and the conductive layer 240b can each be provided to have, for example, a rectangular, substantially rectangular, square, or substantially square shape in a plan view. The conductive layer 220, the conductive layer 240a, and the conductive layer 240b can each have a shape with rounded corners in a plan view.

[0200] 16A to 17B , the insulating layer 280 has a region in contact with the conductive layer 220. 16A to 17B show an example in which the insulating layer 280 is provided so as to have a region in contact with a side surface of the conductive layer 220 and a region in contact with a top surface of the conductive layer 220.

[0201] The top surface of the insulating layer 280 can be flat in a region that does not overlap with the groove portion 290. For example, after the insulating layer 280 is formed, planarization treatment is performed on the insulating layer 280. As the planarization treatment, chemical mechanical polishing (CMP) treatment is preferable. Note that as the planarization treatment, treatment using etching (also referred to as etch-back treatment) may be performed.

[0202] The groove 290 has a region that overlaps with the conductive layer 220. The groove 290 can be formed so as to reach the conductive layer 220. The groove 290 is provided as a recess in a region of the insulating layer 280 that does not overlap with the conductive layer 220. Note that FIG. 16A shows an example in which the conductive layer 220 has a recess. The recess can be included in the groove 290. Note that the recess does not have to be included in the groove 290.

[0203] When the recess of the conductive layer 220 is included in the groove 290, the bottom of the groove 290 includes the bottom surface of the recess of the conductive layer 220. Furthermore, the sidewall of the groove 290 includes the side surface of the recess of the conductive layer 220 and the side surface of the insulating layer 280. The groove 290 includes the groove in the conductive layer 220 and the groove in the insulating layer 280.

[0204] The groove 290 can be formed by processing the insulating layer 280 using an etching process. In particular, a dry etching process is preferable because it is suitable for fine processing. Furthermore, for example, a recess can be formed in the conductive layer 220 by the dry etching process. The recess can be included in the groove 290 as described above.

[0205] The conductive layers 240a and 240b are provided so as to face each other across a groove 290 in plan view. The groove 290 has a region that overlaps with the region between the conductive layers 240a and 240b in plan view. Note that the groove 290 may be provided not only in the insulating layer 280 but also between the conductive layers 240a and 240b, for example.

[0206] 14A to 16A show an example in which the side surface of the inner side (groove 290 side) of the conductive layer 240a coincides or substantially coincides with the side surface of the insulating layer 280 in the groove 290. Also shown are examples in which the side surface of the inner side (groove 290 side) of the conductive layer 240b coincides or substantially coincides with the side surface of the insulating layer 280 in the groove 290. With this configuration, the conductive layer 240a, the conductive layer 240b, and the groove 290 can be formed simultaneously. The side surface of the inner side (groove 290 side) of the conductive layer 240a and the side surface of the insulating layer 280 in the groove 290 may be discontinuous. Similarly, the side surface of the inner side (groove 290 side) of the conductive layer 240b and the side surface of the insulating layer 280 in the groove 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240a on the inner side (groove 290 side) may be different from the inclination of the side surface of the insulating layer 280 at the groove 290. Similarly, the inclination of the side surface of the conductive layer 240b on the inner side (groove 290 side) may be different from the inclination of the side surface of the insulating layer 280 at the groove 290.

[0207] The semiconductor layer 230 is provided so as to cover a portion of the groove 290. The semiconductor layer 230 has a region in contact with the upper surface of the conductive layer 240a, a region in contact with the side surface of the conductive layer 240a, a region in contact with the upper surface of the conductive layer 240b, and a region in contact with the side surface of the conductive layer 240b. The semiconductor layer 230 also has a region in contact with the conductive layer 220 within the groove 290. Specifically, the semiconductor layer 230 can have a region in contact with the bottom surface of the recess of the conductive layer 220 within the groove 290 and a region in contact with the side surface of the recess.

[0208] Furthermore, the semiconductor layer 230 has a region that runs along the side surface of the groove 290 of the insulating layer 280. The semiconductor layer 230 can have a region in contact with the side surface of the insulating layer 280 within the groove 290.

[0209] 14A to 17B show an example in which the end of the semiconductor layer 230 is located outside the end of the conductive layer 240a and the end of the conductive layer 240b in a region that does not overlap with the groove portion 290. In the example shown in Figures 14A to 17B, it can be said that the semiconductor layer 230 covers the entire conductive layer 240a and the entire conductive layer 240b.

[0210] The insulating layer 250 is provided on the semiconductor layer 230 so as to have a region located within the groove 290. The insulating layer 250 can be provided so as to cover the semiconductor layer 230. The insulating layer 250 has a recess at a position overlapping the groove 290.

[0211] The conductive layer 260 is provided so as to be located within the recessed portion of the insulating layer 250. The conductive layer 260 is provided so as to fill at least a portion of the recessed portion of the insulating layer 250. The conductive layer 260 has a region within the groove 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0212] As described above, the semiconductor layer 230 is provided in the groove 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located on the bottom and the other of the source electrode and the drain electrode (here, the conductive layer 240 a and the conductive layer 240 b) is located on the top, and thus, a current flows in the vertical direction. In other words, a channel is formed along the side surface of the insulating layer 280 in the groove 290.

[0213] In the semiconductor layer 230, a region facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween in the groove 290 and a region in the vicinity thereof function as a channel formation region of the transistor 200. A region in the vicinity of the conductive layer 220 of the semiconductor layer 230 functions as one of a source region and a drain region. At least one of a region in the vicinity of the conductive layer 240a and a region in the vicinity of the conductive layer 240b of the semiconductor layer 230 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region. The source region and the drain region are low-resistance regions with higher carrier concentrations than the channel formation region.

[0214] With the above configuration, the channel formation region and the source or drain region of the transistor 200 can be formed in the groove 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, source region, and drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

[0215] The channel length of the transistor 200 is the distance between the source region and the drain region in the semiconductor layer 230. In FIG. 16A , the channel length Lc of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length Lc is the distance between the lower end of the region where the semiconductor layer 230 and the conductive layer 240b contact each other and the upper end of the region where the semiconductor layer 230 and the conductive layer 220 contact each other. Note that the channel length Lc may also be the distance between the lower end of the region where the semiconductor layer 230 and the conductive layer 240a contact each other and the upper end of the region where the semiconductor layer 230 and the conductive layer 220 contact each other in a cross-sectional view.

[0216] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the thickness of the insulating layer 280, etc. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving frequency characteristics.

[0217] Note that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 and the like. Therefore, the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the groove 290 and the like.

[0218] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0219] Here, by having a recess in the conductive layer 220 at a position overlapping the groove 290, for example, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 within the groove 290 can be lowered compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Note that the surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which the semiconductor device is provided may be used as the reference.

[0220] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the semiconductor layer 230. This can improve the electrical characteristics of the transistor 200. Furthermore, regardless of whether the conductive layer 220 or the conductive layer 240a and the conductive layer 240b is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved.

[0221] The insulating layer 283 is located over the conductive layer 260 and the insulating layer 250. The insulating layer 283 can be a barrier insulating layer against impurities such as hydrogen. This can prevent impurities such as hydrogen from entering the transistor 200. Therefore, a highly reliable semiconductor device can be provided. An example of a barrier insulating layer against hydrogen is a silicon nitride film. Note that details of materials for the barrier insulating layer against hydrogen will be described later.

[0222] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0223] The insulating layer 285 is located over the insulating layer 283. The insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230 have an opening 270a that reaches the conductive layer 240a and an opening 270b that reaches the conductive layer 240b. At least a part of the opening 270a overlaps with the conductive layer 240a, and at least a part of the opening 270b overlaps with the conductive layer 240b. The opening 270a and the opening 270b correspond to the opening 270 shown in FIGS. 11 to 13.

[0224] A conductive layer 244a is provided in the opening 270a, and a conductive layer 244b is provided in the opening 270b. For example, the conductive layer 244a is provided to fill the opening 270a, and the conductive layer 244b is provided to fill the opening 270b. The conductive layer 244a may have a region in contact with the conductive layer 240a in the opening 270a. The conductive layer 244b may have a region in contact with the conductive layer 240b in the opening 270b. Hereinafter, the openings 270a and 270b may be collectively referred to as openings 270. Furthermore, the conductive layers 244a and 244b may be collectively referred to as conductive layers 244.

[0225] The conductive layer 245 is provided over the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. The conductive layer 245 can have a region in contact with the top surface of the conductive layer 244a and a region in contact with the top surface of the conductive layer 244b. As described above, the conductive layer 240a and the conductive layer 240b can be connected via the conductive layer 244a, the conductive layer 245, and the conductive layer 244b.

[0226] The conductive layer 245 overlaps with the conductive layer 260 with the insulating layer 283 and the insulating layer 285 interposed therebetween, which function as an interlayer insulating film. This can reduce parasitic capacitance compared to, for example, a case where the conductive layer 240a and the conductive layer 240b are extended in the Y direction without the conductive layer 245 being provided. For example, the parasitic capacitance between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance between the conductive layer 240b and the conductive layer 260 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that the height of the top surfaces of the conductive layers 244a and 244b is preferably the same as or approximately the same as the height of the top surface of the insulating layer 285.

[0227] As described above, the conductive layer 245 intersects with the conductive layer 260 in a plan view, for example, perpendicularly or approximately perpendicularly. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are arranged parallel to each other in a plan view. Therefore, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, when the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be arranged parallel to each other in a plan view.

[0228] 16A and 17B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1, and an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1.

[0229] 16A and 17B show an example in which the opening 270a is provided not only in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, but also in the conductive layer 240a2. Similarly, FIG. 16A shows an example in which the opening 270b is provided in the conductive layer 240b2. Also, an example in which the opening 270a reaches the conductive layer 240a1, and the opening 270b reaches the conductive layer 240b1. In this case, the conductive layer 244a can have a region in contact with the top surface of the conductive layer 240a1 and the side surface of the conductive layer 240a2. Similarly, the conductive layer 244b can have a region in contact with the top surface of the conductive layer 240b1 and the side surface of the conductive layer 240b2.

[0230] By having the conductive layer 244a in contact with the top surface of the conductive layer 240a1, the contact resistance between the conductive layer 240a and the conductive layer 244a can be reduced, even if the contact resistance per unit area between the conductive layer 240a2 and the conductive layer 244a is greater than the contact resistance per unit area between the conductive layer 240a1 and the conductive layer 244a. Furthermore, by having the conductive layer 244a in contact with the side surface of the conductive layer 240a2, the contact area between the conductive layer 240a and the conductive layer 244a can be increased compared to when the conductive layer 244a is in contact only with the top surface of the conductive layer 240a. This reduces the contact resistance between the conductive layer 240a and the conductive layer 244a. Similarly, by having the conductive layer 244b in contact with the top surface of the conductive layer 240b1 and the side surface of the conductive layer 240b2, the contact resistance between the conductive layer 240b and the conductive layer 244b can be reduced.

[0231] Note that the conductive layer 240a2 may not have the opening 270a, and the conductive layer 240b2 may not have the opening 270b. In this case, the opening 270a reaches the upper surface of the conductive layer 240a2, and the opening 270b reaches the upper surface of the conductive layer 240b2. When the conductive layer 240a2 does not have the opening 270a, the opening 270a can be formed more easily than when the conductive layer 240a2 has the opening 270a. Similarly, when the conductive layer 240b2 does not have the opening 270b, the opening 270b can be formed more easily than when the conductive layer 240b2 has the opening 270b.

[0232] 16A and 17B , the opening 270a includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240a2. Similarly, in the example shown in FIG. 16A , the opening 270b includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240b2. Note that the shape and size of the openings 270a and 270b in a planar view may differ depending on the layer. Furthermore, when the shape of the openings 270a and 270b in a planar view is circular, the openings in each layer may or may not be concentric.

[0233] 16A, 17A, and 17B show an example in which the conductive layer 220 has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1. FIG. 16A shows an example in which the upper surface of the conductive layer 220_2 has a recess that is part of the groove 290. The bottom surface of the recess corresponds to the bottom surface of the recess in the conductive layer 220_2. The side surface of the recess corresponds to the side surface of the recess in the conductive layer 220_2. Note that the conductive layer 220_1 may also have a recess that is part of the groove 290. In this case, the conductive layer 220_2 can be configured to be separated by the groove 290.

[0234] 16A to 17A show an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. The conductive layer 260_1 can be disposed to surround the bottom and side surfaces of the conductive layer 260_2.

[0235] 16A to 17A , a conductive film to be the conductive layer 260_1 is first formed over the insulating layer 250, and then a conductive film to be the conductive layer 260_2 is formed over the conductive film. Subsequently, the entire surface of the conductive film is processed by anisotropic etching. Through the above steps, the conductive layers 260_1 and 260_2 shown in FIGS. 16A to 17A can be formed. Note that when the conductive layers 260_1 and 260_2 shown in FIGS. 16A to 17A are formed, it is not necessary to form a resist mask by photolithography, for example.

[0236] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 245 and the insulating layer 285.

[0237] The insulating layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the transistor 200 to the semiconductor layer 230.

[0238] 19 is a cross-sectional view taken along dashed-dotted line J1-J2 in FIGS. 16A and 16B , as described above. As shown in FIG. 19 , in the cross section taken along dashed-dotted line J1-J2, an insulating layer 250 is provided in the groove 290 so as to cover the side of the semiconductor layer 230 that does not contact the insulating layer 280. A conductive layer 260, specifically, a conductive layer 260_2, is provided in the center of the groove 290. In the cross section taken along dashed-dotted line J1-J2, a conductive layer 260_1 is provided in the groove 290 so as to cover the side of the insulating layer 250 opposite the insulating layer 280 and the semiconductor layer 230. Furthermore, a conductive layer 260_2 is provided so as to fill the region inward of the conductive layer 260_1 in the groove 290 (the opposite side of the insulating layer 250).

[0239] The conductive layer 260 and the semiconductor layer 230 are provided in the groove 290 so as to face each other with the insulating layer 250 sandwiched therebetween. That is, in the groove 290, the conductive layer 260 covers the semiconductor layer 230 via the insulating layer 250. In the example shown in FIG. 19 , the channel width of the transistor 200 is determined by the length of the semiconductor layer 230 in the Y direction. In FIG. 19 , the length L230 of the semiconductor layer 230 in the Y direction is shown. The channel width of the transistor 200 can be calculated as "2×L230".

[0240] Increasing the length L230 of the semiconductor layer 230 in the Y direction can increase the channel width per unit area of ​​the transistor 200 and increase the on-state current. On the other hand, decreasing the length L230 can reduce the area occupied by the transistor 200 and increase the integration density of the semiconductor device.

[0241] The width of the groove 290 in the X direction is set by the thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the groove 290. The width of the groove 290 in the X direction is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0242] <Configuration Example 2 of Semiconductor Device> Below, a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device> will be described. Note that descriptions of overlapping parts will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0243] 20A is a diagram showing an example in which the semiconductor layer 230 shown in FIG. 16A has a two-layer stacked structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1. In the semiconductor device shown in FIG. 20A, the semiconductor layer 230_2 can be in contact with the insulating layer 250.

[0244] The semiconductor layer 230_1 can be a metal oxide applicable to the semiconductor layer 230 described above, i.e., a metal oxide applicable to the semiconductor layer 112. Specifically, indium oxide can be used for the semiconductor layer 230_1. The semiconductor layer 230_2 preferably uses a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the semiconductor layer 230_1. In this case, the semiconductor layer 230_1 can mainly function as a current path (channel). That is, the semiconductor layer 230_1 has a channel formation region on the surface on the semiconductor layer 230_2 side and in the vicinity thereof.

[0245] The above-described structure can reduce carriers trapped at the interface of the semiconductor layer 230_1 and in the vicinity thereof. In addition, the channel can be located away from the surface of the insulating layer 250, thereby reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0246] Furthermore, the semiconductor layer 230_2 is preferably made of a material with high oxygen permeability. With such a structure, excess oxygen in the semiconductor layer 230_1 can be discharged to the insulating layer 250. Note that the oxygen permeability of the semiconductor layer 230_2 increases when the thickness of the semiconductor layer 230_2 is reduced. Therefore, the same effect can be achieved even when the thickness of the semiconductor layer 230_2 is reduced. The thickness of the semiconductor layer 230_2 is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and further preferably 0.1 nm to 0.5 nm.

[0247] Examples of metal oxides that can be used for the semiconductor layer 230_2 include In—Ga oxide, In—Zn oxide, indium tin oxide (ITO), indium titanium oxide (In—Ti oxide), In—Al—Zn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0248] Specifically, the In—Zn oxide used in the semiconductor layer 230_2 can have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Furthermore, the IGZO used in the semiconductor layer 230_2 can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, an In:Ga:Zn=1:3:2 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=1:3:4 (atomic ratio) or a composition thereabout.

[0249] The crystallinity of the metal oxide included in the semiconductor layer 230_2 is not particularly limited. For example, the semiconductor layer 230_2 may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0250] FIG. 20B is a diagram showing an example in which an oxide layer 227 is provided under the semiconductor layer 230 shown in FIG. 16A . The oxide layer 227 can be provided so as to be in contact with at least a portion of the surface of the semiconductor layer 230 facing the surface on the insulating layer 250 side. The oxide layer 227 has a portion overlapping with the insulating layer 250 with the semiconductor layer 230 sandwiched therebetween. In other words, the insulating layer 250 has a portion overlapping with the oxide layer 227 with the semiconductor layer 230 sandwiched therebetween. The semiconductor layer 230 is provided on the oxide layer 227 and has a region in contact with the oxide layer 227. The oxide layer 227 is a layer that causes crystal grains contained in the semiconductor layer 230 to grow from below, or a layer that does not inhibit the crystal grains contained in the semiconductor layer 230 from growing from above. When the oxide layer 227 has a function of causing crystal grains contained in the semiconductor layer 230 to grow from below, the oxide layer 227 can be called a seed layer.

[0251] The crystal of indium oxide has a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the oxide layer 227 preferably uses an oxide having a cubic crystal structure. When the crystal of the oxide layer 227 has the same crystal structure as the crystal of the semiconductor layer 230, the semiconductor layer 230 can be epitaxially grown using the oxide layer 227 as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. Note that the crystal of an oxide containing an element of Group 3 in the periodic table is likely to have a cubic crystal structure. Furthermore, the element of Group 3 in the crystal is mainly present as a trivalent cation. Therefore, the oxide layer 227 preferably contains at least one element that can become a trivalent cation. The element that can become a trivalent cation contained in the oxide layer 227 is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0252] For example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. can be used as the oxide layer 227. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0253] Specifically, the oxide layer 227 can be formed using gallium oxide, zinc oxide, indium gallium oxide (In—Ga oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, or indium tin zinc oxide (In—Sn—Zn oxide). When In—Ga—Zn oxide is used as the oxide layer 227, the oxide layer 227 contains indium, gallium, and zinc. Specifically, the oxide layer 227 can have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound. Note that a composition therearound includes a range of ±30% of the desired atomic ratio.

[0254] The oxide layer 227 may be made of an insulating material or a semiconductor material. When a semiconductor material is used for the oxide layer 227, the oxide layer 227 may be considered as part of the semiconductor layer 230. Note that the material used for the oxide layer 227 is not limited to oxide. For example, the oxide layer 227 may be made of a silicon-based semiconductor, such as single crystal silicon.

[0255] The oxide layer 227 preferably has a small thickness. For example, the oxide layer 227 is preferably thinner than the semiconductor layer 230. When the semiconductor layer 230 is in contact with a source electrode or a drain electrode via the oxide layer 227, an increase in contact resistance between the semiconductor layer 230 and the source electrode or the drain electrode can be suppressed. Specifically, the oxide layer 227 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm. Note that the oxide layer 227 may have a layer shape or a granular shape as long as it can enhance the crystal growth of the semiconductor layer 230.

[0256] Fig. 21A is a diagram showing an example in which an oxide layer 227 is provided under the semiconductor layer 230_1 shown in Fig. 20A. That is, Fig. 21A is a diagram showing an example in which the oxide layer 227 is provided and the semiconductor layer 230 has a two-layer stacked structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1.

[0257] In the semiconductor device shown in FIG. 21A , when the oxide layer 227 is formed using a semiconductor material, the semiconductor layer 230_1 is sandwiched between the oxide layer 227 and the semiconductor layer 230_2, which have a wide band gap. As a result, the semiconductor layer 230_1 mainly functions as a current path (channel). By sandwiching the semiconductor layer 230_1 between the oxide layer 227 and the semiconductor layer 230_2, trap levels at the interface of the semiconductor layer 230_1 and its vicinity can be reduced. This allows for a buried channel transistor in which the channel is spaced away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side can be reduced, suppressing photodegradation (e.g., photodegradation due to negative bias current) of the transistor and improving the reliability of the transistor.

[0258] 21B is a diagram showing an example in which a layer 228 is provided between the oxide layer 227 and the semiconductor layer 230 in the semiconductor device shown in FIG. 20B . As described above, if the semiconductor layer 230 contains gallium atoms, the reliability of the transistor may be reduced. Therefore, when an oxide containing gallium, such as an In—Ga—Zn oxide, is used as the oxide layer 227, it is preferable to provide the layer 228 between the oxide layer 227 and the semiconductor layer 230.

[0259] The layer 228 preferably contains a metal that has a stronger bond with oxygen than indium. For example, aluminum oxide is preferably used for the layer 228. In this case, the layer 228 contains aluminum and oxygen. As described above, aluminum oxide is also an insulating material that has the function of capturing or fixing oxygen. By providing the layer 228 containing aluminum oxide, it is possible to suppress the diffusion of gallium contained in the oxide layer 227 into the semiconductor layer 230. Furthermore, excess oxygen in the semiconductor layer 230 can diffuse into the layer 228 and be captured or fixed.

[0260] Note that the layer 228 preferably has a small thickness. For example, the layer 228 preferably has a region whose thickness is equal to or greater than 1 and equal to or less than 5 atomic layers, and more preferably has a region whose thickness is equal to or greater than 1 and equal to or less than 3 atomic layers. By reducing the thickness of the layer 228, the semiconductor layer 230 can be formed having crystal grains that reflect the crystal structure of the oxide layer 227.

[0261] Because the film thickness of the layer 228 is very thin, it may be difficult to clearly detect the boundary between the oxide layer 227 and the layer 228, and the boundary between the layer 228 and the semiconductor layer 230. Whether or not the boundaries between the layers are confirmed can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0262] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device of one embodiment of the present invention will be described below.

[0263] [Substrate] For example, the memory string 10 and the memory cell 150 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride (GaN). Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0264] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 102, insulating layer 105, insulating layer 107, insulating layer 111, insulating layer 113, insulating layer 114, insulating layer 115, insulating layer 121, insulating layer 130, insulating layer 180, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0265] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0266] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0267] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0268] The insulating layer 105, the insulating layer 180, the insulating layer 280, and the insulating layer 285 function as interlayer insulating films, and therefore, it is preferable to use the above-mentioned material having a low relative dielectric constant for the insulating layer 105, the insulating layer 180, the insulating layer 280, and the insulating layer 285. By using a material having a low relative dielectric constant for the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced.

[0269] The insulating layer 130 is preferably made of the above-mentioned material having a high relative dielectric constant. By using a material having a high relative dielectric constant for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be increased.

[0270] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a layered structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0271] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0272] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, if the amount of Group 3 element added is too large, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0273] Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing at least one of element M1 and element M2 and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0274] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiOＸ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0275] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0276] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0277] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0278] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0279] The insulating layer 130 can be made of any of the above-mentioned materials capable of exhibiting ferroelectricity. For example, a metal oxide containing one or both of hafnium and zirconium is preferred as the insulating layer 130 because it can exhibit ferroelectricity even in a thin film of only a few nanometers. The thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the thickness of the insulating layer 130 is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0280] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0281] Yttrium can also be added to metal oxides containing either or both of hafnium and zirconium. For example, adding yttrium to hafnium zirconium oxide can enhance ferroelectricity.

[0282] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor (hereinafter, sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0283] It is preferable that the insulating layer 250 and the insulating layer 283 be barrier insulating layers against hydrogen. When the insulating layer 250 provided on the semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the semiconductor layer 230. Furthermore, when the insulating layer 283 has a barrier property against hydrogen, hydrogen contained in the insulating layer 285 can be prevented from diffusing into the semiconductor layer 230. Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0284] Furthermore, since the insulating layer 250 is in contact with the semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0285] In addition, an insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the semiconductor layer 230, thereby reducing oxygen vacancies in the semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable as the insulating layer 250 because it has a structure that is stable against heat.

[0286] 16A to 17B show an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, it is possible to impart multiple functions to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0287] For example, the insulating layer 250 can have a two-layer structure of a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the semiconductor layer 230 can be reduced and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0288] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the semiconductor layer 230 can be reduced, and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0289] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0290] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230 can be suppressed.

[0291] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer. The fourth insulating layer is a layer that contacts the semiconductor layer 230 among the two or more layers that the insulating layer 250 has.

[0292] It is preferable to use an insulating layer having a barrier property against oxygen as the fourth insulating layer. Note that the same configuration as that of the layers used in the above-described three-layer structure can be applied to the first to third insulating layers. The fourth insulating layer is a layer in contact with the semiconductor layer 230. When the fourth insulating layer has a barrier property against oxygen, oxygen can be prevented from being released from the semiconductor layer 230.

[0293] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen or a barrier property against hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0294] In addition, by using an aluminum oxide film as the fourth insulating layer and an In—Zn oxide film as the semiconductor layer 230_2, diffusion of hydrogen into the semiconductor layer 230_1 can be suppressed in some cases.

[0295] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0296] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Each layer constituting the insulating layer 250 preferably has a region with the above thickness in at least a portion thereof.

[0297] [Conductive Layer] For each of the conductive layers (conductive layer 101, conductive layer 103, conductive layer 104, conductive layer 106, conductive layer 108, conductive layer 110, conductive layer 117, conductive layer 220, conductive layer 240, conductive layer 244, conductive layer 245, conductive layer 260, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0298] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide (also referred to as In—Zn oxide, IZO (registered trademark)). In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0299] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0300] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0301] The conductive layer 110 can be made of a conductive material with high conductivity, such as tungsten. The conductive layer 117 can be made of the above-mentioned conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, either in a single layer or a stacked layer. For example, titanium nitride, ITSO, or the like can be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride, and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can prevent the conductive layer 117 from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can prevent the conductive layer 117 from being oxidized.

[0302] The conductive layer 220, the conductive layer 240a, and the conductive layer 240b are each conductive layers in contact with the semiconductor layer 230, and therefore are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b.

[0303] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240a and the conductive layer 240b, the conductive layer 240a and the conductive layer 240b can maintain their conductivity even if they absorb oxygen. Furthermore, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, this is preferable because the conductive layer 220 can maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220, the conductive layer 240a, and the conductive layer 240b.

[0304] When the conductive layer 220, the conductive layer 240a, and the conductive layer 240b each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230, the contact resistance between the conductive layer 220 and the semiconductor layer 230, between the conductive layer 240a and the semiconductor layer 230, and between the conductive layer 240b and the semiconductor layer 230 can be reduced.

[0305] The conductive layer 220 shown in FIGS. 16A , 17A , and 17B has a two-layer structure including a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1. In this case, the conductive layer 220_2 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layer 220_2 is preferably made of, for example, a conductive material containing oxygen. The conductive layer 220_1 is preferably made of a material having higher conductivity than the conductive layer 220_2. Specifically, the conductive layer 220_2 is preferably made of an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide), and the conductive layer 220_1 is preferably made of tungsten. The conductive layer 220_1 may also be made of ruthenium, titanium nitride, tantalum nitride, or the like. By using an oxide conductor for the conductive layer 220_2 that is mainly in contact with the semiconductor layer 230, it is possible to reduce contact resistance with the semiconductor layer 230. Furthermore, by using a material having higher conductivity than an oxide conductor for a layer that constitutes the conductive layer 220, the conductivity of the conductive layer 220 can be increased.

[0306] Note that a conductive material containing oxygen can be used for the conductive layer 220_1, and a material having higher conductivity than the conductive layer 220_1 can be used for the conductive layer 220_2. In this case, a highly conductive material is used for the layer of the conductive layer 220 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0307] 16A and 17B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a2 and a material having higher conductivity than the conductive layer 240a2 for the conductive layer 240a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240a2 and tungsten for the conductive layer 240a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a1. Using an oxide conductor for the conductive layer 240a2, which is mainly in contact with the semiconductor layer 230, can reduce contact resistance with the semiconductor layer 230. Furthermore, using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240a can increase the conductivity of the conductive layer 240a.

[0308] Note that a conductive material containing oxygen can be used for the conductive layer 240a1, and a material having higher conductivity than the conductive layer 240a1 can be used for the conductive layer 240a2. In this case, an oxide conductor is used for the layer of the conductive layer 240a that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0309] 16A shows an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1. The conductive layer 240b1 can be made of a material that can be used for the conductive layer 240a1. The conductive layer 240b2 can be made of a material that can be used for the conductive layer 240a2.

[0310] The conductive layer 260 has a region that functions as a gate electrode. The conductive layer 260 is preferably made of a highly conductive material such as tungsten or ruthenium. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0311] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0312] 16A to 17A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, a titanium nitride film is preferably used as the conductive layer 260_1 and a tungsten film is preferably used as the conductive layer 260_2. Alternatively, a tantalum nitride film is preferably used as the conductive layer 260_1 and a copper film is preferably used as the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0313] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0314] The conductive layer 244 and the conductive layer 245 can be formed using a material that can be used for the conductive layer 240a and the conductive layer 240b. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 244 and the conductive layer 245. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0315] 16A shows an example in which the conductive layer 244 and the conductive layer 245 have a single-layer structure. Note that the conductive layer 244 and the conductive layer 245 can have a stacked structure of two or more layers.

[0316] <Configuration Example 3 of Semiconductor Device> Below, a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device exemplified in <Configuration Example 1 of Semiconductor Device> will be described. Note that descriptions of overlapping parts will be omitted, and only the differences will be described in detail. Furthermore, even if the position or shape of components differs, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0317] 22 is a diagram showing an example in which the conductive layer 220_1 shown in FIG. 16A has a two-layer stacked structure of a conductive layer 220_11 and a conductive layer 220_12 on the conductive layer 220_11. In this case, the conductive layer 220 can have a three-layer stacked structure of a conductive layer 220_11, a conductive layer 220_12 on the conductive layer 220_11, and a conductive layer 220_2 on the conductive layer 220_12. Also, FIG. 22 shows an example in which the insulating layer 280 has a three-layer stacked structure of an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2.

[0318] For example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 220_11, a material with high conductivity for the conductive layer 220_12, and a conductive material containing oxygen (more preferably, an oxide conductor) for the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the semiconductor layer 230. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the semiconductor layer 230. Compared to tungsten, an oxide conductor has lower contact resistance with the semiconductor layer 230, which shortens the current path between the source and drain, thereby increasing the on-current of the transistor 200. With this structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. When an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. When a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0319] It is preferable to use the above-described material with a low dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3, thereby preventing the conductive layers 220 and 240 from being oxidized and increasing their resistance.

[0320] The inorganic insulating layer exemplified as the barrier insulating layer against hydrogen can also have a barrier property against oxygen. Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0321] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 280_1 and the insulating layer 280_3, and to use silicon oxide for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0322] Fig. 23A is a diagram showing an example in which the inner side surfaces (groove 290 side) of conductive layer 240a and conductive layer 240b shown in Fig. 16A are tapered. Fig. 23B is a diagram showing an example in which the inner side surfaces (groove 290 side) of conductive layer 240a and conductive layer 240b shown in Fig. 16A and the side surface of insulating layer 280 at groove 290 are tapered.

[0323] By tapering at least one of the inner side surface (groove 290 side) of the conductive layer 240a, the inner side surface (groove 290 side) of the conductive layer 240b, and the side surface of the insulating layer 280 at the groove 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced. When the inner side surface (groove 290 side) of the conductive layer 240a, the inner side surface (groove 290 side) of the conductive layer 240b, and the side surface of the insulating layer 280 at the groove 290 are tapered, for example, the taper angle (angle θ240) of the inner side surface (groove 290 side) of the conductive layer 240a, the taper angle (angle θ280) of the inner side surface (groove 290 side) of the conductive layer 240b, and the taper angle (angle θ280) of the side surface of the insulating layer 280 at the groove 290 are each preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable because this allows for miniaturization or high integration of the semiconductor device, as described above. Also, an angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable because it improves the coverage of the film formed in the groove portion 290.

[0324] Furthermore, for example, it is preferable that the angle θ240 is smaller than the angle θ280. This configuration improves the coverage of the semiconductor layer 230 and other layers on the inner side surfaces (groove 290 side) of the conductive layers 240a and 240b, thereby reducing defects such as voids. When the conductive layers 240a and 240b have a stacked structure, the inclination of the inner side surfaces (groove 290 side) of each layer may be different. For example, the inclination of the side surface of the conductive layer 240a1 may be different from the inclination of the side surface of the conductive layer 240a2. Similarly, the inclination of the side surface of the conductive layer 240b1 may be different from the inclination of the side surface of the conductive layer 240b2.

[0325] 24A, 24B, 24C, 24D, and 24E correspond to FIGS. 14A, 16A, 16B, 17A, and 17B, respectively, and show an example in which the conductive layer 260 has a region that does not overlap with the groove portion 290. The conductive layer 260 shown in FIGS. 24A to 24E can have, for example, a region that overlaps with the conductive layer 240a and a region that overlaps with the conductive layer 240b.

[0326] 24A to 24E can be formed by, for example, photolithography. That is, the conductive layer 260 can be formed by forming a mask on a conductive film that will become the conductive layer 260 and removing part of the conductive film by etching or the like. This makes it easier to form the conductive layer 260 in a desired shape than, for example, when the conductive layer 260 is formed by processing the entire surface of the conductive film that will become the conductive layer 260 by anisotropic etching without forming a mask. On the other hand, when the conductive layer 260 is formed by processing the entire surface of the conductive film that will become the conductive layer 260 by anisotropic etching, the number of manufacturing steps for a semiconductor device can be reduced compared to when the conductive layer 260 is formed by using photolithography.

[0327] 25A, 25B, 25C, 25D, and 25E correspond to FIGS. 14A, 16A, 16B, 17A, and 17B, respectively, and illustrate an example in which the ends of the semiconductor layer 230 are located on the conductive layer 220, the conductive layer 240a, and the conductive layer 240b. In the semiconductor device illustrated in FIGS. 25A to 25E, the area occupied by the transistor 200 can be made smaller than that in the semiconductor device illustrated in FIGS. 14A and 16A to 17B. Therefore, the semiconductor device can be miniaturized or highly integrated. Meanwhile, in the semiconductor device illustrated in FIGS. 14A and 16A to 17B, the contact areas between the semiconductor layer 230 and the conductive layer 220, the contact areas between the semiconductor layer 230 and the conductive layer 240a, and the contact areas between the semiconductor layer 230 and the conductive layer 240b can be made larger than those in the semiconductor device illustrated in FIGS. 25A to 25E. This makes it possible to reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220, the contact resistance between the semiconductor layer 230 and the conductive layer 240a, and the contact resistance between the semiconductor layer 230 and the conductive layer 240b compared to the semiconductor device shown in Figures 25A to 25E.

[0328] <Operation Example of Memory String> Next, an operation example of a memory string according to one embodiment of the present invention will be described with reference to the drawings. Here, the operation example of a memory string will be described using a memory string 25 having three memory cells as an example. Figure 26A shows a circuit diagram of the memory string 25.

[0329] In addition, in this embodiment, an example of the operation of the memory string will be described using the structure of the memory string 10A, but the operation of the memory string 10 can be understood in the same way.

[0330] As described above, the transistor Tr functions as a memory cell. Data is written by injecting charges into a charge storage layer (insulating layer 114) included in the transistor Tr. The transistor Tr is preferably a transistor that functions as a normally-on transistor after data erasure. The transistors TrS_1 and TrS_2 are preferably normally-off transistors.

[0331] Here, the Id-Vg characteristics of a transistor will be described. Fig. 26B is a diagram illustrating an example of the Id-Vg characteristics of a transistor. The horizontal axis of Fig. 26B represents the gate voltage (Vg), and the vertical axis represents the drain current (Id). A characteristic 251 represents the Id-Vg characteristics of a normally-off transistor, and a characteristic 252 represents the Id-Vg characteristics of a normally-on transistor.

[0332] In a normally-off transistor, the channel resistance (resistance between the source and drain) is extremely large when Vg is 0 V, and almost no Id flows. On the other hand, a normally-on transistor has a small channel resistance when Vg is 0 V, and a larger amount of Id flows compared to a normally-off transistor. In general, when a transistor is an n-channel transistor, the threshold voltage VthD of a normally-on transistor and the threshold voltage VthE of a normally-off transistor have the relationship VthD<VthE.

[0333] [Erase Operation] When writing information to an arbitrary memory cell, it is necessary to first erase the previously written data. In this embodiment, an example of an erase operation for transistor Tr_2 will be described. It is assumed that electrons corresponding to data "1" have been injected into transistor Tr_2. The Id-Vg characteristics of transistor Tr_2 at this time correspond to the characteristics 251 shown in FIG. 26B.

[0334] 27A is a timing chart for explaining the erase operation. FIG. 27B is a circuit diagram showing the operating state of the memory string 25 during period T12. In FIG. 27B, in order to clearly show the potentials of wirings, etc., potentials such as "H" indicating an H potential or "L" indicating an L potential are written in boxed letters next to the wirings, etc.

[0335] In the period T11, an L potential (0 V) is supplied to the wirings BL and SL. An H potential is supplied to the wirings SEL1 and SEL2. Note that the H potential is a potential that can turn on a normally-off transistor. Therefore, the transistors TrS_1 and TrS_2 are turned on.

[0336] In the period T12, an H potential is supplied to the wirings CG_1 and CG_3. Then, the transistors Tr_1 and Tr_3 are turned on, and an L potential is supplied to the sources and drains of the transistors Tr_1 to Tr_3.

[0337] In addition, a VE potential is supplied to the wiring CG_2. The VE potential is a potential higher than the H potential. The VE potential is a potential at which electrons can be emitted from the charge storage layer (insulating layer 114) to the conductive layer 103 through the tunnel layer (insulating layer 115). The VE potential is a potential at which holes can be injected from the conductive layer 103 to the charge storage layer (insulating layer 114) through the tunnel layer (insulating layer 115).

[0338] By supplying a VE potential to the wiring CG_2, some of the electrons contained in the insulating layer 114_2 are extracted to the conductive layer 103_2. Also, holes are injected from the conductive layer 103_2 into the insulating layer 114_2. The injected holes and the electrons contained in the insulating layer 114_2 recombine and disappear.

[0339] 28A shows a cross-sectional view of a portion of the transistor Tr_2 (memory cell) during the period T12. FIG. 28A schematically shows the movement of electrons and holes during the period T12. FIG. 28B shows an energy band diagram of the transistor Tr_2 during the period T12.

[0340] Although data can be erased efficiently by simply extracting electrons contained in the insulating layer 114, data can also be erased efficiently by injecting holes into the insulating layer 114. When a metal oxide is used for the semiconductor layer 112, it is difficult to inject holes from the semiconductor layer 112 side into the insulating layer 114 because the metal oxide hardly generates holes. According to one embodiment of the present invention, holes can be injected from the conductive layer 103 side into the insulating layer 114, thereby enabling an erase operation to be performed efficiently.

[0341] In the period T13, an L potential is supplied to the wirings SEL1, SEL2, CG_1, CG_2, and CG_3. In this manner, the data held in the transistor Tr_2 can be erased. By erasing the data, the threshold voltage of the transistor Tr_2 shifts in the negative direction, and the transistor Tr_2 becomes a normally-on transistor. The Id-Vg characteristics of the transistor Tr_2 at this time correspond to the characteristics 252 shown in FIG. 26B. It can also be considered that the transistor Tr_2 holds data "0."

[0342] In the memory string according to one embodiment of the present invention, data can be erased not only from one memory cell but also from multiple memory cells simultaneously during the period T12.

[0343] In a memory string in which electrons are extracted from the body side and holes are injected during an erase operation, information stored in all memory cells included in the memory string is erased. Therefore, data that should not be erased must be copied in advance to another memory device (such as another memory string or a backup DRAM) and written back after the erase operation is completed (also referred to as a "temporary save operation"). In a memory device (memory string) according to one embodiment of the present invention, only data from an arbitrary memory cell can be erased, so the aforementioned temporary save operation is unnecessary. Therefore, high-speed operation can be achieved. Furthermore, high-speed operation of a semiconductor device including a memory device according to one embodiment of the present invention can be achieved.

[0344] [Write Operation] Next, a write operation will be described. In this embodiment, an example of a write operation to the transistor Tr_2 will be described. In this embodiment, an operation of writing data "1" to the transistor Tr_2 will be described.

[0345] 29A is a timing chart for explaining the write operation. FIG. 29B is a circuit diagram showing the operating state of the memory string 25 during period T22. In FIG. 29B, in order to clearly show the potentials of wirings, etc., potentials such as "H" indicating an H potential or "L" indicating an L potential are written in boxed letters next to the wirings, etc.

[0346] In the period T21, the VP potential is supplied to the wiring BL, the wiring SL, the wiring SEL1, and the wiring SEL2. The VP potential is a potential higher than the H potential. The VP potential is a potential at which electrons are injected from the conductive layer 103 to the charge accumulation layer (insulating layer 114) through the tunnel layer (insulating layer 115) due to a potential difference between the VP potential and the L potential.

[0347] In a period T22, a potential VP is supplied to the wirings CG_1 and CG_3. A potential L is supplied to the wiring CG_2. Then, in the transistor Tr_2, a potential difference (VP minus L) occurs between the semiconductor layer 112 and the conductive layer 103_2, and electrons are injected into the insulating layer 114_2.

[0348] 30A shows a cross-sectional view of a portion of the transistor Tr_2 (memory cell) during the period T22. FIG. 30A schematically shows the movements of electrons and holes during the period T22. FIG. 30B shows an energy band diagram of the transistor Tr_2 during the period T22.

[0349] Note that in the transistors Tr_1 and Tr_2, the semiconductor layer 112 and the conductive layer 103 are both at the VP potential, so that electrons are not injected into the insulating layer 114.

[0350] In the period T23, an L potential is supplied to the wirings SEL1, SEL2, CG_1, CG_2, and CG_3. In this manner, data "1" can be written to the transistor Tr_2. By writing data "1", the threshold voltage of the transistor Tr_2 is shifted in the positive direction, and the transistor Tr_2 becomes a normally-off transistor. The Id-Vg characteristics of the transistor Tr_2 at this time correspond to the characteristics 251 shown in FIG. 26B.

[0351] [Read Operation] Next, the read operation will be described. In this embodiment, the read operation of data held in transistor Tr_2 will be described. Figure 31A is a timing chart for explaining the read operation. Figures 31B to 31D are circuit diagrams showing the operating states of the memory string 25 in a read / write operation.

[0352] 31B to 31D, in order to make the potential of wirings and the like easier to understand, "H" indicating an H potential or "L" indicating an L potential is attached adjacent to wirings, electrodes, and the like. Also, "H" or "L" is enclosed in a box around wirings and the like in which a potential change has occurred. Also, an "x" symbol may be attached over a transistor in an off state.

[0353] Before the start of the read operation, an L potential is supplied to the wirings SL, BL, SEL1, SEL2, CG_1, CG_2, and CG_3.

[0354] In a period T31, an H potential is supplied to the wiring SEL2, the wiring CG_1, the wiring CG_2, and the wiring CG_3 to turn on the transistors TrS_2, Tr_1, Tr_2, and Tr_3. In addition, the wiring SL and the semiconductor are precharged with an H potential (see FIG. 31B).

[0355] In the period T32, an L potential is supplied to the wiring CG_2. At this time, when data "0" is written to the transistor Tr_2 (when data "1" is not written), the transistor Tr_2 functions as a normally-on transistor and is not turned off. On the other hand, when data "1" is written to the transistor Tr_2, the transistor Tr_2 functions as a normally-off transistor and is turned off.

[0356] Here, it is assumed that data "0" is written to the transistor Tr_2, so the transistor Tr_2 is not turned off (see FIG. 31C).

[0357] In the period T33, an H potential is supplied to the wiring SEL1 to turn on the transistor TrS_1. Then, the wiring BL and the wiring SL are brought into electrical conduction. Because the wiring BL is in a floating state, the potential of the wiring BL changes from an H potential to an L potential (see FIG. 31D).

[0358] On the other hand, when data "1" is written to the transistor Tr_2, the transistor Tr_2 is turned off. In this case, the wiring BL and the wiring SL are not electrically connected to each other, and the potential of the wiring BL remains at the H potential.

[0359] In this manner, by detecting the change in the potential of the wiring BL in the period T33, data held in the memory cell (transistor Tr) can be read.

[0360] As described above, in the semiconductor device according to one embodiment of the present invention, data can be erased, written, and read from any memory cell. Therefore, the semiconductor device according to one embodiment of the present invention functions as a NAND memory device, but can also function as a random access memory (RAM).

[0361] In addition, data written to a plurality of memory cells can be erased simultaneously. Therefore, the semiconductor device according to one embodiment of the present invention can also function as a flash memory.

[0362] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0363] Embodiment 2 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0364] Fig. 32 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 32 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 32 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0365] The memory device described in Embodiment 1 can be applied to the memory cell 950. For example, the memory string 10, the memory string 10A, or the memory string 10B can be applied to the memory cell 950. The memory cell 950 can also have a configuration including the memory string 10, the memory string 10A, or the memory string 10B and the memory cell 150.

[0366] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928. For example, the transistors included in the driver circuit 910 can be the transistors TrS1P, TrS2P, TrS1F, and TrS2F described in Embodiment 1.

[0367] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0368] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0369] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0370] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0371] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0372] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0373] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0374] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 32, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0375] 33A to 33G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0376] 33A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). A memory cell 951 includes a transistor M1 and a capacitance CA.

[0377] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0378] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitor CA is connected to the wiring CAL.

[0379] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0380] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0381] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 951 does not need to include the capacitor CA and the wiring CAL, and the first terminal of the transistor M1 may be in an electrically floating state.

[0382] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951.

[0383] Furthermore, like a memory cell 952 shown in FIG. 33B, one wiring BIL can be provided in common for two or more DRAM memory cells.

[0384] 33C shows an example circuit configuration of a two-transistor, one-capacitor gain cell memory cell. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell memory cell in which the transistor M2 is an OS transistor is referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0385] A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, and a gate of transistor M2 is connected to wiring WOL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to the first terminal of capacitor CB.

[0386] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0387] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0388] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0389] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 33D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0390] 33E is an example in which the capacitance CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 33F is an example in which the capacitance CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0391] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0392] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0393] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0394] 33G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0395] A first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, a second terminal of the transistor M4 is connected to the wiring BIL, and a gate of the transistor M4 is connected to the wiring WOL. A second terminal of the capacitor CC is connected to the first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor CC. A second terminal of the transistor M6 is connected to the wiring BIL, and a gate of the transistor M6 is connected to the wiring RWL.

[0396] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0397] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0398] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0399] Note that at least the transistor M4 is preferably an OS transistor.

[0400] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0401] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 34A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 34B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0402] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0403] 35 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 35 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0404] The arithmetic device 960 shown in FIG. 35 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0405] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0406] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0407] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0408] The arithmetic device 960 shown in FIG. 35 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 35 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0409] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0410] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0411] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0412] In the arithmetic unit 960 shown in FIG. 35 , a register controller 967 selects a holding operation in a register 966 in accordance with an instruction from an ALU 962. That is, it selects whether data is to be held by a flip-flop or by a capacitor in the memory cells of the register 966. If holding data by a flip-flop is selected, a power supply potential is supplied to the memory cells in the register 966. If holding data by a capacitor is selected, the data is rewritten to the capacitor, and the supply of power supply potential to the memory cells in the register 966 can be stopped.

[0413] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 36A and 36B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 36B.

[0414] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0415] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0416] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0417] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0418] 36B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0419] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0420] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0421] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0422] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0423] Also, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 37A shows a perspective view of a semiconductor device 970B.

[0424] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 37A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0425] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0426] Also, multiple memory arrays may be stacked. Figure 37B shows a perspective view of a semiconductor device 970C.

[0427] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0428] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0429] Embodiment 3 In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0430] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 38 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 38, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle requiring faster driving speeds and memory devices located lower in the triangle requiring larger memory capacities and higher recording densities.

[0431] In FIG. 38 , from the top layer of the triangle, there are shown memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs, and storage memories such as 3D NANDs and hard disks (also called HDDs: hard disk drives).

[0432] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high drive speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0433] A cache memory has a function of duplicating and storing a portion of data stored in a DRAM. By duplicating frequently used data and storing it in the cache memory, the access speed to the data can be increased. A cache memory requires a smaller storage capacity than a DRAM, but a faster drive speed than a DRAM. Data rewritten in the cache memory is duplicated and supplied to the DRAM. Note that, although only the L3 cache is illustrated in FIG. 38 , the cache memory is not limited to this. For example, a memory device using a metal oxide according to one embodiment of the present invention can be suitably used in a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of a cache.

[0434] The DRAM has a function of holding programs, data, etc. read from the 3D NAND.

[0435] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires a large storage capacity and a high recording density rather than a fast driving speed.

[0436] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) and the like can be used.

[0437] A memory device using a metal oxide (OS memory) according to one embodiment of the present invention can retain data for a long period of time. Therefore, it can be suitably used in the region of Target 1 shown in FIG. 38 . Note that, as indicated by the diagonal hatching in FIG. 38 , Target 1 also includes a part of the cache (L1, L2, L3) and a part of the 3D NAND. In other words, Target 1 includes a boundary region between the DRAM and the 3D NAND, and a boundary region between the DRAM and the cache (L1, L2, L3). Furthermore, the memory device using a metal oxide according to one embodiment of the present invention has a high drive speed and can therefore achieve excellent write and read operations. Therefore, it can be suitably used in the region of Target 2 shown in FIG. 38 .

[0438] For example, it is preferable to replace the DRAM shown in FIG. 38 with a memory device using a metal oxide according to one embodiment of the present invention. Here, the DRAM requires a refresh operation and is a destructive readout memory device, so it consumes more power than other memory devices. Therefore, a configuration without a DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or one-thousandth of that of a configuration using a DRAM. Therefore, global warming can be mitigated by deploying information processing devices, including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like, to which such a configuration is applied worldwide.

[0439] As described above, the memory device using a metal oxide according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, to memories in the boundary region between DRAMs and 3D NANDs.

[0440] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0441] Embodiment 4 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 39A to 40E.

[0442] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0443] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0444] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0445] [Electronic Component] FIG. 39A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 39A has a semiconductor device 981 inside a mold 984. FIG. 39A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are connected to electrode pads 986, and the electrode pads 986 are connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and connected on the printed circuit board 988 to complete the mounting substrate 989.

[0446] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the interface between the processor and the memory to be driven at high speed.

[0447] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0448] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0449] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0450] 39B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0451] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0452] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0453] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0454] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0455] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0456] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0457] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0458] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 39B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0459] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0460] 40A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 40A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0461] The computer 5620 can have the configuration shown in the perspective view in Fig. 40B, for example. In Fig. 40B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0462] PC card 5621 shown in Figure 40C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 40C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.

[0463] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0464] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0465] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0466] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0467] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0468] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0469] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0470] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0471] Fig. 40D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 40D illustrates a planet 6804 in space.

[0472] 40D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0473] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0474] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0475] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0476] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0477] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0478] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0479] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0480] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires the construction of a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0481] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0482] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0483] Fig. 40E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 40E has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0484] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0485] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0486] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0487] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0488] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0489] 10: memory string, 10A: memory string, 10B: memory string, 11: structure, 11A: structure, 11B: structure, 13: layer, 20A: semiconductor device, 20B: semiconductor device, 20C: semiconductor device, 20D: semiconductor device, 25: memory string, 100: capacitor, 101: conductive layer, 102: insulating layer, 102_1: insulating layer, 102_2: insulating layer, 102_m: insulating layer, 103: conductive layer, 103_1: conductive layer, 103_2: conductive layer, 103_n: conductive layer, 104: conductive layer, 105: insulating layer, 106: conductive layer, 107: insulating layer, 108: conductive layer, 1 10: conductive layer, 111: insulating layer, 112: semiconductor layer, 113: insulating layer, 114: insulating layer, 114_1: insulating layer, 114_2: insulating layer, 114_n: insulating layer, 115: insulating layer, 115_1: insulating layer, 115_n: insulating layer, 117: conductive layer, 121: insulating layer, 130: insulating layer, 150: memory cell, 151: central axis, 180: insulating layer, 190: opening, 200: transistor, 210: insulating layer, 220: conductive layer, 220_1: conductive layer, 220_11: conductive layer, 220_12: conductive layer, 220_2: conductive layer, 227: oxide layer, 228: layer, 230: semiconductor layer, 2 30_1: semiconductor layer, 230_2: semiconductor layer, 240: conductive layer, 240a: conductive layer, 240b: conductive layer, 244: conductive layer, 244a: conductive layer, 244b: conductive layer, 245: conductive layer, 250: insulating layer, 251: characteristics, 252: characteristics, 260: conductive layer, 260_1: conductive layer, 260_2: conductive layer, 270: opening, 270a: opening, 270b: opening, 280: insulating layer, 280_1: insulating layer, 280_2: insulating layer, 280_3: insulating layer, 283: insulating layer, 285: insulating layer, 290: groove, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: Control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 960: arithmetic unit, 961: substrate, 962: ALU, 962c: ALU controller,963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device, 1203: insulating layer, 1700: substrate, 1701: element isolation layer, 1712: conductive layer, 1730: conductive layer, 1790: gate electrode, 1792: well, 1793: channel formation region, 1794: low concentration impurity region, 1796: conductive region, 1797: gate insulating film, 1798: insulating layer, 1799: insulating layer, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor Conductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

a substrate, a structure on the substrate, and a conductive layer; the structure includes a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer; The structure extends in a first direction; the conductive layer extends in a second direction; the first direction is perpendicular or substantially perpendicular to the top surface of the substrate; the second direction intersects the first direction perpendicularly or substantially perpendicularly, the first insulating layer is adjacent to the semiconductor layer; the second insulating layer is adjacent to the first insulating layer; the third insulating layer is adjacent to the second insulating layer; the semiconductor layer, the first insulating layer, the second insulating layer, and the third insulating layer are concentrically arranged when viewed from the first direction at an intersection where the structure and the conductive layer intersect; the conductive layer is adjacent to the third insulating layer at the intersection; the first insulating layer is thicker than the third insulating layer; The semiconductor device, wherein the semiconductor layer comprises indium oxide. 　 In claim 1, the first insulating layer functions as a blocking layer; the second insulating layer functions as a charge storage layer; The third insulating layer functions as a tunnel layer. 　 a substrate; a structure on the substrate; a first conductive layer; an interlayer insulating film; a capacitor; a transistor; a first insulating layer; a second insulating layer; and a second conductive layer; the structure includes a first semiconductor layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer; the capacitor has a sixth insulating layer, a third conductive layer, and a fourth conductive layer; the transistor includes a seventh insulating layer, a second semiconductor layer, the fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer; The structure extends in a first direction; the first conductive layer extends in a second direction; the first direction is perpendicular or substantially perpendicular to the top surface of the substrate; the second direction intersects the first direction perpendicularly or substantially perpendicularly, the third insulating layer is adjacent to the first semiconductor layer; the fourth insulating layer is adjacent to the third insulating layer; the fifth insulating layer is adjacent to the fourth insulating layer; the first semiconductor layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are concentrically arranged when viewed from the first direction at an intersection where the structure and the first conductive layer intersect; the first conductive layer is adjacent to the fifth insulating layer at the intersection; the third insulating layer is thicker than the fifth insulating layer; the interlayer insulating film is located on the structure and on the first conductive layer; the third conductive layer is located on the interlayer insulating film, the sixth insulating layer is located on the third conductive layer; the fourth conductive layer is located on the sixth insulating layer; the first insulating layer is located on the fourth conductive layer; the fifth conductive layer and the sixth conductive layer are located on the first insulating layer; the first insulating layer has a groove portion having a region overlapping the fourth conductive layer and a region overlapping a region between the fifth conductive layer and the sixth conductive layer; the second semiconductor layer has a region located within the groove; the second semiconductor layer has a region in contact with the fourth conductive layer, a region in contact with the fifth conductive layer, and a region in contact with the sixth conductive layer; the seventh insulating layer is provided on the second semiconductor layer so as to have a region located within the groove; the seventh conductive layer has a region facing the second semiconductor layer in the groove with the seventh insulating layer therebetween, the second insulating layer is located on the fifth to seventh conductive layers; the second conductive layer is located on the second insulating layer; the second conductive layer is electrically connected to the fifth conductive layer and the sixth conductive layer; the groove and the seventh conductive layer extend in a third direction in plan view, the third direction intersects the first direction perpendicularly or substantially perpendicularly, the second conductive layer extends in a fourth direction in a plan view, the fourth direction intersects the third direction perpendicularly or substantially perpendicularly, The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer contain indium oxide. 　 In claim 3, an eighth conductive layer and a ninth conductive layer; the second insulating layer has a first opening overlapping the fifth conductive layer and a second opening overlapping the sixth conductive layer; the eighth conductive layer has a region located within the first opening; the ninth conductive layer has a region located within the second opening; the eighth conductive layer has a region in contact with the second conductive layer and a region in contact with the fifth conductive layer, The ninth conductive layer has a region in contact with the second conductive layer and a region in contact with the sixth conductive layer. 　 In claim 3, an eighth insulating layer; the eighth insulating layer is located between the interlayer insulating film and the first insulating layer, the eighth insulating layer has an opening; The third conductive layer, the sixth insulating layer, and the fourth conductive layer have regions located within the opening. 　 In any one of claims 3 to 5, the third insulating layer functions as a blocking layer; the fourth insulating layer functions as a charge storage layer; The fifth insulating layer functions as a tunnel layer.

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