Three-dimensional flash memory using SSP scheme and operating method thereof

Abstract

In order to enable a memory operation in a structure in which vertical channel structures connected to a common bit line share string selection lines, while improving memory integration density and reducing the complexity of a manufacturing process, a three-dimensional flash memory and an operating method thereof are disclosed, wherein the flash memory uses a scheme (string selection line (SSL) separation pattern (SSP) scheme) in which a threshold voltage of each of string selection transistors corresponding to the string selection lines provided in multiple layers is differently configured.

Description

Three-dimensional flash memory using SSP schema and its operating method

[0001] The following examples describe a three-dimensional flash memory and its operating method using the SSP (SSL (String selection line) Separation Pattern) scheme.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is required to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a memory cell string has been proposed.

[0004] In such a three-dimensional flash memory, in order to select a vertical channel structure including a target memory cell to be the target of a memory operation among vertical channel structures connected to a common bit line during a memory operation, string selection lines (SSL) must be divided to correspond to each of the vertical channel structures connected to the common bit line.

[0005] Accordingly, existing 3D flash memory has the disadvantage of low memory integration and increased complexity of the manufacturing process due to the addition of a string selection line division process.

[0006] Therefore, the embodiments below propose a technology to solve the shortcomings of existing three-dimensional flash memory.

[0007]

[0008] One embodiment proposes a three-dimensional flash memory and its operating method in which a string selection line splitting process is omitted and vertical channel structures connected to a common bit line share a string selection line, in order to improve memory integration and reduce the complexity of the manufacturing process.

[0009] At this time, one embodiment proposes a three-dimensional flash memory and its operating method using a method (SSP (SSL (String selection line) Separation Pattern) scheme) of differently setting the threshold voltage of each of the string selection transistors corresponding to the string selection lines provided in multiple layers to enable memory operation in a structure in which vertical channel structures connected to a common bit line share a string selection line.

[0010] In particular, one embodiment proposes a three-dimensional flash memory and a method of operating the same, in which the threshold voltage of each of the string select transistors is electrically set differently by programming each of the string select transistors with a different voltage without changing the physical characteristics of the string select transistors.

[0011] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0012] According to one embodiment, a three-dimensional flash memory may include word lines and string selection lines that are formed to extend horizontally and are sequentially stacked while being spaced apart from each other in the vertical direction; vertical channel structures that are formed to extend vertically through the word lines and the string selection lines, each of the vertical channel structures including a vertical channel pattern that extends vertically and a data storage pattern that is formed in contact with an outer wall of the vertical channel pattern, the data storage pattern and the vertical channel pattern forming memory cells corresponding to the word lines and string selection transistors corresponding to the string selection lines, wherein at least one string selection transistor of each of the vertical channel structures has a different threshold voltage.

[0013] According to one aspect, each of the vertical channel structures may include one string selection transistor having a minimum threshold voltage, and the string selection transistor having the minimum threshold voltage of each of the vertical channel structures may be connected to different string selection lines among the string selection lines.

[0014] According to another aspect, the three-dimensional flash memory may be characterized in that it includes bit lines formed to extend in one of the horizontal directions while being connected to upper portions of the vertical channel structures, and source lines formed to extend in a direction orthogonal to the one of the horizontal directions while being connected to lower portions of the vertical channel structures so as to allow the at least one string selection transistor to have different threshold voltages.

[0015] According to another aspect, the three-dimensional flash memory may further include a dummy string selection line extending in the horizontal direction above the string selection lines so as to allow the at least one string selection transistor to have a different threshold voltage.

[0016] According to another aspect, the at least one string select transistor may be characterized by having different threshold voltages by being programmed using the bit lines, the source lines, the dummy string select line, and the string select lines.

[0017] According to another aspect, the source lines may be characterized in that they are used to select any one of the vertical channel structures including at least one string select transistor whose threshold voltage is to be programmed among the vertical channel structures.

[0018] According to another aspect, the dummy string selection line may be characterized in that it is used to generate GIDL (Gate Induced Drain Leakage) by voltages applied to the bit lines and voltages applied to the string selection lines.

[0019] According to one embodiment, a memory device comprises: word lines and string select lines that extend horizontally and are sequentially stacked while being spaced apart from each other in the vertical direction; vertical channel structures that extend vertically through the word lines and the string select lines, each of the vertical channel structures including a vertical channel pattern that extends vertically and a data storage pattern that is formed in contact with an outer wall of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines and string select transistors corresponding to the string select lines; bit lines that extend in one direction of the horizontal direction while being connected to upper portions of the vertical channel structures; source lines that extend in a direction orthogonal to the one direction of the horizontal direction while being connected to lower portions of the vertical channel structures so that at least one string select transistor has a different threshold voltage; And a memory operation method of a three-dimensional flash memory including a dummy string selection line formed to extend in the horizontal direction from above the string selection lines may include a step of selecting one of the vertical channel structures including a target memory cell to be the target of the memory operation based on a characteristic that at least one of the string selection transistors of each of the vertical channel structures has a different threshold voltage.

[0020] According to one aspect, the selecting step may be characterized in that the step of selecting one of the vertical channel structures includes one string selection transistor having a minimum threshold voltage, and the string selection transistor having the minimum threshold voltage of each of the vertical channel structures is connected to different string selection lines among the string selection lines, based on a characteristic.

[0021] According to another aspect, the memory operation method of the three-dimensional flash memory may further include, prior to the selecting step, a step of programming the at least one string selection transistor to have a different threshold voltage using the bit lines, the source lines, the dummy string selection line, and the string selection lines.

[0022] According to another aspect, the programming step may be characterized by including a step of selecting, using the source lines, one of the vertical channel structures including at least one string select transistor for which a threshold voltage is to be programmed.

[0023] According to another aspect, the programming step may be characterized by including a step of generating GIDL (Gate Induced Drain Leakage) by voltages applied to the bit lines and voltages applied to the string selection lines using the dummy string selection line.

[0024] According to one embodiment, a memory device comprises: word lines and string select lines that extend horizontally and are sequentially stacked while being spaced apart from each other in the vertical direction; vertical channel structures that extend vertically through the word lines and the string select lines, each of the vertical channel structures including a vertical channel pattern that extends vertically and a data storage pattern that is formed in contact with an outer wall of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines and string select transistors corresponding to the string select lines; bit lines that extend in one direction of the horizontal direction while being connected to upper portions of the vertical channel structures; source lines that extend in a direction orthogonal to the one direction of the horizontal direction while being connected to lower portions of the vertical channel structures so that at least one string select transistor has a different threshold voltage; And a threshold voltage setting method for programming a threshold voltage of each of the string selection transistors in a three-dimensional flash memory including a dummy string selection line formed to extend in the horizontal direction from above the string selection lines may include a step of programming at least one of the string selection transistors of each of the vertical channel structures to have a different threshold voltage using the bit lines, the source lines, the dummy string selection line, and the string selection lines.

[0025] According to one aspect, a method for setting a threshold voltage, characterized in that the programming step comprises selecting, using the bit lines and the source lines, one of the vertical channel structures including at least one string select transistor for which a threshold voltage is to be programmed.

[0026] According to another aspect, the programming step may be characterized by including a step of generating GIDL (Gate Induced Drain Leakage) by voltages applied to the bit lines and voltages applied to the string selection lines using the dummy string selection line.

[0027] One embodiment proposes a three-dimensional flash memory and its operating method in which vertical channel structures connected to a common bit line share a string selection line by omitting a string selection line splitting process, thereby achieving a technical effect of improving memory integration and reducing the complexity of a manufacturing process.

[0028] At this time, one embodiment proposes a three-dimensional flash memory and an operating method thereof that utilizes a method (SSP (SSL (String selection line) Separation Pattern) scheme) of differently setting the threshold voltage of each of the string selection transistors corresponding to the string selection lines provided in multiple layers, thereby achieving a technical effect that enables memory operation in a structure in which vertical channel structures connected to a common bit line share the string selection line.

[0029] In particular, one embodiment can propose a three-dimensional flash memory and its operating method that electrically sets the threshold voltage of each of the string select transistors differently by programming each of the string select transistors with a different voltage without changing the physical characteristics of the string select transistors.

[0030] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0031] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0032] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0033] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0034] FIGS. 4A to 4D are simplified circuit diagrams illustrating a three-dimensional flash memory to explain the application of the SSP scheme to the three-dimensional flash memory according to one embodiment.

[0035] FIG. 5 is a flow chart illustrating a threshold voltage setting method for programming the threshold voltage of each string selection transistor in a three-dimensional flash memory according to one embodiment.

[0036] FIG. 6 is a flow chart illustrating a memory operation method of a three-dimensional flash memory according to one embodiment.

[0037] FIG. 7 is a simplified circuit diagram illustrating a three-dimensional flash memory to explain how a memory operation is performed based on an SSP schema in a memory operation method of a three-dimensional flash memory according to one embodiment.

[0038] FIG. 8 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0040] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0041] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0042] Hereinafter, with reference to the drawings, a three-dimensional flash memory having a structure in which string select lines are provided in multiple layers and the threshold voltages of each of the string select transistors corresponding to the string select lines are set differently to enable memory operation in a structure in which vertical channel structures connected to a common bit line share a string select line, and an operating method thereof will be described in detail.

[0043]

[0044] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0045] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a plurality of bit lines (BL0, BL1, BL2), a plurality of source lines (SL0, SL1, SL2), and a plurality of cell strings (CSTR) arranged between the bit lines (BL0, BL1, BL2) and the source lines (SL0, SL1, SL2).

[0046] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0047] The source lines (SL0, SL1, SL2) can be arranged two-dimensionally while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). That is, the source lines (SL0, SL1, SL2) can be arranged in a direction orthogonal to the bit lines (BL0, BL1, BL2) on a horizontal plane.

[0048] Between the bit lines (BL0, BL1, BL2) and the source lines (SL0, SL1, SL2), a dummy string select line (SSL-D), string select lines (SSL1, SSL2), a plurality of word lines (WL0-WLn), and a ground select line (GSL) may be formed to extend along the first direction (D1). Hereinafter, the number of string select lines (SSL1, SSL2) is described as two, but is not limited thereto and may be three or more.

[0049] The structure in which the source lines (SL0, SL1, SL2) are formed orthogonally to the bit lines (BL0, BL1, BL2) is for selecting one of the vertical channel structures (VS) (corresponding to the memory cell string (CSTR) in FIG. 1) that share a common bit line in the SSP (SSL Separation Pattern) scheme described below, including a string select transistor (SST1, SST2) whose threshold voltage is to be programmed.

[0050] Here, the dummy string select line (SSL-D), string select lines (SSL1, SSL2), multiple word lines (WL0-WLn) and ground select line (GSL) can be configured to be shared by cell strings (CSTR) per bit line.

[0051] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2) and may be connected in parallel to each of the source lines (SL0, SL1, SL2). That is, cell strings (CSTR) may be provided between each of the bit lines (BL0, BL1, BL2) and each of the source lines (SL0, SL1, SL2).

[0052] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while extending in the third direction (D3) and may be arranged to be spaced apart from each other along the first direction (D1) for each source line.

[0053] According to an embodiment, each of the cell strings (CSTR) may be configured with a dummy string select transistor (SST-D) connected to bit lines (BL0, BL1, BL2) and connected in series, a ground select transistor (GST) connected to source lines (SL0, SL1, SL2) and connected in series, and first and second string select transistors (SST1, SST2) and memory cell transistors (MCT) disposed between the dummy string select transistor (SST-D) and the ground select transistor (GST). In addition, each of the memory cell transistors (MCT) may include a data storage element. However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include three or more string select transistors. In this case, three or more string select lines may be included between the bit lines (BL0, BL1, BL2) and the source lines (SL0, SL1, SL2) to correspond to three or more string select transistors.

[0054] As another example, the ground select transistor (GST) in each cell string (CSTR) may be composed of a plurality of series-connected MOS transistors, similar to the first and second string select transistors (SST1, SST2).

[0055] Additionally, an erase control line (ECL; not shown) may be arranged between bit lines (BL0, BL1, BL2) and source lines (SL0, SL1, SL2) according to an implementation example, and each of the cell strings (CSTR) may include an erase control transistor (ECT; not shown) connected to the erase control line (ECL).

[0056] Additionally, a dummy word line (DWL; not shown) may be placed between the bit lines (BL0, BL1, BL2) and the source lines (SL0, SL1, SL2) according to an implementation example, and each of the cell strings (CSTR) may further include dummy cell transistors (DMC; not shown) connected to the dummy word line (DWL).

[0057] A single cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) that are spaced at different distances from each of the source lines (SL0, SL1, SL2). That is, the memory cell transistors (MCT) may be connected in series along the third direction (D3) between the first string select transistor (SST1) and the ground select transistor (GST).

[0058] According to an embodiment, a first string select transistor (SST1) may be controlled by a first string select line (SSL1), and a second string select transistor (SST2) may be controlled by a second string select line (SSL2). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), respectively, and a dummy string select transistor (SST-D) may be controlled by a dummy string select line (SSL-D). A ground select transistor (GST) may be controlled by a ground select line (GSL), and source lines (SL0, SL1, SL2) may be connected to a source of the ground select transistor (GST).

[0059] The gate electrodes of the memory cell transistors (MCT) provided at substantially the same distance from the source lines (SL0, SL1, SL2) may be commonly connected to one of the word lines (WL0-WLn, DWL) to be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the source lines (SL0, SL1, SL2), the gate electrodes provided in different rows or columns may be independently controlled.

[0060] A dummy string select transistor (SST-D) may generate gate-induced drain leakage (GIDL) during memory operation. In some embodiments, a GIDL voltage may be applied to bit lines (BL0, BL1, BL2) and / or source lines (SL0, SL1, SL2) during memory operation of a memory cell array, and a gate-induced drain leakage current may be generated in the dummy string select transistor (SST-D).

[0061] That is, the dummy string select line (SSL-D) controlling the dummy string select transistor (SST-D) is provided to generate a GIDL for programming a threshold voltage in a specific string select transistor included in a specific cell string among cell strings (CSTR) sharing a common bit line in the SSP (SSL Separation Pattern) scheme described below.

[0062]

[0063] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment, and FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, which corresponds to a cross-section taken along line A-A' of FIG. 2.

[0064] Referring to the drawings, the laminated structure (ST) can be formed to extend in the first direction (D1) and the second direction (D2). In the drawings, the laminated structure (ST) is illustrated as one, but is not limited thereto, and a plurality of laminated structures (ST) may be provided and arranged two-dimensionally while being spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0065] The stacked structure (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)). The stacked structure (ST) may have a substantially flat upper surface. Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0066] Although omitted in the drawing, the stacked structure (ST) may exist in a state of being arranged on the substrate (SUB) before the formation of the source lines (SL0, SL1, SL2). That is, the stacked structure (ST) may be manufactured by alternately stacking gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) may be removed during the formation of the source lines (SL0, SL1, SL2), so that the substrate (SUB) may not be included as a result.

[0067] The substrate (SUB) used in the manufacturing process of the stacked structure (ST) may be a semiconductor substrate such as a substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0068] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of a ground selection line (GSL), word lines (WL0-WLn, DWL), first string selection lines (SSL1), second string selection lines (SSL2), and dummy string selection line (SSL-D) sequentially stacked in a direction from bottom to top.

[0069] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0070] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to the ground selection line (GSL) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to the first string selection lines (SSL1), the second string selection lines (SSL2), and the dummy string selection line (SSL-D) of FIG. 1.

[0071] Although not shown, the end of the stacked structure (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structure (ST) may have a length in the first direction (D1) that decreases from the bottom toward the top. The third gate electrode (EL3) may have the shortest length in the first direction (D1) and may have the longest distance from the bottom along the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and may have the shortest distance from the bottom along the third direction (D3). By means of the step structure, the thickness of the stacked structure (ST) can decrease as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0072] However, without being limited or restricted thereto, the end of the laminated structure (ST) may have a step structure along the second direction (D2).

[0073] Each of the interlayer insulating layers (ILDs) may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than the other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating layers (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0074] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) may be stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0075] A plurality of channel holes (CH) penetrating a portion of a stacked structure (ST) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be formed to extend in a third direction (D3) while being connected to bit lines (BL0, BL1, BL2) and source lines (SL0, SL1, SL2) as a plurality of cell strings (CSTR) as illustrated in FIG. 1. The vertical channel structures (VS) may be connected to the source lines (SL0, SL1, SL2) by having a lower surface of each of a portion of the vertical channel structures (VS) come into contact with an upper surface of the source lines (SL0, SL1, SL2).

[0076] The rows of vertical channel structures (VS) penetrating the stacked structure (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as illustrated in FIG. 2, 27 vertical channel structures (VS) may penetrate the stacked structure (ST) forming 18 columns and 3 rows. However, the number of vertical channel structures (VS) forming the array is not limited or restricted thereto.

[0077] As vertical channel structures (VS) are formed in a plate shape, the array is formed in a horizontal plane of multiple rows and columns of gate electrodes (EL1, EL2, EL3), so that the three-dimensional flash memory can have a structure in which the integration of memory cell strings is improved.

[0078] In particular, since the string selection lines (SSL1, SSL2) among the third gate electrodes (EL3) are configured in a plate shape without the need to be divided in correspondence with the vertical channel structures (VS) that share the bit line (BL), the memory directivity can be improved.

[0079] At this time, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in different rows on a horizontal plane and shifted so as to be misaligned with each other. For example, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in a zigzag shape along a first direction (D1) and a second direction (D2). Accordingly, the integration of the memory cell string can be further improved compared to the case where the vertical channel structures (VS) included in a pair of adjacent columns are arranged side by side in the same row on a horizontal plane.

[0080] Each of the vertical channel structures (VS) may be formed to extend from the bottom to the top in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases or decreases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0081] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical filled pattern (VFP), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open bottom, the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom, and the vertical filled pattern (VFP) may have a shape that fills an inner space of the vertical channel pattern (VCP). However, without being limited thereto, the vertical channel pattern (VCP) may also have a pipe shape or a macaroni shape with an open bottom.

[0082] The data storage pattern (DSP) can cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the vertical channel pattern (VCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. Accordingly, the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) can form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2) together with the regions corresponding to the second gate electrodes (EL2) of the vertical channel pattern (VCP). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0083] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by a voltage applied through the second gate electrodes (EL2), or by maintaining the state of electrons (e.g., the polarization state of charges). For example, an ONO (tunnel oxide-nitride-blocking oxide) layer or a ferroelectric layer can be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent a binary data value or a multi-valued data value by a change in the trapped charge or hole, or can represent a binary data value or a multi-valued data value by a change in the state of charges.

[0084] Although the above data storage pattern (DSP) is described as being vertically connected and extended, it is not limited to this and may be segmented into multiple pieces and formed only in the portion corresponding to the second gate electrodes (EL), thereby forming memory cells together with the regions corresponding to the second gate electrodes (EL2) among the vertical channel pattern (VCP).

[0085] In addition, the regions corresponding to the string selection lines (SSL1, SSL2) of the third gate electrodes (EL3) among the data storage pattern (DSP) can form string selection transistors (SST1, SST2) illustrated in FIG. 1 together with the regions corresponding to the string selection lines (SSL1, SSL2) of the third gate electrodes (EL3) among the vertical channel pattern (VCP), and the regions corresponding to the dummy string selection line (SSL-D) of the third gate electrodes (EL3) among the data storage pattern (DSP) can form the dummy string selection transistor (SST-D) illustrated in FIG. 1 together with the regions corresponding to the dummy string selection line (SSL-D) of the third gate electrodes (EL3) among the vertical channel pattern (VCP).

[0086] A vertical channel pattern (VCP) is a component that supplies electrons or holes to transfer charges to a data storage pattern (DSP). The vertical channel pattern (VCP) may be formed to extend in a vertical direction (e.g., a third direction (D3)) while covering an inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage. More specifically, the vertical channel pattern (VCP) may perform a memory operation in response to a voltage applied by a bit line (BL), a common source (CS), a back gate (BG), and gate electrodes (EL1, EL2, EL3). For this purpose, the vertical channel pattern (VCP) may be formed of, for example, single-crystalline silicon or polycrystalline silicon.

[0087] The upper surface of the vertical channel pattern (VCP) may be positioned at a higher level than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the vertical channel pattern (VCP) may be positioned between the upper surface and the lower surface of the third gate electrode (EL3). The lower surface of the vertical channel pattern (VCP) may be coplanar with the lower surface of the lowermost one of the interlayer insulating layers (ILD).

[0088] A vertically filled pattern (VFP) may be surrounded by a vertical channel pattern (VCP). The upper surface of the vertically filled pattern (VFP) may be in contact with a capping layer (CAP), and the lower surface of the vertically filled pattern (VFP) may be positioned at a higher level than the lower surface of the vertical channel pattern (VCP). In other words, the vertically filled pattern (VFP) may be electrically floated with respect to the source lines (SL0, SL1, SL2).

[0089] Although a structure in which a vertically buried pattern (VFP) is positioned within a vertically buried pattern (VCP) has been described, the 3D flash memory is not limited thereto and may have a structure including a back gate (BG; not shown) instead of the vertically buried pattern (VFP). In this case, the back gate (BG) may be formed to be in contact with the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP) and to apply a voltage for a memory operation to the vertical channel pattern (VCP). For this purpose, the back gate (BG) may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials. In addition, in this case, an insulating film (INS; not shown) is disposed between the back gate (BG) and the vertical channel pattern (VCP), thereby preventing the back gate (BG) from directly contacting the vertical channel pattern (VCP). The insulating film (INS), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide. However, the insulating film (INS) may be omitted depending on the implementation example.

[0090] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to channels of a dummy string select transistor (SST-D), string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0091] A capping layer (CAP) may be provided on an upper surface of a vertical channel pattern (VCP). The capping layer (CAP) may be connected to an upper portion of the vertical channel pattern (VCP). A side wall of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). An upper surface of the capping layer (CAP) may be substantially coplanar with an upper surface of a stacked structure (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILD). A lower surface of the capping layer (CAP) may be located at a level lower than an upper surface of a third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap the third gate electrode (EL3) in a horizontal direction.

[0092] The capping layer (CAP) may be formed of a material having a lower contact resistance than the contact resistance that the vertical channel pattern (VCP) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP) may reduce the contact resistance between the bit lines (BL0, BL1, BL2) described below and the vertical channel pattern (VCP).

[0093] A capping insulating film (CAP-INS) may be provided on the stacked structure (ST) and the vertical channel structures (VS). The capping insulating film (CAP-INS) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD) and an upper surface of the capping layer (CAP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0094] Bit lines (BL0, BL1, BL2) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit lines (BL0, BL1, BL2) may be formed to extend along a second direction (D2) using a conductive material. The conductive material forming the bit lines (BL0, BL1, BL2) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0095] The bit lines (BL0, BL1, BL2) may be electrically connected to the upper portions of the vertical channel structures (VS) through bit line contact plugs (BLPG). Here, the connection of the bit lines (BL0, BL1, BL2) to the upper portions of the vertical channel structures (VS) may mean that they are connected to the upper portions of the vertical channel patterns (VCP) included in the vertical channel structures (VS).

[0096] The source lines (SL0, SL1, SL2) may be formed by extending along the first direction (D1) using a conductive material. The conductive material forming the source lines (SL0, SL1, SL2) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0097] The source lines (SL0, SL1, SL2) may be electrically connected to the lower portions of the vertical channel structures (VS). Here, the source lines (SL0, SL1, SL2) being connected to the lower portions of the vertical channel structures (VS) may mean that they are in contact with and connected to the lower portions of the vertical channel patterns (VCP) included in the vertical channel structures (VS).

[0098] At this time, the source lines (SL0, SL1, SL2) are formed to extend in a direction (e.g., the first direction (D1)) orthogonal to the direction in which the bit lines (BL0, BL1, BL2) extend (e.g., the second direction (D2)) on the horizontal plane, so that they can be independently connected to the vertical channel structures (VS) for each bit line.

[0099] The structure in which the source lines (SL0, SL1, SL2) are formed orthogonally to the bit lines (BL0, BL1, BL2) is for selecting one of the vertical channel structures (VS) that share a common bit line in the SSP (SSL Separation Pattern) scheme described below, which includes a string selection transistor for which a threshold voltage is to be programmed.

[0100] Additionally, the source lines (SL0, SL1, SL2) may be implemented in a form provided inside a substrate insulating film (SUB-INS; not shown). That is, the substrate insulating film (SUB-INS) formed of an insulating material may be provided in a form surrounding the source lines (SL0, SL1, SL2).

[0101]

[0102] FIGS. 4A to 4D are simplified circuit diagrams illustrating a three-dimensional flash memory to explain that an SSP scheme is applied to the three-dimensional flash memory according to one embodiment, FIG. 5 is a flow chart illustrating a threshold voltage setting method for programming the threshold voltage of each string selection transistor in the three-dimensional flash memory according to one embodiment, FIG. 6 is a flow chart illustrating a memory operation method of the three-dimensional flash memory according to one embodiment, and FIG. 7 is a simplified circuit diagram illustrating a three-dimensional flash memory to explain that a memory operation is performed based on an SSP scheme in the memory operation method of the three-dimensional flash memory according to one embodiment.

[0103] Referring to FIG. 4a, an SSP scheme according to one embodiment means a state in which the threshold voltages of the string select transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) corresponding to the string select lines (SSL1, SSL2, SSL3) provided in multiple layers are set differently to enable memory operation in a structure in which vertical channel structures (VS1, VS2, VS3) connected to a common bit line (e.g., BL0) share the string select lines (SSL1, SSL2, SSL3) by omitting the string select line (SSL) splitting process.

[0104] In more detail, at least one string selection transistor (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) of each of the vertical channel structures (VS1, VS2, VS3) is selected from among the string selection transistors (SST1-1, SST2-2, SST3-3) of each of the vertical channel structures (VS1, VS2, VS3), except for at least one string selection transistor (SST1-1, SST2-2, SST3-3) of the remaining string selection transistors (SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) of each of the vertical channel structures (VS1, VS2, VS3). By setting the threshold voltage to be different from SST2-1, SST2-3, SST3-1, SST3-2), the SSP scheme can be applied.

[0105] That is, each of the vertical channel structures (VS1, VS2, VS3) includes one string select transistor (SST1-1, SST2-2, SST3-3) having a minimum threshold voltage (Vth_min) compared to the threshold voltages (Vth_1, Vth_2) of each of the remaining string select transistors (SST1-2, SST1-3, SST2-1, SST2-3, SST3-1, SST3-2) among the string select transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3), and each of the vertical channel structures (VS1, VS2, VS3) has a string select transistor (SST1-1, SST2-2, SST3-3) having a minimum threshold voltage (Vth_min). The SSP schema can be applied in a state where different string selection lines are connected among the string selection lines (SSL1, SSL2, SSL3).

[0106] For such an SSP scheme to be applied, the three-dimensional flash memory must include source lines (SL0, SL1, SL2) formed in a direction orthogonal to the bit lines (BL0, BL1, BL2) on the horizontal plane to select one of the vertical channel structures (VS1, VS2, VS3) including at least one string select transistor (SST1-1, SST2-2, or SST3-3) whose threshold voltage is to be programmed, and a dummy string select line (SSL-D) must be included above the string select lines (SSL1, SSL2, SSL3) to generate GIDL by voltages (e.g., GIDL voltage) applied to the bit lines (BL0, BL1, BL2) and voltages applied to the string select lines (SSL1, SSL2, SSL3) during the threshold voltage programming process.

[0107] Accordingly, the three-dimensional flash memory, as shown in Fig. 5, which illustrates a threshold voltage setting method, uses bit lines (BL0, BL2, BL3), source lines (SL0, SL1, SL2), a dummy string selection line (SSL-D) and string selection lines (SSL1, SSL2, SSL3) through step (S510), so that at least one string selection transistor (SST1-1, SST2-2, SST3-3) selects the remaining strings except for at least one string selection transistor (SST1-1, SST2-2, SST3-3) among the string selection transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) of each of the vertical channel structures (VS1, VS2, VS3). The SSP scheme can be applied by programming the transistors (SST1-2, SST1-3, SST2-1, SST2-3, SST3-1, SST3-2) to have different threshold voltages.

[0108] For example, a three-dimensional flash memory can program a threshold voltage in at least one string select transistor (SST1-1, SST2-2, SST3-3) among vertical channel structures (VS1, VS2, VS3) by selecting one of the vertical channel structures (VS1, VS2, VS3) using bit lines (BL0, BL1, BL2) and source lines (SL0, SL1, SL2), and then generating a GIDL by voltages applied to the bit lines (BL0, BL1, BL2) and voltages applied to the string select lines (SSL1, SSL2, SSL3) using a dummy string select line (SSL-D).

[0109] In other words, the three-dimensional flash memory can apply the SSP scheme by programming the string select transistors (SST1-1, SST2-2, SST3-3) included in each of the vertical channel structures (VS1, VS2, VS3) connected to different string select lines among the string select lines (SSL1, SSL2, SSL3) using bit lines (BL0, BL2, BL3), source lines (SL0, SL1, SL2), a dummy string select line (SSL-D), and string select lines (SSL1, SSL2, SSL3) to have a minimum threshold voltage.

[0110] An example of programming the threshold voltage of each of the string select transistors (SST1-1, SST2-1, SST3-1) included in the vertical channel structure (VS1) in the SSP scheme will be described. As shown in FIG. 4b, the three-dimensional flash memory applies a ground voltage (GND; for example, 0 V) ​​to a selected bit line (BL0) corresponding to the string select transistor (SST1-1) to be programmed with a minimum threshold voltage (Vth_min), applies a GIDL voltage (for example, 8 V) to each of the unselected bit lines (BL1, BL2), applies a ground voltage (GND; for example, 0 V) ​​to a dummy string select line (SSL-D), and applies a minimum program voltage (Vpgm_min; for example, A ground voltage (GND; for example, 0 V) ​​may be applied to each of the unselected string select lines (SSL2, SSL3), a pass voltage (Vpass; for example, 7 V) may be applied to each of the word lines (WL0-WLn), a ground voltage (GND; for example, 0 V) ​​may be applied to the ground select line (GSL), a ground voltage (GND; for example, 0 V) ​​may be applied to the selected source line (SL0) corresponding to the string select transistor (SST1-1) among the source lines (SL0, SL1, SL2), and a GIDL voltage (for example, 8 V) may be applied to each of the unselected source lines (SL1, SL2). Accordingly, the vertical channel structure (VS1) is selected and GIDL may be generated, so that a minimum threshold voltage (Vth_min) may be programmed to the string select transistor (SST1-1).

[0111] At this time, the value of the threshold voltage at which the string select transistor (SST1-1) is programmed can be determined according to the program voltage value applied to the string select line (SSL1) that controls the string select transistor (SST1-1). For example, as the program voltage value applied to the string select line (SSL1) increases, the value of the threshold voltage at which the string select transistor (SST1-1) is programmed can also increase. Accordingly, when the minimum threshold voltage (Vth_min) is programmed to the string select transistor (SST1-1), the program voltage value applied to the string select line (SSL1) can be determined as the minimum value below that satisfies the programming possible condition.

[0112] Next, the 3D flash memory applies a ground voltage (GND; for example, 0 V) ​​to the selected bit line (BL0) corresponding to the string select transistor (SST2-1) to be programmed with a first threshold voltage (Vth_1; Vth_1>Vth_min), as illustrated in FIG. 4c, applies a GIDL voltage (for example, 8 V) to each of the unselected bit lines (BL1, BL2), applies a ground voltage (GND; for example, 0 V) ​​to the dummy string select line (SSL-D), applies a first program voltage (Vpgm_1; Vpgm_1>Vpgm_min; for example, 15 V) to the selected string select line (SSL2) corresponding to the string select transistor (SST2-1) among the string select lines (SSL1, SSL2, SSL3), and applies a first program voltage (Vpgm_1; Vpgm_1>Vpgm_min; for example, 15 V) to the unselected string select lines (SSL1, SSL3). A ground voltage (GND; for example, 0 V) ​​may be applied to each of the word lines (WL0-WLn), a pass voltage (for example, 7 V) may be applied to each of the word lines (WL0-WLn), a ground voltage (GND; for example, 0 V) ​​may be applied to a ground select line (GSL), a ground voltage (GND; for example, 0 V) ​​may be applied to a selected source line (SL0) corresponding to a string select transistor (SST2-1) among the source lines (SL0, SL1, SL2), and a GIDL voltage (for example, 8 V) may be applied to each of the unselected source lines (SL1, SL2). Accordingly, the vertical channel structure (VS1) is selected and GIDL is generated, so that a first threshold voltage (Vth_1) may be programmed to the string select transistor (SST2-1).

[0113] Next, the 3D flash memory applies a ground voltage (GND; for example, 0 V) ​​to the selected bit line (BL0) corresponding to the string select transistor (SST3-1) to be programmed with a second threshold voltage (Vth_2; Vth_2>Vth_1>Vth_min), as shown in FIG. 4d, applies a GIDL voltage (for example, 8 V) to each of the unselected bit lines (BL1, BL2), applies a ground voltage (GND; for example, 0 V) ​​to the dummy string select line (SSL-D), and applies a second program voltage (Vpgm_2; Vpgm_2>Vpgm_1>Vpgm_min; for example, 17 V) to the selected string select line (SSL3) corresponding to the string select transistor (SST3-1) among the string select lines (SSL1, SSL2, SSL3), and applies a second program voltage (Vpgm_2; Vpgm_2>Vpgm_1>Vpgm_min; for example, 17 V) to the unselected bit lines (BL1, BL2). A ground voltage (GND; for example, 0 V) ​​may be applied to each of the string select lines (SSL1, SSL3), a pass voltage (for example, 7 V) may be applied to each of the word lines (WL0-WLn), a ground voltage (GND; for example, 0 V) ​​may be applied to the ground select line (GSL), a ground voltage (GND; for example, 0 V) ​​may be applied to the selected source line (SL0) corresponding to the string select transistor (SST2-1) among the source lines (SL0, SL1, SL2), and a GIDL voltage (for example, 8 V) may be applied to each of the unselected source lines (SL1, SL2). Accordingly, the vertical channel structure (VS1) is selected and GIDL may be generated, so that a second threshold voltage (Vth_2) may be programmed to the string select transistor (SST3-1).

[0114] Through the same principle and process, the threshold voltages of each of the string select transistors (SST1-2, SST2-2, SST3-2) included in another vertical channel structure (VS2) and the threshold voltages of each of the string select transistors (SST1-3, SST2-3, SST3-3) included in another vertical channel structure (VS3) are programmed (in another vertical channel structure (VS2), the string select transistor (SST2-2) is programmed with the minimum threshold voltage (Vth_min), and in another vertical channel structure (VS3), the string select transistor (SST3-3) is programmed with the minimum threshold voltage (Vth_min)), so that an SSP scheme as illustrated in FIG. 4a can be applied.

[0115] In this way, the 3D flash memory to which the SSP scheme is applied is, as shown in Fig. 6, which illustrates a memory operation method, through step (S610), at least one string selection transistor (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) of each of the vertical channel structures (VS1, VS2, VS3) is selected from among the string selection transistors (SST1-1, SST2-2, SST3-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) of each of the vertical channel structures (VS1, VS2, VS3). Based on the characteristic of having a threshold voltage different from that of the remaining string select transistors (SST1-2, SST1-3, SST2-1, SST2-3, SST3-1, SST3-2) except for SST3-3, any one of the vertical channel structures (VS1, VS2, VS3) including a target memory cell to be the target of the memory operation can be selected.

[0116] Step (S610) is expressed in another way, each of the vertical channel structures (VS1, VS2, VS3) includes one string select transistor (SST1-1, SST2-2, SST3-3) having a minimum threshold voltage compared to the threshold voltage of each of the remaining string select transistors (SST1-2, SST1-3, SST2-1, SST2-3, SST3-1, SST3-2) among the string select transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3), and each of the string select transistors (SST1-1, SST2-2, SST3-3) having a minimum threshold voltage of each of the vertical channel structures (VS1, VS2, VS3) is connected to the string select lines (SSL1, SSL2, SSL3). It may be a step of selecting one vertical channel structure based on the characteristics of the string selection lines that are different from each other.

[0117] At this time, it is self-evident that the SSP scheme described above before step (S610) is applied to select one vertical channel structure including a target memory cell that is the target of the memory operation in step (S610).

[0118] That is, step (S610) can be performed on the premise that step (S510) is performed before step (S610).

[0119] For example, in step (S610), the three-dimensional flash memory can select a vertical channel structure (VS1) in which all of the string selection transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) having their respective threshold voltages set by applying the SSP scheme as illustrated in FIG. 4a are selectively turned on or off according to an applied voltage as illustrated in FIG. 7. Accordingly, the three-dimensional flash memory can perform a memory operation on a target memory cell included in the selected vertical channel structure (VS1).

[0120] Accordingly, the 3D flash memory can perform a memory operation (e.g., a program operation or a read operation) on a target memory cell included in any one of the selected vertical channel structures. Since the voltages applied during the memory operation on the target memory cell included in the selected vertical channel structure (VS1) are the same as those of the prior art, a detailed description thereof will be omitted.

[0121] The three-dimensional flash memory to which the SSP scheme described above is applied is characterized in that the source lines (SL0, SL1, SL2) are independently formed in a direction orthogonal to the bit lines (BL0, BL1, BL2).

[0122] Accordingly, the remaining components except for the source lines (SL0, SL1, SL2) in the 3D flash memory can be manufactured in the same manner as the existing manufacturing method, and the source lines (SL0, SL1, SL2) can be formed based on the Xtacking process performed by flipping the stacked structure (ST). Since the Xtacking process is also a known technology, a detailed description thereof will be omitted.

[0123] In this way, the three-dimensional flash memory according to one embodiment can achieve a technical effect of reducing process complexity and improving memory integration by using an SSP scheme that sets the threshold voltage of each of the string selection transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3) only in an electrical manner without changing the physical characteristics of each of the string selection transistors (SST1-1, SST1-2, SST1-3, SST2-1, SST2-2, SST2-3, SST3-1, SST3-2, SST3-3).

[0124]

[0125] FIG. 8 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0126] Referring to FIG. 8, an electronic system (800) including a three-dimensional flash memory according to embodiments may include a main substrate (801), a controller (802) mounted on the main substrate (801), one or more semiconductor packages (803), and a DRAM (804).

[0127] The semiconductor package (803) and DRAM (804) can be connected to the controller (802) by wiring patterns (805) provided on the main substrate (801).

[0128] The main board (801) may include a connector (806) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (806) may vary depending on the communication interface between the electronic system (800) and the external host.

[0129] The electronic system (800) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (800) may operate by power supplied from an external host, for example, through a connector (806). The electronic system (800) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (802) and a semiconductor package (803).

[0130] The controller (802) can write data to the semiconductor package (803) or read data from the semiconductor package (803), and can improve the operating speed of the electronic system (800).

[0131] The DRAM (804) may be a buffer memory to mitigate the speed difference between the semiconductor package (803), which is a data storage space, and an external host. The DRAM (804) included in the electronic system (800) may also function as a type of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package (803). When the electronic system (800) includes the DRAM (804), the controller (802) may further include a DRAM controller for controlling the DRAM (804) in addition to the NAND controller for controlling the semiconductor package (803).

[0132] The semiconductor package (803) may include first and second semiconductor packages (803a, 803b) spaced apart from each other. The first and second semiconductor packages (803a, 803b) may each be a semiconductor package including a plurality of semiconductor chips (820). Each of the first and second semiconductor packages (803a, 803b) may include a package substrate (810), semiconductor chips (820) on the package substrate (810), adhesive layers (830) disposed on a lower surface of each of the semiconductor chips (820), connection structures (840) electrically connecting the semiconductor chips (820) and the package substrate (810), and a molding layer (850) covering the semiconductor chips (820) and the connection structures (840) on the package substrate (810).

[0133] The package substrate (810) may be a printed circuit board including package upper pads (811). Each of the semiconductor chips (820) may include input / output pads (821). Each of the semiconductor chips (820) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 7. More specifically, each of the semiconductor chips (820) may include a gate stack structure (822) and memory channel structures (823). The memory channel structures (823) may correspond to the vertical channel structures (VS) described above.

[0134] The connection structures (840) may be, for example, bonding wires that electrically connect the input / output pads (821) and the package upper pads (811). Accordingly, in each of the first and second semiconductor packages (803a, 803b), the semiconductor chips (820) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (811) of the package substrate (810). According to embodiments, in each of the first and second semiconductor packages (803a, 803b), the semiconductor chips (820) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (840).

[0135] Unlike the illustration, the controller (802) and the semiconductor chips (820) may be included in one package. The controller (802) and the semiconductor chips (820) may be mounted on a separate interposer substrate different from the main substrate (801), and the controller (802) and the semiconductor chips (820) may be connected to each other by wiring provided on the interposer substrate.

[0136]

[0137] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0138] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Word lines and string selection lines that are formed extending horizontally and are sequentially stacked while being spaced apart from each other in the vertical direction; Vertical channel structures formed to extend in the vertical direction through the word lines and the string selection lines, each of the vertical channel structures including a vertical channel pattern formed to extend in the vertical direction and a data storage pattern formed in contact with an outer wall of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines and string selection transistors corresponding to the string selection lines. Including, At least one string select transistor among the string select transistors of each of the vertical channel structures, A three-dimensional flash memory characterized by having different threshold voltages.

2. In paragraph 1, Each of the above vertical channel structures, Containing one string select transistor having a minimum threshold voltage, A string select transistor having the minimum threshold voltage of each of the above vertical channel structures, A three-dimensional flash memory characterized in that the string selection lines are connected to different string selection lines among the above string selection lines.

3. In paragraph 1, The above three-dimensional flash memory, A three-dimensional flash memory characterized in that it includes bit lines formed to extend in one of the horizontal directions while being connected to the upper portions of the vertical channel structures, and source lines formed to extend in a direction orthogonal to the one of the horizontal directions while being connected to the lower portions of the vertical channel structures so that the at least one string selection transistor has a different threshold voltage.

4. In paragraph 3, The above three-dimensional flash memory, A three-dimensional flash memory characterized in that it further includes a dummy string selection line formed to extend in the horizontal direction above the string selection lines so that at least one string selection transistor has a different threshold voltage.

5. In paragraph 4, At least one string select transistor, A three-dimensional flash memory characterized in that it has different threshold voltages by being programmed using the bit lines, the source lines, the dummy string selection line, and the string selection lines.

6. In paragraph 5, The above source lines are, A three-dimensional flash memory characterized in that it is used to select any one of the vertical channel structures including at least one string select transistor for which a threshold voltage is to be programmed among the vertical channel structures.

7. In paragraph 6, The above dummy string selection line is, A three-dimensional flash memory characterized in that it is used to generate GIDL (Gate Induced Drain Leakage) by voltages applied to the bit lines and voltages applied to the string selection lines.

8. A memory operation method of a three-dimensional flash memory, comprising: word lines and string selection lines that extend horizontally and are sequentially stacked while being spaced apart from each other in the vertical direction; vertical channel structures that extend vertically through the word lines and the string selection lines, each of the vertical channel structures including a vertical channel pattern that extends vertically and a data storage pattern that is formed in contact with an outer wall of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines and string selection transistors corresponding to the string selection lines; bit lines that extend in one direction of the horizontal direction while being connected to upper portions of the vertical channel structures; source lines that extend in a direction orthogonal to one direction of the horizontal direction while being connected to lower portions of the vertical channel structures so that at least one string selection transistor has a different threshold voltage; and a dummy string selection line that extends in the horizontal direction from above the string selection lines, A step of selecting one of the vertical channel structures including a target memory cell to be a target of a memory operation based on a characteristic that at least one of the string selection transistors of each of the vertical channel structures has a different threshold voltage. A memory operation method of a three-dimensional flash memory including .

9. In paragraph 8, The above selection steps are: A memory operation method of a three-dimensional flash memory, characterized in that each of the vertical channel structures includes one string selection transistor having a minimum threshold voltage, and a step of selecting one of the vertical channel structures based on a characteristic that the string selection transistor having the minimum threshold voltage of each of the vertical channel structures is connected to different string selection lines among the string selection lines.

10. In paragraph 8, The above three-dimensional flash memory memory operation method is: Prior to the selecting step, a step of programming the at least one string selection transistor to have a different threshold voltage using the bit lines, the source lines, the dummy string selection line, and the string selection lines. A memory operation method of a three-dimensional flash memory, characterized in that it further includes.

11. In paragraph 10, The above programming steps are: A step of selecting one of the vertical channel structures including at least one string select transistor whose threshold voltage is to be programmed using the source lines among the vertical channel structures. A memory operation method of a three-dimensional flash memory, characterized in that it includes.

12. In paragraph 11, The above programming steps are: A step of generating GIDL (Gate Induced Drain Leakage) by using the dummy string selection line and the voltages applied to the bit lines and the voltages applied to the string selection lines. A memory operation method of a three-dimensional flash memory, characterized in that it includes.

13. Word lines and string select lines that are formed to extend horizontally and are sequentially stacked while being spaced apart from each other in the vertical direction; vertical channel structures that are formed to extend vertically through the word lines and the string select lines, each of the vertical channel structures including a vertical channel pattern that extends vertically and a data storage pattern that is formed in contact with an outer wall of the vertical channel pattern, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines and string select transistors corresponding to the string select lines; bit lines that are formed to extend in one direction of the horizontal direction while being connected to upper portions of the vertical channel structures; source lines that are formed to extend in a direction orthogonal to one direction of the horizontal direction while being connected to lower portions of the vertical channel structures so that at least one string select transistor has a different threshold voltage; And a threshold voltage setting method for programming the threshold voltage of each of the string selection transistors in a three-dimensional flash memory including a dummy string selection line formed to extend in the horizontal direction from the upper portion of the string selection lines, A step of programming at least one string selection transistor among the string selection transistors of each of the vertical channel structures to have a different threshold voltage using the bit lines, the source lines, the dummy string selection line, and the string selection lines. A method for setting a threshold voltage including:

14. In paragraph 13, The above programming steps are: A step of selecting one of the vertical channel structures including at least one string select transistor whose threshold voltage is to be programmed using the bit lines and the source lines. A threshold voltage setting method characterized by including:

15. In paragraph 14, The above programming steps are: A step of generating GIDL (Gate Induced Drain Leakage) by using the dummy string selection line and the voltages applied to the bit lines and the voltages applied to the string selection lines. A threshold voltage setting method characterized by including:

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