Method for isolating vertical conductive lines in high aspect ratio features

Abstract

A method for isolating bitlines of a 3D-DRAM includes depositing a conductive layer on an etch stop layer and in trenches between facing stacks of transistors; depositing a filler material in the trenches; and depositing and patterning a mask layer including a plurality of vertical openings on the etch stop layer and the filler material. The plurality of vertical openings of the mask layer are arranged above corresponding locations of the conductive layer that need to be removed to isolate bitlines of the 3D-DRAM. The method includes etching the filler material in the trenches through the plurality of vertical openings to remove portions of the filler material to expose portions of the conductive layer located between vertical bitline locations.

Description

METHOD FOR ISOLATING VERTICAL CONDUCTIVE LINES IN HIGH ASPECTRATIO FEATURESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 634,285, filed on April 15, 2024. The entire disclosure of the above application is incorporated herein by reference.FIELD

[0002] The present disclosure relates to methods for processing substrates, and more particularly to methods for isolating vertical conductive lines in high aspect ratio features.BACKGROUND

[0003] The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] In 3D-DRAM applications, a conductive layer is deposited in a high aspect ratio trench between facing stacks of transistors. Vertical bitlines are etched / defined (and electrically isolated) in the conductive layer using a hard mask. Due to the high aspect ratio of the trench, isolation is difficult to achieve while maintaining selectivity to materials that may be used for the hard mask and the conductive layer.SUMMARY

[0005] A method for isolating bitlines of a 3D-DRAM includes depositing a conductive layer on an etch stop layer and in trenches between facing stacks of transistors; depositing a filler material in the trenches; and depositing and patterning a mask layer including a plurality of vertical openings on the etch stop layer and the filler material. The plurality of vertical openings of the mask layer are arranged above corresponding locations of the conductive layer that need to be removed to isolate bitlines of the 3D- DRAM. The method includes etching the filler material in the trenches through theplurality of vertical openings to remove portions of the filler material to expose portions of the conductive layer located between vertical bitline locations.

[0006] In other features, the method includes removing the mask layer; and etching the exposed portions of the conductive layer between the vertical bitline locations in the trenches to isolate vertical bitlines in the conductive layer.

[0007] In other features, depositing the conductive layer includes using a conformal deposition process. The method includes planarizing the filler material after filling the trenches with the filler material. The conductive layer comprises at least one of tungsten and molybdenum.

[0008] In other features, the plurality of vertical openings of the mask layer are arranged in an array. The plurality of vertical openings of the mask layer have a rectangular cross section. Depositing the conductive layer includes using a bottom heavy deposition process.

[0009] In other features, each of the facing stacks of transistors comprise greater than or equal to 8 transistors. The trenches have an aspect ratio greater than 200.

[0010] A method for isolating bitlines of a 3D-DRAM includes depositing a conductive layer on an etch stop layer and in trenches between facing stacks of transistors; depositing a liner layer on the conductive layer in the trenches; depositing plugs in the trenches; depositing and patterning a mask layer including a plurality of vertical openings on the etch stop layer and the plugs. The plurality of vertical openings of the mask layer are arranged above corresponding locations of the conductive layer that need to be removed to isolate bitlines of the 3D-DRAM. The method includes etching selected ones of the plugs in the trenches through the plurality of vertical openings to etch at least one of the selected ones of the plugs and portions of the liner layer to expose portions of the conductive layer located between vertical bitline locations.

[0011] In other features, etching at least one of the selected ones of the plugs and the portions of the liner layer includes etching both the selected ones of the plugs and the portions of the liner layer.

[0012] In other features, the method includes removing the mask layer; and etching at least one of the exposed portions of the conductive layer and the portions of the linerlayer between the vertical bitline locations in the trenches to isolate vertical bitlines in the conductive layer.

[0013] In other features, wherein depositing the conductive layer includes using a conformal deposition process. The method includes planarizing the plugs after filling the trenches with the plugs. The conductive layer comprises at least one of tungsten and molybdenum. The plurality of vertical openings of the mask layer are arranged in an array. The plurality of vertical openings of the mask layer have a rectangular cross section.

[0014] In other features, depositing the conductive layer includes using a bottom heavy deposition process.

[0015] In other features, each of the facing stacks of transistors comprise greater than or equal to 8 transistors. The trenches have an aspect ratio greater than 200.

[0016] Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims, and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0018] FIG. 1 is a perspective view of an example of a partially fabricated 3D-DRAM including a conductive layer deposited in a high aspect ratio trench arranged between facing stacks of transistors;

[0019] FIG. 2 is a perspective view of an example of the partially fabricated 3D-DRAM including fill material deposited on the conductive layer and in the trench;

[0020] FIG. 3 is a perspective view of an example of the partially fabricated 3D-DRAM after planarizing the fill material to the conductive layer;

[0021] FIG. 4 is a perspective view of an example of the partially fabricated 3D-DRAM after deposition of multiple layers including a hard mask layer that is patterned;

[0022] FIG. 5 is a perspective view of an example of the partially fabricated 3D-DRAM after etching using the hard mask and isolation of bitlines in the conductive layer;

[0023] FIG. 6 is a perspective view of an example of the partially fabricated 3D-DRAM after etching of the fill material;

[0024] FIGS. 7A and 7B are side cross sections of examples of self-aligned and nonself-aligned bitlines, respectively;

[0025] FIG. 8 is an enlarged view of a vertical bitline in the trench after isolation;

[0026] FIG. 9 is a cutaway perspective view of a partially fabricated 3D-DRAM with mask layer including a plurality of vertical openings before etching of the fill material according to the present disclosure;

[0027] FIGS. 10 and 11 are side cross sections of the partially fabricated 3D-DRAM before etching of the fill material according to the present disclosure;

[0028] FIGS. 12A to 12D are horizontal cross sections at the mask layer, and upper middle, and lower locations of the transistor stacks, respectively, before etching of the fill material according to the present disclosure;

[0029] FIG. 13 is a cutaway perspective view of a partially fabricated 3D-DRAM after etching of the fill material (through the vertical openings in the mask layer) to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0030] FIGS. 14 and 15 are side cross sections of the partially fabricated 3D-DRAM after etching of the fill material to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0031] FIGS. 16A to 16D are horizontal cross sections at the mask layer, and upper middle, and lower locations of the transistor stacks, respectively, after etching of the fill material to expose selected locations of the conductive layer to be removed to isolate the vertical bitlines according to the present disclosure;

[0032] FIGS. 17A to 17C are side cross sections of the partially fabricated 3D-DRAM showing the trench, the conductive layer, a liner layer, and plugs according to the present disclosure;

[0033] FIG. 17D is a cutaway perspective view of a partially fabricated 3D-DRAM after etching of the fill material to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0034] FIGS. 18 and 19 are side cross sections of the partially fabricated 3D-DRAM after etching of the fill material and some of the plugs to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0035] FIGS. 20A to 20D are horizontal cross sections at the mask layer, and upper middle, and lower locations of the transistor stacks, respectively, after etching of the fill material to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0036] FIG. 21 is a side cross section of plug locations and open locations according to the present disclosure;

[0037] FIG. 22 is a cutaway perspective view of a partially fabricated 3D-DRAM after etching of the fill material and some of the plugs to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0038] FIGS. 23 and 24 are side cross sections of the partially fabricated 3D-DRAM after etching of the fill material and some of the plugs to expose selected locations of the conductive layer to be removed according to the present disclosure;

[0039] FIGS. 25A to 25D are horizontal cross sections at the mask layer, and upper middle, and lower locations of the transistor stacks, respectively, after etching of the fill material and some of the plugs to expose selected locations of the conductive layer to be removed according to the present disclosure; and

[0040] FIGS. 26A and 26B are enlarged side cross sections of plug locations and open locations according to the present disclosure.

[0041] In the drawings, reference numbers may be reused to identify similar and / or identical elements.DETAILED DESCRIPTION

[0042] While the present disclosure is described in the context of vertical bitlines of 3D-DRAM, the methods described below can be used to isolate conductive lines in other high aspect ratio applications.

[0043] For 3D-DRAM applications, a conductive layer is deposited in a high aspect ratio trench between facing stacks of transistors. During processing, adjacent vertical bitlines are defined and isolated in the conductive layer. After isolation, the vertical bitlines form “U”-shaped vertical contacts on sidewalls and a bottom surface of thetrench. Due to the high aspect ratio of the features, isolation is difficult to achieve while maintaining selectivity to materials used for a hard mask and the conductive layer.

[0044] The present disclosure relates to alternative methods for isolating bit lines in a conductive layer deposited in high aspect ratio trenches. In some examples, a mask layer including a plurality of vertical openings is deposited and patterned over an etch stop layer and above the trenches that include the conductive layer and are filled with filler material. The filler material is etched through the vertical openings to expose portions of the conductive layer that need to be removed to isolate the vertical bitlines.

[0045] In other examples, a liner layer and plugs are deposited in the trench. Then, the mask layer with the plurality of vertical openings is deposited. Portions of the liner layer and / or plugs are etched through the vertical openings (to expose selected areas of the conductive layer to be removed to isolate the vertical bitlines). Other portions of the liner layer and / or plugs remain in other locations to provide an etch stop to prevent etching of portions of the conductive layer corresponding to the vertical bitlines.

[0046] The methods described herein increase the number of material combinations that can be used while maintaining relative costs (e.g. liner layer vs. solid seamless fill options). The methods described herein help to modulate hard mask thickness and shape to manage plasma species into the high aspect ratio features and to enable better isolation control. The methods described herein help to modulate liner layer profile and thicknesses to open up the isolation window and to reduce hard mask requirements to isolate the liner layer vs. the solid fill material. Overall, isolation feasibility increases with the potential to reduce costs as compared to current the solid void-free fill approach.

[0047] Referring now to FIGS. 1 to 8, a 3D-DRAM 50 is shown and includes a substrate 52. In some examples, the substrate 52 comprises silicon, silicon germanium (SiGe), although other substrate materials can be used. The 3D-DRAM 50 includes transistors 54 arranged in a plurality of stacks. After manufacturing, wordlines and bitlines provide connections to the plurality of transistors 54. In some examples, the transistors 54 include an active area including silicon (Si) surrounded by deep trench isolation (DTI) oxide 53.

[0048] In FIG. 1 , a portion of the 3D-DRAM 50 is shown during processing. The portion of the 3D-DRAM 50 is shown to include a first stack of transistors 54A facing a second stack of transistors 54B (collectively transistors 54) (additional transistor stacksare not shown). In some examples, each stack of transistors includes 8 to 100 or more transistors. In some examples, the transistors 54 include gate all around transistors, although other types of transistors can be used. Metal wordlines 55 forming the gate are surrounded by an oxide layer 56 (e.g., such as atomic layer deposition (ALD) oxide). An insulating layer 57 (such as silicon nitride (SiN)) is arranged between the transistors 54 and other structures. At this stage of the process, a trench 58 having a high aspect ratio is located between the first stack of transistors 54A and the second stack of transistors 54B. In some examples, the aspect ratio in the trench 58 is greater than 100, 150, 200, 250 or higher aspect ratios.

[0049] A conductive layer 62 (that is patterned into individual bitlines in subsequent process steps described below) is deposited on an exposed top surface (e.g., an etch stop layer 60 such as a silicon nitride (SiN) layer), and on sidewalls and a bottom surface in the trench 58. In some examples, the conductive layer 62 includes tungsten / molybdenum (W / Mo), although other metals can be used.

[0050] In FIG. 2, a fill material 66 is deposited on the conductive layer 62 in the trench 58 and on the upper exposed surface of the 3D-DRAM 50. In some examples, the fill material 66 comprises a material that can be easily selectively etched relative to other exposed materials. In some examples, the fill material 66 comprises solid carbon, although other materials can be used. In FIG. 3, chemical mechanical polishing (CMP) or another suitable process is performed to remove the fill material 66 located on the upper exposed surface of the conductive layer 62 and / or to planarize the fill material relative to the upper horizontal surface of the conductive layer 62.

[0051] In FIG. 4, an oxide layer 70, a carbon layer 72, and an oxide layer 74 are deposited on the exposed upper surface. A hard mask (HM) layer 78 is patterned and deposited on the oxide layer 74. The HM layer 78 prevents etching of material located below the HM layer 78. Etching in the trench 58 is performed in other locations not blocked by the pattern of the HM layer 78. The HM process steps shown in FIG. 4 allow etching of the fill material 66 and the conductive layer 62 to isolate a plurality of vertical bitlines 82 that extend vertically adjacent to another in the trench 58 as shown in FIG. 5. In some examples, the adjacent vertical bitlines 82 have a “U”-shaped cross section extending along the opposite sidewalls and the bottom surface in the trench 58. In FIG. 6, the fill material 66 is removed to fully expose the adjacent vertical bitlines 82 and further processing of the 3D-DRAM is performed.

[0052] In FIGS. 7A and 7B, while a self-aligned process is shown in FIGS. 1 -6 and 7A, a conventional (or non-self-aligned process) may be used as shown in FIG. 7B. In FIG. 8, the vertical bitlines 82 are shown relative to the insulating layer 57, the metal wordlines 55, and the oxide layer 56.

[0053] Referring now to FIGS. 9 to 12D, the method according to the present disclosure performs alternate integration steps after CMP in FIG. 3 (instead of the hard mask steps shown in FIG. 4). FIG. 9 is a cutaway perspective view illustrating stacks of the transistors 54, trenches 58 filled with the fill material 66, and a mask layer 110 including a plurality of vertical openings 114. FIG. 10 is a side cross section looking through a longer side of the plurality of vertical openings 114. FIG. 11 is a side cross section looking through a shorter side of the plurality of vertical openings 114. FIGS. 12A to 12D are horizontal slices at increasing depths (e.g., a location in the mask layer, and upper, middle, and lower portions of the stack of transistors).

[0054] While the example in FIGS. 1 to 8 includes 8 transistors (8T), the 3D-DRAM in FIGS. 9 to 12D includes 32T. As can be appreciated, the transistor stacks can include additional or fewer transistors. As can be seen in FIGS. 9 to 12D, the fill material 66 fills the trench 58.

[0055] Rather than using the oxide layer 70, the carbon layer 72, the oxide layer 74, and the HM layer 78 to isolate the vertical bitlines 82 as shown in FIG. 4, the mask layer 110 is deposited on the etch stop layer 60 above the trenches 58. The mask layer 110 is patterned to create a plurality of vertical openings 114 having a predetermined shape. In some examples, the plurality of vertical openings 114 are arranged in an array and the predetermined shape is rectangular. The plurality of vertical openings 114 are arranged in locations vertically above areas of the fill material 66 that need to be removed to isolate the vertical bitlines 82 in the conductive layer 62 in subsequent processing steps.

[0056] Referring now to FIGS. 13 to 16D, after patterning of the plurality of vertical openings 114 in the mask layer 110, an etch process is performed to remove the fill material 66 located below the plurality of vertical openings 114 and to expose the conductive layer 62 in these locations. The exposed conductive layer 62 is etched in a subsequent etch step to isolate the vertical bitlines 82. FIG. 13 is a cutaway perspective view illustrating stacks of the transistors 54, trenches 58, and the mask layer 110 including the plurality of vertical openings 114. Alternating portions of the trenches 58are filled with the fill material 66 or etched through the vertical openings of the mask layer 110. FIG. 14 is a side cross section looking through a longer side of the plurality of vertical openings 114. FIG. 15 is a side cross section looking through a shorter side of the plurality of vertical openings 114. FIGS. 16A to 16D are horizontal slices at increasing depths (e.g., a location in the mask layer, and upper, middle, and lower portions of the stack of transistors).

[0057] The plurality of vertical openings 114 control etching of portions of the fill material 66 to selected areas 124 (alternatively located between other portions of the fill material 66). After etching of the fill material in the selected areas 124, an etch step can be performed on the conductive layer 62 to remove the conductive layer 62 in the selected areas 124 to isolate the bit lines. The fill material 66 protects the conductive layer 62 in areas other than the selected areas 124 during subsequent etching. In some examples, the process returns to FIG. 5 after isolating the vertical bitlines 82 and continues with removal of the fill material 66.

[0058] Referring now to FIGS. 17A to 21 , a liner layer and plugs can be used to isolate the vertical bitlines 82. In FIG. 17A, the conductive layer 62 is deposited in the trench 58. In some examples, the conductive layer 62 is deposited conformally. In other examples, the conductive layer 62 is deposited with a bottom heavy deposition process (e.g., the thickness of the conductive layer 62 increases with depth). The bottom heavy deposition process can be used to intentionally taper a profile of the conductive layer from the bottom of the trench to the top of the trench, which improves the ability to isolate the vertical bitlines. In FIG. 17B, a liner layer 230 is deposited in the trench 58 on the conductive layer 62. In FIG. 17C, plugs 220 are deposited in an upper portion of the trench 58 using a non-conformal deposition process to fill only an uppermost portion of the trench 58 at the top of the stack of transistors.

[0059] In FIG. 17D, the mask layer 110 is deposited and patterned to create the plurality of vertical openings 114. When etching the plurality of vertical openings 114, the etch process also etches some of the plugs 220 (in open locations 244) located below the plurality of vertical openings 114. Some of the plugs 220 remain in plug locations 246 of the trench 58 after etching as can be seen in FIGS. 18, 19 and 20A to 20D.

[0060] In FIGS. 20B and 21 , the plug locations 246 and the open locations 244 are arranged in an alternating pattern with the open locations 244 located below theplurality of vertical openings 114 in the upper cross section of the transistor stack in FIG. 20B. In the middle and lower cross sections of the transistor stacks (located below the plugs 220), the liner layer 230 remains.

[0061] Referring now to FIGS. 17D and 22 to 26B, another method using the plugs 220 is shown. Referring back to FIG. 17D, the mask layer 110 is deposited and patterned to create the plurality of vertical openings 114 in the mask layer 110. In this example, when etching through the plurality of vertical openings 114, the etch process etches some of the plugs 220 and the liner layer 230 located below the plurality of vertical openings 114. Portions of the conductive layer 62 located below the plurality of vertical openings 114 are exposed after etching while some of the liner layer 230 and the plugs 220 remain in other locations as can be seen in FIGS. 22 to 26B.

[0062] In FIGS. 25B, 26A, and 26B, plug locations 272 and open locations 270 are arranged in an alternating pattern with the open locations 270 located below the plurality of vertical openings 114 of the mask layer 110 as can be seen in the upper cross section of the stack of transistors in FIG. 25B. In the middle and lower cross sections located below the plugs 220, the liner layer 230 remains at 274 below the plug locations 272 and is removed in the open locations 270.

[0063] The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and / or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

[0064] Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using variousterms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”

Claims

CLAIMSWhat is claimed is:1 . A method for isolating bitlines of a 3D-DRAM, comprising: depositing a conductive layer on an etch stop layer and in trenches between facing stacks of transistors; depositing a filler material in the trenches; depositing and patterning a mask layer including a plurality of vertical openings on the etch stop layer and the filler material, wherein the plurality of vertical openings of the mask layer are arranged above corresponding locations of the conductive layer that need to be removed to isolate bitlines of the 3D-DRAM; and etching the filler material in the trenches through the plurality of vertical openings to remove portions of the filler material to expose portions of the conductive layer located between vertical bitline locations.

2. The method of claim 1 , further comprising: removing the mask layer; and etching the exposed portions of the conductive layer between the vertical bitline locations in the trenches to isolate vertical bitlines in the conductive layer.

3. The method of claim 1 , wherein depositing the conductive layer includes using a conformal deposition process.

4. The method of claim 1 , further comprising planarizing the filler material after filling the trenches with the filler material.

5. The method of claim 1 , wherein the conductive layer comprises at least one of tungsten and molybdenum.

6. The method of claim 1 , wherein the plurality of vertical openings of the mask layer are arranged in an array.

7. The method of claim 1 , wherein the plurality of vertical openings of the mask layer have a rectangular cross section.

8. The method of claim 1 , wherein depositing the conductive layer includes using a bottom heavy deposition process.

9. The method of claim 1 , wherein each of the facing stacks of transistors comprise greater than or equal to 8 transistors.

10. The method of claim 1 , wherein the trenches have an aspect ratio greater than 200.

11. A method for isolating bitlines of a 3D-DRAM, comprising: depositing a conductive layer on an etch stop layer and in trenches between facing stacks of transistors; depositing a liner layer on the conductive layer in the trenches; depositing plugs in the trenches; depositing and patterning a mask layer including a plurality of vertical openings on the etch stop layer and the plugs, wherein the plurality of vertical openings of the mask layer are arranged above corresponding locations of the conductive layer that need to be removed to isolate bitlines of the 3D-DRAM; and etching selected ones of the plugs in the trenches through the plurality of vertical openings to etch at least one of the selected ones of the plugs and portions of the liner layer to expose portions of the conductive layer located between vertical bitline locations.

12. The method of claim 11 , wherein etching at least one of the selected ones of the plugs and the portions of the liner layer includes etching both the selected ones of the plugs and the portions of the liner layer.

13. The method of claim 11 , further comprising: removing the mask layer; and etching at least one of the exposed portions of the conductive layer and the portions of the liner layer between the vertical bitline locations in the trenches to isolate vertical bitlines in the conductive layer.

14. The method of claim 11 , wherein depositing the conductive layer includes using a conformal deposition process.

15. The method of claim 11 , further comprising planarizing the plugs after filling the trenches with the plugs.

16. The method of claim 11 , wherein the conductive layer comprises at least one of tungsten and molybdenum.

17. The method of claim 11 , wherein the plurality of vertical openings of the mask layer are arranged in an array.

18. The method of claim 11 , wherein the plurality of vertical openings of the mask layer have a rectangular cross section.

19. The method of claim 11 , wherein depositing the conductive layer includes using a bottom heavy deposition process.

20. The method of claim 11 , wherein each of the facing stacks of transistors comprise greater than or equal to 8 transistors.21 . The method of claim 11 , wherein the trenches have an aspect ratio greater than

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