Direct attached memory assembly

Abstract

Multiple stacks of dynamic random access memory devices are coupled with, and attached to, a buffer device to form a memory assembly. The buffer device interfaces between a controller and the memory device stacks such that each memory device stack function as separate ranks of memory residing on the same memory channel. The buffer device also serializes / deserializes data communicated with the memory device stacks such that the memory devices of a stack being accessed concurrently communicate with the buffer device using wider data words than are used to communicate with the controller. The buffer device and the controller may communicate using unidirectional communication links and a deterministic protocol using commands that combine the row and column functions and addressing. Read access commands may be pre-scheduled to allow multiple consecutive read commands to be issued without delaying read commands to allow for communication data on the unidirectional command / data links.

Description

DIRECT ATTACHED MEMORY ASSEMBLY BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure l is a block diagram of a memory system.

[0002] Figures 2A-2B are isometric exploded views illustrating example direct attached memory assemblies.

[0003] Figure 3 is a illustrates an example direct attached memory assembly with a reduced area buffer die.

[0004] Figures 4A-4B are timing diagrams illustrating example communication with a direct attached memory assembly.

[0005] Figures 5A-5B are timing diagrams illustrating example sequenced communication with a direct attached memory assembly.

[0006] Figure 6 is a flowchart illustrating a method of operating a direct attached memory assembly.

[0007] Figure 7 is a flowchart illustrating a method of operating a direct attached memory assembly to access data and error detection information.

[0008] Figure 8 is a flowchart illustrating a method of operating a direct attached memory assembly using a sequenced command protocol.

[0009] Figure 9 is a flowchart illustrating a method of operating a controller to communicate with direct attached memory assembly using a sequenced command protocol.

[0010] Figure 10 is a block diagram illustrating a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In an embodiment, multiple (e.g., four) stacks of dynamic random access memory (DRAM) devices are coupled with, and attached to, a buffer device to form a memory assembly. The buffer device interfaces between a controller (e.g., host) and the memory device stacks such that each memory device stack function as separate ranks of memory residing on the same memory channel. The buffer device also serializes / deserializes data communicated with the memory device stacks such that the memory devices of a stack being accessed concurrently communicate with the buffer device using wider data words than are used to communicate with the controller. For example, the buffer device may communicate with the controller using 8-bit data words while each of eight (8) memory devices in a stack concurrently communicates 64-bits in parallel with the buffer device. Thus, in this example, the buffer device would serialize / deserialize 512 bits (64-bits times 8 memory devices) into / from 8-bit words for communication with the controller.

[0012] In an embodiment, the buffer device and the controller communicate using unidirectional communication links. The buffer device and the controller may communicate using a deterministic protocol using commands that combine the row and column functions and addressing. In an embodiment, commands and data are communicated on the same unidirectional links (command / data links). In this embodiment, at least read access commands may be pre-scheduled (or queued) to allow multiple consecutive read commands to be issued without the necessity of delaying read commands to allow the communication of write data on the unidirectional command / data links.

[0013] Figure 1 is a block diagram of a memory system. In Figure 1, memory system 100 comprises controller 120 and assembly 101. Assembly 101 includes buffer device 140 and memory device stacks 130a-130d. Each of memory device stacks 130a-130d is stacked at least partially on buffer device 140.

[0014] Controller 120 and memory devices 110aa-l lOde may be integrated circuit type devices, such as are commonly referred to as a “chips”. A memory controller, such as controller 120, manages the flow of data going to and from memory devices and / or memory assemblies. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller may be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC).

[0015] Each of memory device stacks 130a-130d respectively include memory devices HOaa-l lOae, memory devices HOba-l lObe, memory devices HOca-l lOce, and memory devices HOda-l lOde, command / address (CA) interfaces 13 la-13 Id, data (DQ) interfaces 132a-132d, and error detection and correction (EDC) information interfaces 133a-133d. Each memory device 110aa-l lOde respectively includes a CA interface 11 laa-11 Ide and a data interface 112aa-l 12de. In an embodiment, each CA interface 11 laa-11 Ide is operatively coupled to the memory device stack 130a-130d CA interface 13 la-13 Id of the memory device stack 130a-130d that includes the memory device 11 laa-11 Ide.

[0016] Buffer device 140 includes CA interfaces 141a-141d, data interfaces 142a-142d, and EDC information interfaces 143a-143d, control circuitry 145, optional access sequencer circuitry 147, command and data receive interface (dRx) 146r, data transmit interface (dTx)146t, EDC information receive interface (eRx) 147r, and EDC information transmit interface (eTx) 147t. Control circuitry 145 includes mode circuitry 145a (e.g., registers). CA interfaces 14 la- 14 Id are respectively operatively coupled to CA interfaces 131a-131d of memory device stacks 130a-130d. Data interfaces 142a-142d are respectively operativelycoupled to data interfaces 132a-132d of memory device stacks 130a-130d. EDC interfaces 143 a- 143 d are respectively operatively coupled to EDC interfaces 142a-142d of memory device stacks 130a-130d.

[0017] Controller 120 includes control circuitry 125, command and data transmit interface (dTx)126t, data receive interface (dRx) 126r, EDC information transmit interface (eTx)127t, and EDC information receive interface (eRx) 127r. Data transmit interface 126t of controller 120 is operatively coupled to data receive interface 146r of buffer device 140 of assembly 101. Data receive interface 126r of controller 120 is operatively coupled to data transmit interface 146t of buffer device 140 of assembly 101. EDC transmit interface 127t of controller 120 is operatively coupled to EDC information receive interface 147r of buffer device 140 of assembly 101. EDC information receive interface 127r of controller 120 is operatively coupled to EDC information transmit interface 147t of buffer device 140 of assembly 101. Thus, it should be understood that, in an embodiment, controller 120 is operatively coupled to assembly 101 via unidirectional communication links.

[0018] In an embodiment, each of memory device stacks 130a-130d respectively include ten (10) memory devices stacked with each other. However, other numbers of devices (e.g., 12, 14, 20, etc.) are contemplated. In an embodiment, eight of the ten memory devices in each memory device stack 130a-130d are used to store data, and two memory devices in each memory device stack 130a-130d are used to store error detection and correction (EDC) information. For example, memory device stack 130a may include ten memory devices 110aa-l lOae, where memory device 1 lOac and memory device 1 lOae are used to store EDC information and the rest of the memory devices in memory device stack 130a are used to store data.

[0019] The memory devices in a memory device stack 130a-130d storing data are operatively coupled to, and respectively communicate data via data interfaces 142a-142d. The memory devices in a memory device stack 130a-130d storing EDC information are operatively coupled to, and respectively communicate EDC information via EDC interfaces 143a-143d.

[0020] In an embodiment, the EDC information stored by the memory devices (e.g., memory devices 1 lOaa and 1 lOae) in a memory device stack (e.g., memory device stack 130a) is associated with (i.e., protects) the data stored by the other memory devices in that stack. In another embodiment, the EDC information stored by the memory devices (e.g., memory devices 110a and 1 lOe) in a memory device stack is associated with (i.e., protects) the data stored by a different memory device stack (e.g., memory device stack 130b). In thismanner, a “die kill” level of EDC protection may be achieved. “Die kill” refers to the ability to detect and correct errors that affect all bits transmitted by a single die in an accessed DRAM stack. Common EDC codes require 2x the amount of bits (symbols) to detect and correct a symbol worth of bits; (e.g. if a die provides 64b of data per access (1 symbol) than 128 EDC bits (2 symbols) are required to perform the ’’die kill” correction.)

[0021] In an embodiment, memory device stacks 130a-130d each function as a separate rank. Thus, assembly 101 may function and appear to controller 120 as a complete memory channel. Commands and addresses transmitted by controller 120 to buffer device 140 (i.e., assembly 101) via data transmit interface 126t and data receive interface 146r may conform to a deterministic access protocol. For accessing one of memory stacks 130a-130d, controller 120 may transmit a command packet via data transmit interface 126t and data receive interface 146r that combines both row operations, column operations, and associated row and column addressing. An example command packet format, and associated EDC transmissions to protect the command packet from errors, is illustrated in Table 1.

[0022] Based on the commands from controller 120 received via data receive interface 146r, buffer device accesses memory device stacks 130a-130d. For example, in response to a command from controller 120, buffer device 140 (and control circuitry 145, in particular) may translate the command packet into commands and address transactions (e.g., precharge, activate, read, write, refresh, mode register set, etc.) that are compatible with the CAinterfaces 11 laa-11 Ide of memory devices 110aa-l lOde, and transmits those command and address transactions to the addressed memory stack (rank) 130a-130d. Based on the command and address transactions, data is communicated between individual memory devices (e.g., memory devices 110aa-l lOae) of the addressed memory device stack (e.g., memory device stack 130a) and buffer device in parallel. Also, in response to the command, buffer device 140 serializes or deserializes, as appropriate, data communicated with the accessed memory device stack 130a-130d.

[0023] For example, in response to a read command from controller 120 directed to memory device stack 130a, buffer device 140 may issue a read command sequence (e.g., ACT, RD), via CA interface 141a and CA interface 13 la the memory devices 110aa-l lOae of memory device stack 130a. In response, each of the accessed memory devices 110aa-l lOae of memory device stack 130a provides the data read from its memory array(s) to buffer device 140 via data interface 132a and data interface 142a in parallel. Buffer device serializes the received data from memory devices 110aa-l lOae into a data packet with less width (i.e., few bits, more transfers) than was used to transfer the data between memory device stack 130a and buffer device 140. Buffer then transmits that data packet to controller 120. An example data packet format, and associated EDC transmissions to protect the command packet from errors, is illustrated in Table 2.

[0024] For another example, consider an assembly 101 where: (1) each memory device stack 130a-130d includes ten (10) memory devices 110aa-l lOde; (2) eight memory devices of each memory device stack 130a-130d are configured or assigned to store data; (3) two memory devices of each memory device stack 130a-130d are configured or assigned to store EDC information; (4) data transmit interface 126t, data receive interface 126r, data transmit interface 146t, and data receive interface 146r are all eight bits wide (i.e., each communicates via eight data links - e.g., eight single-ended signaling wires or sixteen differential signaling wires); (5) EDC information transmit interface 127t, EDC information receive interface 127r, EDC information transmit interface 147t, and EDC information receive interface 147r are all two bits wide (i.e., each communicates via two data links - e.g., two single-ended signaling wires or four differential signaling wires); and (6) each memory device 110aa-l lOde communicates bidirectionally and in parallel with buffer device 140 64 bits per communication transfer (i.e., each communicates via 64 data links - e.g., 64 single-ended signaling wires or 128 differential signaling wires). In this example, buffer device 140 would communicate 512 bits of data from / to an accessed stack per communication transfer and 128 bits of EDC information per communication transfer. For a read, buffer device serializes datafrom the accessed memory device stack into eight bit wide transfers (i.e., number of data links), and serializes the EDC from the accessed memory device stack for communication to controller 120. For a write, buffer device deserializes data from the eight bit transfers from controller into 512 bit wide transfers to the accessed memory device stack, and deserializes the EDC information from the two bit transfers from controller into 128 bit wide transfers to the accessed memory device stack. To generalize this example, if data blocks communicated with memory stacks 130a-130d are N (e.g., N=512) number of bits in size, the parallel transfer units communicated with controller are M (e.g., M=8) number of bits in size, the data bursts with controller 120 have P number of parallel transfer units, where P is equal to N divided by M (e.g., P=64=512 / 8), and N, M, and P are positive integers greater than two.

[0025] As discussed herein, EDC information and data may, in response to the same command to assembly 101, be accessed using different memory device stacks. In this embodiment, for a read, buffer device serializes data from the addressed memory device stack into eight bit wide transfers (i.e., number of data links), and serializes the EDC from a different (e.g., hardwired, command specified, and / or mode specified) memory device stack for communication to controller 120. For a write, buffer device deserializes data from the eight bit transfers from controller into 512 bit wide transfers to the addressed memory device stack, and deserializes the EDC information from the two bit transfers from controller into 128 bit wide transfers to the different memory device stack.

[0026] Figures 2A-2B are isometric exploded views illustrating example direct attached memory assemblies. In Figure 2A, assembly 200 is illustrated with memory device stacks 230a-230d disposed on buffer device 240. In Figure 2B, assembly 201 is also illustrated with memory device stacks 230a-230d disposed on buffer device 240. However, in Figure 2B, memory device 210ac and memory device 210ae of memory device stack 230a, memory device 210bc and memory device 21 Obe of memory device stack 230b, , memory device 210cc and memory device 210ce of memory device stack 230c, and , memory device 21 Ode and memory device 21 Ode of memory device stack 23 Od are designated or configured to store EDC information. This is illustrated in Figure 2B by the hashing of the visible sides of those memory devices.

[0027] Figure 3 is a illustrates an example direct attached memory assembly with a reduced area buffer die. In Figure 3, memory device stacks 330a-330d are illustrated only by their outlines (e.g., wireframe) to allow for visibility. In Figure 3, assembly 300 is illustrated with memory device stacks 330a-330c disposed partially on substrate 301 and partially on buffer device 340. In particular, each of memory device stacks 330a-330d is disposed on (over) different quadrants of buffer device 340. In this manner, buffer device 340 may be smaller (i.e., less area) than buffer device 240 and still make connections (e.g., through- silicon vias - TSVs) with memory device stacks 330a-330c (and the memory devices therein).

[0028] Figures 4A-4B are timing diagrams illustrating example communication with a direct attached memory assembly. In Figures 4A-4B, example communication between a controller (e.g., controller 120) and an assembly (e.g., assembly 101) is illustrated from the perspective of the unidirectional data transmit and data receive interfaces (dTx, dRx) of the controller. In Figures 4A-4B, on the controller’s data transmit interface (or links), the controller transmits a first read command (RD1). In response to the first read command, the assembly, on its unidirectional data transmit links, transmits the first read data (RDQ1) to the controller’s data receive interface after a predetermined (i.e., uniform) delay period. This is illustrated in Figure 4B by arrow 401 running from the transmission of RD1 to the reception ofRDQl.

[0029] Immediately following the first read command (RD1), the controller transmits a first write command (WR1). The first write command is immediately followed on the controller’s data transmit interface by a first portion of the first write data (WDQla). This isillustrated in Figure 4B by arrow 402 running from the transmission of WR1 to the transmission of WDQla. Following the transmission of WDQla, the controller transmits a second read command (RD2). The second read command RD2 is immediately followed on the controller’s data transmit interface by a second portion of the first write data (WDQlb) associated with WR1. This is illustrated in Figure 4B by arrow 403 running from the transmission of WR1 to the transmission of WDQlb. In response to the second read command RD2, the assembly, on its unidirectional data transmit links, transmits the second read data (RDQ2) to the controller’s data receive interface immediately following RDQ2 (i.e., without any unused transfer cycles) and after the predetermined (i.e., uniform) delay period from when RD2 was transmitted. This is illustrated in Figure 4B by arrow 404 running from the transmission of RD2 to the reception of RDQ2.

[0030] Following the transmission of RD2, the controller transmits a refresh command (REF). This refresh command may be, for example, a single bank refresh directed to a precharged bank in a rank (memory device stack) that is being accessed. In another example, this refresh command may be, an all-bank refresh directed to a rank that is not currently being accessed.

[0031] Following the transmission of REF, the controller transmits a third read command (RD3). The third read command RD3 is immediately followed on the controller’s data transmit interface by a second write command (WR2). The second write command is immediately followed on the controller’s data transmit interface by a first portion of the second write data (WDQ2a). This is illustrated in Figure 4B by arrow 406 running from the transmission of WR2 to the transmission of WDQ2a. Following the transmission of WDQ2a, the controller transmits a fourth read command (RD4). The fourth read command RD2 is immediately followed on the controller’s data transmit interface by a second portion of the second write data (WDQ2b) associated with WR2. This is illustrated in Figure 4B by arrow 407 running from the transmission of WR2 to the transmission of WDQ2b. In response to the third read command, the assembly, on its unidirectional data transmit links, transmits the third read data (RDQ3) to the controller’s data receive interface immediately following RDQ2 (i.e., without any unused transfer cycles) and after the predetermined (i.e., uniform) delay period from when RD3 was transmitted. This is illustrated in Figure 4B by arrow 405 running from the transmission of RD2 to the reception of RDQ2.

[0032] Figures 5A-5B are timing diagrams illustrating example sequenced communication with a direct attached memory assembly. In Figures 5A-5B, example communication between a controller (e.g., controller 120) and an assembly (e.g., assembly101) is illustrated from the perspective of the unidirectional data transmit and data receive interfaces (dTx, dRx) of the controller. In Figures 5A-5B, on the controller’s data transmit interface (or links), the controller transmits, in succession, a first read command (RD1), a second read command (RD2), a third read command (RD3) a fourth read command (RD4), a refresh command (REF), and a first write command (WR1). In response to the commands RD1-RD4, the assembly, on its unidirectional data transmit links, respectively transmits, in immediate succession, first read data (RDQ1), second read data (RDQ2), third read data (RDQ3), and fourth read data (not shown in Figures 5A-5B) to the controller’s data receive interface. Note that since the commands RD1-RD4 take fewer bus cycles to transmit than the associated read data RDQ1-RDQ4, the immediate succession of RD1-RD4 and immediate succession of RDQ1-RDQ4 result in non-uniform delays between the transmission of each of the RD1-RD4 commands and the transmission of the associated data RDQ1-RDQ4. These are illustrated in Figure 5B by arrow 501 running from the transmission of RD1 to the reception of RDQ1, arrow 502 running from the transmission of RD2 to the reception of RDQ2, and arrow 503 running from the transmission of RD3 to the reception of RDQ3.

[0033] Immediately following the first write command WR1, and on the controller’s data transmit interface, the data associated with the first write command (WDQ1) is transmitted. This is illustrated in Figure 5B by arrow 504 running from the transmission of WR1 to the transmission of WDQ1 immediately after the transmission of WR1. Immediately following the transmission of WDQ1, a second write command (WR2) is transmitted by the controller. Immediately following the second write command WR2, and on the controller’s data transmit interface, the data associated with the second write command (WDQ2) is transmitted. This is illustrated in Figure 5B by arrow 505 running from the transmission of WR2 to the transmission of WDQ2 immediately after the transmission of WR2. Thus, it should be evident that in comparison the command sequence illustrated in Figure 4A-4B, the sequencing or queuing (e.g., sequenced or queued by sequencer circuitry 147) of commands illustrated in Figures 5A-5B results in non-uniform delays between read commands and their associated data, allows write data to be sent in single blocks (i.e., not split into portions), and may simplify command scheduling on the controller’s data transmit interface. The sequencer 147 contains a statemachine that schedules the access command , received from controller 120, to the DRAM stacks 130a-d in accordance with the DRAM timing parameters. In this example the sequencer 147 schedules the received read commands and addresses to the respective DRAM ranks in accordance with the DRAM read timing requirements (e.g. tCCD) to ensure that the read data becomes available at the correct time and to avoid DRAM timingconflicts, since the DRAM response to the read requests has a uniform delay. The sequencer also ensures that the assembly 101 executes all received commands in order of reception. In other words, the sequencer 147 ensures the the communication between the buffer 140 and the DRAM stacks 130a-130d remains deterministic with uniform delays. This way the access response for each command remains deterministic for the controller 120, even though the command response delay at the interface to the controller is non-uniform.

[0034] Figure 6 is a flowchart illustrating a method of operating a direct attached memory assembly. One or more steps illustrated in Figure 6 may be performed by, for example, memory system 100, and / or its components. By an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stacks is received (602). For example, assembly 101 (and buffer device 140, in particular) may receive a command from controller 120 to access memory device stack 130a.

[0035] By the first stack and based on the first command, a first data block is communicated with the buffer integrated circuit in parallel (604). For example, based on the first command, buffer device 140 may control memory devices 110aa-l lOae of memory device stack 130a to communicate a block of data (e.g., 640 bits of read / write data) with each memory device 110aa-l lOae in parallel and using a wide data transfer width (e.g., 64 bits in parallel per memory device 110aa-l lOae for a total of 640 bits being communicated in parallel with buffer device 140 per transfer). By the buffer integrated circuit and based on the first command, the first block of data is communicated in a first data burst with a controller that transmitted the first command, where the first data burst comprises a first plurality of data sub-blocks communicated with the controller using parallel transfer units that are smaller than the first data block (606). For example, buffer device 140 may serialize / deserialize data blocks (e.g., 640 bit blocks) from / to memory device stack 130a and communicate those data blocks with controller 120 using smaller parallel transfer units (e.g., 8 bits, 10 bits, etc.).

[0036] By the assembly, a second command to be performed by a second stack of the plurality of memory integrated circuit device stacks is received (608). For example, assembly 101 (and buffer device 140, in particular) may receive a command from controller 120 to access memory device stack 130b.

[0037] By the second stack and based on the second command, a second data block is communicated with the buffer integrated circuit in parallel (610). For example, based on the second command, buffer device 140 may control memory devices 110ba-l lObe of memorydevice stack 130b to communicate a block of data (e.g., 640 bits of read / write data) with each memory device 110ba-l lObe in parallel and using a wide data transfer width (e.g., 64 bits in parallel per memory device 110ba-l lObe for a total of 640 bits being communicated in parallel with buffer device 140 per transfer). By the buffer integrated circuit and based on the first command, the second block of data is communicated in a second data burst with the controller that transmitted the first command and the second command, where the second data burst comprises a second plurality of data sub-blocks communicated with the controller using parallel transfer units that are smaller than the first data block (612). For example, buffer device 140 may serialize / deserialize data blocks (e.g., 640 bit blocks) from / to memory device stack 130b and communicate those data blocks with controller 120 using smaller parallel transfer units (e.g., 8 bits, 10 bits, etc.).

[0038] Figure 7 is a flowchart illustrating a method of operating a direct attached memory assembly to access data and error detection information. One or more steps illustrated in Figure 7 may be performed by, for example, memory system 100, and / or its components. By an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first access command to be performed by the assembly is received (702). For example, assembly 101 (and buffer device 140, in particular) may receive, from controller 120, an access command to be performed by assembly 101.

[0039] By a first stack and based on the first command, a first data block is communicated with the buffer integrated circuit in parallel (704). For example, based on the first command, buffer device 140 may control a first subset (e.g., 8 devices) of memory device stack 130a to communicate a block of data (e.g., 512 bits of read / write data) with each memory device of the first subset in parallel and using a wide data transfer width (e.g., 64 bits in parallel per memory device of the eight memory device in the first subset for a total of 512 bits being communicated in parallel with buffer device 140 per transfer). By a second stack and based on the first command, a first error detection information block is communicated with the buffer integrated circuit in parallel (706). For example, based on the first command, buffer device 140 may control a second subset (e.g., 2 devices) of memory device stack 130b to communicate a block of EDC information data (e.g., 128 bits of EDC read / write data) with each memory device of the second subset in parallel and using a wide data transfer width (e.g., 64 bits in parallel per memory device of the two memory device in the second subset for a total of 128 bits being communicated in parallel with buffer device 140 per transfer).

[0040] By the buffer integrated circuit and based on the first command, the first block of data and the first error detection information block are communicated in a first data burst with the controller that transmitted the first command, where the first data burst comprises a first plurality of data sub-blocks communicated with the controller using parallel transfer units that are smaller than the first data block (708). For example, buffer device 140 may serialize / deserialize data blocks (e.g., 512-bit blocks) from / to memory device stack 130a and communicate those data blocks with controller 120 using smaller parallel transfer units (e.g., 8 bits). Buffer device 140 may also, for example, serialize / deserialize EDC information data blocks (e.g., 1128-bit blocks) from / to memory device stack 130b and communicate those EDC information data blocks with controller 120 using smaller parallel transfer units (e.g., 2 bits).

[0041] Figure 8 is a flowchart illustrating a method of operating a direct attached memory assembly using a sequenced command protocol. One or more steps illustrated in Figure 8 may be performed by, for example, memory system 100, and / or its components. A plurality of commands are received from a controller (802). For example, controller 120 may transmit, and assembly 101 receive, in immediate succession, a first read command (RD1), a second read command (RD2), a third read command (RD3), and a fourth read command (RD4).

[0042] Based on the plurality of read commands, data associated with respective ones of the plurality of read commands is transmitted with non-uniform delays between receipt of the respective ones of the plurality of read commands and the transmission of the data associated with the respective ones of the plurality of read commands (804). For example, the assembly, on its unidirectional data transmit links, may respectively transmit, in immediate succession and in response to read command RD1-RD3 that were transmitted in immediate succession, first read data (RDQ1), second read data (RDQ2), and third read data (RDQ3). Since, for example, the commands RD1-RD3 take fewer bus cycles to transmit than the associated read data RDQ1-RDQ3, the immediate succession of RD1-RD3 and immediate succession of RDQ1-RDQ3 results in non-uniform delays between the transmission of each of the RD1- RD3 commands and the transmission of the associated data RDQ1-RDQ3.

[0043] Figure 9 is a flowchart illustrating a method of operating a controller to communicate with direct attached memory assembly using a sequenced command protocol. One or more steps illustrated in Figure 9 may be performed by, for example, memory system 100, and / or its components. A plurality of read commands are transmitted to an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit devicestacks disposed at least partially on the buffer integrated circuit (902). For example, controller 120 may transmit, and assembly 101 receive, in immediate succession, a first read command (RD1), a second read command (RD2), a third read command (RD3), and a fourth read command (RD4).

[0044] Based on the plurality of read commands, determine a corresponding plurality of non-uniform delay between transmission of the respective ones of the plurality of read commands and the receipt of the data from the assembly associated with the respective ones of the plurality of read commands (904). For example, controller 120 may determine, using the information that read commands RD1-RD3 were (or will be) transmitted in immediate succession (and optionally other data information such as refresh command transmission time, etc.), and the information that the commands RD1-RD3 take fewer bus cycles to transmit than the associated read data RDQ1-RDQ3, determine respective non-uniform delays from RD1 to when RDQ1 will be receive, from RD2 to when RDQ2 will be received, and from RD3 to when RDQ3 will be received.

[0045] Based on the corresponding plurality of non-uniform delays, the data associated with the respective ones of the plurality of read commands is received (906). For example, based on the determined non-uniform delays from RD1 to when RDQ1 will be receive, from RD2 to when RDQ2 will be received, and from RD3 to when RDQ3 will be received, controller 120 may receive RDQ1-RDQ3.

[0046] While the CA and data transmissions between the assembly 101 and the controller 120 are performed on unidirectional links in the above embodiments, it is also possible to implement the invention using bidirectional links between the controller 120 and the assembly 101.

[0047] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable fdes containing software descriptions of such circuits. This includes, but is not limited to one or more elements memory system 100, and / or its components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0048] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting registertransfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0049] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating, a representation of a circuit component 1020. Processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communications devices 1006. Processors 1002, memory 1004, and communications devices 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0050] Processors 1002 execute instructions of one or more processes 1012 stored in a memory 1004 to process and / or generate circuit component 1020 responsive to user inputs 1014 and parameters 1016. Processes 1012 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1020 includes data that describes all or portions of memory system 100, and / or its components, as shown in the Figures.

[0051] Representation 1020 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1020 may be stored on storage media or communicated by carrier waves.

[0052] Data formats in which representation 1020 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

[0053] User inputs 1014 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1016 may include specifications and / or characteristics that are input to help define representation 1020. For example, parameters 1016 may include information thatdefines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0054] Memory 1004 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1012, user inputs 1014, parameters 1016, and circuit component 1020.

[0055] Communications devices 1006 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1006 may transmit circuit component 1020 to another system. Communications devices 1006 may receive processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 and cause processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 to be stored in memory 1004.

[0056] Implementations discussed herein include, but are not limited to, the following examples:

[0057] Example 1: A memory device, comprising: a buffer device including an external memory channel interface to communicate commands, addresses, and data with a controller; and a plurality of memory device stacks disposed with, and coupled to, the buffer device, each of the plurality of memory device stacks comprising a respective plurality of memory devices, each of the respective plurality of memory devices of a respective memory device stack to function as a rank of memory devices that are accessed concurrently in response to commands, addresses, and data communicated via the buffer device.

[0058] Example 2: The memory device of example 1, wherein data bursts communicated based on accesses via the external memory channel interface are to be communicated in parallel with each memory device stack.

[0059] Example 3: The memory device of example 1, wherein the external memory channel interface comprises a plurality of unidirectional receive links and a plurality of unidirectional transmit links.

[0060] Example 4: The memory device of example 3, wherein the plurality of unidirectional receive links include a plurality of error detection and correction (EDC) information links to receive EDC information and wherein the plurality of unidirectional transmit links include a plurality of EDC information links to transmit EDC information.

[0061] Example 5: The memory device of example 1, further comprising: access sequencing circuitry to schedule communication via the plurality of unidirectional transmit links with non-constant delays relative to commands received via the plurality of unidirectional receive links.

[0062] Example 6: The memory device of example 1, wherein data and associated error detection and correction (EDC) information are to be accessed using different ones of the plurality of memory device stacks.

[0063] Example 7: The memory device of example 1, wherein a first area of a first surface of each of the plurality of memory device stacks is respectively disposed upon each of a plurality of portions of a second surface of the buffer device.

[0064] Example 8: The memory device of example 7, wherein a total area of the first surfaces of the plurality of memory device stacks is greater than the area of the second surface of the buffer device.

[0065] Example 9: A memory device, comprising: a first memory device stack comprising a first plurality of memory devices configured to function as a first rank of memory devices that are accessed concurrently; a second memory device stack comprising a second plurality of memory devices configures to function as a second rank of memory devices that are accessed concurrently; and a buffer device disposed on, and coupled with, the first memory device stack and the second memory device stack, the buffer device comprising an external memory channel interface to communicate a plurality of commands, a plurality of addresses, and a plurality of data bursts with a controller, a first data block corresponding to a first data burst of the plurality of data bursts to be communicated with the first memory device stack in parallel, and a second data block corresponding to a second data burst of the plurality of data bursts to be communicated with the second memory device stack in parallel.

[0066] Example 10: The memory device of example 9, wherein the external memory channel interface comprises a first plurality of unidirectional receive links to communicate a first command from the controller to the buffer device.

[0067] Example 11 : The memory device of example 10, wherein the first plurality of unidirectional receive links are to, based on the first command, receive the first data burst, and the buffer device is to, based on the first command, communicate the first data block to the first memory device stack.

[0068] Example 12: The memory device of example 11, wherein the external memory channel interface further comprises a first plurality of unidirectional transmit links, the buffer device to, based on a second command communicated via the first plurality of unidirectionalreceive links, access the second data block from the second memory device stack and communicate the second data burst to the controller via the first plurality of unidirectional transmit links.

[0069] Example 13: The memory device of example 12, wherein the external memory channel further comprises a second plurality of unidirectional receive links to receive error detection and correction (EDC) information from the controller and wherein the external memory channel further comprises a second plurality of unidirectional transmit links to transmit EDC information to the controller.

[0070] Example 14: The memory device of example 13, further comprising:

[0071] access sequencing circuitry to schedule communication via the first plurality of unidirectional transmit links with non-constant delays relative to commands received via the first plurality of unidirectional receive links.

[0072] Example 15: The memory device of example 9, wherein the first data block is associated with first error detection and correction (EDC) information that is accessed using the second memory device stack.

[0073] Example 16: The memory device of example 15, wherein the second data block is associated with second EDC information that is accessed using the first memory device stack.

[0074] Example 17: A method, comprising: receiving, by an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stacks; communicating, by the first stack and based on the first command, a first data block with the buffer integrated circuit in parallel; communicating, by the buffer integrated circuit and based on the first command, the first data block in a first data burst with a controller that transmitted the first command, the first data burst comprising a first plurality of data sub-blocks communicated, with the controller, using parallel transfer units that are smaller than the first data block; receiving, by the assembly, a second command to be performed by a second stack of the plurality of memory integrated circuit device stacks; communicating, by the second stack and based on the second command, a second data block with the buffer integrated circuit in parallel; and communicating, by the buffer integrated circuit and based on the second command, the second data block in a second data burst with the controller that transmitted the first command and the second command, the second data burst comprising a second plurality of data sub-blocks communicated, with the controller, using the parallel transfer units that are smaller than the first data block.

[0075] Example 18: The method of example 17, further comprising: communicating, by the second stack and based on the first command, first error detection and correction (EDC) information with the buffer integrated circuit; and communicating, by the buffer integrated circuit and based on the first command, the first EDC information with the controller.

[0076] Example 19: The method of example 17, further comprising: receiving a plurality of read commands from the controller; transmitting, based on respective ones of the plurality of read commands, data associated with the respective ones of the plurality of read commands with non-uniform delays between receipt of the respective ones of the plurality of read commands and the data associated with the respective ones of the plurality of read commands.

[0077] Example 20: The method of example 17, wherein the first data block and the second data block are N number of bits in size, the parallel transfer units are M number of bits in size, the first data burst and the second data burst have P number of parallel transfer units, where P is equal to N divided by M, and N, M, and P are positive integers greater than two.

[0078] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A memory device, comprising: a buffer device including an external memory channel interface to communicate commands, addresses, and data with a controller; and a plurality of memory device stacks disposed with, and coupled to, the buffer device, each of the plurality of memory device stacks comprising a respective plurality of memory devices, each of the respective plurality of memory devices of a respective memory device stack to function as a rank of memory devices that are accessed concurrently in response to commands, addresses, and data communicated via the buffer device.

2. The memory device of claim 1, wherein data bursts communicated based on accesses via the external memory channel interface are to be communicated in parallel with each memory device stack.

3. The memory device of claim 1, wherein the external memory channel interface comprises a plurality of unidirectional receive links and a plurality of unidirectional transmit links.

4. The memory device of claim 3, wherein the plurality of unidirectional receive links include a plurality of error detection and correction (EDC) information links to receive EDC information and wherein the plurality of unidirectional transmit links include a plurality of EDC information links to transmit EDC information.

5. The memory device of claim 1, further comprising: access sequencing circuitry to schedule communication via the plurality of unidirectional transmit links with non-constant delays relative to commands received via the plurality of unidirectional receive links.

6. The memory device of claim 1, wherein data and associated error detection and correction (EDC) information are to be accessed using different ones of the plurality of memory device stacks.

7. The memory device of claim 1, wherein a first area of a first surface of each of the plurality of memory device stacks is respectively disposed upon each of a plurality of portions of a second surface of the buffer device.

8. The memory device of claim 7, wherein a total area of the first surfaces of the plurality of memory device stacks is greater than the area of the second surface of the buffer device.

9. A memory device, comprising: a first memory device stack comprising a first plurality of memory devices configured to function as a first rank of memory devices that are accessed concurrently; a second memory device stack comprising a second plurality of memory devices configures to function as a second rank of memory devices that are accessed concurrently; and a buffer device disposed on, and coupled with, the first memory device stack and the second memory device stack, the buffer device comprising an external memory channel interface to communicate a plurality of commands, a plurality of addresses, and a plurality of data bursts with a controller, a first data block corresponding to a first data burst of the plurality of data bursts to be communicated with the first memory device stack in parallel, and a second data block corresponding to a second data burst of the plurality of data bursts to be communicated with the second memory device stack in parallel.

10. The memory device of claim 9, wherein the external memory channel interface comprises a first plurality of unidirectional receive links to communicate a first command from the controller to the buffer device.

11. The memory device of claim 10, wherein the first plurality of unidirectional receive links are to, based on the first command, receive the first data burst, and the buffer device is to, based on the first command, communicate the first data block to the first memory device stack.

12. The memory device of claim 11, wherein the external memory channel interface further comprises a first plurality of unidirectional transmit links, the buffer device to, based on a second command communicated via the first plurality of unidirectional receive links, accessthe second data block from the second memory device stack and communicate the second data burst to the controller via the first plurality of unidirectional transmit links.

13. The memory device of claim 12, wherein the external memory channel further comprises a second plurality of unidirectional receive links to receive error detection and correction (EDC) information from the controller and wherein the external memory channel further comprises a second plurality of unidirectional transmit links to transmit EDC information to the controller.

14. The memory device of claim 13, further comprising: access sequencing circuitry to schedule communication via the first plurality of unidirectional transmit links with non-constant delays relative to commands received via the first plurality of unidirectional receive links.

15. The memory device of claim 9, wherein the first data block is associated with first error detection and correction (EDC) information that is accessed using the second memory device stack.

16. The memory device of claim 15, wherein the second data block is associated with second EDC information that is accessed using the first memory device stack.

17. A method, comprising: receiving, by an assembly comprising a buffer integrated circuit and a plurality of memory integrated circuit device stacks disposed at least partially on the buffer integrated circuit, a first command to be performed by a first stack of the plurality of memory integrated circuit device stacks; communicating, by the first stack and based on the first command, a first data block with the buffer integrated circuit in parallel; communicating, by the buffer integrated circuit and based on the first command, the first data block in a first data burst with a controller that transmitted the first command, the first data burst comprising a first plurality of data sub-blocks communicated, with the controller, using parallel transfer units that are smaller than the first data block;receiving, by the assembly, a second command to be performed by a second stack of the plurality of memory integrated circuit device stacks; communicating, by the second stack and based on the second command, a second data block with the buffer integrated circuit in parallel; and communicating, by the buffer integrated circuit and based on the second command, the second data block in a second data burst with the controller that transmitted the first command and the second command, the second data burst comprising a second plurality of data sub-blocks communicated, with the controller, using the parallel transfer units that are smaller than the first data block.

18. The method of claim 17, further comprising: communicating, by the second stack and based on the first command, first error detection and correction (EDC) information with the buffer integrated circuit; and communicating, by the buffer integrated circuit and based on the first command, the first EDC information with the controller.

19. The method of claim 17, further comprising: receiving a plurality of read commands from the controller; and transmitting, based on respective ones of the plurality of read commands, data associated with the respective ones of the plurality of read commands with non-uniform delays between receipt of the respective ones of the plurality of read commands and the data associated with the respective ones of the plurality of read commands.

20. The method of claim 17, wherein the first data block and the second data block are N number of bits in size, the parallel transfer units are M number of bits in size, the first data burst and the second data burst have P number of parallel transfer units, where P is equal to N divided by M, and N, M, and P are positive integers greater than two.

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