Direct heterogeneous integration of oxide materials on transition metal dichalcogenides

Abstract

A device includes a source region, a drain region, a two-dimensional channel formed of one of either molybdenum disulfide (MoS2) or tungsten disulfide (WS2), a gate positioned to control flow of current between the source region and the drain region in the two-dimensional channel, and a gate oxide directly integrated on the channel. A method of forming a gate oxide includes depositing a transition metal sulfur layer comprised of one or either amorphous MoSx or WSx on a substrate, where x >3, forming a layer of oxide on the transition metal sulfur layer, and annealing the transition metal sulfur to form one of either MoS2 or WS2.

Description

DIRECT HETEROGENEOUS INTEGRATION OF OXIDE MATERIALS ON TRANSITION METAL DICHALCOGENIDESTECHNICAL FIELD

[0001] This disclosure relates to integrated gate dielectrics, more particularly to integrated gate dielectrics with transition metal dichalcogenides, interfaces of oxide films on two- dimensional semiconducting layers, and semimetal films.BACKGROUND

[0002] The electronic industry essentially revolves around the field-effect transistor, where current flow between electrodes is regulated by biases applied through a gate electrode.Silicon has been the dominant semiconductor due to its reliable carrier mobility in various chemical and thermal environments, with entire infrastructures and fabrication facilities developed exclusively for silicon over time. One of the key advantages of silicon is that its native oxide, silicon dioxide (SiO?), could function as a gate dielectric, although significant gate leakage attributed to the quantum tunneling effect could occur when it is thinned down to around 5 atoms thickness. For the aid of this, Si CMOS technology incorporates materials with high dielectric constants, known as high-& dielectrics, through atomic layer deposition (ALD) processes.

[0003] Recently, there has been a growing demand for transistors and other electronic devices to have reduced dimensions for several reasons: device performance enhancement and low power consumption by shorting the path for electrons flow, high-density integration to accommodate more transistors in a specific region, thereby accelerating computational speed for Al algorithms. In response to this demand, two-dimensional (2D) materials from graphene to molybdenum disulfide (M0S2) and tungsten disulfide (WS2) sit at the forefront ofdedications and efforts to replace silicon as the channel in smaller devices. Numerous studies on the fabrication and application of 2D materials have provided in-depth insight into material synthesis and strategies to optimize their electrical properties for use in lowdimensional devices.

[0004] Like silicon-based transistors, transistors with 2D channels also require isolation from the gate electrode through insulating layers for proper device operation. Fortunately, 2D materials are often compatible with high-& dielectrics in terms of gate control and scalability. For instance, using a 30 nm -thick hafnium oxide gate oxide on monolayer M0S2 demonstrates exceptional device performances, such as high on / off ratio of -108, nearly ideal subthreshold swing of - 70 mV / dec, and high mobility of up to 200 cm2 / V s. This highlights the importance of the ALD step employed to grow hi gh-Xr dielectric on 2D materials during device fabrication, yet challenges still exist in achieving homogeneous, high-quality dielectric films with sub-nanometric control.

[0005] The typical ALD process relies on substantial dangling bonds on the surface of interest to facilitate chemisorption of oxide precursors in the early stages of the process, initiating nucleation and forming a uniform film. However, 2D materials inherently lack dangling bonds out-of-plane, causing these precursors to physically absorb and aggregate into nanoparticles and islands, resulting in an inhomogeneous layer with poor coverage. This issue becomes more pronounced when the gate dielectric thickness is less than 10 nm.

[0006] Efforts have been made to address this challenge. One of the most representative approaches is to introduce dangling bonds or active sites on the surface of 2D materials through methods, such as oxygen plasma, ultraviolet / ozone treatment, forming seeding nuclei or layers prior to the oxide deposition. However, these approaches can cause chronic damage to the 2D materials and degrade their electrical properties, despite improving the geometricflatness and uniformity of the oxide film. Therefore, the direct integration of homogeneous gate dielectrics on 2D materials necessitates the demand for improvement.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 shows an embodiment of a process to spin on transition metal dichalcogenides (TMDs).

[0008] FIGs. 2A-2H show graphics of embodiments and results of direct oxide integration on spin-on M0S3.

[0009] FIGs. 3 A-3C show HRTEM images of spin-on M0S2 at 450 °C, 650 °C, and 850 °C.

[0010] FIGs. 4A-4I shows embodiments and results of direct oxide integration of 3 nm AI2O3 on spin-on M0S2.

[0011] FIGs. 5A-5C shows embodiments and results of inhomogeneous AI2O3 mechanically exfoliate from a crystal.

[0012] FIG. 6 shows different embodiments of transistors with transition metal dichalcogenide channels.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The embodiments here involve a straightforward approach to directly integrate gate dielectrics with transition metal dichalcogenides (TMDs) grown by spin-on molecular chemistries, known as xanthate molecules, employing a standard ALD process. As discussed above, transistors with 2D channels also require isolation from the gate electrode through insulating layers for proper device operation. Fortunately, 2D materials are often compatible with hi gh-Xr dielectrics in terms of gate control and scalability. The transistors of the embodiments may comprise field-effect transistors (FET), nanosheet transistors, gate all around transistors, and complementary FETs, among others.

[0014] The transistors resulting from the embodiments disclosed herein will have a source region, a drain region, and a channel region. A gate oxide is positioned to reside on thechannel region or may encompass the entire gate in the embodiment of a gate all around transistor. This provides the needed electrical separation. The source and drain may comprise metal or metallic materials. “Metallic materials” as used here means materials that are a combination of one or metals and one or more non-metallic materials.

[0015] Spin-on molecular chemistries are the growth method of 2D materials where singlesource precursors are spin-coated, or using other coating methods, onto desired insulating substrates. The other methods may include, but are not limited to, atomic layer deposition, thermal evaporation, and sputtering. The substrates comprise crystalline materials such as sapphire, or amorphous materials, such as SiCh, and converted into spin-on TMDs, including M0S2 and WS2, during post-annealing. FIG. 1 illustrates the schematics of spin-on TMDs formation. The process begins with TMDs being spin coated on to a substrate. The TMD comprises a transition metal, such as 10 and a chalcogen such as 12. During the annealing process 14, spin-on TMD polymorphs undergo a phase transition from amorphous M0S3, or WS3, to crystalline M0S2, or WS2, through sulfur dimer gas depletion, with the 3D integration shown at 16 and 18.

[0016] In an initial embodiment, the inventors considered amorphous M0S3 as a starting material for direct integration with ALD aluminum oxide (AI2O3). Amorphous M0S3 consists of diverse oligomer building blocks, containing a rich variety of sulfur ligands, including dimers or atomic sulfurs atoms at bridging, terminal and hallow sites in the molecular structure. The open structure of amorphous M0S3 provides abundant structural distortions and in-plane defects that could serve as preferential binding sites for oxide precursors to facilitate ALD-assisted oxide growth.

[0017] FIG. 2 shows a direct oxide integration of spin-on M0S3. FIG. 2 A shows a schematic of an embodiment of a process that involves spin coating a transition metal such as molybdenum or tungsten as examples, in this embodiment amorphous M0S3, and a chalcogensuch as an oxide. The oxide layer, in this embodiment AI2O3 may have a thickness in a range from 1 nanometer to 1 micron. FIG. 2B shows AFM images of 5 nm AhCh / a-MoSs. FIG. 2C shows height variation along the line shown in FIG. 2B. FIG. 2D shows a schematic of the material after annealing, in which the amorphous molybdenum had converted to crystalline molybdenum, and 2E shows AFM images of 5 nm AI2O3 / C-MOS2 after post-annealing process. FIG. 2F shows a height variation along the line shown in FIG. 2E. FIG. 2G shows EDS mapping and 2H shows cs-TEM images of the homogeneous AI2O3 / MOS2 heterostructure following annealing subsequent to stacking heterolayers.

[0018] To verify this, one embodiment involving a two-step process was conducted where 5 nm AI2O3 was deposited on amorphous M0S3 followed by post-annealing as shown in FIG. 2A. The roughness of the resulting structure was characterized by atomic force microscopy (AFM). The root mean square (RMS) roughness of 5 nm AhCh / amorphous M0S3 was approximately 614 ± 54 pm without noticeable height variations, shown in FIGs. 2B, and 2C, indicating that 5 nm AI2O3 achieved complete, homogeneous coverage on the amorphous M0S3 surface. Subsequently, the sample was post-annealed at 650 °C to transform the amorphous M0S3 into crystalline M0S2 while retaining the 5 nm AI2O3 on top as shown in FIG. 2D. Remarkably, even after post-annealing, this heterostructure maintained its smoothness, with the RMS roughness of 529 ± 42 pm, shown in FIGs. 2E and 2F. This demonstrates the effectiveness of the process in preserving the surface smoothness while achieving the desired phase transition from amorphous M0S3 to crystalline M0S2.

[0019] Moreover, AhCh / spin-on M0S2 superlattices were demonstrated through a single step of post-annealing subsequent to vertically stacking AhCh / amorphous M0S3 heterolayers. FIG. 2G presents the EDS mapping of cs-TEM images of the AhCh / spin-on M0S2 heterostructures. Despite the AI2O3 layers being sandwiched between amorphous M0S3 and undergoing thermolysis into crystalline M0S2 in close proximity, sulfur and molybdenumatoms exhibit minimal diffusion into adjacent AI2O3 layers. Instead, they tend to remain confined within the crystalline M0S2 layers, contributing to the multilayer M0S2 formation with great crystallinity, shown in FIG. 2H. However, sulfur complexes and by-products in the gas phase during the conversion of M0S2 could pressurize adjacent oxide layers, resulting in structural damage if an excess of applied amorphous M0S3 is present during spin-coating.

[0020] Another embodiment uses the binding affinity of ALD-assisted oxide on spin-on M0S2 to assess if spin-on M0S2 is a feasible template for homogeneous oxide integration at a scale of a few nm. As shown in FIGs. 3A-3C, although the grain sizes of spin-on M0S2 prominently depend on post-annealing temperatures, individual spin-on M0S2 coalesces into polycrystalline films with sub-micron grains. FIG. 3 A shows the difference in the conversion from amorphous M0S3 at 450 °C, FIG. 3B shows it as 650 °C, and FIG. 3C at 850 °C.

[0021] It is well known that the grain boundaries (GB) of grown M0S2 could be multifarious: stitched GB, where two monolayer grains horizontally attach one the other in a layer, and van der Waals GB, where two individual monolayer grains stack vertically in overlaps. Inherent GBs of grown M0S2 arise strain and tensile forces along GBs and are relatively more reactive to initiate nucleation of ALD precursors for their direct chemisorption over M0S2 basal planes. The sub-micron grain boundaries of spin-on M0S2 possibly enable the creation of ultra-flat AI2O3 directly under a nanometer thickness region through the standard ALD.

[0022] The direct deposition of 3 nm AI2O3 was performed on spin-on M0S2 grown at 650 °C as illustrated in FIG. 4A. FIGs. 4B and C display the AFM result and the height profile along a white line on the surface of the AI2O3 / MOS2 heterostructure. No height variation is observable across the area of 50 x 50 pm, suggesting a remarkably uniform and conformally covered AI2O3 on M0S2. The corresponding RMS roughness is approximately 579.0 pm, which is lower than that of AhCh / a-MoSs. FIG. 4D shows the Raman spectroscopy, and 4E shows the photoluminescence spectra. FIG. 4F shows the molybdenum 3d core levels, andFIG. 4G shows the sulfur 2p core levels of XPS results. This is clearly distinct from the AI2O3 on reference M0S2 mechanically exfoliated from a bulk crystal shown in FIG. 5.

[0023] FIG. 5 A shows a schematic of an inhomogeneous AI2O3 film on reference M0S2 mechanically exfoliated from a crystal. FIG. 5B shows AFM height profiles of 5nm AI2O3 on M0S2. FIG. 5C shows height variation of a region along with a wight line depicted in FIG. 5B. In summary, the first of the above embodiments deposited the oxide prior to the annealing, and the second deposited the oxide after the annealing.

[0024] The results underwent evaluation of the quality of M0S2 with and without a top dielectric layer to confirm whether the subsequent ALD process degrades spin-on M0S2 in terms of optical and chemical properties. FIGs. 4D and 4E, shows Raman and PL spectra that exhibit no distinguishable changes before and after AI2O3 deposition. In accordance with that, AI2O3 / MOS2 sustains its chemical bonds at Mo 3d and S 2p core levels without any emerging peaks associated with additional oxidation compared to pristine M0S2.

[0025] Moreover, the EDS mapping and cs-STEM measurement were carried out on the AI2O3 / MOS2 heterostructure, as shown in FIGs. 4H and 41. The 3 nm AI2O3 conformally covers a single grain of spin-on M0S2 while any potential lattice structure distortion of M0S2 caused by AI2O3 is rarely seen at the nanoscale. Consequently, due to amorphous and polycrystalline features, spin-on TMD polymorphs offer substantial active sites for ALD precursors to promote chemisorption and coalesce on a conformal film even in a nanometer scale. Therefore, spin-on TMDs polymorphs enable the formation of heterogeneous gate insulator using the standard ALD, opening avenues for state-of-the-art device fabrication, compatible with conventional Si-based CMOS production processes.

[0026] As discussed above, this process may be used to produce various transistor types having an M0S2 channel with a gate oxide. In some embodiments, the gate oxide comprises AI2O3, spun on by any of the embodiments discussed above.

[0027] In FIG. 6, transistor 20 comprises a field-effect transistor (FET). The transistor has a source 22, a drain 24, a channel 25 comprised of M0S2 or WS2, a gate oxide 26 and a gate layer 28 on a substrate. Transistor 30 comprises a gate-all-around transistor, having a source 32, a drain 34, an M0S2 or WS2 channel 35, and gate oxide 36 and gate layer 38. The gate layer surrounds the device completely, and this view has a portion removed so the internal structures can be seen. Another embodiment involved a complementary FET structure in which devices are stacked on one footprint. In the embodiment of transistor 40, the first transistor 42 may comprise a gate-all-around transistor of a first polarity, such as N+or P', and the second transistor 44 may comprise the second polarity. Only two transistors are shown stacked here, but more could be stacked in an alternative polarity position, each one manufactured by the processes set out above.

[0028] All features disclosed in the specification, including the claims, abstract, and drawings, and all the steps in any method or process disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. Each feature disclosed in the specification, including the claims, abstract, and drawings, can be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly stated otherwise.

[0029] Additionally, this written description refers to particular features. It is to be understood that the disclosure in this specification includes all possible combinations of those particular features. For example, where a particular feature is disclosed in the context of a particular aspect, that feature can also be used, to the extent possible, in the context of other aspects.

[0030] Also, when reference is made in this application to a method having two or more defined steps or operations, the defined steps or operations can be carried out in any order or simultaneously, unless the context excludes those possibilities.

[0031] Although specific aspects of this disclosure have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A device, comprising: a source region; a drain region; a two-dimensional channel formed of one of either molybdenum disulfide (M0S2) or tungsten disulfide (WS2); a gate positioned to control flow of current between the source region and the drain region in the two-dimensional channel; and a gate oxide directly integrated on the channel between the gate and the channel.

2. The device as claimed in claim 1, wherein the device comprises one of a field-effect transistor (FET), a gate all around transistor, or a complementary FET.

3. The device as claimed in claim 1, wherein the source region is formed of one of a metal, a metallic material, or a combination of a metal and a metallic material.

4. The device as claimed in claim 1, wherein the drain region is formed of one of a metal, a metallic material, or a combination of a metal and a metallic material.

5. The device as claimed in claim 1, wherein the gate is positioned to surround the channel, separated by a gate oxide.

6. A method of forming a gate oxide, comprising: depositing a transition metal sulfur layer comprised of one or either amorphous MoSx or WSx on a substrate, where x >3; forming a layer of oxide on the transition metal sulfur layer; and annealing the transition metal sulfur to form one of either M0S2 or WS2.

7. The method as claimed in claim 6, wherein forming a layer of oxide comprises deposition prior to the annealing such that the annealing applies to both the transition metal and the oxide.

8. The method as claimed in claim 6, wherein forming a layer of oxide comprises depositing the layer of oxide after the annealing using atomic layer deposition.

9. The method as claimed in claim 6, wherein the layer of oxide has a thickness in a range of 1 nanometer to 1 micron.

10. The method as claimed in claim 6, wherein the layer of oxide comprises aluminum oxide (AI2O2).

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