Wiring substrate and preparation method therefor, and display apparatus

Abstract

Provided are a wiring substrate and a preparation method therefor, and a display apparatus. The wiring substrate comprises a base substrate, which comprises at least one bonding region and bending regions. The wiring substrate further comprises: a plurality of metal wiring layers, which are located above the base substrate; and a plurality of dielectric layers, wherein one dielectric layer is correspondingly arranged on the side of each of the plurality of metal wiring layers that is away from the base substrate, and each dielectric layer comprises an organic dielectric layer and an inorganic dielectric layer that are stacked, the orthographic projection of the organic dielectric layer on the base substrate not overlapping with the orthographic projection of the bonding region on the base substrate, and the orthographic projection of the inorganic dielectric layer on the base substrate at least partially overlapping with the orthographic projection of the bonding region on the base substrate.

Description

Wiring substrate, its fabrication method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a wiring substrate, a method for fabricating the same, and a display device. Background Technology

[0002] Large-sized electronic products such as LCD monitors, LCD TVs, and plasma TVs, as well as small and medium-sized electronic products such as mobile phones and digital cameras, are all trending towards thinner and lighter designs. This necessitates a new generation of packaging technologies that are high-density, small-volume, and allow for flexible installation to meet these requirements.

[0003] With the continuous development of 3D (3D) display technology, the market demand for 3D display products is rapidly increasing. Among the main development trends, increasing the resolution of 3D products (16K, 32K, etc.) to support the amount of information displayed is a key focus. To support technologies such as multi-viewpoints and X-Zone, 3D display products require a significantly increased number of data channels. For example, a 4K, 32View 3D light field display product requires 32K channels, a substantial increase compared to traditional 2D display products. Therefore, higher resolution IC packaging technology is needed to handle the massive data transmission. High-channel-count IC packaging technology, supporting more functions, has become a limiting factor for the future development of 3D display products.

[0004] The information disclosed in this section is only for understanding the background of the technical concept of this disclosure, and therefore may contain information that does not constitute prior art.

[0005] Summary of the Invention

[0006] In one aspect, a wiring substrate is provided, comprising: a substrate including at least one bonding region and a bending region;

[0007] The wiring substrate further includes:

[0008] A multilayer metal wiring layer is located above the substrate; and

[0009] A multilayer dielectric layer, wherein at least one of the multilayer metal wiring layers has at least one dielectric layer disposed on the side away from the substrate, wherein...

[0010] At least one of the dielectric layers includes an organic dielectric layer and an inorganic dielectric layer stacked together, wherein the orthographic projection of the organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate; and the orthographic projection of the inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the bonding region on the substrate.

[0011] According to some exemplary embodiments, the multilayer dielectric layer and the multilayer metal wiring layer located in the bonding region have a first thickness as a whole, and the multilayer dielectric layer and the multilayer metal wiring layer located in the bending region have a second thickness as a whole, wherein the first thickness is less than the second thickness.

[0012] According to some exemplary embodiments, the multilayer dielectric layer includes m layers, the m-layer dielectric layer includes an i-th dielectric layer, the i-th dielectric layer includes an i-th organic dielectric layer and an i-th inorganic dielectric layer, wherein the thickness of the i-th organic dielectric layer is greater than the thickness of the i-th inorganic dielectric layer, and m is a positive integer greater than or equal to 2, and i is a positive integer less than or equal to m.

[0013] According to some exemplary embodiments, the i-th inorganic dielectric layer includes a first portion located at the intersection of the bonding region and the bending region, wherein the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the i-th organic dielectric layer on the substrate.

[0014] According to some exemplary embodiments, the first portion of the i-th inorganic dielectric layer overlaps with the portion of the i-th organic dielectric layer projected onto the substrate with a first width, the first width being greater than or equal to 5 micrometers.

[0015] According to some exemplary embodiments, the multilayer dielectric layer includes m layers, the m-layer dielectric layer includes an i-th dielectric layer and an i+1-th dielectric layer, wherein the i-th dielectric layer includes an i-th inorganic dielectric layer, the i+1-th dielectric layer includes an i+1-th inorganic dielectric layer, the i+1-th inorganic dielectric layer is located on the side of the i-th inorganic dielectric layer away from the substrate, the i-th inorganic dielectric layer includes a first portion located at the intersection of the bonding region and the bending region, the i+1-th inorganic dielectric layer includes a first portion located at the intersection of the bonding region and the bending region; and the first portion of the i+1-th inorganic dielectric layer protrudes a first protrusion distance relative to the first portion of the i-th inorganic dielectric layer in a direction closer to the bending region, wherein the first protrusion distance is greater than or equal to 5 micrometers, and i is a positive integer less than or equal to m-1.

[0016] According to some exemplary embodiments, the dielectric layer m further includes an i-th organic dielectric layer and an i+1-th organic dielectric layer, wherein the i-th organic dielectric layer is located between the i-th inorganic dielectric layer and the i+1-th inorganic dielectric layer, and the i+1-th organic dielectric layer is located on the side of the i+1-th inorganic dielectric layer away from the substrate.

[0017] According to some exemplary embodiments, the dielectric layer m further includes an i-th organic dielectric layer and an i+1-th organic dielectric layer, wherein the i-th organic dielectric layer is located on the side of the i-th inorganic dielectric layer close to the substrate, and the i+1-th organic dielectric layer is located between the i-th inorganic dielectric layer and the i+1-th inorganic dielectric layer.

[0018] According to some exemplary embodiments, the wiring substrate further includes a green solder resist layer disposed on the side of the m-th dielectric layer away from the substrate, the green solder resist layer being located in the bending region; and

[0019] The orthographic projection of any organic dielectric layer contained in any of the m-layer dielectric layers onto the substrate falls within the orthographic projection of the green solder resist layer onto the substrate.

[0020] According to some exemplary embodiments, the green solder resist layer includes a first side edge near the bonding region, and the m-th organic dielectric layer includes a second side edge near the bonding region, wherein the first side edge and the second side edge are separated by a first spacing distance, the first spacing distance being greater than or equal to 50 micrometers.

[0021] According to some exemplary embodiments, the orthographic projection of the i-th organic dielectric layer on the substrate falls within the orthographic projection of the (i+1)-th organic dielectric layer on the substrate.

[0022] According to some exemplary embodiments, the side of the i-th organic dielectric layer near the bonding region is separated from the side of the (i+1)-th organic dielectric layer near the bonding region by a second spacing distance, the second spacing distance being greater than or equal to 10 micrometers.

[0023] According to some exemplary embodiments, the multilayer metal wiring layer includes a plurality of pin transitions, the pin transitions being at least partially located in the bonding region; and

[0024] The inorganic dielectric layer includes a plurality of first openings located in the bonding region, wherein at least one of the first openings exposes a portion of at least one of the pin transition portions.

[0025] According to some exemplary embodiments, the wiring substrate further includes a metal bonding layer disposed on the side of the m-th dielectric layer away from the substrate, the metal bonding layer including a plurality of pins, at least one of the pins being electrically connected to at least one of the pin adapters through at least the first opening.

[0026] According to some exemplary embodiments, the wiring substrate further includes an IC chip disposed on the side of the metal bonding layer away from the substrate, the IC chip being electrically connected to a plurality of the pins; and

[0027] The bonding region includes a chip bonding region, wherein the IC chip is located in the chip bonding region, and the boundary of the IC chip is at least 100 micrometers away from the boundary of the green solder resist layer.

[0028] According to some exemplary embodiments, the m-layer dielectric layer comprises m inorganic dielectric layers, each of which includes a second opening located in the bending region; and

[0029] The orthographic projections of the second openings in any two inorganic dielectric layers of the m-layer inorganic dielectric layer on the substrate at least partially overlap; or...

[0030] The second openings in any two inorganic dielectric layers of the m-layer inorganic dielectric layer have completely overlapping orthogonal projections onto the substrate.

[0031] According to some exemplary embodiments, the second opening in any one of the m inorganic dielectric layers has a second width along a first direction, the second width being greater than or equal to 1 mm and less than or equal to 10 mm, wherein the first direction is the direction from the bonding region toward the bending region.

[0032] In another aspect, a method for fabricating a wiring substrate is provided, comprising: providing a substrate, the substrate including at least one bonding region and a bending region;

[0033] Multiple metal wiring layers and multiple dielectric layers are sequentially formed on the substrate. Each of the multiple metal wiring layers has a dielectric layer disposed on the side furthest from the substrate.

[0034] Each of the dielectric layers includes an organic dielectric layer and an inorganic dielectric layer stacked together, wherein the orthographic projection of the organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate; and the orthographic projection of the inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the bonding region on the substrate.

[0035] According to some exemplary embodiments, the multilayer metal wiring layer includes m layers, and forming the multilayer metal wiring layer and the multilayer dielectric layer includes:

[0036] A first metal wiring layer is formed on the substrate, and a patterning process is performed on the first metal wiring layer.

[0037] A first dielectric layer is formed on the side of the first metal wiring layer away from the substrate, wherein,

[0038] Forming the first dielectric layer includes: forming a first inorganic dielectric layer and performing a patterning process on the first inorganic dielectric layer to form a plurality of first openings located in the bonding region; and

[0039] A first organic dielectric layer is formed, and a patterning process is performed on the first organic dielectric layer so that the orthographic projection of the first organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate.

[0040] Repeat the above steps for fabricating metal wiring layers and dielectric layers to form m alternating metal wiring layers and m dielectric layers, thereby forming the multilayer metal wiring layers and multilayer dielectric layers, where m is a positive integer greater than or equal to 2.

[0041] In another aspect, a display device is provided, wherein the display device includes a wiring substrate as described in any of the preceding claims. Attached Figure Description

[0042] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0043] FIG1 is a plan view of a wiring substrate according to some exemplary embodiments of the present disclosure; FIG2 is a plan view of a wiring substrate according to some other exemplary embodiments of the present disclosure;

[0044] Figure 3 is a partial cross-sectional view of the bonding area in the wiring substrate taken along line AA' in Figure 1;

[0045] Figures 4A-C are partial planar schematic diagrams of the bonding region in a wiring substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 5A is a plan view of a wiring substrate according to an embodiment of the present disclosure; Figure 5B is a plan view of a wiring substrate according to an embodiment of the present disclosure.

[0047] Figure 6 is a partial cross-sectional view of a wiring substrate of some embodiments taken along line BB' in Figure 2, showing two metal wiring layers;

[0048] Figure 7 is a partial cross-sectional view of a wiring substrate of some other embodiments taken along line BB' in Figure 2, showing three metal wiring layers;

[0049] Figure 8 is a locally enlarged cross-sectional schematic diagram of region S in Figure 6;

[0050] Figure 9 is a partially enlarged cross-sectional schematic diagram of a wiring substrate according to some other embodiments of the present disclosure;

[0051] Figure 10 is a schematic plan view of a wiring substrate according to some other exemplary embodiments of the present disclosure;

[0052] Figure 11 is a partial cross-sectional view of a wiring substrate of some embodiments taken along line BB' in Figure 2, showing two metal wiring layers;

[0053] Figure 12 is a partial cross-sectional view of a wiring substrate of some other embodiments taken along line BB' in Figure 2, showing three metal wiring layers;

[0054] Figure 13 is a flowchart of a method for fabricating a wiring substrate according to an embodiment of the present disclosure;

[0055] Figure 14 is a flowchart of the specific steps in the SO2 step of the preparation method according to Figure 13;

[0056] Figures 15A-15F are schematic cross-sectional views of partial structures during the fabrication process of a wiring substrate according to some exemplary embodiments of the present disclosure;

[0057] Figure 16 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0058] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of the present invention may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0061] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0062] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0063] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0064] It should be noted that in this paper, "the same layer" refers to a layer structure formed by using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask to pattern this film layer in a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and formed by the same single patterning process. These specific patterns may also be at different heights or have different thicknesses.

[0065] In this document, unless otherwise stated, the term "electrical connection" can mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and an electrical signal can be transmitted between them; it can also mean that two components or elements are electrically connected through a conductive medium, such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit an electrical signal between the two components or elements; it can also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit an electrical signal between the two components or elements.

[0066] Those skilled in the art will understand that, unless otherwise stated, the terms “height” or “thickness” herein refer to the dimensions of the surfaces of the individual film layers disposed perpendicular to the substrate.

[0067] Large-size electronic products such as LCD monitors, LCD TVs, and plasma TVs, as well as small-to-medium-size electronic products such as mobile phones and digital cameras, are all trending towards thinner and lighter designs. This necessitates a new generation of packaging technologies that offer high density, small size, and flexible mounting capabilities to meet these demands. COF (Chip On Film) packaging technology emerged to address this need. In COF packaging, chips (source driver ICs or gate driver ICs) are bonded and mounted on a flexible wiring substrate with a formed wiring pattern. The COF wiring pattern consists of internal leads connected to the chip's electrodes and external leads connected to external circuitry.

[0068] With the continuous development of 3D display technology, the market demand for 3D display products is rapidly increasing. The main development trend of 3D products is the continuous improvement of resolution (16K, 32K, etc.) to support the amount of information in 3D displays. As resolution increases, the number of signal transmission channels required for display products also increases significantly. Taking 4K, 32-view 3D light field display products as an example, the required number of channels is 32K, a significant increase compared to traditional 2D display products. Therefore, higher resolution IC packaging technology is needed to meet the massive data transmission and support more functions. High-channel-count IC packaging technology has become a limiting factor for the future development of 3D display products. Currently, COF products on the market are all manufactured using roll-to-roll technology and can be divided into single-sided COF and double-sided COF. Due to the limitations of the Cu process trace spacing in roll-to-roll technology, the minimum linewidth of COF can only reach 16um, and the number of metal layers can only be single or double. Therefore, it cannot meet the needs of 3D display products with more than 5000 chip pins.

[0069] In related technologies, multilayer wiring is used to increase the number of traces, with PSPI (photosensitive polyimide resin) used as an insulating layer between the multilayer traces. However, the Tg (glass transition temperature) of PSPI is around 300°C, while the IC bonding conditions in COF are typically above 400°C and above 100 MPa. Under these bonding conditions, the PSPI material in the bonding area is prone to deformation leading to cracks, and may also release gas, causing film peeling and resulting in defects.

[0070] In some embodiments of this disclosure, a wiring substrate is provided. The wiring substrate includes: a substrate including at least one bonding region and a bending region; the wiring substrate further includes: multiple metal wiring layers located above the substrate; and multiple dielectric layers, wherein each of the multiple metal wiring layers has a dielectric layer disposed on the side away from the substrate, wherein each dielectric layer includes a stacked organic dielectric layer and an inorganic dielectric layer, wherein the orthographic projection of the organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate. The orthographic projection of the inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the bonding region on the substrate.

[0071] By removing the organic dielectric layer in the bonding region and using an inorganic dielectric layer as the insulating layer, the bonding yield can be improved due to the high temperature resistance of the inorganic dielectric layer.

[0072] FIG1 is a plan view of a wiring substrate according to some exemplary embodiments of the present disclosure; FIG2 is a plan view of a wiring substrate according to some other exemplary embodiments of the present disclosure.

[0073] In some embodiments of this disclosure, referring to FIG1, the wiring substrate 100 may include a substrate 1, which includes at least one bonding region 2 and a bending region. The bonding region may be an area for connecting pins located in the bonding region of the wiring substrate to other components (e.g., IC chips, display panels, PCB boards, etc.) by bonding. The bending region may be a portion of the wiring substrate excluding the bonding region. Exemplarily, the bonding region 2 may include multiple bonding regions located at both ends of the bending region. For example, the bonding region 2 may include a chip bonding region and a panel bonding region, and the bonding region may include at least one pin for bonding to other components. For example, an IC chip may be bonded to pins located in the chip bonding region, and a display panel may be bonded to pins located in the panel bonding region.

[0074] With this design, the IC chip can transmit signals to the display panel.

[0075] In some embodiments, the wiring substrate may include an IC chip located in the chip bonding area.

[0076] In some embodiments, the wiring substrate may not include the IC chip located in the chip bonding area.

[0077] The bending area is located between the panel bonding area and the chip bonding area. The bending area can be bent, thereby improving the flexibility of the wiring substrate, reducing the space occupied by the wiring substrate, and achieving narrow bezel or even bezel-less display effects.

[0078] Exemplary examples, in some embodiments of this disclosure, referring to FIG2, the bonding area of ​​the wiring substrate may further include a circuit board bonding area (PCB bonding area). Pins in the wiring substrate can be connected to the PCB board via the PCB bonding area. The PCB bonding area can be connected to the chip bonding area via metal wires 106 in the input channel.

[0079] For example, the bending area may also include a portion located between the chip bonding area and the PCB board bonding area.

[0080] Figure 3 is a partial cross-sectional view of the bonding region in the wiring substrate taken along line AA' in Figure 1; Figures 4A-C are partial planar schematic diagrams of the bonding region in the wiring substrate according to exemplary embodiments of the present disclosure.

[0081] Exemplary examples, in some embodiments of this disclosure, referring to FIG3, the wiring substrate includes a substrate 1 and a multilayer metal wiring layer 102. The multilayer metal wiring layer 102 is located above the substrate 1. The wiring substrate may also include a multilayer dielectric layer 104. For example, at least one dielectric layer 104 is disposed on the side of the multilayer metal wiring layer 102 away from the substrate. The dielectric layer 104 may be made of an insulating material to ensure that some metal lines in adjacent metal wiring layers are insulated from each other, thereby enabling multilayer wiring in a limited space and increasing the number of signal transmission channels. For example, the multilayer metal wiring layer may include two, three, four, or more metal wiring layers, and the embodiments of this disclosure do not specifically limit this.

[0082] By way of example, referring to Figures 1 and 3, a three-layer multilayer metal wiring layer is used as an example. The three-layer metal wiring layer 102 includes a plurality of pin adapters 105. The pin adapters 105 are at least partially located in the bonding region. A plurality of adapter holes VH are provided on the multilayer dielectric layer 104. At least a portion of the metal lines located in different layers can be electrically connected through the adapter holes VH.

[0083] The wiring substrate also includes a metal bonding layer 10 disposed on the side of the dielectric layer 104 away from the substrate, and the metal bonding layer 10 may include a plurality of pins 103.

[0084] For example, the plurality of pins 103 may include a plurality of pins located in the chip bonding area for bonding connection with the IC chip.

[0085] For example, the plurality of pins 103 may also include a plurality of pins located in the panel bonding area or the PCB board bonding area for bonding connection with the panel or bonding connection with the PCB board.

[0086] For example, at least one pin adapter 105 in at least one metal wiring layer can be connected to the pin 103 via at least one adapter hole. For instance, referring to FIG3, the pin adapter 1051 in the first metal wiring layer 1021 is connected to the top pin 103 via three adapter holes. The pin adapter 1052 in the second metal wiring layer 1022 is connected to the top pin 103 via two adapter holes. The pin adapter 1053 in the third metal wiring layer 1023 is connected to the top pin 103 via one adapter hole.

[0087] For example, the material of pin 103 may be copper.

[0088] Exemplary examples, in embodiments of this disclosure, the metal wiring layer in the wiring substrate may include a single-layer metal wiring layer (as shown in FIG. 4A), a double-layer metal wiring layer (as shown in FIG. 4B), a triple-layer metal wiring layer (as shown in FIG. 4C), or more layers of metal wiring layers. Referring to FIG. 4A-C, the orthographic projections of the pins 103 on the substrate do not overlap. The orthographic projections of the pin adapters 105 on the substrate do not overlap. The orthographic projections of the metal lines 106 on the substrate may not overlap, may overlap, or may partially overlap. The orthographic projections of the pins 103 and their corresponding pin adapters 105 on the substrate partially overlap.

[0089] For example, referring to Figure 4B, the orthographic projections of the metal lines 106 in a double-layer metal wiring layer onto the substrate may not overlap. As another example, referring to Figure 4C, at least a portion of the orthographic projections of the metal lines 106 in a triple-layer metal wiring layer partially overlap onto the substrate. For wiring substrates with the same planar area, the more metal wiring layers there are, the more metal lines can be arranged, providing more output channels for the chip.

[0090] The inventors discovered that the performance of the multiple dielectric layers in a multilayer metal wiring layer significantly impacts the bending performance and bonding yield of the wiring substrate. For example, in the bending region, PSPI (photosensitive polyimide resin) as an insulating layer can improve the bending performance. However, in the bonding region, the Tg (glass transition temperature) of PSPI is around 300°C, while the bonding conditions for IC chips in the bonding region are typically above 400°C and 100 MPa. Under these bonding conditions, if PSPI is used as the dielectric layer in the bonding region, deformation can easily occur, leading to cracks, and gas release may cause film peeling, resulting in defects. Therefore, in the bonding region, the dielectric layer needs to have better high-temperature resistance to meet the high-temperature bonding conditions and improve the bonding yield.

[0091] In some embodiments of this disclosure, the multilayer dielectric layer between the multilayer metal wiring layers in the bonding region can be an inorganic dielectric layer. Since the inorganic dielectric layer has high temperature resistance, the bonding yield can be improved.

[0092] Figure 5A is a plan view of a wiring substrate according to an embodiment of the present disclosure; Figure 5B is a plan view of a wiring substrate according to an embodiment of the present disclosure.

[0093] Exemplary examples, in some embodiments of this disclosure, the bonding region may include an inorganic insulating layer. For instance, in FIG. 5A, the dashed regions M1 and M2 can be bonding regions; for example, dashed region M1 may be a panel bonding region, and dashed region M2 may be a chip bonding region. The panel bonding region or chip bonding region may include an inorganic insulating layer to achieve partial insulation between the multiple metal layers located within the bonding region. The bending region may include an organic insulating layer. For example, in FIG. 5B, the portion of dashed region M3 excluding dashed region M2 can be a bending region. The bending region may include an organic insulating layer to achieve partial insulation between the multiple metal layers located within the bending region. This design ensures insulation between the multiple metal wiring layers while maintaining the bending performance of the bending region and the high-temperature resistance of the dielectric layer in the bonding region. Removing the organic insulating layer within the bonding region prevents damage to the organic layer during bonding, avoids short circuits in the metal wiring layers, and improves the bonding yield of the IC chip.

[0094] Figure 6 is a partial cross-sectional view of a wiring substrate according to some embodiments of the present disclosure, taken along line BB' in Figure 2, showing two metal wiring layers; Figure 7 is a partial cross-sectional view of a wiring substrate according to some other embodiments of the present disclosure, taken along line BB' in Figure 2, showing three metal wiring layers.

[0095] For example, in some embodiments of this disclosure, referring to FIG2 and FIG6, the wiring substrate 100 may include a panel bonding area and a chip bonding area, as well as a bending area located between the panel bonding area and the chip bonding area, such as a first bending area. The wiring substrate may also include a bending area located between the chip bonding area and the PCB board bonding area, such as the second bending area located to the right of the chip bonding area shown in FIG6.

[0096] Referring again to FIG6, the wiring substrate 100 may include a substrate 1. Exemplarily, the substrate 1 may be a flexible film. For example, the flexible film may be made of polyimide (PI) with a thickness between 10 μm and 40 μm.

[0097] In some embodiments, the wiring substrate may further include a water-insulating inorganic film 2 located between the substrate and the multilayer metal wiring layers. Exemplarily, the water-insulating inorganic film 2 may be made of silicon dioxide or silicon nitride, and its thickness may be between 10 nm and 200 nm. The water-insulating inorganic film 2 on the wiring substrate can prevent the polyimide from absorbing water.

[0098] To improve the bending performance of the substrate, the thickness of the substrate 1 can be 30 μm, and the thickness of the water-insulating inorganic film 2 on the surface of the substrate can be between 50 nm and 100 nm.

[0099] For example, the wiring substrate may further include a multilayer metal wiring layer 102 and a multilayer dielectric layer 104 sequentially stacked on the side of the water-insulating inorganic film 2 away from the substrate.

[0100] In some embodiments, the multilayer metal wiring layer includes m layers, and the multilayer dielectric layer includes m layers, where m can be 2, 3, or other positive integers greater than 3. The number of dielectric layers is related to the number of metal wiring layers, ensuring that at least one dielectric layer is provided between every two metal wiring layers.

[0101] In some embodiments, the number of multilayer metal wiring layers is two, and the number of dielectric layers is two. For example, referring to FIG6, the wiring substrate may include: a first metal wiring layer 1021 disposed on the side of the water-insulating inorganic film 2 away from the substrate 1; a first dielectric layer 1041 disposed on the side of the first metal wiring layer 1021 away from the substrate 1; a second metal wiring layer 1022 disposed on the side of the first dielectric layer 1041 away from the substrate 1; and a second dielectric layer 1042 disposed on the side of the second metal wiring layer 1022 away from the substrate 1.

[0102] In some embodiments, the number of metal wiring layers is three, and the number of dielectric layers is three. For example, referring to FIG7, the wiring substrate may include: a first metal wiring layer 1021 disposed on the side of the water-insulating inorganic film 2 away from the substrate 1; a first dielectric layer 1041 disposed on the side of the first metal wiring layer 1021 away from the substrate 1; a second metal wiring layer 1022 disposed on the side of the first dielectric layer 1041 away from the substrate 1; a second dielectric layer 1042 disposed on the side of the second metal wiring layer 1022 away from the substrate 1; a third metal wiring layer 1023 disposed on the side of the second dielectric layer 1042 away from the substrate 1; and a third dielectric layer 1043 disposed on the side of the third metal wiring layer 1023 away from the substrate 1.

[0103] By way of example, referring to Figures 6 and 7, the wiring substrate may further include a metal bonding layer 10 located on the side of the m-th dielectric layer (the dielectric layer furthest from the substrate in the multilayer dielectric layers) away from the substrate. At least one dielectric layer is also disposed between the topmost metal wiring layer (the layer furthest from the substrate in the multilayer metal wiring layers) and the metal bonding layer. For example, in Figure 6, a second dielectric layer 1042 is disposed between the second metal wiring layer 1022 and the metal bonding layer 10. As another example, in Figure 7, a third dielectric layer 1043 is disposed between the third metal wiring layer 1023 and the metal bonding layer 10.

[0104] For example, at least one dielectric layer may include stacked organic dielectric layers and inorganic dielectric layers. For instance, in some embodiments, the number of dielectric layers is m, where m is a positive integer greater than or equal to 2. The m dielectric layers may include the i-th dielectric layer, where i is a positive integer less than or equal to m. The i-th dielectric layer includes the i-th organic dielectric layer and the i-th inorganic dielectric layer. The thickness of the i-th organic dielectric layer is greater than the thickness of the i-th inorganic dielectric layer. Taking a wiring substrate in FIG. 6 containing two metal wiring layers and two dielectric layers as an example, the first dielectric layer 1041 includes a first organic dielectric layer OL1041 and a first inorganic dielectric layer IL1041, with the first inorganic dielectric layer IL1041 located on the side of the first organic dielectric layer OL1041 closest to the substrate 1. The thickness h1 of the first organic dielectric layer OL1041 is greater than the thickness h2 of the first inorganic dielectric layer IL1041. The second dielectric layer 1042 includes a second organic dielectric layer OL1042 and a second inorganic dielectric layer IL1042, with the second inorganic dielectric layer IL1042 located on the side of the second organic dielectric layer OL1042 closest to the substrate 1. The thickness h3 of the second organic dielectric layer OL1042 is greater than the thickness h4 of the second inorganic dielectric layer IL1042. It should be noted that in this embodiment, the number of layers in the multilayer metal wiring layer includes two layers, but the embodiments of this disclosure are not limited to this; the multilayer metal wiring layer may include more layers, and the corresponding multilayer dielectric layer may also include more layers.

[0105] For example, in the bonding region, the organic dielectric layer contained in each of the multilayer dielectric layers is removed within the area of ​​the bonding region, ensuring that the orthographic projection of the organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate, thereby avoiding damage to the organic dielectric layer caused by high temperatures during the bonding process. For example, continuing to refer to FIG6, in the chip bonding region or panel bonding region, both the first organic dielectric layer OL1041 and the second organic dielectric layer OL1042 are removed.

[0106] To ensure insulation between the multiple metal wiring layers in the bonding region, at least a portion of the inorganic dielectric layer between the multiple metal wiring layers is retained as an insulating layer. The orthographic projection of the inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the bonding region on the substrate. For example, continuing to refer to FIG6, a first inorganic dielectric layer IL1041 is disposed between the first metal wiring layer 1021 and the second metal wiring layer 1022 in the bonding region. A second inorganic dielectric layer IL1042 is disposed between the second metal wiring layer 1022 and the metal bonding layer 10.

[0107] For example, the inorganic dielectric layer in the bonding region can be made of materials such as silicon oxide or silicon nitride as an insulating layer.

[0108] For example, a multilayer metal wiring layer includes a plurality of pin adapters 105, each pin adapter 105 being at least partially located in a bonding region. For instance, at least one metal wiring layer includes at least one pin adapter for electrically connecting a metal wire in that layer to a pin in a metal bonding layer. For example, a first metal wiring layer 1021 includes at least one pin adapter 1051 for connecting a metal wire in the first metal wiring layer to a pin. A second metal wiring layer 1022 includes at least one pin adapter 1052 for connecting a metal wire in the second metal wiring layer to a pin.

[0109] The inorganic dielectric layer includes a plurality of first openings VH1 located in the bonding region. At least one first opening VH1 exposes a portion of at least one pin transition portion 105. The metal bonding layer 10 includes a plurality of pins 103, at least one pin 103 being electrically connected to at least one pin transition portion 105 through at least one first opening VH1. For example, referring to FIG6, the inorganic dielectric layer includes a first inorganic dielectric layer IL1041 and a second inorganic dielectric layer IL1042. The first inorganic dielectric layer IL1041 includes at least one first opening VH11 located in the first inorganic dielectric layer, thereby forming a transition via, such that at least one pin transition portion 1051 located in a first metal wiring layer is electrically connected to a portion of a conductive component in a second metal wiring layer. The second inorganic dielectric layer IL1042 includes at least one first opening VH12 located in the second inorganic dielectric layer, thereby forming a transition hole, such that at least one pin transition portion 1052 located in the second metal wiring layer is electrically connected to at least one pin 103 in the metal bonding layer 10, or such that a conductive component located in the second metal wiring layer 1022 and connected to the pin transition portion 1051 in the first metal wiring layer 1021 is electrically connected to at least one pin 103 in the metal bonding layer 10.

[0110] It should be noted that the above embodiments illustratively illustrate that when the number of metal wiring layers is two, the pin transition portions 105 in different metal wiring layers 102 in the bonding region are electrically connected to the pins 103 in the metal bonding layer 10 through the transition holes formed by the first opening VH1. However, the embodiments of this disclosure are not limited to this. The number of metal wiring layers may also include three or more layers, and the electrical connection method between the pin transition portions 105 in different metal wiring layers 102 and the pins 103 in the metal bonding layer 10 is similar to the connection method in the embodiments with two metal wiring layers, and will not be described again here.

[0111] By setting multiple first openings VH1 on the inorganic dielectric layer in the bonding region, multiple pin adapters 105 in the multilayer metal wiring layer can be connected to multiple pins 103 in the metal bonding layer 10 respectively, thereby realizing the electrical connection between the metal lines in different metal wiring layers and external signal lines or pins.

[0112] In some embodiments, the material in the metal wiring layer can be a metallic material composed of at least one of aluminum, copper, titanium, molybdenum, and nickel, with a thickness between 300 nm and 1000 nm. The metal wiring layer can also be a multilayer alloy composed of these metals, such as a Ti / Al / Ti alloy, a MoTiNi / Cu / MoTiNi alloy, etc. To improve the conductivity of the metallic properties, a multilayer copper alloy, such as a Mo / Cu / Mo alloy, can be selected, with a thickness between 300 nm and 1000 nm.

[0113] For example, in the bending region, the organic dielectric layer included in the multilayer dielectric layer can be retained, thereby improving the bending performance of the bending region. The multilayer dielectric layer can include two, three, or more dielectric layers. For instance, referring to FIG6, the first organic dielectric layer OL1041 and the second organic dielectric layer OL1042 are retained in the bending region. As another example, referring to FIG7, the first organic dielectric layer OL1041, the second organic dielectric layer OL1042, and the third organic dielectric layer OL1043 are retained in the bending region.

[0114] For example, the organic dielectric layer in the bending region can be PSPI (photosensitive polyimide resin) as the insulating layer. PSPI has a high elongation at break (>40%), a low Young's modulus (<10 GPa), which can meet the bending performance of the substrate, and a low dielectric constant (≤3.0 / GHz), which can reduce crosstalk between output signals.

[0115] For example, in the bending region, the inorganic dielectric layer contained in the multilayer dielectric layer can be designed to be disconnected. For instance, most of the inorganic dielectric layer in the bending region can be removed, leaving only a small portion of the inorganic dielectric layer at the junction with the bonding region. The junction of the bending region and the bonding region refers to the surrounding area of ​​the boundary shared by the bonding region and the bending region, which may include a portion of the bonding region and a portion of the bending region, as well as the boundary shared by the bending region and the bonding region. For example, referring to FIG5B, the junction of the bending region and the bonding region may include the region M4 near the boundary N1 shared by the bending region and the bonding region. Due to the brittleness of the inorganic dielectric layer, it is prone to fracture during bending. By adopting a design that removes most of the inorganic dielectric layer in the bending region, the impact of the inorganic dielectric layer in the bending region on the bending performance can be reduced.

[0116] Figure 8 is a locally enlarged cross-sectional schematic diagram of region S in Figure 6.

[0117] In some embodiments, the multilayer dielectric layer and the multilayer metal wiring layer located in the bonding region have a first thickness H1, and the multilayer dielectric layer and the multilayer metal wiring layer located in the bending region have a second thickness H2. The first thickness H1 is less than the second thickness H2. For example, when the number of multilayer metal wiring layers is two, referring to FIG8, in the bonding region, the multilayer metal wiring layer includes a first metal wiring layer 1021 and a second metal wiring layer 1022, and the multilayer dielectric layer includes a first inorganic dielectric layer IL1041 and a second inorganic dielectric layer IL1042. The total thickness of the first metal wiring layer 1021, the second metal wiring layer 1022, the first inorganic dielectric layer IL1041, and the second inorganic dielectric layer IL1042 in the bonding region is H1. In the bending region, the multilayer metal wiring layer includes a first metal wiring layer 1021 and a second metal wiring layer 1022, and the multilayer dielectric layer includes a first inorganic dielectric layer IL1041, a second inorganic dielectric layer IL1042, a first organic dielectric layer OL1041, and a second organic dielectric layer OL1042. In the bending region, the overall thickness of the six layers—the first metal wiring layer 1021, the second metal wiring layer 1022, the first inorganic dielectric layer IL1041, the second inorganic dielectric layer IL1042, the first organic dielectric layer OL1041, and the second organic dielectric layer OL1042—is H2. Exemplarily, H1 is less than H2.

[0118] This design allows the overall film layer of the multilayer dielectric and multilayer metal wiring layers in the bonding region to form a groove structure relative to the overall film layer of the multilayer dielectric and multilayer metal wiring layers in the bending region, which helps to reduce the thickness of the bonding region. After subsequent bonding of the IC chip, maintaining a small overall thickness of the wiring substrate facilitates the thinner and lighter design of the display device.

[0119] In some embodiments, the number of dielectric layers is m, where m is a positive integer greater than or equal to 2. The inorganic dielectric layer included in the m dielectric layers may include a first portion P1 located at the intersection of the bonding region and the bending region. For example, the m dielectric layers may include an i-th dielectric layer, where i is a positive integer less than or equal to m. The i-th dielectric layer includes an i-th organic dielectric layer and an i-th inorganic dielectric layer. The i-th inorganic dielectric layer includes a first portion P1i located at the intersection of the bonding region and the bending region, and the orthographic projection of the first portion P1i of the i-th inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the i-th organic dielectric layer on the substrate. The overlapping portion of the first portion P1i of the i-th inorganic dielectric layer and the projection of the i-th organic dielectric layer on the substrate has a first width d1i, where the first width d1i is greater than or equal to 5 micrometers.

[0120] For example, referring to Figures 6 and 8, the multilayer dielectric layer 104 has two layers, including a first dielectric layer 1041 and a second dielectric layer 1042. The first dielectric layer 1041 includes a first inorganic dielectric layer IL1041 and a first organic dielectric layer OL1041. The first inorganic dielectric layer IL1041 includes a first portion P11 located at the intersection of the bonding region and the bending region. The orthographic projection of the first portion P11 in the first inorganic dielectric layer IL1041 onto the substrate at least partially overlaps with the orthographic projection of the first organic dielectric layer OL1041 onto the substrate. The width d11 of the overlapping portion of the projections of the first portion P11 in the first inorganic dielectric layer IL1041 and the first organic dielectric layer OL1041 onto the substrate is greater than or equal to 5 micrometers. The second inorganic dielectric layer IL1042 includes a first portion P12 located at the intersection of the bonding region and the bending region. The orthographic projection of the first portion P12 of the second inorganic dielectric layer IL1042 onto the substrate at least partially overlaps with the orthographic projection of the second organic dielectric layer OL1042 onto the substrate. The width d12 of the overlapping portion of the projections of the first portion P12 of the second inorganic dielectric layer IL1042 and the second organic dielectric layer OL1042 onto the substrate is greater than or equal to 5 micrometers.

[0121] For example, referring to Figure 7, the multilayer dielectric layer has three layers, including a third dielectric layer 1043. The third inorganic dielectric layer IL1043 includes a first portion P13 located at the intersection of the bonding region and the bending region. The orthographic projection of the first portion P13 of the third inorganic dielectric layer IL1043 onto the substrate at least partially overlaps with the orthographic projection of the third organic dielectric layer OL1043 onto the substrate. The width d13 of the overlapping portion of the projections of the first portion P13 of the third inorganic dielectric layer IL1043 and the third organic dielectric layer OL1043 onto the substrate is greater than or equal to 5 micrometers.

[0122] In the embodiments of this disclosure, the inorganic dielectric layer and the organic dielectric layer in each dielectric layer located at the junction of the bending region and the bonding region have at least partial overlap on the substrate, thereby ensuring the insulation effect at the junction of the bending region and the bonding region and avoiding short circuits between the metal wiring layers.

[0123] In some embodiments, the multilayer dielectric layer includes m layers, which include an i-th dielectric layer and an (i+1)-th dielectric layer. The i-th dielectric layer includes an i-th inorganic dielectric layer, and the (i+1)-th dielectric layer includes an (i+1)-th inorganic dielectric layer. The (i+1)-th inorganic dielectric layer is located on the side of the i-th inorganic dielectric layer away from the substrate, where i is a positive integer less than or equal to m-1. The i-th inorganic dielectric layer includes a first portion located at the intersection of the bonding region and the bending region, and the (i+1)-th inorganic dielectric layer also includes a first portion located at the intersection of the bonding region and the bending region. The first portion of the (i+1)-th inorganic dielectric layer protrudes a first protrusion distance m1 relative to the first portion of the i-th inorganic dielectric layer in a direction closer to the bending region, wherein the first protrusion distance m1 is greater than or equal to 5 micrometers.

[0124] For example, taking a metal wiring layer with 2 layers as an example, referring to Figure 8, the first protrusion distance m1 of the first part P12 of the second inorganic dielectric layer IL1042 protruding relative to the first part P11 of the first inorganic dielectric layer IL1041 in the direction closer to the bending area is greater than or equal to 5 micrometers.

[0125] In some embodiments, the number of metal wiring layers can be more, such as 3, 4, or more layers. Correspondingly, the number of dielectric layers can also be 3, 4, or more layers. Taking a dielectric layer with 3 layers as an example, the first protrusion distance of the first portion of the second inorganic dielectric layer protruding relative to the first portion of the first inorganic dielectric layer in the direction near the bending region can be greater than or equal to 5 micrometers. The first protrusion distance of the first portion of the third inorganic dielectric layer protruding relative to the first portion of the second inorganic dielectric layer in the direction near the bending region can also be greater than or equal to 5 micrometers.

[0126] By designing the boundary wrapping relationship of multiple inorganic dielectric layers, short circuits between adjacent metal layers can be prevented.

[0127] Exemplarily, the m-layer dielectric layer may further include an i-th organic dielectric layer and an i+1-th organic dielectric layer. The i-th organic dielectric layer is located between the i-th inorganic dielectric layer and the i+1-th inorganic dielectric layer, and the i+1-th organic dielectric layer is located on the side of the i+1-th inorganic dielectric layer away from the substrate. That is, in some embodiments, the organic dielectric layer included in each dielectric layer is located on the side of the corresponding inorganic dielectric layer away from the substrate. For example, referring to FIG8, the metal wiring layer has two layers, with the first organic dielectric layer OL1041 located on the side of the first inorganic dielectric layer IL1041 away from the substrate 1, the second inorganic dielectric layer IL1042 located on the side of the first organic dielectric layer OL1041 away from the substrate, and the second organic dielectric layer OL1042 located on the side of the second inorganic dielectric layer IL1042 away from the substrate 1.

[0128] Figure 9 is a partially enlarged cross-sectional schematic diagram of a wiring substrate according to some other embodiments of the present disclosure.

[0129] In some embodiments, the m-layer dielectric layer further includes an i-th organic dielectric layer and an i+1-th organic dielectric layer. The i-th organic dielectric layer is located on the side of the i-th inorganic dielectric layer closest to the substrate, and the i+1-th organic dielectric layer is located between the i-th and i+1-th inorganic dielectric layers. That is, in some embodiments, the inorganic dielectric layer included in each dielectric layer may be located on the side of the corresponding organic dielectric layer furthest from the substrate. For example, referring to FIG9, the metal wiring layer has two layers. The first inorganic dielectric layer IL1041 is located on the side of the first organic dielectric layer OL1041 furthest from the substrate 1, the second organic dielectric layer OL1042 is located on the side of the first inorganic dielectric layer IL1041 furthest from the substrate 1, and the second inorganic dielectric layer IL1042 is located on the side of the second organic dielectric layer OL1042 furthest from the substrate 1.

[0130] In some embodiments, for a wiring substrate including m dielectric layers, a portion of the dielectric layers may include inorganic dielectric layers located on the side of the corresponding organic layer away from the substrate, while another portion of the dielectric layers may include inorganic dielectric layers located on the side of the corresponding organic layer close to the substrate.

[0131] In the embodiments of this disclosure, the stacking relationship between the inorganic dielectric layer and the organic dielectric layer in each dielectric layer can be flexibly set. That is, the inorganic dielectric layer in the same dielectric layer can be located on the side of the corresponding organic dielectric layer closer to the substrate, or on the side of the corresponding organic dielectric layer farther away from the substrate, thereby improving the flexibility of process design.

[0132] For example, referring to FIG6, a tin layer 20 may be provided on the surface of pin 103 away from the substrate to prevent copper oxidation and facilitate the formation of gold-tin eutectic bonding with the chip. The thickness of the tin layer 20 is greater than or equal to 0.1 micrometers and less than or equal to 0.2 micrometers.

[0133] Figure 10 is a plan view of a wiring substrate according to some exemplary embodiments of the present disclosure.

[0134] For example, referring to Figures 6 and 10, the wiring substrate may further include a green solder resist layer SR disposed on the side of the m-th dielectric layer (the dielectric layer furthest from the substrate in the multilayer dielectric layers) away from the substrate. The green solder resist layer SR may be located in the bending region, i.e., outside the chip bonding region, panel bonding region, and PCB bonding region. For example, the green solder resist layer SR may be located in the region shown by the dashed box M5 in Figure 10, which may be located on the side of the panel bonding region away from the chip bonding region. For example, the green solder resist layer SR may also be located in the region shown by the dashed box M6 in Figure 10, which may be located on the side of the PCB bonding region away from the chip bonding region. For example, the green solder resist layer SR may also be located in the region shown by the dashed box M7 in Figure 10 excluding the dashed box M8. The dashed box M8 may be the chip bonding region. The thickness of the green solder resist layer SR is between 10 and 20 micrometers. To ensure the bending performance of the wiring substrate, the green solder mask layer must be made of a high-bending-resistance adhesive with high tensile strength at break and low Young's modulus.

[0135] For example, the orthographic projection of any organic dielectric layer in the m dielectric layers onto the substrate falls within the orthographic projection of the green solder resist layer onto the substrate. For instance, referring to Figure 6, when m is 2, the m dielectric layers include a first organic dielectric layer OL1041 and a second organic dielectric layer OL1042. The orthographic projections of the first organic dielectric layer OL1041 and the second organic dielectric layer OL1042 onto the substrate both fall within the orthographic projection of the green solder resist layer SR onto the substrate.

[0136] For example, referring to FIG9, the green solder resist layer SR includes a first side SR1 near the bonding region, and the m-th organic dielectric layer (the organic dielectric layer furthest from the substrate in the multilayer organic dielectric layers) includes a second side OL2 near the bonding region. The first side SR1 and the second side OL2 are separated by a first spacing distance D1, which is greater than or equal to 50 micrometers. For example, referring to FIG9, when m is 2, the second side OL2 of the second organic dielectric layer OL1042 is separated from the first side SR1 of the green solder resist layer SR by a first spacing distance D1, which is greater than or equal to 50 micrometers. This design ensures that, while considering both the printing accuracy and the waviness accuracy of the green solder resist layer, the boundary of the green solder resist layer SR can encompass the boundary of the second organic dielectric layer OL1042. During the bonding process, the green solder resist layer can better protect the organic dielectric layer, improving the bonding yield.

[0137] In some embodiments, the orthographic projection of the i-th organic dielectric layer on the substrate falls within the orthographic projection of the (i+1)-th organic dielectric layer on the substrate. For example, referring to FIG6, when the wiring substrate includes a first organic dielectric layer OL1041 and a second organic dielectric layer OL1042, the second organic dielectric layer OL1042 is located on the side of the first organic dielectric layer OL1041 away from the substrate 1. The orthographic projection of the first organic dielectric layer OL1041 on the substrate 1 falls within the orthographic projection of the second organic dielectric layer OL1042 on the substrate 1. As another example, referring to FIG7, when the wiring substrate includes a first organic dielectric layer OL1041, a second organic dielectric layer OL1042, and a third organic dielectric layer OL1043, the second organic dielectric layer OL1042 is located on the side of the first organic dielectric layer OL1041 away from the substrate 1, and the orthographic projection of the first organic dielectric layer OL1041 on the substrate 1 falls within the orthographic projection of the second organic dielectric layer OL1042 on the substrate 1. The third organic dielectric layer OL1043 is located on the side of the second organic dielectric layer OL1042 away from the substrate 1, and the orthographic projection of the second organic dielectric layer OL1042 on the substrate 1 falls within the orthographic projection of the third organic dielectric layer OL1043 on the substrate 1.

[0138] The side of the i-th organic dielectric layer near the bonding region is separated from the side of the (i+1)-th organic dielectric layer near the bonding region by a second spacing distance D2, which is greater than or equal to 10 micrometers. For example, referring to FIG9, the wiring substrate may include a first organic dielectric layer OL1041 and a second organic dielectric layer OL1042. The side of the first organic dielectric layer OL1041 near the bonding region is separated from the side of the second organic dielectric layer OL1042 near the bonding region by a second spacing distance D2, which is greater than or equal to 10 micrometers.

[0139] It should be noted that the number of dielectric layers can be even greater. The encapsulation relationship between two adjacent organic dielectric layers can be similar to that when there are two dielectric layers. This ensures that the organic layer furthest from the substrate in two adjacent organic dielectric layers can encapsulate the organic layer closest to the substrate.

[0140] By setting the boundary wrapping relationship of multiple organic dielectric layers, it is beneficial to avoid residual problems during metal wiring and reduce the probability of short circuits in metal wiring.

[0141] In some embodiments, referring to Figures 6 and 8, the wiring substrate may further include an IC chip disposed on the side of the metal bonding layer away from the substrate. The IC chip is electrically connected to multiple pins 103, thereby providing control signals to multiple metal lines in the metal wiring layer. For example, the bonding region includes a chip bonding region, and the IC chip is located in the chip bonding region. Referring to Figure 9, the minimum spacing distance D3 between the boundary of the IC chip and the boundary SR1 of the solder resist layer SR is greater than or equal to 100 micrometers. This design ensures sufficient space between the IC chip and the solder resist layer, facilitating subsequent dispensing.

[0142] For example, continuing to refer to FIG6, the wiring substrate may also include a dispensing layer 40. The dispensing layer 40 can be used to protect the IC chip and the pins 103, and improve the stability of the connection between the IC chip and the pins 103.

[0143] In practical applications, the actual area that needs to be bent in the bending zone of the wiring substrate is usually smaller than the overall range of the bending zone of the wiring substrate.

[0144] In some embodiments of this disclosure, the inorganic dielectric layers included in the bending region of the wiring substrate can be partially removed only in the area where bending is actually required. In this way, most of the inorganic dielectric layers in the bending region can be retained, which is beneficial for improving the insulation performance in the bending region. At the same time, it can ensure the insulation effect at the junction of the bending region and the bonding region, avoiding short circuits between the metal wiring layers.

[0145] It should be noted that the actual area that needs to be bent can be adjusted according to the specific dimensions and wiring design of the product when the wiring board is actually applied to it.

[0146] FIG11 is a partial cross-sectional view of a wiring substrate according to some exemplary embodiments of the present disclosure, taken along line BB' in FIG2, showing two metal wiring layers; FIG12 is a partial cross-sectional view of a wiring substrate according to some other exemplary embodiments of the present disclosure, taken along line BB' in FIG2, showing three metal wiring layers.

[0147] In some embodiments, the m-layer dielectric layer includes m-layer inorganic dielectric layers, and any one of the m-layer inorganic dielectric layers includes a second opening VH2 located in the bending region. The orthographic projections of the second openings VH2 in any two of the m-layer inorganic dielectric layers onto the substrate at least partially overlap. Alternatively, the orthographic projections of the second openings VH2 in any two of the m-layer inorganic dielectric layers onto the substrate completely overlap. The second opening VH2 in any one of the m-layer inorganic dielectric layers has a second width d2 along a first direction X, the second width d2 being greater than or equal to 1 mm and less than or equal to 10 mm, wherein the first direction X is the direction from the bonding region toward the bending region. For example, referring to FIG11, when m is 2, the first dielectric layer 1041 includes a first inorganic dielectric layer IL1041, and the second dielectric layer 1042 includes a second inorganic dielectric layer IL1042. The first inorganic dielectric layer IL1041 includes a second opening VH21 located in the bending region, and the second inorganic dielectric layer IL1042 includes a second opening VH22 located in the bending region. The orthographic projections of the second opening VH21 in the first inorganic dielectric layer IL1041 and the second opening VH22 in the second inorganic dielectric layer IL1042 onto the substrate at least partially or completely overlap. Exemplarily, the second width d21 of the second opening VH21 in the first inorganic dielectric layer along the first direction is greater than or equal to 1 mm and less than or equal to 10 mm. The second width d22 of the second opening VH22 in the second inorganic dielectric layer along the first direction is greater than or equal to 1 mm and less than or equal to 10 mm.

[0148] For example, referring to Figure 12, when m is 3, the first dielectric layer 1041 includes a first inorganic dielectric layer IL1041, the second dielectric layer 1042 includes a second inorganic dielectric layer IL1042, and the third dielectric layer 1043 includes a third inorganic dielectric layer IL1043. The first inorganic dielectric layer IL1041 includes a second opening VH21 located in the bending region, and the second inorganic dielectric layer IL1042 includes a second opening VH22 located in the bending region. The third inorganic dielectric layer IL1043 includes a second opening VH23 located in the bending region. The orthographic projections of any two of the second openings VH21, VH22, and VH23 in the first and third inorganic dielectric layers onto the substrate at least partially or completely overlap. Exemplarily, the second width d21 of the second opening VH21 in the first inorganic dielectric layer along the first direction is greater than or equal to 1 mm and less than or equal to 10 mm. The second opening VH22 of the second inorganic dielectric layer has a second width d22 along the first direction that is greater than or equal to 1 mm and less than or equal to 10 mm. The second opening VH23 of the third inorganic dielectric layer has a second width d23 along the first direction that is greater than or equal to 1 mm and less than or equal to 10 mm.

[0149] It should be noted that as the number of metal wiring layers increases, the wiring substrate can also include more inorganic dielectric layers, such as 4 or more inorganic dielectric layers.

[0150] By designing the inorganic dielectric layer in the bending zone to only remove the portion corresponding to the actual bending area, the insulation performance in the bending zone can be improved. Simultaneously, it ensures insulation at the junction of the bending and bonding zones, preventing short circuits between metallic wiring layers.

[0151] Figure 13 is a flowchart of a method for fabricating a wiring substrate according to an embodiment of the present disclosure.

[0152] Exemplary, in some embodiments of this disclosure, referring to FIG13, the method for fabricating a wiring substrate may include steps S01-S02:

[0153] In step S01, a substrate is provided, the substrate including at least one bonding region and a bending region.

[0154] In step S02, multiple metal wiring layers and multiple dielectric layers are sequentially formed on the substrate. Each of the multiple metal wiring layers has a dielectric layer disposed on the side furthest from the substrate. Each dielectric layer includes a stacked organic dielectric layer and an inorganic dielectric layer. The orthographic projection of the organic dielectric layer onto the substrate does not overlap with the orthographic projection of the bonding region onto the substrate. The orthographic projection of the inorganic dielectric layer onto the substrate at least partially overlaps with the orthographic projection of the bonding region onto the substrate.

[0155] Figure 14 is a flowchart illustrating the specific steps in step S02 of the fabrication method according to Figure 13. Figures 15A-15F are schematic cross-sectional views of partial structures during the fabrication process of a wiring substrate according to some exemplary embodiments of the present disclosure.

[0156] Exemplary, in some embodiments of this disclosure, the multilayer metal wiring layer includes an m-layer, and forming the multilayer metal wiring layer and the multilayer dielectric layer includes:

[0157] In step S021, referring to FIG15A, a first metal wiring layer 1021 is formed on the substrate 1, and a patterning process is performed on the first metal wiring layer.

[0158] In step S022, referring to Figures 15A and 15B, a first dielectric layer 1041 is formed on the side of the first metal wiring layer 1021 away from the substrate. The formation of the first dielectric layer includes: forming a first inorganic dielectric layer IL1041 and performing a patterning process on the first inorganic dielectric layer IL1041 to form a plurality of first openings VH11 located in the bonding region; and forming a first organic dielectric layer OL1041 and performing a patterning process on the first organic dielectric layer such that the orthographic projection of the first organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate.

[0159] Step S023, referring to Figure 15C, repeats the fabrication steps of the metal wiring layer 102 and dielectric layer 104 in steps S021 and S022 above to form m alternating metal wiring layers and m dielectric layers, thereby forming the multilayer metal wiring layer and multilayer dielectric layer, where m is a positive integer greater than or equal to 2. For example, referring to Figure 15, the number of metal wiring layers m is 2. A second inorganic dielectric layer IL1042 is formed, and a patterning process is performed on the second inorganic dielectric layer IL1042 to form a plurality of first openings VH12 located in the bonding region; and a second organic dielectric layer OL1042 is formed, and a patterning process is performed on the second organic dielectric layer OL1042 so that the orthographic projection of the second organic dielectric layer OL1042 on the substrate does not overlap with the orthographic projection of the bonding region on the substrate.

[0160] Exemplary, in some embodiments of this disclosure, referring to FIG13, the method for fabricating a wiring substrate may further include steps S03-S05:

[0161] In step S03, referring to FIG15D, a metal bonding layer 10 is prepared on the side of the m-th dielectric layer away from the substrate, and a patterning process is performed on the metal bonding layer to form a plurality of pins 103. For example, the metal bonding layer 10 can be formed by a copper electroplating process.

[0162] In step S04, referring to FIG15E, tin is plated on the side of the metal bonding layer away from the substrate to form a tin metal layer 20 including the leads in the metal bonding layer. For example, the tin metal layer can be chemically plated. And, a green solder resist layer SR is printed in the bending area.

[0163] In step S05, referring to Figure 15F, the bonding between the IC chip and the pins is completed in the chip bonding area, and the bonding area between the IC chip and the pins is protected by dispensing adhesive layer to form adhesive layer 40.

[0164] In some embodiments, during steps S01-S04 described above, the substrate can be disposed on a glass substrate. After completing step S04, the glass substrate can be removed, for example, by laser lift-off. Then, IC chip bonding and adhesive dispensing protection are performed to obtain a flexible wiring substrate.

[0165] Figure 16 is a schematic diagram of the structure of a display device provided according to some embodiments of the present disclosure.

[0166] Optionally, embodiments of this disclosure also provide a display device. Referring to FIG16, the display device 300 may include the wiring substrate 100 described above. The display device may include, but is not limited to, any product or component with display function such as electronic paper, mobile phone, tablet computer, monitor, laptop computer, digital photo frame, and navigator. It should be understood that this display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0167] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A wiring substrate, characterized in that, include: A substrate, the substrate comprising at least one bonding region and a bending region; The wiring substrate further includes: A multilayer metal wiring layer is located above the substrate; and A multilayer dielectric layer, wherein at least one of the multilayer metal wiring layers has at least one dielectric layer disposed on the side away from the substrate, wherein... At least one of the dielectric layers includes an organic dielectric layer and an inorganic dielectric layer stacked together, wherein the orthographic projection of the organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate; and the orthographic projection of the inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the bonding region on the substrate.

2. The wiring substrate according to claim 1, wherein, The multilayer dielectric layer and the multilayer metal wiring layer located in the bonding region have a first thickness, and the multilayer dielectric layer and the multilayer metal wiring layer located in the bending region have a second thickness, wherein the first thickness is less than the second thickness.

3. The wiring substrate according to claim 1 or 2, wherein, The multilayer dielectric layer includes m layers, the m-layer dielectric layer includes the i-th dielectric layer, the i-th dielectric layer includes the i-th organic dielectric layer and the i-th inorganic dielectric layer, wherein the thickness of the i-th organic dielectric layer is greater than the thickness of the i-th inorganic dielectric layer, and m is a positive integer greater than or equal to 2, and i is a positive integer less than or equal to m.

4. The wiring substrate according to claim 3, wherein, The i-th inorganic dielectric layer includes a first portion located at the intersection of the bonding region and the bending region, wherein the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the i-th organic dielectric layer on the substrate.

5. The wiring substrate according to claim 4, wherein, The first portion of the i-th inorganic dielectric layer overlaps with the portion of the i-th organic dielectric layer projected onto the substrate, and the first width is greater than or equal to 5 micrometers.

6. The wiring substrate according to claim 1 or 2, wherein, The multilayer dielectric layer includes m layers, each including an i-th dielectric layer and an (i+1)-th dielectric layer. The i-th dielectric layer includes an i-th inorganic dielectric layer, and the (i+1)-th dielectric layer includes an (i+1)-th inorganic dielectric layer. The (i+1)-th inorganic dielectric layer is located on the side of the i-th inorganic dielectric layer away from the substrate. The i-th inorganic dielectric layer includes a first portion located at the intersection of the bonding region and the bending region. The (i+1)-th inorganic dielectric layer also includes a first portion located at the intersection of the bonding region and the bending region. The first portion of the (i+1)th inorganic dielectric layer protrudes a first protrusion distance relative to the first portion of the ith inorganic dielectric layer in a direction closer to the bending region, wherein the first protrusion distance is greater than or equal to 5 micrometers, and i is a positive integer less than or equal to m-1.

7. The wiring substrate according to claim 6, wherein, The dielectric layer m further includes an i-th organic dielectric layer and an i+1-th organic dielectric layer, wherein the i-th organic dielectric layer is located between the i-th inorganic dielectric layer and the i+1-th inorganic dielectric layer, and the i+1-th organic dielectric layer is located on the side of the i+1-th inorganic dielectric layer away from the substrate.

8. The wiring substrate according to claim 6, wherein, The dielectric layer m further includes an i-th organic dielectric layer and an i+1-th organic dielectric layer, wherein the i-th organic dielectric layer is located on the side of the i-th inorganic dielectric layer close to the substrate, and the i+1-th organic dielectric layer is located between the i-th inorganic dielectric layer and the i+1-th inorganic dielectric layer.

9. The wiring substrate according to any one of claims 3-8, wherein, The wiring substrate further includes a green solder resist layer disposed on the side of the m-th dielectric layer away from the substrate, the green solder resist layer being located in the bending region; and The orthographic projection of any organic dielectric layer contained in any of the m-layer dielectric layers onto the substrate falls within the orthographic projection of the green solder resist layer onto the substrate.

10. The wiring substrate according to claim 9, wherein, The green solder resist layer includes a first side near the bonding region, and the m-th organic dielectric layer includes a second side near the bonding region, wherein the first side and the second side are separated by a first gap distance, which is greater than or equal to 50 micrometers.

11. The wiring substrate according to any one of claims 6-8, wherein, The orthographic projection of the i-th organic dielectric layer on the substrate falls within the orthographic projection of the (i+1)-th organic dielectric layer on the substrate.

12. The wiring substrate according to claim 11, wherein, The side of the i-th organic dielectric layer near the bonding region is separated from the side of the (i+1)-th organic dielectric layer near the bonding region by a second spacing distance, the second spacing distance being greater than or equal to 10 micrometers.

13. The wiring substrate according to any one of claims 1-12, wherein, The multilayer metal wiring layer includes a plurality of pin transition portions, which are at least partially located in the bonding region; as well as The inorganic dielectric layer includes a plurality of first openings located in the bonding region, wherein at least one of the first openings exposes a portion of at least one of the pin transition portions.

14. The wiring substrate according to claim 13, wherein, The wiring substrate further includes a metal bonding layer disposed on the side of the m-th dielectric layer away from the substrate, the metal bonding layer including a plurality of pins, at least one of the pins being electrically connected to at least one of the pin adapters through at least the first opening.

15. The wiring substrate according to claim 14, wherein, The wiring substrate further includes an IC chip disposed on the side of the metal bonding layer away from the substrate, the IC chip being electrically connected to a plurality of pins; and The bonding region includes a chip bonding region, wherein the IC chip is located in the chip bonding region, and the boundary of the IC chip is at least 100 micrometers away from the boundary of the green solder resist layer.

16. The wiring substrate according to any one of claims 3-15, wherein, The m-layer dielectric layer comprises m inorganic dielectric layers, each of which includes a second opening located in the bending region; and The orthographic projections of the second openings in any two inorganic dielectric layers of the m-layer inorganic dielectric layer on the substrate overlap at least partially; or, the orthographic projections of the second openings in any two inorganic dielectric layers of the m-layer inorganic dielectric layer on the substrate completely overlap.

17. The wiring substrate according to claim 16, wherein, The second opening in any one of the m inorganic dielectric layers has a second width along the first direction, the second width being greater than or equal to 1 mm and less than or equal to 10 mm, wherein the first direction is the direction from the bonding region toward the bending region.

18. A method for fabricating a wiring substrate, characterized in that, include: A substrate is provided, the substrate comprising at least one bonding region and a bending region; Multiple metal wiring layers and multiple dielectric layers are sequentially formed on the substrate. Each of the multiple metal wiring layers has a dielectric layer disposed on the side furthest from the substrate. Each of the dielectric layers includes an organic dielectric layer and an inorganic dielectric layer stacked together, wherein the orthographic projection of the organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate; and the orthographic projection of the inorganic dielectric layer on the substrate at least partially overlaps with the orthographic projection of the bonding region on the substrate.

19. The method according to claim 18, wherein, The multilayer metal wiring layer includes m layers, and the formation of the multilayer metal wiring layer and the multilayer dielectric layer includes: A first metal wiring layer is formed on the substrate, and a patterning process is performed on the first metal wiring layer. A first dielectric layer is formed on the side of the first metal wiring layer away from the substrate, wherein, Forming the first dielectric layer includes: forming a first inorganic dielectric layer and performing a patterning process on the first inorganic dielectric layer to form a plurality of first openings located in the bonding region; and A first organic dielectric layer is formed, and a patterning process is performed on the first organic dielectric layer so that the orthographic projection of the first organic dielectric layer on the substrate does not overlap with the orthographic projection of the bonding region on the substrate. Repeat the above steps for fabricating metal wiring layers and dielectric layers to form m alternating metal wiring layers and m dielectric layers, thereby forming the multilayer metal wiring layers and multilayer dielectric layers, where m is a positive integer greater than or equal to 2.

20. A display device, characterized in that, The display device includes the wiring substrate according to any one of claims 1-17.

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