Micro-display system, clock synchronization method therefor, micro-display panel, and device

Abstract

A micro-display system, a clock synchronization method therefor, a micro-display panel, and a device. The method comprises: in response to a micro-display system being powered on, a first micro-display panel of the micro-display system generates a first clock signal, wherein the first clock signal can control the display of the first micro-display panel, and the first clock signal generated by the first micro-display panel can be output to a second micro-display panel of the micro-display system and control the display of the second micro-display panel. By means of the solution, as long as micro-display panels in a color optical engine are kept connected to each other, clock signals of all of the micro-display panels in the entire color optical engine can be kept synchronous without the need for an upper computer to provide clock signals for each micro-display panel, thus reducing production costs and aiding in subsequent miniaturization. In addition, not using the upper computer for providing clock signals can further avoid the interference of the clock signals provided by the upper computer with other signals, thereby improving the reliability of the micro-display panels.

Description

Microdisplay systems and their clock synchronization methods, microdisplay panels and devices

[0001] This application claims priority to Chinese Patent Application No. 202410511663.3, filed on April 25, 2024, entitled “Microdisplay System and Clock Synchronization Method Thereof, Microdisplay Panel and Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of Micro LED technology, and in particular to a micro display system and its clock synchronization method, micro display panel and device. Background Technology

[0003] Micro LEDs, also known as inorganic micropixel light-emitting diodes, miniature light-emitting diodes, or μ-LEDs, are widely used in self-emissive microdisplays, visible light communication, optogenetics, and other fields. Compared to traditional LEDs, Micro LEDs offer advantages such as better strain relaxation, higher light extraction efficiency, more uniform current diffusion, and higher output performance. Micro LEDs also boast improved thermal effects, faster response times, a wider operating temperature range, higher resolution, a broader color gamut, higher contrast, lower power consumption, and higher current density.

[0004] Existing microdisplay panels composed of Micro LED arrays are typically monochrome, meaning they can only emit light of one color. To achieve color display, three Micro LED microdisplay panels capable of emitting different colors of light need to be assembled together to form a microdisplay system.

[0005] In existing microdisplay systems, when the clock signals controlling the three microdisplay panels are not synchronized, the scanning states of the different microdisplay panels will be misaligned, resulting in color separation and display asynchrony during display, which affects the display effect.

[0006] To improve the display effect, the common practice is to use the same host computer to generate three clock signals, which are then input to the three micro-display panels of the color optical engine to control the corresponding micro-display panels to display.

[0007] However, while the above method can keep the clock signals of the three micro-display panels synchronized, it increases production costs, especially when there are more than two color optical engines in an electronic device.

[0008] Summary of the Invention

[0009] The technical problem solved by this invention is to reduce the production cost of micro-display systems.

[0010] To address the aforementioned problems, embodiments of the present invention provide a clock synchronization method for a microdisplay system. The method includes: in response to power-on of the microdisplay system, a first microdisplay panel of the microdisplay system generates a first clock signal, the first clock signal being capable of controlling the display of the first microdisplay panel; the first clock signal generated by the first microdisplay panel being output to a second microdisplay panel of the microdisplay system, and controlling the display of the second microdisplay panel.

[0011] Embodiments of the present invention also provide a micro-display system, the micro-display system comprising:

[0012] A first micro-display panel, which generates a first clock signal when the micro-display system is powered on, and the first clock signal controls the display of the first micro-display panel;

[0013] The second micro-display panel is communicatively connected to the first micro-display panel. The first clock signal generated by the first micro-display panel can be output to the second micro-display panel and control the display of the second micro-display panel.

[0014] Embodiments of the present invention also provide a micro-display panel, the micro-display panel comprising:

[0015] A panel body, the panel body including a pixel array and a pixel driving circuit, the pixel driving circuit being connected to the pixel array;

[0016] A clock generation module is embedded in the panel body. The clock generation module can generate a clock signal when the panel body is powered on, and the pixel driving circuit can control the display of the pixel array based on the clock signal.

[0017] Embodiments of the present invention also provide a micro-display system, the micro-display system comprising:

[0018] Three or more micro-display panels according to any one of the above embodiments, wherein the connection interfaces of the three or more micro-display panels are interconnected.

[0019] This invention also provides an electronic device, which includes any of the above-described micro-display systems.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In this invention, after the micro-display system is powered on, the first micro-display panel itself can generate a first clock signal. This first clock signal can not only control the display of the first micro-display panel, but also be output to a second micro-display panel of the micro-display system to control its display. Thus, the entire micro-display system can use the clock signal generated by one of the micro-display panels for display. Therefore, as long as the micro-display panels in the system are connected, the clock signals of all micro-display panels in the entire system can be kept synchronized, without requiring a host computer to provide a clock signal for each micro-display panel. This eliminates the need to connect the host computer to each micro-display panel, reducing the number of connection lines between the host computer and each micro-display panel, thereby reducing cable consumption, decreasing the total physical width of the connection lines, lowering production costs, and facilitating subsequent miniaturization. Furthermore, eliminating the need for a host computer to provide a clock signal also avoids interference with other signals caused by the host computer's clock signal, improving the reliability of the micro-display panel. Instead of each microdisplay panel generating its own clock signal to control its own display, since the frequency of the clock signal generated by each microdisplay panel may fluctuate with temperature, voltage, process, etc., sharing a clock signal generated by a single microdisplay panel can ensure that the frequency of the clock signals of all microdisplay panels is consistent, which is beneficial for display synchronization. Attached Figure Description

[0022] Figure 1 is a timing diagram of three asynchronous clock signals;

[0023] Figure 2 is a schematic diagram of the internal structure of a micro-display panel;

[0024] Figure 3 is a schematic diagram of a micro-display system;

[0025] Figure 4 is a schematic diagram of a micro-display system according to an embodiment of the present invention;

[0026] Figure 5 is a three-dimensional structural schematic diagram of a color optical engine in an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of a connection between the color optical engine and the external circuit board in Figure 5;

[0028] Figure 7 is a schematic diagram of another connection between the color optical engine and the external circuit board in Figure 5;

[0029] Figure 8 is a schematic diagram of the structure of the other side of the external circuit board in Figure 7;

[0030] Figure 9 is a three-dimensional structural schematic diagram of another color optical engine in an embodiment of the present invention;

[0031] Figure 10 is a schematic diagram of the connection between the color optical engine and the external circuit board in Figure 9;

[0032] Figure 11 is a schematic diagram of the connection between the color optical engine and the external circuit board in Figure 9;

[0033] Figure 12 is a flowchart of a clock synchronization method for a micro-display system according to an embodiment of the present invention;

[0034] Figure 13 is a schematic diagram of the structure of a micro-display panel in an embodiment of the present invention;

[0035] Figure 14 is a schematic diagram of the working principle of a clock generation module in an embodiment of the present invention;

[0036] Figure 15 is a schematic diagram of a micro-display system according to an embodiment of the present invention;

[0037] Figure 16 is a schematic diagram of another micro-display system in an embodiment of the present invention. Detailed Implementation

[0038] Existing microdisplay systems are typically formed by assembling three monochromatic Micro LED microdisplay panels that emit different colors of light. For example, a microdisplay system can be formed by assembling a red microdisplay panel, a green microdisplay panel, and a blue microdisplay panel.

[0039] For example, a microdisplay system may include a lens, a light-combining prism, a red light microdisplay panel, a green light microdisplay panel, and a blue light microdisplay panel. Light emitted from the red, green, and blue light microdisplay panels enters the interior of the light-combining prism through its three different incident surfaces, converges within the prism, and then exits through its exit surface. The lens corresponds to the exit surface of the light-combining prism, allowing light emitted from this surface to pass through the lens before exiting.

[0040] In the aforementioned microdisplay system, three microdisplay panels are controlled by three separate clock signals. The clock signals controlling the color display of the three microdisplay panels need to be synchronized to achieve a good display effect. If the clock signals controlling the three microdisplay panels are not synchronized, the scanning states of the different microdisplay panels will be misaligned, resulting in color separation and display asynchrony, thus affecting the display quality.

[0041] For example, referring to Figure 1, the three clock signals are clockA, clockB, and clockC. ClockA and clockB are synchronized but have a certain delay. ClockC is not synchronized with clockA and clockB.

[0042] Specifically, referring to Figure 2, the clock signal CKIN is subsequently input to the pixel driving circuit of the microdisplay panel. The pixel driving circuit typically includes a scanning module 21 and a modulation module 22. The scanning module 21 generates a scanning drive signal SFx based on the clock signal CKIN. The scanning drive signal SFx is used to drive the scanning operation of some or all pixels in the pixel array. The scanning drive signal SFx is input to the modulation module 22, which generates a pulse modulation signal PWM. The pulse modulation signal PWM controls the switching of the switching transistor Q1, thereby controlling the scanning of the pixel connected to the switching transistor Q1. The source of the switching transistor Q1 is connected to the power supply voltage VDD through a current source L1, and the drain is connected to the voltage VCOM through the pixel.

[0043] The clock signal CKIN determines the scanning state of a pixel. Specifically, it determines the duty cycle of the pulse modulation signal PWM, thereby determining the scanning duration of the pixel. The clock signal CKIN can also control the switching state of the switching transistor Q1 via the pulse modulation signal PWM, thus determining the scanning frequency of the pixel.

[0044] If the pixel scanning states of the micro-display panels are misaligned, it can easily lead to color separation in the micro-display panels and asynchronous display.

[0045] To improve the display effect of the color optical engine, the usual practice is to use the same host computer to output a clock signal to the three micro display panels of the color optical engine.

[0046] While this method can maintain clock signal synchronization among the three micro-display panels, it requires a host computer to generate the relevant clock signals. Furthermore, it necessitates connecting cables between the host computer and each of the three micro-display panels, with the clock signals generated by the host computer being transmitted to the corresponding micro-display panels via these cables. This increases the consumption of these connecting cables, ultimately raising the production cost of the color optical engine.

[0047] In some applications, an electronic device may need to use more than two color optical engines. For example, binocular AR glasses require two color optical engines. In this case, the number of leads connecting to the host computer increases exponentially, greatly increasing the production cost of the electronic device.

[0048] For example, referring to Figure 3, a binocular AR glasses system includes a first micro-display system 31, a second micro-display system 32, and a host computer 33. The micro-display system 31 has three micro-display panels: a first red light micro-display panel R1, a first green light micro-display panel G1, and a first blue light micro-display panel B1. The micro-display system 32 has three micro-display panels: a second red light micro-display panel R2, a second green light micro-display panel G2, and a second blue light micro-display panel B2. The host computer 33 generates a clock signal clock1 to both the micro-display systems 31 and 32. However, the host computer 33 needs to connect to both the first and second micro-display systems 31 and 32 via connecting cables, increasing cable consumption and thus production costs.

[0049] Based on this, the present invention provides a clock synchronization method for a micro-display system. After the micro-display system is powered on, the first micro-display panel of the micro-display system can generate a first clock signal on its own. This first clock signal can not only control the display of the micro-display panel where it is located, but also control the display of the second micro-display panel, without the need for the host computer to provide clock signals for each micro-display panel. This reduces the consumption of connecting lines, lowers the production cost, and helps to ensure that the clock signals of all micro-display panels have the same frequency.

[0050] To make the above-mentioned objectives, features, and advantages of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] In the description of this invention, it should be understood that the terms "upper," "lower," "top surface," "bottom surface," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the indicated position or element must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship, order, or relative importance between these entities or operations.

[0052] Referring to Figure 4, an embodiment of the present invention provides a micro-display system, which may include: a first micro-display panel 41 and a second micro-display panel 42. Wherein:

[0053] The first micro-display panel 41 can generate a first clock signal when the micro-display system is powered on, and the first clock signal can control the display of the first micro-display panel 41;

[0054] The second micro-display panel 42 is communicatively connected to the first micro-display panel 41. The first clock signal generated by the first micro-display panel 41 can be output to the second micro-display panel 42 and control the display of the second micro-display panel 42.

[0055] In a specific implementation, the first microdisplay panel 41 can be any microdisplay panel in the microdisplay system. The second microdisplay panel 42 can be any microdisplay panel within the microdisplay system that is different from the first microdisplay panel 41. The first clock signal can be output to the microdisplay system to control the second microdisplay panel 42 to display, without the need for the host computer to provide a clock signal to the second microdisplay panel 42, or for the second microdisplay panel 42 to generate its own clock signal.

[0056] In specific implementations, the structures of the first micro-display panel 41 and the second micro-display panel 42 may be the same or different.

[0057] In one embodiment of the present invention, the second microdisplay panel 42 has a different structure from the first microdisplay panel 41.

[0058] Specifically, referring to FIG4, the first micro-display panel 41 may include: a first oscillator OSC1, a first driving circuit 411, and a first connection interface IO1. The output terminal of the first oscillator OSC1 is connected to the first driving circuit 411 and the first connection interface IO1 respectively. The first oscillator OSC1 can generate the first clock signal. The first driving circuit 411 can control the display of the first micro-display panel 41 based on the first clock signal.

[0059] Referring to Figure 4, the second micro-display panel 42 may include: a second driving circuit 421 and a second connection interface IO2. The second connection interface IO2 is connected to the second driving circuit 421 and is also connected to the first connection interface IO1. The first clock signal can be transmitted to the second driving circuit 421 through the first connection interface and the second connection interface. The second driving circuit 421 can control the display of the second micro-display panel 42 based on the first clock signal.

[0060] In another embodiment of the present invention, the second microdisplay panel 42 has the same structure as the first microdisplay panel 41. In this case, referring to FIG4, the second microdisplay panel 42 further includes a second oscillator OSC2, the output terminal of the second oscillator OSC2 being connected to the second driving circuit 421 and the second connection interface IO2, respectively.

[0061] The second micro-display panel 42 can configure the second oscillator OSC2 to generate a second clock signal based on external configuration instructions, so that the second driving circuit 421 controls the display of the second micro-display panel 42 based on the second clock signal, and configures the second connection interface IO2 to output the second clock signal to the first micro-display panel 41.

[0062] The first micro-display panel 41 can be configured to use the first clock signal to control the display of the first micro-display panel 41 based on external configuration instructions.

[0063] In a specific implementation, based on the external configuration command, the first micro-display panel 41 can be configured to stop the first oscillator OSC1 from generating the first clock signal and to receive the second clock signal through the first connection interface IO1, so that the first driving circuit 411 controls the display of the first micro-display panel 41 based on the first clock signal.

[0064] In other words, in practical applications, for a microdisplay system including a first microdisplay panel 41 and a second microdisplay panel 42, external configuration commands can be used to configure the first microdisplay panel 41 to generate a first clock signal and provide it to the second microdisplay panel 42, or vice versa. At any given time, only one microdisplay panel can provide clock signals to itself and other microdisplay panels. External configuration commands can be used to switch the clock signal used by the microdisplay system.

[0065] In one embodiment of the present invention, referring to FIG4, the first micro-display panel 41 further includes a first selection switch X1. The first selection switch X1 has two input ports and one output port. The two input ports of the first selection switch X1 are respectively connected to the first oscillator OSC1 and the first connection interface IO1, and the output port of the first selection switch X1 is connected to the first driving circuit 411.

[0066] In practical applications, based on the external configuration instructions, the first micro-display panel 41 can be configured to receive the second clock signal through the first connection interface IO1, and the first selection switch X1 can be configured to send the second clock signal to the first driving circuit 411, so that the first driving circuit 411 controls the display of the first micro-display panel 41 based on the first clock signal.

[0067] In one embodiment of the present invention, the second micro-display panel 42 further includes a second selection switch X2, the second selection switch X2 having two input ports and one output port, the two input ports of the second selection switch X2 being connected to the second oscillator OSC2 and the second connection interface IO2 respectively, and the output port of the second selection switch X2 being connected to the second driving circuit 421.

[0068] In practical applications, the second micro-display panel 42 can configure the second oscillator OSC2 to generate a second clock signal based on external configuration instructions, and then configure the second selection switch X2 of the second micro-display panel 42 so that the second clock signal is sent to the second driving circuit 421 in the second micro-display panel 42.

[0069] In a specific implementation, the first microdisplay panel 41 may contain a first register, which is connected to the first oscillator OSC1. The second microdisplay panel 42 contains a second register, which is connected to the second oscillator OSC2. Through external configuration instructions, the configuration information stored in the first register can be modified, thereby controlling the first oscillator OSC1 to generate or stop generating the first clock signal. Similarly, through external configuration instructions, the configuration information stored in the second register can be modified, thereby controlling the second oscillator OSC2 to generate or stop generating the second clock signal.

[0070] For example, when the first micro-display panel 41 needs to provide a first clock signal, the value of the first register can be modified to "1111" through an external configuration instruction. Once the value of the first register is modified, the first oscillator OSC1 will be automatically triggered to generate the first clock signal. At this time, the value of the second register remains unchanged, so that the second oscillator OSC2 does not generate a second clock signal, but displays by receiving the first clock signal.

[0071] In a specific implementation, when the first micro-display panel 41 generates a first clock signal, referring to FIG4, the micro-display system further includes: at least one third micro-display panel 43, the at least one third micro-display panel 43 being communicatively connected to the first micro-display panel 41, the first clock signal generated by the first micro-display panel 41 being output to the at least one third micro-display panel 43, and controlling the display of the at least one third micro-display panel 43.

[0072] In a specific implementation, when the second micro-display panel 42 generates a second clock signal, the at least one third micro-display panel 43 can also be connected to the second micro-display panel 42 for communication. The second clock signal generated by the second micro-display panel 42 can be output to the at least one third micro-display panel 43 and control the display of the at least one third micro-display panel 43.

[0073] In one embodiment, the number of the third microdisplay panel 43 may be only one, that is, the microdisplay system includes only one third microdisplay panel 43. The first microdisplay panel 41, the second microdisplay panel 42, and the third microdisplay panel 43 can emit three different colors of light, namely red, green, and blue; the first microdisplay panel 41, the second microdisplay panel 42, and the third microdisplay panel 43 can be assembled into a color optical engine.

[0074] In another embodiment, the number of the at least one third microdisplay panel 43 is four. One of the third microdisplay panels, together with the first microdisplay panel 41 and the second microdisplay panel 42, can emit three different colors of light, namely red, green, and blue; the first microdisplay panel 41, the second microdisplay panel 42, and the one third microdisplay panel can be assembled into a first color optical engine. The other three third microdisplay panels 43 can emit three different colors of light, namely red, green, and blue; the three third microdisplay panels can be assembled into a second color optical engine.

[0075] In other words, of the four third micro-display panels 43, one third micro-display panel 43, together with the first micro-display panel 41 and the second micro-display panel 42, forms the first color optical engine, and the remaining three third micro-display panels 43 can be assembled into the second color optical engine. Of the three micro-display panels in the first color optical engine, only one micro-display panel can be configured to provide clock signals to itself and the other two micro-display panels. All three micro-display panels in the second color optical engine can be connected to the clock signal generated in the first color optical engine for synchronized display.

[0076] In a specific implementation, the microdisplay system may further include a circuit board; the circuit board includes a first connector, a second connector, and a third connector. The first connector is used to connect to a first microdisplay panel. The second connector is used to connect to a second microdisplay panel. The third connector is used to connect to a third microdisplay panel. One port of the first, second, and third connector is adapted to receive a clock signal generated by the connected microdisplay panel, and transmits it to the connected microdisplay panel through the other two ports for connecting the first, second, and third microdisplay panels.

[0077] The circuit board can be implemented with reference to the description of Figure 6 and sub-Figure 8 below, and will not be repeated here.

[0078] Figure 5 is a three-dimensional structural schematic diagram of a color optical engine. Figure 6 is a schematic diagram of one connection between the color optical engine in Figure 5 and the external circuit. Figures 7 and 8 are schematic diagrams of another connection between the color optical engine in Figure 5 and the external circuit. Figure 9 is a three-dimensional structural schematic diagram of another color optical engine. Figures 10 and 11 are schematic diagrams of the connection between the color optical engine in Figure 9 and the external circuit.

[0079] In a specific implementation, referring to Figures 5 and 9, in addition to the micro-display panel, the color optical engine may also include a mounting frame 81 and a light-combining assembly (not shown). The mounting frame 81 has a mounting space, and the side of the mounting space has multiple light-inlet openings and a light-outlet opening communicating with the mounting space. The light-combining assembly is installed within the mounting space.

[0080] The light-combining assembly includes multiple light-incident surfaces, each corresponding to a light-incident port on the mounting frame 81. A first semi-transparent and semi-reflective film and a second semi-transparent and semi-reflective film are disposed within the lens body of the light-combining assembly, and these two films are alternately arranged within the lens body.

[0081] In some embodiments, the color optical engine may further include a lens assembly 85, which is fixed to the light outlet of the mounting frame 81. Light emitted from the light outlet can enter the lens assembly 85, and the lens assembly 85 can also limit the position of the light combining component.

[0082] Taking the light combining component having three light-incident surfaces as an example, these three light-incident surfaces are the first light-incident surface, the second light-incident surface, and the third light-incident surface. In this case, the color optical engine includes three micro-display panels, namely the first micro-display panel 82, the second micro-display panel 83, and the third micro-display panel 84.

[0083] The first microdisplay panel 82, the second microdisplay panel 83, and the third microdisplay panel 84 are each fixed to the mounting frame 81 through a light entrance. Light generated by the first microdisplay panel 82 enters the lens of the light combining assembly through the first light entrance surface; light generated by the second microdisplay panel 83 enters the lens of the light combining assembly through the second light entrance surface; and light generated by the third microdisplay panel 84 enters the lens of the light combining assembly through the third light entrance surface. The light entering the lens of the light combining assembly is then transmitted through the first and second semi-transparent reflective films 1301 and 1301, and exits through the light exit surface of the light combining assembly.

[0084] In the embodiments shown in Figures 5 and 6, each microdisplay panel has the same structure. Each microdisplay panel may include a display segment, a circuit board, and a connector segment. One end of the circuit board is electrically connected to the display segment, and the other end is electrically connected to the connector segment. The display segment includes a Micro LED chip and a chip reinforcement plate. The Micro LED chip is fixed to the surface of the chip reinforcement plate facing the light-combining component, and the chip reinforcement plate provides mechanical support for the Micro LED chip. The connector segment includes a connector and a connecting reinforcement plate. The connector is fixed to the outward-facing surface of the connecting reinforcement plate. The circuit board of each microdisplay panel is elongated and extends from the display segment of the microdisplay panel toward the connector segment of the microdisplay panel.

[0085] In some embodiments, the connector segment may further include a shielding cover. The shielding cover is fixed to the inward-facing surface of the connecting reinforcement plate. The shielding cover is used to shield other electronic components on the connecting reinforcement plate, besides the connector, from electromagnetic interference. The shielding cover is disposed opposite to the connector. The connecting reinforcement plate can provide mechanical support for the shielding cover and the connector.

[0086] In specific implementations, the connector may only include an external connector, which connects the microdisplay panel to an external circuit board. Alternatively, the connector may only include an internal connector, which connects the microdisplay panel to other microdisplay panels in the color optical engine. The connector may also include both external and internal connectors, in which case it can achieve connections between the microdisplay panel and other microdisplay panels, as well as connections between the microdisplay panel and an external circuit board.

[0087] In the embodiments shown in Figures 5 and 6, the connectors of each micro-display panel are external connectors. The external connectors of each micro-display panel can be connected to the external circuitry of the color optical engine, thereby enabling the micro-display panel to be powered or transmitted signals through the connection between the connectors and the external circuitry of the color optical engine.

[0088] Specifically, referring to Figures 5 and 6, the first microdisplay panel 82 may include: a first display segment, a first circuit board 822, and a first connector segment. The first display segment includes a first Micro LED chip and a first chip reinforcement plate 821. The first connector segment includes a first connector 823a, a first connection reinforcement plate 823b, and a first shielding cover 823c.

[0089] The second microdisplay panel 83 may include a second display segment, a second circuit board 832, and a second connector segment. The second display segment includes a second Micro LED chip and a second chip reinforcement plate 831. The second connector segment includes a second connector 833a, a second connection reinforcement plate, and a second shielding cover.

[0090] The third microdisplay panel 84 may include a third display segment, a third circuit board 842, and a third connector segment. The second display segment includes a third Micro LED chip and a third chip reinforcement plate 841. The third connector segment includes a third connector 843a, a third connection reinforcement plate 843b, and a third shielding cover 843c.

[0091] This invention also provides a circuit board. Referring to Figures 6 to 8, the circuit board includes a first connector 80a, a second connector 80b, and a third connector 80c. The first connector 80a is used to connect to a first micro-display panel 82, the second connector 80b is used to connect to a second micro-display panel 83, and the third connector 80c is used to connect to a third micro-display panel 84.

[0092] Among them, one of the first connector 80a, the second connector 80b and the third connector 80c is adapted to receive the clock signal generated by the connected microdisplay panel and send it to the connected microdisplay panel through the other two ports.

[0093] Specifically, the first microdisplay panel 82 is connected to the first connector 80a of the circuit board 80 via a first connector 823a. The second microdisplay panel 83 is connected to the second connector 80b of the circuit board 80 via a second connector 833a. The third microdisplay panel 84 is connected to the third connector 80c of the circuit board 80 via a third connector 843a. On the circuit board 80, the second connector 80b is located between the first connector 80a and the third connector 80c, and its distance from the first connector 80a and the third connector 80c is close. The circuit board 80 is the external circuit board of the color optical engine.

[0094] In a specific implementation, the circuit board 80 may include internal circuitry. The first connector 80a, the second connector 80b, and the third connector 80c are connected via the internal circuitry.

[0095] In one embodiment, a microdisplay panel connected to the second connector 80b can be configured to provide clock signals for itself and the other two microdisplay panels. Specifically, referring to Figures 5 and 6, the second microdisplay panel can be configured to provide clock signals for itself, the first microdisplay panel 82, and the third microdisplay panel 84. A clock generation module within the second microdisplay panel generates a clock signal, which is transmitted through the circuit board 832 of the second microdisplay panel to the second connector 833a, and then through the second connector 833a to the circuit board 80. Upon receiving the clock signal, the circuit board 80 transmits it, on one hand, through the first connector 80a to the first connector 823a, and then through the circuit board 822 to the pixel array of the first microdisplay panel; on the other hand, it transmits it through the third connector 80c to the third connector 833a, and then through the circuit board 832 to the pixel array of the third microdisplay panel.

[0096] In the embodiment shown in Figure 6, the circuit board 80 is tree-shaped, with the first connector 80a, the second connector 80b, and the third connector 80c located at the leaf ends of the tree, respectively.

[0097] In some embodiments, the circuit board 80 may also have other shapes. For example, referring to Figures 7 and 8, the circuit board 80 is mountain-shaped. A first connector 80a, a second connector 80b, and a third connector 80c are located at the three ends of the mountain-shaped structure, respectively. The second connector 80b may be a G connector for connecting to the second connector of the second micro-display panel. The first connector 80a may be an R connector for connecting to the first connector of the first micro-display panel. The third connector 80c may be a B connector for connecting to the third connector of the third micro-display panel. The first connector 80a and the second port 80 may be located on one side of the circuit board 80, and the third connector 80c may be located on the other side of the circuit board 80.

[0098] In one embodiment, the circuit board 80 may also be provided with a circuit board connector Y, which is used to connect the circuit board to the outside.

[0099] In a specific implementation, referring to Figures 7 and 8, the first connector 80a is located on the first surface of the circuit board 80, and the second connector 80b, the third connector 80c and the circuit board connector Y are located on the second surface of the circuit board 80, with the first surface and the second surface opposite to each other.

[0100] In a specific implementation, referring to Figures 7 and 8, the line connecting the circuit board connector Y to the first connector 80a and the third connector 80c is on the same straight line, and the line connecting the circuit board connector Y to the second connector 80b intersects with the line connecting the circuit board connector Y, the first connector 80a and the third connector 80c.

[0101] In a specific implementation, on the second surface of the circuit board 80, the area between the first connector 80a and the circuit board connector Y may have a first pre-fold Z1, the area between the second connector 80b and the circuit board connector Y may have a second pre-fold Z2, and the area between the third connector 80c and the circuit board connector Y has a third pre-fold Z3 and a fourth pre-fold Z4. Folding along the first pre-fold Z1, the second pre-fold Z2, the third pre-fold Z3, and the fourth pre-fold Z4, such that the first connector 80a, the second connector 80b, and the third connector 80c face the center of the same cube and are located on the three sides of the cube arranged in a U-shape (as shown in Figure 9).

[0102] In a specific implementation, the connector is folded along the first pre-fold Z1 so that the first connector is located above the circuit board connector Y; it is bent 90° along the second pre-fold Z2 so that the second connector 80b is located on one side of the circuit board connector Y; it is bent 90° along the third pre-fold Z3 and 90° along the fourth pre-fold Z4 so that the third connector 80c is opposite to the circuit board connector Y (as shown in Figure 9).

[0103] In the embodiments shown in Figures 9 to 11, the second microdisplay panel 83 includes not only an external connector but also two internal connectors, which are disposed opposite to each other on the two surfaces of the second connecting reinforcement plate 833b. In this case, the first shielding cover may not be provided on the outer side of the second connecting reinforcement plate 833b, and both the first connector 823a of the first microdisplay panel 82 and the third connector 843a of the third microdisplay panel 84 are internal connectors.

[0104] Specifically, the second microdisplay panel 83 has one external connector, namely the second connector 833a. The surface of the second connecting reinforcement plate 833b opposite to the second connector 833a is also provided with a fourth connector 833d and a fifth connector 833e. The fourth connector 833d is adapted to connect the second microdisplay panel 83 to the first connector 823a of the first microdisplay panel 82, thereby achieving the connection between the second microdisplay panel 82 and the third microdisplay panel 84. The fifth connector 833e is adapted to connect the second microdisplay panel 82 to the third connector 843a of the third microdisplay panel 83, thereby achieving the connection between the second microdisplay panel 82 and the third microdisplay panel 84.

[0105] In a specific implementation, referring to Figures 10 and 11, a second microdisplay panel 83 can be configured to generate a clock signal. This clock signal can be transmitted to the first microdisplay panel 82 via the fourth connector 833d, and to the third microdisplay panel 84 via the fifth connector 833e.

[0106] Referring to Figure 12, an embodiment of the present invention provides a clock synchronization method for a micro-display system, the method comprising:

[0107] Step 101: In response to the power-on of the microdisplay system, a first microdisplay panel of the microdisplay system generates a first clock signal, which can control the display of the first microdisplay panel.

[0108] In practical implementation, the first microdisplay panel can be any microdisplay panel in the microdisplay system. The first microdisplay panel can be pre-configured to generate a first clock signal of a fixed frequency. In this way, without additional configuration, the first clock signal of the required frequency can be generated behind the microdisplay panel.

[0109] In some embodiments, in order to adjust the frequency of the first clock signal more flexibly to meet diverse display requirements, first clock frequency configuration information may be received before the first clock signal is generated.

[0110] In practice, various methods can be used to receive the first clock frequency configuration information. For example, a clock frequency adjustment button can be set on the micro-display panel, and the user can change the frequency of the clock signal by operating the clock frequency adjustment button.

[0111] In one embodiment, the clock frequency configuration information is pre-configured by a host computer via clock configuration commands. Specifically, the micro-display panel may be equipped with an external communication interface that can communicate with the host computer. The host computer can send clock configuration commands to the micro-display panel through this communication interface, thereby changing the frequency of the first clock signal. This improves the frequency adjustment accuracy of the first clock signal and better meets display requirements.

[0112] Step 102: The first clock signal generated by the first micro-display panel can be output to a second micro-display panel of the micro-display system, and control the display of the second micro-display panel.

[0113] In practice, the second micro-display panel can be any micro-display panel within the micro-display system that is different from the first micro-display panel. The first clock signal can be output to the micro-display system to control the second micro-display panel to display, without the need for the host computer to provide a clock signal to the second micro-display panel, or for the second micro-display panel to generate its own clock signal.

[0114] In one embodiment of the present invention, the method may further include: receiving a first clock off indication signal to stop generating the first clock signal.

[0115] Specifically, the first clock signal can be generated upon power-on, and when it needs to be turned off, the generation of the first clock signal can be stopped by a first clock off indication signal.

[0116] In some embodiments, the first clock-off indication signal can be generated based on a host computer configuration. For example, the host computer can send a clock configuration command to the microdisplay panel, which can carry the first clock-off indication information. After receiving the clock configuration command, the microdisplay panel generates the first clock-off indication signal based on the expected first clock-off indication information to stop generating the first clock signal. After the microdisplay panel stops generating the first clock signal, it can receive the first clock signals generated by other microdisplay panels in the same color optical engine for color display.

[0117] In another embodiment, the generation of the first clock signal can be stopped by adjusting the clock frequency adjustment button on the microdisplay panel. For example, turning the clock frequency adjustment button to the position where the clock frequency is 0 will stop the generation of the first clock signal.

[0118] After the microdisplay panel is powered on, once it receives the first clock off indication signal, it stops generating the first clock signal and the first clock signal is provided by other connected microdisplay panels.

[0119] In one embodiment of the present invention, referring to FIG12, the method further includes:

[0120] Step 103: In response to receiving an external configuration command, configure the second microdisplay panel to use a second clock signal to control the display of the second microdisplay panel, and output the second clock signal to the first microdisplay panel, wherein the second clock signal is generated by the second microdisplay panel; and configure the first microdisplay panel to use the second clock signal to control the display of the first microdisplay panel.

[0121] The external configuration command can be sent from the host computer to the micro-display system. The external configuration command is used to switch the clock signal used by the micro-display system to control the display.

[0122] In some embodiments, the external configuration command may carry an identifier of the microdisplay panel that provides the clock signal for the microdisplay system to control the display, so that the microdisplay system can select the corresponding microdisplay panel to generate the clock signal based on the external configuration command.

[0123] In other embodiments, the external configuration command may not carry an identifier for the microdisplay panel that provides the clock signal for the microdisplay system to control the display. As long as the microdisplay system receives the external configuration command, it can autonomously select another microdisplay panel to generate the clock signal according to the current situation.

[0124] In practical implementation, after receiving external configuration commands, the microdisplay system can use a second clock signal to replace the first clock signal for display control. This second clock signal can be generated by the second microdisplay panel. In other words, under the configuration of external commands, the microdisplay system can switch the clock signal used to control the display.

[0125] In practical implementation, when the micro-display system selects the second clock signal generated by the second micro-display panel for control system display, it should control the output of the second clock signal to the first micro-display panel so that the first micro-display panel uses the second clock signal to control the display of the first micro-display panel.

[0126] In a specific implementation, referring to Figure 4, before configuring the second microdisplay panel 42 to control the display of the second microdisplay panel using a second clock signal, the method further includes: in response to the power-on of the microdisplay system, the second microdisplay panel 42 generates the second clock signal. That is, by powering on the microdisplay system, the second microdisplay panel 42 generates the second clock signal.

[0127] Specifically, the microdisplay system can configure a second selection switch X2 on the second microdisplay panel 42, so that the second clock signal is sent to the second driving circuit 421 within the second microdisplay panel 42. The microdisplay system can also configure a second connection interface IO2 on the second microdisplay panel 42, so that the second clock signal is output to the first microdisplay panel 41. Thus, the second microdisplay panel 42 can generate the second clock signal to control both itself and the first microdisplay panel 41 to perform displays.

[0128] In a specific implementation, the second microdisplay panel 42 can generate the second clock signal in the following manner: first, configure a second oscillator OSC1 of the second microdisplay panel 42 to generate the second clock signal; then, configure a second selection switch X2 of the second microdisplay panel 42 to transmit the second clock signal to the second driving circuit 421 in the second microdisplay panel 42; finally, configure a second connection interface IO2 of the second microdisplay panel 42 to output the second clock signal to the first microdisplay panel 41.

[0129] In a specific implementation, referring to Figure 4, when configuring the first micro-display panel 41 to use the second clock signal to control the display of the first micro-display panel 41, a first connection interface IO1 of the first micro-display panel 41 can be configured to receive the second clock signal, and then a first selection switch X1 of the first micro-display panel 41 can be configured to transmit the second clock signal to the first driving circuit 411 within the first micro-display panel 41. When the first driving circuit 411 receives the second clock signal, it displays the signal under the control of the second clock signal.

[0130] In another embodiment, configuring the first microdisplay panel 41 to use the second clock signal to control the display of the first microdisplay panel 41 may include: first configuring a first oscillator OSC1 of the first microdisplay panel 41 to stop generating the clock signal, then configuring a first connection interface IO1 of the first microdisplay panel 41 to receive the second clock signal, and transmitting the second clock signal to a first driving circuit 411 of the first microdisplay panel 41.

[0131] In a specific implementation, the first oscillator OSC1 can be controlled to stop generating the first clock signal by sending a first clock off indication signal to the first oscillator OSC1 receiving the first micro-display panel 41. The first clock signal can be generated upon power-on, and its generation can be stopped by the first clock off indication signal when it needs to be turned off.

[0132] In some embodiments, the first clock-off indication signal can be generated based on a host computer configuration. For example, the host computer can send a clock configuration command to the microdisplay panel, which can carry the first clock-off indication information. After receiving the clock configuration command, the microdisplay panel generates the first clock-off indication signal based on the expected first clock-off indication information to stop generating the first clock signal. After the microdisplay panel stops generating the first clock signal, it can receive the first clock signals generated by other microdisplay panels in the same color optical engine for color display.

[0133] In another embodiment, the generation of the first clock signal can be stopped by adjusting the clock frequency adjustment button on the microdisplay panel. For example, turning the clock frequency adjustment button to the position where the clock frequency is 0 will stop the generation of the first clock signal.

[0134] After the microdisplay panel is powered on, once it receives the first clock off indication signal, it stops generating the first clock signal and the first clock signal is provided by other connected microdisplay panels.

[0135] In specific implementations, the microdisplay system may further include at least one third microdisplay panel. The third microdisplay panel is a microdisplay panel in the microdisplay system that differs from the first and second microdisplay panels. The number of third microdisplay panels may be one or more.

[0136] When the first microdisplay panel generates a first clock signal, the first clock signal can also be output to at least one third microdisplay panel of the microdisplay system and control the display of the third microdisplay panel.

[0137] When the second microdisplay panel generates a second clock signal, the second clock signal can also be output to at least one third microdisplay panel of the microdisplay system and control the display of the third microdisplay panel.

[0138] After the micro-display system is powered on, the first micro-display panel generates a first clock signal, and controls all micro-display panels in the micro-display system to display in color through the first clock signal, thereby reducing the consumption of connecting lines and thus reducing production costs.

[0139] Figure 13 is a schematic diagram of the structure of a microdisplay panel 50 according to an embodiment of the present invention. Referring to Figure 13, an embodiment of the present invention also provides a microdisplay panel 50, which may include: a panel body and a clock generating module 53. Wherein:

[0140] The panel body includes a pixel array 51 and a pixel driving circuit 52, and the pixel driving circuit 52 is connected to the pixel array 51.

[0141] The clock generation module 53 is embedded in the panel body. The clock generation module 53 can generate a clock signal when the panel body is powered on. The pixel driving circuit 52 can control the display of the pixel array 51 based on the clock signal.

[0142] In specific implementations, the clock generation module 53 can be implemented using a variety of devices.

[0143] In one embodiment, the clock generation module 53 can be implemented using an oscillator. The oscillator generates an output signal through self-oscillation using an internal feedback circuit, converting DC power into AC power with a specific frequency. Oscillators are typically integrated and packaged from a quartz crystal resonator and related functional circuitry. Oscillators offer high frequency accuracy and are commonly used to generate stable high-frequency signals. Furthermore, oscillators are relatively less affected by environmental factors such as temperature and humidity, exhibiting high stability and thus are suitable for various operating environments, providing a stable clock signal across different temperature ranges.

[0144] In a specific implementation, the pixel array 51, the pixel driving circuit 52, and the clock generation module 53 can be integrated onto the Micro LED chip. The clock generation module 53 can be connected to the pixel driving circuit 52 to provide a clock signal to the pixel driving circuit 52. The pixel driving circuit 52 controls the scanning state of some or all of the pixels in the pixel array 51 based on this clock signal.

[0145] The pixel array 51 is located in the light-emitting area of ​​the Micro LED chip. The pixel arrangement in the pixel array 51 can be one of 320×240, 640×480, 1600×1200, 1920×1080, or 2560×1440. In some embodiments, the size of a single pixel in the pixel array is between 100nm and 100μm. In some embodiments, the size of a single pixel in the pixel array is between 150nm and 15μm. In some embodiments, the size of a single pixel in the pixel array can also be less than 10μm.

[0146] In a specific implementation, referring to Figure 12, the clock generation module 53 receives an enable signal EN and generates a clock signal OSC_CLK upon power-on. At this time, the frequency of the clock signal OSC_CLK is preset and fixed.

[0147] In some embodiments, the clock generation module 53 is further adapted to receive clock frequency configuration information TR before generating the clock signal OSC_CLK, the clock frequency configuration information TR being adapted to control the frequency of the clock signal OSC_CLK.

[0148] The clock frequency configuration information TR can be configured by the host computer through clock configuration instructions. Of course, other methods can also be used to change the frequency of the clock signal OSC_CLK, and there are no restrictions here.

[0149] In a specific implementation, the micro-display panel may have a connection interface, which is connected to the oscillator, and the clock signal can be output to the outside through the connection interface. Specifically, referring to FIG4, taking the first micro-display panel 41 as an example, the first micro-display panel 41 may have a first connection interface IO1, which is connected to the first oscillator OSC1, and the first clock signal can be output to the outside through the first connection interface IO1.

[0150] In a specific implementation, the micro-display panel further includes a selection switch, which has two input ports and one output port. The two input ports are respectively connected to the oscillator and the connection interface, and the output port is connected to the driving circuit. The selection switch can be configured to select whether to send the clock signal generated by the oscillator to the driving circuit or to send the clock signal received from the outside through the connection port to the driving circuit.

[0151] Specifically, referring to Figure 4, taking the first micro-display panel 41 as an example, the first micro-display panel 41 may include a first selection switch X1, which is connected to the first driving circuit 411. Through the first selection switch X1, the first clock signal generated by the first oscillator OSC1 can be output to the first driving circuit 411, and the external clock signal can be received through the first connection interface IO1.

[0152] This invention also provides a micro-display system, which includes three or more micro-display panels according to any of the above embodiments, and the connection interfaces of the three or more micro-display panels are interconnected.

[0153] In one embodiment, referring to FIG13, the microdisplay system may include a red light microdisplay panel 71, a green light microdisplay panel 72, and a blue light microdisplay panel 73.

[0154] In some embodiments, only the red light micro-display panel 71 may be provided with a first clock generation module OSC1, which provides clock signals to the red light micro-display panel 71, the green light micro-display panel 72 and the blue light micro-display panel 73.

[0155] In some embodiments, a first clock generation module OSC1 is provided in the red light micro-display panel 71, and a second clock generation module OSC2 is provided in the green light micro-display panel 72. The first clock generation module OSC1 can provide clock signals to the red light micro-display panel 71, the green light micro-display panel 72, and the blue light micro-display panel 73, and the second clock generation module OSC2 can also provide clock signals to the red light micro-display panel 71, the green light micro-display panel 72, and the blue light micro-display panel 73.

[0156] In some embodiments, a first clock generation module OSC1 is provided in the red microdisplay panel 71, a second clock generation module OSC2 is provided in the green microdisplay panel 72, and a third clock generation module OSC3 is provided in the blue microdisplay panel 73. The first clock generation module OSC1 can provide clock signals to the red microdisplay panel 71, the green microdisplay panel 72, and the blue microdisplay panel 73. Alternatively, the second clock generation module OSC2 can provide clock signals to the red microdisplay panel 71, the green microdisplay panel 72, and the blue microdisplay panel 73. Or, the third clock generation module OSC3 can provide clock signals to the red microdisplay panel 71, the green microdisplay panel 72, and the blue microdisplay panel 73.

[0157] In practical implementation, each micro-display panel of the micro-display system can be equipped with a connection interface, and the connection interfaces of the three micro-display panels are connected to each other. For example, referring to Figure 9, the connection interface of the red light micro-display panel 71 is connected to the connection interfaces of the green light micro-display panel 72 and the blue light micro-display panel 73. In this way, no matter which micro-display panel generates a clock signal, it can be output to the other two micro-display panels through the connection interface.

[0158] When two or more micro-display panels in a micro-display system are equipped with clock generation modules, if the clock generation module in one of the micro-display panels fails, the clock signal can be switched to another micro-display panel with a clock generation module.

[0159] For example, referring to Figure 13, when the first clock generation module OSC1 in the red light micro-display panel 71 fails, the clock signal can be switched to the second clock generation module OSC2 in the green light micro-display panel 72. This allows the clock signal to be obtained again without replacing or repairing the micro-display panel, thereby reducing the cost of use and improving the convenience of use.

[0160] In one embodiment, referring to FIG16, the microdisplay system may include two color optical engines, namely a first color optical engine 131 and a second color optical engine 132. The first color optical engine 131 includes three microdisplay panels, namely a first microdisplay panel 1311, a second microdisplay panel 1312, and a third microdisplay panel 1313. The second color optical engine 132 includes three third microdisplay panels, namely a fourth microdisplay panel 1321, a fifth microdisplay panel 1322, and a sixth microdisplay panel 1323.

[0161] Specifically, the first micro-display panel 1311 houses a first clock generation module OSC1, the second micro-display panel 1312 houses a second clock generation module OSC2, the third micro-display panel 1313 houses a third clock generation module OSC3, the fourth micro-display panel 1321 houses a fourth clock generation module OSC4, the fifth micro-display panel 1322 houses a fifth clock generation module OSC5, and the sixth micro-display panel 1323 houses a sixth clock generation module OSC6.

[0162] In practical implementation, a clock generation module can be set in any micro-display panel within the color optical engine to provide the clock signal. For example, a second clock generation module OSC2 of the second micro-display panel 1312 can be set to provide clock signals for the first micro-display panel 1311 and the third micro-display panel 1313. A fifth clock generation module OSC5 of the fifth micro-display panel 1322 can be set to provide clock signals for the fourth micro-display panel 1321 and the sixth micro-display panel 1323.

[0163] In a specific implementation, the microdisplay system may further include a host computer. The host computer can be connected to the color optical engine and is adapted to select a clock generation module of a microdisplay panel from the color optical engine to generate the clock signal. For example, referring to FIG16, the microdisplay system may include a host computer 133, which can be connected to a first color optical engine 131 and a second color optical engine 132, and can select a clock generation module of a microdisplay panel from the first color optical engine 131 to generate the clock signal, and select a clock generation module of a microdisplay panel from the second color optical engine 132 to generate the clock signal.

[0164] As can be seen from the above, the solution of this embodiment of the invention reduces the number of connection lines between the host computer and the micro-display panel because the micro-display panel does not require a clock signal from the host computer. This reduces the total physical width of the connection lines between the host computer and the micro-display panel, which is beneficial for product miniaturization. It also reduces the interference of the clock signal output by the host computer on other signals of the micro-display panel, improves the reliability of the micro-display panel, and helps to ensure that the clock signal frequency of all micro-display panels is consistent.

[0165] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A clock synchronization method for a micro-display system, characterized in that, include: In response to the power-on of the microdisplay system, a first microdisplay panel of the microdisplay system generates a first clock signal, which can control the display of the first microdisplay panel; The first clock signal generated by the first micro-display panel can be output to a second micro-display panel of the micro-display system and control the display of the second micro-display panel.

2. The clock synchronization method for a micro-display system as described in claim 1, characterized in that, The synchronization method further includes: In response to receiving an external configuration command, the system configures the second microdisplay panel to use a second clock signal to control the display of the second microdisplay panel, and outputs the second clock signal to the first microdisplay panel, wherein the second clock signal is generated by the second microdisplay panel; and configures the first microdisplay panel to use the second clock signal to control the display of the first microdisplay panel.

3. The clock synchronization method for a micro-display system as described in claim 2, characterized in that, Prior to configuring the second microdisplay panel to control its display using a second clock signal, the process further includes: In response to the power-on of the microdisplay system, the second microdisplay panel generates the second clock signal; The step of generating the second clock signal from the second micro-display panel includes: Configure a second selection switch on the second micro-display panel so that the second clock signal is sent to the second driving circuit within the second micro-display panel; Configure a second connection interface of the second microdisplay panel so that the second clock signal is output to the first microdisplay panel.

4. The clock synchronization method for a micro-display system as described in claim 2, characterized in that, The step of configuring the second microdisplay panel to use a second clock signal to control the display of the second microdisplay panel and outputting the second clock signal to the first microdisplay panel, wherein the second clock signal is generated by the second microdisplay panel, includes: A second oscillator configured in the second microdisplay panel generates the second clock signal; Configure a second selection switch on the second micro-display panel so that the second clock signal is sent to the second driving circuit within the second micro-display panel; Configure a second connection interface of the second microdisplay panel so that the second clock signal is output to the first microdisplay panel.

5. The clock synchronization method for a microdisplay system as described in claim 3 or 4, characterized in that, The steps of configuring the first microdisplay panel to control the display of the first microdisplay panel using the second clock signal include: The first connection interface of the first micro-display panel is configured to receive the second clock signal; A first selection switch configured in the first microdisplay panel transmits the second clock signal to the first driving circuit within the first microdisplay panel.

6. The clock synchronization method for a microdisplay system as described in claim 3 or 4, characterized in that, The steps of configuring the first microdisplay panel to control the display of the first microdisplay panel using the second clock signal include: A first oscillator in the first microdisplay panel is configured to stop generating the clock signal; A first connection interface of the first microdisplay panel is configured to receive the second clock signal and transmit the second clock signal to a first driving circuit of the first microdisplay panel.

7. The clock synchronization method for a micro-display system as described in claim 1, characterized in that, The first clock signal generated by the first microdisplay panel can also be output to at least one third microdisplay panel of the microdisplay system and control the display of the third microdisplay panel.

8. The clock synchronization method for a microdisplay system as described in claim 2, characterized in that, The second clock signal generated by the second micro-display panel can also be output to at least one third micro-display panel of the micro-display system and control the display of the third micro-display panel.

9. A micro-display system, characterized in that, include: A first micro-display panel, which generates a first clock signal when the micro-display system is powered on, and the first clock signal controls the display of the first micro-display panel; The second micro-display panel is communicatively connected to the first micro-display panel. The first clock signal generated by the first micro-display panel can be output to the second micro-display panel and control the display of the second micro-display panel.

10. The microdisplay system as described in claim 9, characterized in that, The first micro-display panel includes a first oscillator, a first driving circuit, and a first connection interface. The output terminal of the first oscillator is connected to the first driving circuit and the first connection interface respectively. The first oscillator can generate the first clock signal. The first driving circuit can control the display of the first micro-display panel based on the first clock signal; The second micro-display panel includes a second driving circuit and a second connection interface. The second connection interface is connected to the second driving circuit and also to the first connection interface. The first clock signal can be transmitted to the second driving circuit through the first connection interface and the second connection interface, and the second driving circuit can control the display of the second micro display panel based on the first clock signal.

11. The microdisplay system as claimed in claim 10, characterized in that, The second micro-display panel further includes a second oscillator, the output of which is connected to the second driving circuit and the second connection interface respectively; The second micro-display panel can configure the second oscillator to generate a second clock signal based on external configuration instructions, so that the second driving circuit controls the display of the second micro-display panel based on the second clock signal, and configures the second connection interface to output the second clock signal to the first micro-display panel; The first micro-display panel can be configured to use the first clock signal to control the display of the first micro-display panel based on external configuration instructions.

12. The microdisplay system as claimed in claim 11, characterized in that, Based on the external configuration instructions, the first micro-display panel can configure the first oscillator to stop generating the first clock signal and configure the first connection interface to receive the second clock signal, so that the first driving circuit controls the display of the first micro-display panel based on the first clock signal.

13. The microdisplay system as claimed in claim 11, characterized in that, The first micro-display panel further includes a first selection switch, which has two input ports and one output port. The two input ports of the first selection switch are respectively connected to the first oscillator and the first connection interface, and the output port of the first selection switch is connected to the first driving circuit. Based on the external configuration instructions, the first micro-display panel can be configured to receive the second clock signal through the first connection interface, and the first selection switch can be configured to send the second clock signal to the first driving circuit, so that the first driving circuit controls the display of the first micro-display panel based on the first clock signal.

14. The microdisplay system as described in claim 13, characterized in that, The second micro-display panel further includes a second selection switch, which has two input ports and one output port. The two input ports of the second selection switch are respectively connected to the second oscillator and the second connection interface, and the output port of the second selection switch is connected to the second driving circuit. The second micro-display panel can configure the second oscillator to generate a second clock signal based on external configuration instructions, and then configure the second selection switch of the second micro-display panel so that the second clock signal is sent to the second driving circuit in the second micro-display panel.

15. The microdisplay system as claimed in claim 11, characterized in that, The first micro-display panel has a first register, which is connected to the first oscillator; the second micro-display panel has a second register, which is connected to the second oscillator. Modifying the configuration information stored in the first register can control the first oscillator to generate or stop generating the first clock signal; Modifying the configuration information stored in the second register can control the second oscillator to generate or stop generating the second clock signal.

16. The microdisplay system as claimed in claim 9, characterized in that, The microdisplay system further includes at least one third microdisplay panel, which is communicatively connected to the first microdisplay panel. The first clock signal generated by the first microdisplay panel can be output to the at least one third microdisplay panel and control the display of the at least one third microdisplay panel.

17. The microdisplay system as claimed in claim 11, characterized in that, The microdisplay system further includes at least one third microdisplay panel, which is communicatively connected to the second microdisplay panel. The second clock signal generated by the second microdisplay panel can be output to the at least one third microdisplay panel and control the display of the at least one third microdisplay panel.

18. The microdisplay system as described in claim 16 or 17, characterized in that, The number of the at least one third micro-display panel is one; The first microdisplay panel, the second microdisplay panel, and the third microdisplay panel can emit three different colors of light, namely red, green, and blue; the first microdisplay panel, the second microdisplay panel, and the third microdisplay panel can be assembled into a color optical engine.

19. The microdisplay system as described in claim 16 or 17, characterized in that, The number of the at least one third micro-display panel is four; One of the third micro-display panels, together with the first micro-display panel and the second micro-display panel, can emit three different colors of light, namely red, green and blue; the first micro-display panel, the second micro-display panel and the third micro-display panel can be assembled into a first color optical engine; The other three third micro-display panels can emit three different colors of light, namely red, green and blue; the three third micro-display panels can be assembled into a second color optical engine.

20. The microdisplay system as claimed in claim 16 or 17, characterized in that, Also includes: A circuit board; the circuit board includes: a first connector, a second connector, and a third connector; The first connector is used to connect to the first micro-display panel; The second connector is used to connect to the second micro-display panel; The third connector is used to connect to the third micro-display panel; Among them, one port of the first connector, the second connector and the third connector is adapted to receive the clock signal generated by the connected micro display panel, and send it to the connected micro display panel through the other two ports for connecting the first micro display panel, the second micro display panel and the third micro display panel.

21. A circuit board, characterized in that, include: A first connector, a second connector, and a third connector; the first connector is used to connect to a first micro-display panel, the second connector is used to connect to a second micro-display panel, and the third connector is used to connect to the third micro-display panel. Among them, one of the first connector, the second connector, and the third connector is adapted to receive the clock signal generated by the connected microdisplay panel and send it to the connected microdisplay panel through the other two ports.

22. The circuit board as claimed in claim 21, characterized in that, Also includes: Internal circuitry; the first connector, the second connector, and the third connector are connected via the internal circuitry.

23. The circuit board as described in claim 22, characterized in that, Also includes: A circuit board connector for connecting the circuit board to an external environment.

24. The circuit board as claimed in claim 23, characterized in that, The circuit board is tree-shaped, with the first connector, the second connector, and the third connector located at the leaf ends of the tree, respectively.

25. The circuit board as described in claim 23, characterized in that, The circuit board is mountain-shaped, and the first connector, the second connector, and the third connector are located at the three ends of the mountain-shaped structure, respectively.

26. The circuit board as described in claim 25, characterized in that, The first connector is located on the first surface of the circuit board, and the second connector, the third connector and the circuit board connector are located on the second surface of the circuit board, with the first surface and the second surface opposite to each other.

27. The circuit board as claimed in claim 26, characterized in that, On the second surface of the circuit board, the area between the first connector and the circuit board connector has a first pre-fold, the area between the second connector and the circuit board connector has a second pre-fold, and the area between the third connector and the circuit board connector has a third and a fourth pre-fold. Folding along the first, second, third, and fourth pre-folds, the first, second, and third connectors face the center of the same cube and are located on the three sides of the cube arranged in a U-shape.

28. The circuit board as claimed in claim 27, characterized in that, Fold along the first pre-fold so that the first connector is above the circuit board connector; bend 90° along the second pre-fold so that the second connector is on one side of the circuit board connector; bend 90° along the third pre-fold and bend 90° along the fourth pre-fold so that the third connector is opposite the circuit board connector.

29. The circuit board as claimed in claim 26, characterized in that, The circuit board connector is connected to the first connector and the third connector on the same straight line, and the circuit board connector is connected to the second connector, which intersects with the circuit board connector, the first connector and the third connector.

30. A micro-display panel, characterized in that, include: A panel body, the panel body including a pixel array and a pixel driving circuit, the pixel driving circuit being connected to the pixel array; A clock generation module is embedded in the panel body. The clock generation module can generate a clock signal when the panel body is powered on, and the pixel driving circuit can control the display of the pixel array based on the clock signal.

31. The microdisplay panel as claimed in claim 30, characterized in that, The clock generation module is an oscillator.

32. The microdisplay panel as claimed in claim 31, characterized in that, The micro-display panel has a connection interface, which is connected to the oscillator, and the clock signal can be output to the outside through the connection interface.

33. The microdisplay panel as described in claim 32, characterized in that, The micro-display panel further includes a selection switch, which has two input ports and one output port. The two input ports are respectively connected to the oscillator and the connection interface, and the output port is connected to the driving circuit. The selection switch can be configured to either send the clock signal generated by the oscillator to the drive circuit, or send the clock signal received from the outside via the connection port to the drive circuit.

34. A micro-display system, characterized in that, It includes three or more microdisplay panels as described in any one of claims 30 to 33, and the connection interfaces of the three or more microdisplay panels are interconnected.

35. An electronic device, characterized in that, The microdisplay system included in any one of claims 9-19 and 34.

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