Coding apparatus and coding method for pipelined ADC

Abstract

Disclosed in the present application is a coding apparatus for a pipelined ADC. The coding apparatus comprises: a comparator circuit, which is connected to a differential input signal, and outputs a plurality of comparison results; a first coding circuit, which performs an NAND operation on every two of the plurality of comparison results to output a plurality of NAND operation results, and outputs a first signal and / or a second signal on the basis of the plurality of NAND operation results and the level of a first selection signal and under the control of a clock signal; a coding control circuit, which generates a second selection signal on the basis of the probability of the occurrence of each signal in a first digital code, receives a third signal and a fourth signal, and outputs the first selection signal on the basis of the level of the second selection signal; and a second coding circuit, which outputs a second digital code on the basis of the first digital code and under the switching control of a plurality of switch transistors. By means of the coding apparatus provided in the present invention, it is not necessary to provide a dedicated offset voltage correction mode of a comparator, such that an ADC can correct an offset voltage of the comparator during normal operation, thereby simplifying the operation timing of a circuit.

Description

A pipelined ADC encoding device and encoding method Technical Field

[0001] This application relates to the field of analog integrated circuit technology, specifically to a pipelined ADC encoding device and encoding method. Background Technology

[0002] In traditional pipelined ADCs, the sub-ADCs in a single-stage pipeline are typically flash memory ADCs. Flash memory ADCs contain multiple comparators. During operation, these comparators are enabled by the same clock and simultaneously compare the same input signal with different reference voltages. After comparison, the outputs of the comparators are input to the encoding circuit for encoding. The encoded digital code is then input to the digital circuit and added with the output digital codes of the remaining stages in a staggered manner to output the final conversion result digital code of the ADC. Because offset voltages exist between the multiple comparators in a flash memory ADC, errors occur in the output digital code of the encoding circuit, ultimately affecting the accuracy of the entire ADC. Therefore, a correction method for comparator offset voltage has been proposed. The traditional method is an analog domain correction method, which involves connecting multiple correction capacitors to the comparator inputs. When the flash ADC is powered on, an offset voltage correction mode is set. By adjusting the correction capacitors at the inputs of each comparator, the offset voltage of the comparator is adjusted, ultimately ensuring that the comparator offset voltage meets the accuracy requirements.

[0003] In traditional pipelined ADCs, the offset voltage correction of flash ADCs has the following problems: (1) Due to the need for a dedicated offset voltage correction mode, the offset voltage of multiple comparators is corrected in this mode, which makes the circuit operation timing more complicated; (2) Due to the use of analog domain correction method, the digital domain signal needs to be introduced into the analog domain. When there are many comparators, it will lead to complex layout routing, and will also introduce non-ideal jitter and noise in the digital domain, reducing the accuracy of analog circuits; (3) Due to the introduction of trimming capacitors at the comparator input, the load of the sampling network is increased, the input bandwidth is reduced, and the circuit area and complexity are increased.

[0004] Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a pipelined ADC encoding device and encoding method to solve at least one problem existing in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a pipelined ADC encoding apparatus, the encoding apparatus comprising:

[0007] A comparator circuit has a differential input signal at its input terminal and outputs multiple comparison results.

[0008] The first encoding circuit, connected to the comparator circuit, performs pairwise NAND operations on the multiple comparison results, outputs multiple NAND operation results, and outputs one or more first signals and / or one or more second signals based on the multiple NAND operation results and the high or low level of the first selection signal under the control of the clock signal; the one or more first signals and / or one or more second signals constitute a first digital code;

[0009] The encoding control circuit is connected to the output of the first encoding circuit. It generates a second selection signal based on the occurrence probability of each signal in the first digital code, and receives a third signal and a fourth signal and outputs a first selection signal according to the high or low level of the second selection signal. The third signal is generated by a random number generator.

[0010] The second encoding circuit has its input terminal connected to the output terminal of the first encoding circuit, and outputs the second digital code according to the first digital code under the switching control of multiple switching transistors.

[0011] In one embodiment of the present invention, the comparator circuit includes a plurality of comparators arranged in parallel, and the first encoding circuit includes:

[0012] The NAND gate has its input connected to the comparison result, which is output through two adjacent outputs of two adjacent comparators. One output outputs a positive output signal, and the other output outputs a positive and a negative output signal.

[0013] A D flip-flop, whose signal input terminal is connected to the output terminal of the NAND gate, whose first output terminal outputs a first signal and whose second output terminal outputs a second signal;

[0014] The first selection module has a first input terminal connected to a first signal, a second input terminal connected to a second signal, a control terminal connected to a first selection signal, and outputs the first signal or the second signal according to the high or low level of the first selection signal.

[0015] In one embodiment of the present invention, when the first selection signal is high, the first selection module uses the first signal as the output signal; when the first selection signal is low, the first selection module uses the second signal as the output signal.

[0016] In one embodiment of the present invention, the encoding control circuit includes:

[0017] A random number generator that generates and outputs a third signal as a sequence of random numbers;

[0018] Multiple second selection modules have their input terminals connected to the output terminal of the random number generator, and are connected to a third signal and a fourth signal. Their control terminals are connected to the second selection signal and output a first selection signal according to the high or low level of the second selection signal. Each of the multiple second selection modules corresponds one-to-one with a multiple first selection module.

[0019] The code density determination module has its input end connected to the output end of the first selection module, receives the first digital code, and outputs a second selection signal according to the occurrence probability of each signal in the first digital code.

[0020] In one embodiment of the present invention, when the second selection signal is high, the second selection module uses the third signal as the output signal; when the second selection signal is low, the second selection module uses the fourth signal as the output signal.

[0021] In one embodiment of the present invention, the fourth signal is 0.

[0022] In one embodiment of the present invention, the second encoding circuit includes:

[0023] The first encoding module has its input terminal connected to the first digital code, and outputs the fifth signal according to the first digital code under the switching control of multiple switching transistors;

[0024] The second encoding module has its input terminal connected to the first digital code, and outputs a sixth signal according to the first digital code under the switching control of multiple switching transistors.

[0025] In one embodiment of the present invention, the first encoding module includes: a first MOS transistor to a fifth MOS transistor, a first resistor, and a first NOT gate; the source of the first MOS transistor is connected to a first voltage, the drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the second MOS transistor is connected to the drain of the third MOS transistor and forms a first connection node, and the source of the third MOS transistor is connected to a second voltage; the source of the fourth MOS transistor is connected to the first voltage, the drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor, the drain of the fifth MOS transistor, one end of the first resistor, and the input terminal of the first NOT gate are respectively connected to the first connection node, the other end of the first resistor is connected to the second voltage, and the output terminal of the first NOT gate outputs a fifth signal; the gates of the first MOS transistor, the third MOS transistor, and the fourth MOS transistor are respectively connected to an enable signal, and the gates of the second MOS transistor and the fifth MOS transistor are connected to a first digital code.

[0026] In one embodiment of the present invention, the first encoding module includes: a sixth MOS transistor to a tenth MOS transistor, a second resistor, and a second NOT gate; the source of the sixth MOS transistor is connected to a second voltage, the drain of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and forms a second connection node, and the source of the eighth MOS transistor is connected to a second voltage; the source of the ninth MOS transistor is connected to a first voltage, the drain of the ninth MOS transistor is connected to the source of the tenth MOS transistor, the drain of the tenth MOS transistor, one end of the second resistor, and the input terminal of the second NOT gate are respectively connected to the second connection node, the other end of the second resistor is connected to the second voltage, and the output terminal of the second NOT gate outputs a sixth signal; the gates of the sixth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are respectively connected to an enable signal, and the gates of the seventh MOS transistor and the tenth MOS transistor are connected to a first digital code.

[0027] To achieve the above and other related objectives, the present invention provides a pipelined ADC encoding method, the encoding method comprising:

[0028] It receives differential input signals and outputs multiple comparison results;

[0029] The multiple comparison results are subjected to pairwise NAND operations to output multiple NAND operation results. Under the control of the clock signal, one or more first signals and / or one or more second signals are output based on the multiple NAND operation results and the high or low level of the first selection signal. The one or more first signals and / or one or more second signals constitute a first digital code.

[0030] The system generates a second selection signal based on the occurrence probability of each signal in the first digital code, and receives a third signal and a fourth signal and outputs a first selection signal according to the high or low level of the second selection signal. The third signal is generated by a random number generator.

[0031] Under the switching control of multiple switching transistors, the second digital code is output according to the first digital code.

[0032] As described above, the pipelined ADC encoding device and encoding method provided in this application have the following features: Beneficial effects:

[0033] This invention provides a pipelined ADC encoding device, comprising: a comparator circuit whose input is connected to a differential input signal and outputs multiple comparison results; a first encoding circuit connected to the comparator circuit, which performs pairwise NAND operations on the multiple comparison results, outputs multiple NAND operation results, and outputs one or more first signals and / or one or more second signals based on the multiple NAND operation results and the high / low level of a first selection signal under the control of a clock signal; the one or more first signals and / or one or more second signals constitute a first digital code; an encoding control circuit connected to the output of the first encoding circuit, which generates a second selection signal based on the occurrence probability of each signal in the first digital code, and receives a third signal and a fourth signal and outputs a first selection signal based on the high / low level of the second selection signal, wherein the third signal is generated by a random number generator; and a second encoding circuit whose input is connected to the output of the first encoding circuit, which outputs a second digital code based on the first digital code under the switching control of multiple switching transistors. The encoding device proposed in this invention does not require a dedicated comparator offset voltage correction mode, allowing the ADC to correct the comparator offset voltage during normal operation, simplifying the circuit's timing. Simultaneously, this invention employs a digital domain correction method for flash memory. The offset voltage of the ADC is corrected without the need to interact between the digital domain signal and the analog domain signal, which reduces the complexity of the layout and the introduction of non-ideal jitter and noise in the digital domain, thus improving the accuracy of the circuit. Moreover, this invention eliminates the trimming capacitor at the comparator input in the traditional structure, reduces the load on the sampling network, increases the input bandwidth, and reduces the circuit area and complexity.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 is a schematic diagram of a single-stage flash ADC in a pipelined ADC in the prior art;

[0037] Figure 2 is a schematic diagram of a single-stage transfer function in a pipelined ADC in the prior art;

[0038] Figure 3 is a schematic diagram of a pipelined ADC encoding device according to an embodiment of this application;

[0039] Figures 4(a) to 4(c) are detailed circuit diagrams of a pipelined ADC encoding device according to an embodiment of this application;

[0040] Figures 5(a) to 5(e) are schematic diagrams of the comparator offset voltage and B0-B3 encoded output according to an embodiment of this application;

[0041] Figure 6 is a flowchart of an encoding method for pipelined ADC encoding according to an embodiment of this application. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0043] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] Although the terms “first,” “second,” “A,” and “B,” etc., may be used herein to describe various elements, these elements should not be limited by these terms and are used only to distinguish one element from another. For example, without departing from the scope of the art described below, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” includes a combination of multiple related items or any one of multiple related items.

[0045] As used herein, unless the context otherwise indicates, the singular form is also intended to include the plural form, and it will be understood that the term “comprising” means the presence of the stated feature, quantity, step, operation, element, or combination thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0046] Before describing the accompanying drawings in detail, it is intended to clarify that the division of components in this specification is based solely on the primary function of each component. That is, two or more components described below may be combined into one component, or may be divided into two or more components based on more detailed functions. In addition to the primary functions of the components, each component described below may also perform some or all of the functions of other components, and some primary functions of each component may be performed specifically by other components.

[0047] Pipeline ADCs have become an important architecture for ADCs due to their ability to achieve a good trade-off between speed and accuracy, and are widely used in radar, satellite positioning, and sensors. In traditional pipelined ADCs, the sub-ADCs in a single pipeline stage are typically flash memory ADCs. Flash memory ADCs contain multiple comparators. When the flash memory ADC is operating, these comparators are enabled by the same clock and simultaneously compare the same input signal with different reference voltages. After comparison, the outputs of the multiple comparators are input to the encoding circuit for encoding. After encoding, the digital code is input to the digital circuit, added with the output digital codes of the remaining stages in a staggered manner, and the final conversion result digital code of the ADC is output. Because there is an offset voltage between the multiple comparators in a flash memory ADC, errors occur in the output digital code of the encoding circuit, ultimately affecting the accuracy of the entire ADC. Therefore, a correction method for comparator offset voltage has been proposed. The traditional correction method is an analog domain correction method, which involves connecting multiple correction capacitors at the comparator input. After the flash ADC is powered on, the offset voltage correction mode is set. By adjusting the capacitance value of the correction capacitor at the input of each comparator, the offset voltage of the comparator is adjusted, so that the offset voltage of the comparator meets the accuracy requirements.

[0048] The advantages and disadvantages of existing comparator offset voltage correction methods in traditional pipelined ADC design are analyzed below. Taking a single-stage output 2-bit digital code as an example, the schematic diagram of a single-stage flash ADC in a traditional pipelined ADC is shown in Figure 1. A single-stage flash ADC consists of four comparators (comparator 0-comparator 3), comparator input adjustment capacitors (Ccp and Ccn), and an encoding circuit. The final output code of the encoding circuit is D1 / D0. The Flash ADC consists of comparators 0-comparator 3. The input terminals of each comparator are connected to the input signals VIP and VIN, respectively. For simplicity, the reference voltage at each comparator input terminal is not shown here. The input terminals of the four comparators are connected to the offset correction capacitors Ccp and Ccn, respectively. The positive output signals of the four comparators are OUT0-OUT3, and the negative output signals are OUTN0-OUTN3. After the positive and negative output signals of the four comparators are input to the encoding circuit, a 2-bit code D0 / D1 is finally generated. When the comparators are in offset voltage correction mode, a specific input signal is input, and the output terminals of the four comparators generate corresponding output signals. The digital circuit reads the output signals of the four comparators to determine the offset of each comparator. Then, it adjusts the correction capacitors Ccp and Ccn at the input terminals of each comparator through digital control signals. When the values ​​of the correction capacitors Ccp and Ccn at the comparator input terminals change, the offset voltage of the comparator is compensated, thereby realizing the comparator offset voltage correction function.

[0049] In traditional pipelined ADCs, the offset voltage correction of flash ADCs has the following problems: (1) Due to the need for a dedicated offset voltage correction mode, the offset voltage of multiple comparators is corrected in this mode, resulting in a more complex circuit timing. (2) Due to the use of analog domain correction methods, digital domain signals need to be introduced into the analog domain. When there are many comparators, it will lead to complex layout routing, and will also introduce non-ideal jitter and noise in the digital domain, reducing the accuracy of the analog circuit. (3) Due to the introduction of trimming capacitors at the comparator input, the load on the sampling network is increased, the input bandwidth is reduced, and the circuit area and complexity are increased.

[0050] Figure 2 shows a schematic diagram of the single-stage transfer function of a traditional pipelined ADC, where V0-V3 represent the threshold voltages of the four comparators, and the three-bit digital code corresponds to the output code of the corresponding interval. Since pipelined ADCs employ inter-stage redundancy bit technology, as long as the comparator offset does not exceed the threshold voltage of adjacent intervals, the final digital code will not have errors. For example, in Figure 2, as long as the fluctuation of the comparator threshold voltage V2 is between its two adjacent comparator threshold voltages V1 and V3, the pipeline's inter-stage redundancy bit technology can correct the aforementioned offset. When the comparator offset exceeds the threshold voltage of adjacent intervals, the inter-stage redundancy bit technology cannot effectively correct the offset voltage. This invention addresses the shortcomings of traditional comparator offset voltage correction methods in existing pipelined ADCs by proposing a pipelined ADC encoding device that uses digital correction to correct comparator offset. This device can correct the comparator offset when the fluctuation of V2 exceeds the range between V1 and V3.

[0051] Please refer to Figure 3, which is a schematic diagram of a pipelined ADC encoding device according to an embodiment of this application. As shown in Figure 3, the pipelined ADC encoding device includes:

[0052] Comparator circuit 310 has a differential input signal at its input terminal and outputs multiple comparison results;

[0053] The first encoding circuit 320 is connected to the comparator circuit. It performs pairwise NAND operations on the multiple comparison results, outputs multiple NAND operation results, and outputs one or more first signals and / or one or more second signals based on the multiple NAND operation results and the high or low level of the first selection signal under the control of the clock signal. The one or more first signals and / or one or more second signals constitute a first digital code.

[0054] The encoding control circuit 330 is connected to the output terminal of the first encoding circuit. It generates a second selection signal based on the occurrence probability of each signal in the first digital code, and receives a third signal and a fourth signal and outputs a first selection signal according to the high or low level of the second selection signal. The third signal is generated by a random number generator.

[0055] The second encoding circuit 340 has its input terminal connected to the output terminal of the first encoding circuit, and outputs the second digital code according to the first digital code under the switching control of multiple switching transistors.

[0056] The following provides a detailed explanation of each component module, using a single-level output of a 2-bit digital code as an example.

[0057] The comparator circuit includes multiple comparators arranged in parallel, as shown in Figure 4(a). The circuit has five comparators: Comparator 0, Comparator 1, Comparator 2, Comparator 3, and Comparator 4. Each comparator outputs differential input signals VIP and VIN. For simplicity, the reference voltage at each comparator input is not shown in the figure. Each comparator has two outputs: a positive output and a negative output. The positive output outputs signal OUTi (i = 0, 1, 2, 3, 4), and the negative output outputs signal OUTNi (i = 1, 2, 3, 4). The CLK signal is the clock signal for the comparator. When CLK is low, the comparator is in a reset state, and the D flip-flop (DFF) latches the output signal of the comparator from the previous comparator cycle. When CLK is high, the comparator is in a comparison state, comparing the input signals.

[0058] In one specific implementation, the first encoding circuit 320 includes multiple encoding modules, each of which includes:

[0059] The NAND gate has its input connected to the comparison result, which is output through two adjacent outputs of two adjacent comparators. One output outputs a positive output signal, and the other output outputs a positive and a negative output signal.

[0060] A D flip-flop (DFF) has its signal input terminal connected to the output terminal of the NAND gate, and its first output terminal outputs a first signal and its second output terminal outputs a second signal.

[0061] The first selection module MUX has a first input terminal connected to a first signal, a second input terminal connected to a second signal, a control terminal connected to a first selection signal, and outputs the first signal or the second signal according to the high or low level of the first selection signal.

[0062] Among them, comparator 4 and comparator 3 are two adjacent comparators, and the negative output terminal of comparator 4 and the positive output terminal of comparator 3 are two adjacent output terminals; the NAND gate includes two input terminals, which are connected to the comparison results output by the comparators.

[0063] As shown in Figure 4(a), one input of the first NAND gate is connected to the negative output OUTi of comparator 4, and the other input is connected to the positive output OUT of comparator 3. The D flip-flop (DFF) includes a signal input D, a clock input CP, a first output Q, and a second output QN. The signal input D is connected to the output of the NAND gate, the clock input CP is connected to the clock signal CLKN, and CLKN is the inverted signal of CLK. The first output Q outputs the first signal, and the second output QN outputs the second signal. The first selection module includes a control terminal S, a first input B, a second input A, and an output VO. The first input B is connected to the first output Q of the D flip-flop (DFF), and the second input A is connected to the second output QN of the D flip-flop (DFF). The control terminal is connected to the first selection signal, and outputs either the first signal or the second signal according to the level of the first selection signal. When the first selection signal is low, the first selection module MUX selects the value of the second input terminal A and outputs it to the output terminal VO. When the first selection signal is high, the MUX selects the value of the first input terminal B and outputs it to the output terminal VO. That is, when the first selection signal is low, the output terminal VO outputs the second signal, and when the first selection signal is high, the output terminal VO outputs the first signal. The control signals Si (i = 0, 1, 2, 3) control the corresponding MUX modules respectively.

[0064] Therefore, it can be seen that after comparators 0-5 receive the differential input signal, the signal passes through NAND gates, D flip-flops, and the first selection module, and then outputs the first digital code B0-B3.

[0065] Please refer to Figure 4(b), which is a circuit diagram of the encoding control circuit in this embodiment. In Figure 4(b), the encoding control circuit 330 includes:

[0066] A random number generator that generates and outputs a third signal as a sequence of random numbers;

[0067] Multiple second selection modules have their input terminals connected to the output terminal of the random number generator, and are connected to a third signal and a fourth signal. Their control terminals are connected to the second selection signal and output a first selection signal according to the high or low level of the second selection signal. Each of the multiple second selection modules corresponds one-to-one with a multiple first selection module.

[0068] The code density determination module has its input end connected to the output end of the first selection module, receives the first digital code, and outputs a second selection signal according to the occurrence probability of each signal in the first digital code.

[0069] In this embodiment, the number of second selection modules is the same as the number of first selection modules, each second selection module corresponds to one first selection module, and the output signal of the second selection module serves as the control signal of the first selection module.

[0070] As shown in Figure 4(b), the second selection module includes two input terminals, a control terminal S, and an output terminal VO. The first input terminal B is connected to the output of the random number generator, receiving data from the random number sequence, i.e., the third signal. The second input terminal A is connected to the fourth signal. In one embodiment, the fourth signal is 0. The control terminal S and the output of the code density judgment module are connected to the second selection signal. The second selection module MUX outputs either the third or fourth signal based on the level of the second selection signal. Specifically, when the second selection signal is low, the second selection module MUX selects the value of the second input terminal A and outputs it to the output terminal VO; when the second selection signal is high, the second selection module MUX selects the value of the first input terminal B and outputs it to the output terminal VO. In Figure 4(b), the random number generator generates random high and low level signals with the comparator's clock signal CLK as the period. These signals are input to the first input terminal B of the subsequent second selection module MUX. The second input terminal A of the second selection module MUX is connected to 0. The second selection module MUX outputs control signals Si (i = 0, 1, 2, 3), i.e., the first selection signal. In control diagram 4(b), the second selection signal ENi (i = 0, 1, 2, 3) controls each of the second selection modules MUX modules respectively. Figure 4(b) shows the code density judgment module, which determines the density of each code in the current level of digital codes B3-B0. When the density of a certain code in digital codes B3-B0 is 0, the corresponding control signal EN3-EN0 is generated.

[0071] Please refer to Figure 4(c), which is a circuit diagram of a second encoding circuit according to an embodiment of this application. In Figure 4(c), the second encoding circuit includes:

[0072] The first encoding module has its input terminal connected to the first digital code, and outputs the fifth signal according to the first digital code under the switching control of multiple switching transistors;

[0073] The second encoding module has its input terminal connected to the first digital code, and outputs a sixth signal according to the first digital code under the switching control of multiple switching transistors.

[0074] Specifically, the first encoding module includes: a first MOSFET to a fifth MOSFET, a first resistor, and a first NOT gate; the source of the first MOSFET is connected to a first voltage, the drain of the first MOSFET is connected to the source of the second MOSFET, the drain of the second MOSFET is connected to the drain of the third MOSFET to form a first connection node, and the source of the third MOSFET is connected to a second voltage; the source of the fourth MOSFET is connected to the first voltage, the drain of the fourth MOSFET is connected to the source of the fifth MOSFET, the drain of the fifth MOSFET, one end of the first resistor, and the input of the first NOT gate are respectively connected to the first connection node, the other end of the first resistor is connected to the second voltage, and the output of the first NOT gate outputs a fifth signal, which is a part of the second digital code; the gates of the first MOSFET, the third MOSFET, and the fourth MOSFET are respectively connected to an enable signal, and the gates of the second MOSFET and the fifth MOSFET are connected to the first digital code.

[0075] The first encoding module includes: a sixth to a tenth MOS transistor, a second resistor, and a second NOT gate; the source of the sixth MOS transistor is connected to a second voltage, the drain of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and forms a second connection node, and the source of the eighth MOS transistor is connected to the second voltage; the source of the ninth MOS transistor is connected to a first voltage, the drain of the ninth MOS transistor is connected to the source of the tenth MOS transistor, the drain of the tenth MOS transistor, one end of the second resistor, and the input of the second NOT gate are respectively connected to the second connection node, the other end of the second resistor is connected to the second voltage, and the output of the second NOT gate outputs a sixth signal, which is another part of the second digital code; the gates of the sixth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are respectively connected to an enable signal, and the gates of the seventh MOS transistor and the tenth MOS transistor are connected to the first digital code.

[0076] In this circuit, the first and second resistors form a master resistor. The first MOSFET M0, third MOSFET M4, fourth MOSFET M1, sixth MOSFET M5, ninth MOSFET M6, and eighth MOSFET M9 are enable transistors connected to the enable signal. The third MOSFET M3, fifth MOSFET M3, seventh MOSFET M7, and tenth MOSFET M8 are signal control transistors connected to the first digital code. As shown in the figure, the third MOSFET is connected to the encoding signal B2, the fifth MOSFET M3 to the encoding signal B3, the seventh MOSFET M7 to the encoding signal B1, and the tenth MOSFET M10 to the encoding signal B3. The final outputs are signal D1 from the first NOT gate and signal D0 from the second NOT gate, i.e., the sixth and fifth signals; where signals D1 and D0 are -2 bits. The truth table of the second-stage encoding circuit is shown in Table 1.

[0077] Table 1

[0078] The principle of the encoding device is described below. As shown in Figure 5(a), when there is no offset voltage in any of the comparators, as the differential input signal VIP-VIN increases, the positive output terminals OUTi (i = 0, 1, 2, 3, 4) of comparators 0 to 4 gradually change from low level to high level, and the negative output terminals OUTNi (i = 0, 1, 2, 3, 4) of comparators 0 to 4 gradually change from high level to low level. At this time, assuming that the control signals S0-S3 of the first selection module MUX in Figure 4(a) are all low level, the first selection module MUX selects the signal output of the second input terminal A. From the logic relationship in Figure 4(a), it can be seen that when there is no offset voltage in comparators 0 to 4, the output signals of each comparator are as shown in Figure 5(a). As the input signal increases, the digital codes B0-B3 will output 0001, 0010, 0100, and 1000 in sequence. If the input signal changes linearly, the probability of these four digital codes appearing is approximately the same. Assuming only comparator 2 exhibits a negative voltage, as shown in Figure 5(b), with the input signal remaining unchanged, the time it takes for OUT2 to transition from low to high will be earlier. The probability of the digit code 0010 appearing will gradually decrease, and the original occurrence of digit code 0010 will be gradually replaced by digit code 0100. Therefore, the probability of digit code 0100 appearing will gradually increase. Compared to the case where comparator 2 has no negative offset, the density changes of these three digit codes are as follows: the density of 0001 remains unchanged, the density of 0010 decreases, and the density of 0100 increases. As the negative offset of comparator 2 increases, causing the threshold voltage of comparator 2 to be lower than the threshold voltage of comparator 1, the digit code 0010 will not appear at all, and the original occurrence of digit code 0010 will be completely replaced by digit code 0100. At this point, the completely absent digit code is 0010, with digit codes 0001 and 0100 on either side. Compared to the case where comparator 2 has no negative offset, the density changes of these three digit codes are as follows: the density of 0001 remains unchanged, the density of 0010 is 0, and the density of 0100 is approximately twice that of the case without offset. As described above, when the threshold voltage of comparator 2 is lower than the threshold voltage of comparator 1, the pipeline inter-stage redundancy technique cannot effectively correct the negative offset of comparator 2. In this case, additional correction is needed for the negative offset voltage of comparator 2 that exceeds the correction range of the inter-stage redundancy technique.

[0079] When the threshold voltage of comparator 2 is less than the threshold voltage of comparator 1, the digital code that should have been 0010 becomes 0100. Therefore, if a portion of the 0100 digital code is selected and directly converted to 0010 through digital circuitry, a portion of the 0010 digital code can be obtained again. There are two scenarios for the selected 0100 digital code: First, if the selected 0100 digital code would already be 0010 without the negative offset of comparator 2, then the negative offset of comparator 2 needs to be compensated. Second, if the selected 0100 digital code is still 0100 without the negative offset of comparator 2, then a positive offset is introduced into comparator 2, increasing its equivalent threshold voltage. However, even with this correction approach, the digital code 0100 will still appear. This means that even if the equivalent threshold voltage of comparator 2 increases, its threshold voltage will still be less than the threshold voltage of comparator 3. Therefore, the positive offset voltage introduced by the correction will not cause the equivalent threshold voltage of comparator 2 to exceed the threshold voltage of comparator 3. At this point, the equivalent threshold voltage of comparator 2 is limited to between the threshold voltages of comparator 1 and comparator 3. Pipeline inter-stage redundancy can completely correct the positive offset introduced by the correction in comparator 2.

[0080] As shown in Figure 4(b), when all four digital codes 0001, 0010, 0100, and 1000 corresponding to Bi (i = 0, 1, 2, 3) appear, it means that the threshold voltage of the comparator is always between the threshold voltages of its adjacent comparators. The output ENi (i = 0, 1, 2, 3) of the code density judgment module is set to 0. At this time, the output digital codes Bi (i = 0, 1, 2, 3) in Figure 4(a) are not corrected. The offset voltage of the comparator can be corrected through pipeline inter-stage redundancy technology. When the negative offset voltage of comparator 2 makes the threshold voltage of comparator 2 less than the threshold voltage of comparator 1, the code density of 0010 will be 0. The code density judgment module judges the adjacent digital codes of the digital code 0010 with a code density of 0. There are two scenarios: First, the density of the codeword 0001 adjacent to 0010 increases significantly, while the density of the codeword 0100 adjacent to 0010 remains unchanged. This indicates that the 0010 code density is zero because the threshold voltage of comparator 1 exceeds the threshold voltage of comparator 2, as shown in Figure 5(b). The correction method involves randomly inverting the outputs of B0 and B1 in Figure 4(a). The outputs EN3-EN0 of the code density judgment module in Figure 4(b) are set to 0011, thus configuring the outputs S3-S0 of the MUX module in Figure 4(b) to 0011. Consequently, the corresponding MUX in Figure 4(a) randomly selects the Q and QN terminals of its preceding D flip-flop, causing B1 and B0 in Figure 4(a) to change from a constant output of 01 to a random output of 10 or 01, ultimately controlling the equivalent threshold voltage of comparator 1 between comparator 0 and comparator 2. The second scenario is that the density of the codeword 0001 adjacent to 0010 remains unchanged, while the density of the codeword 0100 adjacent to 0010 increases significantly. In this case, it indicates that the phenomenon of 0010 code density being 0 is due to the decrease in the threshold voltage of comparator 2, and its encoding relationship is shown in Figure 5(c). Therefore, the correction method is to randomly invert the outputs of B1 and B2 in Figure 4(a). At this time, the outputs EN3-EN0 of the code density judgment module in Figure 4(b) are set to 0110, so that the outputs S3-S0 of the MUX module in Figure 5(b) are configured to 0110. Thus, the corresponding MUX in Figure 4(a) will randomly select the Q and QN terminals of its preceding D flip-flop DFF, causing B2 and B1 in Figure 4(a) to change from a constant output of 10 to a random output of 10 or 01, ultimately controlling the equivalent threshold voltage of comparator 2 between comparator 1 and comparator 3. According to the above rules, the truth table of the code density judgment module is shown in Table 2.

[0081] Table 2

[0082] As described above regarding the working principle of the encoding circuit, when the four digital codes 0001, 0010, 0100, and 1000 corresponding to Bi (i = 0, 1, 2, 3) exhibit a code density of 0, it indicates that the threshold voltage of the corresponding comparator exceeds the threshold voltage range of the two adjacent comparators. Using the code density judgment module and random number generator in Figure 4(b), a digital correction method is employed to control the equivalent threshold voltage of each comparator between its two adjacent comparators. Furthermore, pipelined inter-stage redundancy bit technology is used to effectively correct the comparator offset, ensuring the final conversion accuracy. This correction process proceeds from the low-order comparator to the high-order comparator, sequentially correcting the offset voltage of each comparator until the equivalent threshold voltage of each comparator is within the range of the threshold voltages of the two adjacent comparators.

[0083] When the code density of 0010 in the four digital codes 0001, 0010, 0100 and 1000 corresponding to Bi (i = 0, 1, 2, 3) is 0, the correction method is as follows: First, the code density judgment module determines the cause of the 0 code density, whether it is due to a negative offset of the current comparator or a positive offset of its adjacent lower-order comparator. Second, after the judgment is completed, the output signal ENi (i = 0, 1, 2, 3) of the code density judgment module controls the positive and negative signals of the two adjacent random output D flip-flops DFF in Figure 4(a) to generate the corrected digital signal Bi (i = 0, 1, 2, 3). Finally, the second encoding circuit shown in Figure 4(c) generates a two-bit digital code. Similarly, when the code density of 0100 in the four digital codes 0001, 0010, 0100 and 1000 corresponding to Bi (i = 0, 1, 2, 3) is 0, the code density judgment circuit needs to determine whether it is caused by a positive offset of comparator 2 (as shown in Figure 5(d)). In this case, the code density output signal EN3-EN0 needs to be set to 0110, causing B2 and B1 in Figure 4(a) to randomly output high and low levels, thus controlling the equivalent threshold voltage of comparator 2 between the threshold voltages of comparator 1 and comparator 3. If the offset of comparator 3 is caused by a negative offset (as shown in Figure 5(e)), the code density output signal EN3-EN0 needs to be set to 1100, causing B3 and B2 in Figure 4(a) to randomly output high and low levels, thus controlling the equivalent threshold voltage of comparator 3 between the threshold voltages of comparator 2 and comparator 4. The correction process for the remaining codes is similar.

[0084] In summary, the encoding device proposed in this invention does not require a dedicated comparator offset voltage correction mode, enabling the ADC to correct the comparator offset voltage during normal operation, thus simplifying the circuit timing. Furthermore, this invention employs a digital domain correction method to correct the offset voltage of the flash ADC, eliminating the need for interaction between digital and analog domain signals, reducing layout complexity and the introduction of digital domain non-ideal jitter and noise, thereby improving circuit accuracy. Moreover, this invention eliminates the trimming capacitor at the comparator input in traditional structures, reducing the load on the sampling network, increasing input bandwidth, and reducing circuit area and complexity.

[0085] Figure 6 is a flowchart illustrating a pipelined ADC encoding method according to an exemplary embodiment of this application. As shown in Figure 6, a pipelined ADC encoding method includes:

[0086] Step S610: Receive the differential input signal and output multiple comparison results;

[0087] Step S620: Perform pairwise NAND operations on the multiple comparison results to output multiple NAND operation results, and under the control of the clock signal, output one or more first signals and / or one or more second signals based on the multiple NAND operation results and the high or low level of the first selection signal; the one or more first signals and / or one or more second signals constitute a first digital code;

[0088] Step S630: Generate a second selection signal based on the occurrence probability of each signal in the first digital code, and receive a third signal and a fourth signal and output a first selection signal according to the high or low level of the second selection signal, wherein the third signal is generated by a random number generator;

[0089] In step S640, under the switching control of multiple switching transistors, the second digital code is output according to the first digital code.

[0090] It should be noted that the pipelined ADC encoding method provided in the above embodiments and the pipelined ADC encoding device provided in the above embodiments belong to the same concept. The specific way in which each module and unit performs operations has been described in detail in the device embodiments, and will not be repeated here.

[0091] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A pipelined ADC encoding device, characterized in that, The encoding device includes: A comparator circuit has a differential input signal at its input terminal and outputs multiple comparison results. The first encoding circuit, connected to the comparator circuit, performs pairwise NAND operations on the multiple comparison results, outputs multiple NAND operation results, and outputs one or more first signals and / or one or more second signals based on the multiple NAND operation results and the high or low level of the first selection signal under the control of the clock signal; the one or more first signals and / or one or more second signals constitute a first digital code; The encoding control circuit is connected to the output of the first encoding circuit. It generates a second selection signal based on the occurrence probability of each signal in the first digital code, and receives a third signal and a fourth signal and outputs a first selection signal according to the high or low level of the second selection signal. The third signal is generated by a random number generator. The second encoding circuit has its input terminal connected to the output terminal of the first encoding circuit, and outputs the second digital code according to the first digital code under the switching control of multiple switching transistors.

2. The pipelined ADC encoding device according to claim 1, characterized in that, The comparator circuit includes multiple comparators arranged in parallel, and the first encoding circuit includes multiple encoding modules, each of which includes: The NAND gate has its input connected to the comparison result, which is output through two adjacent outputs of two adjacent comparators. One output outputs a positive output signal, and the other output outputs a positive and a negative output signal. A D flip-flop, whose signal input terminal is connected to the output terminal of the NAND gate, whose first output terminal outputs a first signal and whose second output terminal outputs a second signal; The first selection module has a first input terminal connected to a first signal, a second input terminal connected to a second signal, a control terminal connected to a first selection signal, and outputs the first signal or the second signal according to the high or low level of the first selection signal.

3. The pipelined ADC encoding device according to claim 2, characterized in that, When the first selection signal is high, the first selection module uses the first signal as the output signal; when the first selection signal is low, the first selection module uses the second signal as the output signal.

4. The pipelined ADC encoding device according to claim 2, characterized in that, The encoding control circuit includes: A random number generator that generates and outputs a third signal as a sequence of random numbers; Multiple second selection modules have their input terminals connected to the output terminal of the random number generator, and are connected to a third signal and a fourth signal. Their control terminals are connected to the second selection signal and output a first selection signal according to the high or low level of the second selection signal. Each of the multiple second selection modules corresponds one-to-one with a multiple first selection module. The code density determination module has its input end connected to the output end of the first selection module, receives the first digital code, and outputs a second selection signal according to the occurrence probability of each signal in the first digital code.

5. The pipelined ADC encoding device according to claim 4, characterized in that, When the second selection signal is high, the second selection module uses the third signal as the output signal; when the second selection signal is low, the second selection module uses the fourth signal as the output signal.

6. The pipelined ADC encoding apparatus according to claim 4 or 5, characterized in that, The fourth signal is 0.

7. The pipelined ADC encoding device according to claim 1, characterized in that, The second encoding circuit includes: The first encoding module has its input terminal connected to the first digital code, and outputs the fifth signal according to the first digital code under the switching control of multiple switching transistors; The second encoding module has its input terminal connected to the first digital code, and outputs a sixth signal according to the first digital code under the switching control of multiple switching transistors.

8. The pipelined ADC encoding device according to claim 7, characterized in that, The first encoding module includes: a first MOSFET to a fifth MOSFET, a first resistor, and a first NOT gate; the source of the first MOSFET is connected to a first voltage, the drain of the first MOSFET is connected to the source of the second MOSFET, the drain of the second MOSFET is connected to the drain of the third MOSFET and forms a first connection node, and the source of the third MOSFET is connected to a second voltage; the source of the fourth MOSFET is connected to the first voltage, the drain of the fourth MOSFET is connected to the source of the fifth MOSFET, the drain of the fifth MOSFET, one end of the first resistor, and the input of the first NOT gate are respectively connected to the first connection node, the other end of the first resistor is connected to the second voltage, and the output of the first NOT gate outputs a fifth signal; the gates of the first MOSFET, the third MOSFET, and the fourth MOSFET are respectively connected to an enable signal, and the gates of the second MOSFET and the fifth MOSFET are connected to a first digital code.

9. The pipelined ADC encoding device according to claim 8, characterized in that, The first encoding module includes: a sixth MOS transistor to a tenth MOS transistor, a second resistor, and a second NOT gate; the source of the sixth MOS transistor is connected to a second voltage, the drain of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and forms a second connection node, and the source of the eighth MOS transistor is connected to a second voltage; the source of the ninth MOS transistor is connected to a first voltage, the drain of the ninth MOS transistor is connected to the source of the tenth MOS transistor, the drain of the tenth MOS transistor, one end of the second resistor, and the input of the second NOT gate are respectively connected to the second connection node, the other end of the second resistor is connected to the second voltage, and the output of the second NOT gate outputs a sixth signal; the gates of the sixth MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are respectively connected to an enable signal, and the gates of the seventh MOS transistor and the tenth MOS transistor are connected to a first digital code.

10. A pipelined ADC encoding method, characterized in that, The encoding method includes: It receives differential input signals and outputs multiple comparison results; The multiple comparison results are subjected to pairwise NAND operations to output multiple NAND operation results. Under the control of the clock signal, one or more first signals and / or one or more second signals are output based on the multiple NAND operation results and the high or low level of the first selection signal. The one or more first signals and / or one or more second signals constitute a first digital code. The system generates a second selection signal based on the occurrence probability of each signal in the first digital code, and receives a third signal and a fourth signal and outputs a first selection signal according to the high or low level of the second selection signal. The third signal is generated by a random number generator. Under the switching control of multiple switching transistors, the second digital code is output according to the first digital code.

Images