Chip, preparation method, and electronic device

Abstract

The present application discloses a chip, a preparation method, and an electronic device. The chip comprises a substrate, a plurality of vertical channels, a first dielectric layer, a gate structure, and a second dielectric layer. The first dielectric layer surrounds first spacer regions of the vertical channels, the gate structure covers at least some regions of the side walls of channel regions of the vertical channels, and the second dielectric layer surrounds second spacer regions of the vertical channels. The first dielectric layer comprises a silicon dioxide layer and a protective layer which are respectively in contact with the side wall of each vertical channel, and the silicon dioxide layer is arranged between the protective layer and the substrate. The stacked structure can reduce parasitic capacitance, and can also use the protective layer to resist hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)) when hydrofluoric acid (e.g., the DHF) is used to clean a device, preventing the silicon dioxide layer from being corroded, thereby improving the performance and power consumption of the device.

Description

A chip, a fabrication method, and an electronic device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410511112.7, filed on April 26, 2024, entitled "A Chip, Preparation Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a chip, a fabrication method, and an electronic device. Background Technology

[0004] The continuous miniaturization of transistors and the increase in integration density to achieve better PPAC (power consumption, performance, area / cost) are the goals and driving forces behind the development of integrated circuit technology. As the basic unit in a chip, field-effect transistors (FETs) are currently predominantly horizontally configured, where charge carriers move horizontally from the source to the drain, such as FinFETs. With the evolution of Moore's Law, further reductions in the critical dimension (CD) of horizontally configured FETs, such as gate length and contacted gate pitch (CGP), will lead to a significant increase in parasitic capacitance and thus chip power consumption. To address this, the industry has proposed vertical transport field-effect transistors (VTFETs), where charge carriers move vertically from the source to the drain. This decouples the CGP from the gate length and the source-drain-to-gate pitch, significantly reducing parasitic capacitance and chip power consumption while also reducing reliance on advanced lithography techniques. In practical applications, the isolation layer between the source / drain and the gate is the main source of parasitic capacitance in VTFETs. Using a silicon dioxide layer with a low dielectric constant as the isolation layer can reduce the parasitic capacitance between the source / drain and the gate. However, the hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)) cleaning involved in the actual process will lead to the loss of the silicon dioxide layer, thus affecting the subsequent fabrication and performance of the device. Summary of the Invention

[0005] This application provides a chip, a fabrication method, and an electronic device that can reduce the parasitic capacitance between the gate and source of a VTFET, avoid the silicon dioxide layer being corroded by hydrofluoric acid, and improve the device's performance and power consumption.

[0006] In a first aspect, embodiments of this application provide a chip comprising: a substrate, a plurality of vertical channels, a first dielectric layer, a gate structure, and a second dielectric layer. The plurality of vertical channels are spaced apart on the substrate, and each vertical channel extends in a direction perpendicular to the plane of the substrate. Each vertical channel includes a channel region, a first spacer region disposed on the side of the channel region facing the substrate, and a second spacer region disposed on the side of the channel region facing away from the substrate. The first dielectric layer is disposed on the substrate and surrounds the first spacer region of each vertical channel. The gate structure is disposed on the side of the first dielectric layer facing away from the substrate, and the gate structure covers at least a portion of the sidewall of the channel region of each vertical channel. The second dielectric layer is disposed on the side of the gate structure facing away from the substrate and surrounds the second spacer region of each vertical channel. This configuration allows for the formation of a plurality of VTFETs in the chip. The first dielectric layer includes a stacked structure of a silicon dioxide layer and a protective layer respectively contacting the sidewall of each vertical channel, to directly cover the sidewall of the first spacer region, achieving physical isolation between the first electrode layer and the gate structure. Furthermore, the protective layer is made of a material that is not easily corroded by hydrofluoric acid (such as diluted hydrofluoric acid (DHF)), which can protect the silicon dioxide layer during the cleaning process and avoid affecting the subsequent fabrication of the device.

[0007] Carbon-containing dielectric materials not only have strong resistance to hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)) but also have a low dielectric constant. Therefore, the protective layer in the embodiments of this application can be set as a carbon-containing dielectric material to further improve the performance of the chip.

[0008] In some examples, the carbon-containing dielectric material may include, but is not limited to, one or more of silicon oxycarbonate (SiOC), silicon oxycarbonitrile (SiOCN), and silicon carbonitride (SiCN).

[0009] In some examples, the material of the protective layer can be set as silicon carbide (SiOC), so that in the process, the silicon dioxide layer can be carbon-doped by ion implantation to form a stacked silicon dioxide layer and protective layer.

[0010] In some embodiments, each vertical channel further includes a first electrode region disposed on the side of the first spacing region facing the substrate. Furthermore, the chip also includes a first electrode layer disposed between the substrate and the first dielectric layer, the first electrode layer being connected to the first electrode region of the vertical channel. This configuration allows signals to be transmitted using the first electrode layer.

[0011] In some embodiments, the chip further includes a second electrode layer disposed on the substrate-facing side of each vertical channel, the second electrode layer being connected to the vertical channel. This configuration allows signals to be transmitted using the second electrode layer.

[0012] In some embodiments, the gate structure surrounds the sidewalls of the channel regions of each of the vertical channels to form a vertical gate-all-around (VGAA) FET.

[0013] In some embodiments, the gate structure is a high-k metal gate.

[0014] In some embodiments, the vertical channel includes: a fin-shaped vertical channel or a columnar vertical channel.

[0015] Secondly, embodiments of this application also provide an electronic device, which includes a circuit board and a chip as described in the first aspect or any of the embodiments in the first aspect, wherein the chip is disposed on the circuit board. Furthermore, the technical effects of the corresponding solutions in the second aspect can be referred to the technical effects obtainable by the corresponding solutions in the first aspect, and repeated details will not be elaborated.

[0016] Thirdly, embodiments of this application also provide a method for fabricating a chip, the method comprising:

[0017] Multiple vertical channels are formed on the substrate at intervals from each other. Each vertical channel extends in a direction perpendicular to the plane of the substrate. Each vertical channel includes: a channel region, a first spacing region disposed on the side of the channel region facing the substrate, and a second spacing region disposed on the side of the channel region facing away from the substrate.

[0018] A first dielectric layer, a gate structure, and a second dielectric layer are formed on a substrate, with the first dielectric layer surrounding a first spacer region of each vertical channel, the gate structure surrounding a channel region of each vertical channel, and the second dielectric layer surrounding a second spacer region of each vertical channel; wherein the first dielectric layer includes a silicon dioxide layer and a protective layer that are in contact with the sidewalls of each vertical channel, and the silicon dioxide layer is disposed between the protective layer and the substrate.

[0019] In some embodiments, forming the first dielectric layer may include, but is not limited to, the following process: depositing an initial silicon dioxide layer on a substrate, ensuring that the surface of the initial silicon dioxide layer facing away from the substrate is not higher than the interface between the first spacer region and the channel region. Subsequently, using an ion implantation process, carbon ions are implanted onto the surface of the initial silicon dioxide layer facing away from the substrate, thereby forming a silicon dioxide layer and a protective layer in the vertical direction. Attached Figure Description

[0020] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0021] Figure 2 is a top view of a chip structure in an embodiment of this application;

[0022] Figure 3a is a schematic cross-sectional view of the structure along the AA' direction in Figure 2;

[0023] Figure 3b is a schematic cross-sectional view of the structure along the BB' direction in Figure 2;

[0024] Figures 4a to 4e are schematic diagrams of the chip in the embodiment of this application during the fabrication process.

[0025] Reference numerals in the attached figures: 100 - housing; 200 - circuit board; 300 - chip; 310 - substrate; 311 - vertical channel; 320 - first electrode layer; 330 - first dielectric layer; 331 - silicon dioxide layer; 332 - protective layer; 333 - initial silicon dioxide layer; 340 - gate structure; 341 - silicon oxide gate oxide layer; 342 - high-k gate dielectric layer; 343 - gate metal layer; 350 - second dielectric layer; 360 - second electrode layer; 370 - isolation structure; A1 - first electrode region; A2 - first spacer region; A3 - channel region; A4 - second spacer region; F1 - first direction; F2 - second direction; F3 - vertical direction. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0027] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0028] The chip provided in this application embodiment can be any electronic device or integrated circuit device used to implement one or more functions, and can be widely used in various electronic devices. Electronic devices include, but are not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc. Electronic devices include, but are not limited to, device modules, storage circuits, logic circuits, power devices, etc., and are not listed here. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario, and is not limited here.

[0029] Figure 1 is a schematic diagram of an electronic device according to an embodiment of this application. Referring to Figure 1, the electronic device includes: a housing 100, a circuit board 200 disposed within the housing 100, and a chip 300 fixed on the circuit board 200. The chip 300 and the circuit board 200 can be connected by bonding, splicing, or other methods to achieve an electrical connection between the chip 300 and the circuit board 200, thereby enabling signal transmission between them. Exemplarily, the circuit board 200 includes, but is not limited to, a printed circuit board (PCB).

[0030] Figure 2 is a top view of a chip in an embodiment of this application. Figure 3a is a cross-sectional view along the AA' direction in Figure 2, and Figure 3b is a cross-sectional view along the BB' direction in Figure 2. Referring to Figures 2 to 3b, the chip provided in this embodiment may include a substrate 310. Exemplarily, the material of the substrate 310 includes, but is not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), III-V compound semiconductors, or II-VI compound semiconductors. In some examples, the substrate 310 may be composed entirely of silicon.

[0031] Multiple vertical channels 311 are spaced apart on a substrate 310, thereby forming multiple VTFETs. Each vertical channel 311 extends along a vertical direction F3 perpendicular to the plane of the substrate 310, forming a vertical channel 311 extending perpendicular to the plane of the substrate 310. Each vertical channel 311 includes a channel region A3, a first spacer region A2 disposed on the side of the channel region A3 facing the substrate 310, a first electrode region A1 disposed on the side of the first spacer region A2 facing the substrate 310, and a second spacer region A4 disposed on the side of the channel region A3 facing away from the substrate 310. That is, the first electrode region A1, the first spacer region A2, the channel region A3, and the second spacer region A4 are arranged sequentially along the vertical direction F3. Furthermore, the multiple vertical channels 311 can be arranged along the first direction F1 and the second direction F2, respectively, parallel to the plane of the substrate 310. In specific implementation, the vertical channel 311 can be configured as a fin-shaped vertical channel 311. For example, each vertical channel 311 can also extend along the first direction F1. Alternatively, the vertical channel 311 can also be configured as a cylindrical (e.g., cylindrical, elliptical, etc.) vertical channel 311.

[0032] A first electrode layer 320 is also disposed on the substrate 310, and the first electrode layer 320 is connected to the first electrode region A1 of the vertical channel 311, thereby transmitting signals to the first electrode region A1 of each vertical channel 311 through the first electrode layer 320. Exemplarily, the first electrode layer 320 is disposed around the first electrode region A1 of the vertical channel 311. Furthermore, the material of the first electrode layer 320 can be heavily doped silicon, heavily doped germanium silicon, a metal material, a metal silicide material, etc. It is understood that an isolation structure 370 (e.g., a shallow trench isolation (STI) structure) can be disposed in the substrate 310 between vertical channels 311 with different functions, and the STI structure also extends to the surface of the first electrode layer 320 on the side facing away from the substrate 310, isolating the first electrode layers 320 connecting the vertical channels 311 with different functions from each other.

[0033] A first dielectric layer 330 is disposed on the side of the first electrode layer 320 facing away from the substrate 310, and the first dielectric layer 330 surrounds the first spacing region A2 of each vertical channel 311. The first dielectric layer 330 includes a silicon dioxide layer 331 and a protective layer 332 that are in contact with the sidewalls of each vertical channel 311, respectively. The silicon dioxide layer 331 and the protective layer 332 can be in direct contact with the sidewalls of the first spacing region A2 of each vertical channel 311, so as to directly cover the sidewalls of the first spacing region A2 through the silicon dioxide layer 331 and the protective layer 332, thereby achieving isolation between the first electrode layer 320 and the gate structure. Furthermore, the silicon dioxide layer 331 is disposed between the protective layer 332 and the substrate 310, which can not only reduce the parasitic capacitance between the first electrode layer and the gate structure, but also protect the silicon dioxide layer 331 when the device is cleaned with hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)). Since the silicon dioxide layer 331 is provided with a material protective layer 332 that is not easily corroded by hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)), the protective layer can protect the silicon dioxide layer 331.

[0034] Carbon-containing dielectric materials have stronger resistance to hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)) compared to existing dielectric materials. The protective layer material in the embodiments of this application can be set as a carbon-containing dielectric material to further improve the performance of the chip.

[0035] This application does not specifically limit the carbon-containing dielectric material. For example, the carbon-containing dielectric material may include, but is not limited to, one or more of silicon oxycarbonate (SiOC), silicon oxycarbonitrile (SiOCN), and silicon carbonitride (SiCN). Exemplarily, the protective layer can be made of silicon oxycarbonate (SiOC), thereby depositing a silicon dioxide layer and performing carbon ion doping on the silicon dioxide layer during the process to form a stacked silicon dioxide layer and protective layer, reducing process steps and costs.

[0036] A gate structure 340 is disposed on the side of the first dielectric layer 330 facing away from the substrate 310. The gate structure 340 covers a portion of the sidewall of the channel region A3 of each vertical channel 311, or it covers the entire sidewall of the channel region A3 of each vertical channel 311. Thus, the gate structure 340 surrounds the channel region A3 of each vertical channel 311, thereby forming multiple vertical gate-all-around (VGAA) FETs. Exemplarily, the gate structure 340 can be a high-k metal gate (HKMG). For example, the high-k metal gate includes a silicon oxide gate oxide layer 341, a high-k gate dielectric layer 342, and a gate metal layer 343. Of course, one or more of a work function layer and a pad layer can also be disposed between the high-k gate dielectric layer 342 and the gate metal layer 343. Furthermore, for the gate structures 340 surrounding the vertical channels 311 with different functions, these gate structures 340 are spaced apart.

[0037] A second dielectric layer 350 is disposed on the side of the gate structure 340 facing away from the substrate 310, and the second dielectric layer 350 surrounds the second spacing region A4 of each vertical channel 311. Exemplarily, the second dielectric layer 350 can be a single-layer structure or a multi-layer structure, and the material of the second dielectric layer 350 includes, but is not limited to, one or more of the following: silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiOCN), and silicon carbonitride (SiCN).

[0038] A second electrode layer 360 is provided on the side of the multiple vertical channels 311 facing away from the substrate 310. The second electrode layer 360 is connected to the vertical channels 311, thereby transmitting signals to each vertical channel 311 through the second electrode layer 360, and is isolated from the gate structure 340 by a second dielectric layer 350. Exemplarily, the second electrode layer 360 is connected to the surface of the vertical channel 311 facing away from the substrate 310. Furthermore, the material of the second electrode layer 360 can be heavily doped silicon, heavily doped germanium silicon, a metal material, a metal silicide material, etc. Moreover, the second electrode layers 360 connected to the vertical channels 311 with different functions are also isolated from each other.

[0039] In this embodiment, the first dielectric layer 330 and the second dielectric layer 350 can also be configured with different structures to decouple the morphology of the first dielectric layer 330 and the second dielectric layer 350. Of course, the first dielectric layer 330 and the second dielectric layer 350 can also be configured with the same structure, and no specific limitation is made here.

[0040] It is worth mentioning that the first electrode layer is the source of the VTFET, and the second electrode layer is the drain of the VTFET. Alternatively, the first electrode layer is the drain of the VTFET, and the second electrode layer is the source of the VTFET.

[0041] It is understandable that Figure 2 only shows the protective layer 332 and the vertical channel 311, and the other structures or membranes are not shown. The other structures or membranes can be referred to Figures 3a and 3b.

[0042] Taking the structure of the chip shown in Figure 3a as an example, the chip fabrication method provided in this application embodiment may include the following:

[0043] (1) Referring to FIG4a, FIG4a is a schematic diagram of a chip in the present application embodiment during the fabrication process. Exemplarily, a substrate 310 is provided, for example, the substrate 310 is a silicon substrate 310, a silicon-on-insulator (SOI) substrate 310, etc., wherein the SOI substrate 310 may have a lower silicon layer, a buried insulating layer and an upper silicon layer stacked together. During the fabrication process, a vertical channel 311 can be formed by etching the upper silicon layer of the SOI substrate 310 or by etching the silicon substrate 310. The first electrode region A1, the first spacer region A2 and the second spacer region A4 of the vertical channel 311 can be heavily doped. Then, a first electrode layer 320 is deposited on the substrate 310 using a metal material, and the first electrode layer 320 surrounds the first electrode region A1.

[0044] (2) Referring to Figure 4b, which is another structural schematic diagram of the chip in the embodiment of this application during the fabrication process. Exemplarily, silicon dioxide (SiO2) is used, and an initial silicon dioxide layer 333 is deposited on the side of the first electrode layer 320 facing away from the substrate 310 using a suitable process such as a High Aspect Ratio Process (HARP). Then, a chemical mechanical polishing (CMP) process is used to planarize the initial silicon dioxide layer 333, exposing the vertical channel 311. Then, an etching process is used to etch the initial silicon dioxide layer 333 so that the surface of the initial silicon dioxide layer 333 facing away from the substrate 310 is aligned with the interface between the first spacer region A2 and the channel region A3, or so that the surface of the initial silicon dioxide layer 333 facing away from the substrate 310 is not higher than the interface between the first spacer region A2 and the channel region A3. Subsequently, carbon ions (e.g., low-energy carbon ions) are implanted into the surface of the initial silicon dioxide layer 333 on the side facing away from the substrate 310 using an ion implantation (IMP) process. The carbon ion-implanted initial silicon dioxide layer 333 is then densified using a process such as Rapid Thermal Processing (RTP), resulting in a stacked structure of doped and undoped layers in the vertical direction F3 of the initial silicon dioxide layer 333. The doped layer is then the protective layer 332, and the undoped layer is the silicon dioxide layer 331. Afterward, hydrofluoric acid (e.g., diluted hydrofluoric acid (DHF)) cleaning can be performed.

[0045] The deposited first electrode layer 320 is typically an epitaxial, heavily doped silicon layer, resulting in a significant surface morphology variation. In this embodiment, before forming the protective layer, an initial silicon dioxide layer 333 is filled onto the first electrode layer 320, followed by the application of, for example, Certas... TM The initial silicon dioxide layer 333 is isotropically etched using equipment to define its thickness and morphology. This method decouples the morphology of the initial silicon dioxide layer 333 from that of the first electrode layer 320, improving the surface smoothness and uniformity of the initial silicon dioxide layer 333, thereby enhancing the performance of the VTFET and ultimately improving the overall chip performance.

[0046] It is understandable that due to limitations in process conditions or other factors, some deviations or errors may exist in the actual process, which may cause the "alignment" described above to be not completely accurate. For example, the "alignment" described above may be an alignment that is allowed within the allowable error range. Of course, "alignment" can also be understood as "basic alignment" or "complete alignment". Therefore, as long as the "alignment" relationship described above roughly meets the above conditions, it falls within the protection scope of this application.

[0047] (3) Referring to FIG4c, FIG4c is another structural schematic diagram of the chip in the present application embodiment during the fabrication process. Exemplarily, a silicon oxide gate oxide layer 341 is deposited, and the silicon oxide gate oxide layer 341 covers the entire surface of the sidewall of the channel region A3. Then, a high-k gate dielectric layer 342 is deposited, and the high-k gate dielectric layer 342 covers the areas of the silicon oxide gate oxide layer 341 and the first dielectric material layer 332 that are not covered by the silicon oxide gate oxide layer 341. Then, a gate metal layer 343 is deposited.

[0048] (4) Referring to FIG4d, FIG4d is another structural schematic diagram of the chip in the embodiment of this application during the fabrication process. Exemplarily, a second dielectric layer 350 is deposited using silicon dioxide (SiO2), and then the second dielectric layer 350 is planarized using a CMP process to expose vertical channels 311, so that the second dielectric layer 350 surrounds the second spacing region A4 of each vertical channel 311.

[0049] (5) Referring to FIG4e, FIG4e is another structural schematic diagram of the chip in the present application embodiment during the fabrication process. Exemplarily, heavy doped silicon is used for epitaxial deposition of a second electrode layer 360 on the side of a plurality of vertical channels 311 facing away from the substrate 310, and the second electrode layer 360 is connected to the vertical channels 311, and the second electrode layers 360 connected to the vertical channels 311 with different functions are also isolated from each other.

[0050] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A chip, characterized in that, include: Substrate; Multiple vertical channels are disposed at intervals on the substrate. Each vertical channel extends in a vertical direction perpendicular to the plane of the substrate. Each vertical channel includes: a channel region, a first spacing region disposed on the side of the channel region facing the substrate, and a second spacing region disposed on the side of the channel region facing away from the substrate. A first dielectric layer is disposed on the substrate. The first dielectric layer surrounds a first spacing region of each of the vertical channels. The first dielectric layer includes a silicon dioxide layer and a protective layer that are respectively in contact with the sidewalls of each of the vertical channels. The silicon dioxide layer is disposed between the protective layer and the substrate. A gate structure is disposed on the side of the first dielectric layer facing away from the substrate, and the gate structure covers at least a portion of the sidewall of the channel region of each of the vertical channels; A second dielectric layer is disposed on the side of the gate structure facing away from the substrate, and the second dielectric layer surrounds the second spacing region of each of the vertical channels.

2. The chip as described in claim 1, characterized in that, The protective layer is made of carbon-containing dielectric materials.

3. The chip as described in claim 2, characterized in that, The carbon-containing dielectric material includes one or more of silicon oxycarbonate, silicon oxycarbonitrile, and silicon carbonitride.

4. The chip according to any one of claims 1-3, characterized in that, Each of the vertical channels further includes: a first electrode region disposed in the first spacing region on the side facing the substrate; The chip further includes a first electrode layer disposed between the substrate and the first dielectric layer, the first electrode layer being connected to the first electrode region of the vertical channel.

5. The chip according to any one of claims 1-4, characterized in that, The chip also includes a second electrode layer disposed on the side of a plurality of vertical channels facing away from the substrate, the second electrode layer being connected to the vertical channels.

6. The chip according to any one of claims 1-5, characterized in that, The gate structure surrounds the sidewalls of the channel region of each of the vertical channels; and / or, the gate structure is a high-k metal gate.

7. The chip according to any one of claims 1-6, characterized in that, The vertical channels include: fin-shaped vertical channels or columnar vertical channels.

8. An electronic device, characterized in that, include: The circuit board and the chip as described in any one of claims 1-7, wherein the chip is disposed on the circuit board.

9. A method for fabricating a chip, characterized in that, include: A plurality of vertical channels are formed on a substrate at intervals from each other. Each vertical channel extends in a vertical direction perpendicular to the plane of the substrate. Each vertical channel includes: a channel region, a first spacing region disposed on the side of the channel region facing the substrate, and a second spacing region disposed on the side of the channel region facing away from the substrate. A first dielectric layer, a gate structure, and a second dielectric layer are formed on the substrate, with the first dielectric layer surrounding a first spacer region of each vertical channel, the gate structure surrounding a channel region of each vertical channel, and the second dielectric layer surrounding a second spacer region of each vertical channel; wherein the first dielectric layer includes a silicon dioxide layer and a protective layer that are in contact with the sidewalls of each vertical channel, and the silicon dioxide layer is disposed between the protective layer and the substrate.

10. The preparation method according to claim 9, characterized in that, The formation of the first dielectric layer includes: An initial silicon dioxide layer is deposited on the substrate, and the surface of the initial silicon dioxide layer facing away from the substrate is not higher than the interface between the first spacer region and the channel region. Using an ion implantation process, carbon ions are implanted into the surface of the initial silicon dioxide layer on the side facing away from the substrate, so that the initial silicon dioxide layer forms the silicon dioxide layer and the protective layer in the vertical direction.

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