Semiconductor packaging structure and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a semiconductor packaging structure and an electronic device, for use in reducing area costs of semiconductor structures. The semiconductor packaging structure comprises a packaging substrate, a logic chip, and a plurality of functional chips. Each functional chip comprises a plurality of first external connection portions, and the plurality of first external connection portions are exposed on the surface of the functional chip facing away from the logic chip. The logic chip comprises a plurality of second external connection portions, a signal acceleration module and a plurality of third external connection portions, the second external connection portions are connected to the first external connection portions, the signal acceleration module is connected between at least some of the second external connection portions and at least some of the third external connection portions, the signal acceleration module is used for accelerating signals transmitted by the second external connection portions and outputting the signals to the third external connection portions, and the number of the third external connection portions is less than that of the second external connection portions. The packaging substrate further comprises a plurality of fourth external connection portions, and the fourth external connection portions are connected to the third external connection portions. The semiconductor packaging structure is used for an electronic device.

Description

Semiconductor packaging structure and electronic devices

[0001] This application claims priority to Chinese patent application filed on April 26, 2024, with application number 202410520555.2 and entitled "Semiconductor Packaging Structure and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and electronic device. Background Technology

[0003] As semiconductor technology evolves, the bandwidth of semiconductor packaging structures gradually increases. However, to further increase the bandwidth of semiconductor packaging structures, it is necessary to increase the number of output ports of semiconductor packaging structures, which leads to higher area costs for semiconductor packaging structures. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor packaging structure and electronic device for reducing the area cost of semiconductor structures.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0006] On one hand, a semiconductor packaging structure is provided. This semiconductor packaging structure includes: a packaging substrate, a logic chip, and multiple functional chips. The packaging substrate includes a first surface, the logic chip is disposed on the first surface, and the multiple functional chips are disposed on a side of the logic chip facing away from the packaging substrate. Each functional chip includes multiple first external connections, which are exposed on the surface of the functional chip facing away from the logic chip. The logic chip includes multiple second external connections, a signal acceleration module, and multiple third external connections. The second external connections are connected to the first external connections, and the signal acceleration module is connected between at least a portion of the second external connections and at least a portion of the third external connections. The signal acceleration module is used to accelerate the signal transmitted by the second external connections and output it to the third external connections, wherein the number of third external connections is less than the number of second external connections. The packaging substrate also includes multiple fourth external connections, which are exposed on the first surface and connected to the third external connections.

[0007] In this system, the signal output by the functional chip through the first external connection can be transmitted to the second external connection. A portion of the signal received by the second external connection can be transmitted to the signal acceleration module, which accelerates the received signal and outputs it to a portion of the third external connection. After acceleration by the signal acceleration module, not only is the signal bandwidth increased, but the number of third external connections is also reduced, resulting in a number of third external connections less than that of second external connections. Furthermore, the fourth external connection is connected to the third external connection; therefore, the number of fourth external connections can also be reduced, thereby reducing the area occupied by the fourth connection, reducing the area of ​​the packaging substrate, lowering the area cost of the semiconductor structure, facilitating the miniaturization of the semiconductor packaging structure, and increasing the bandwidth of the semiconductor packaging structure per unit area.

[0008] In some embodiments, the plurality of first external connections include a plurality of first-type first external connections and a plurality of second-type first external connections, wherein the first-type first external connections are used to transmit data signals, and the plurality of second-type first external connections are used to transmit power signals. The plurality of second external connections include a plurality of first-type second external connections and a plurality of second-type second external connections, with the first-type second external connections connected to the first-type first external connections and the second-type second external connections connected to the second-type first external connections. The plurality of third external connections include a plurality of first-type third external connections and a plurality of second-type third external connections, with the signal acceleration module connected between the plurality of first-type second external connections and the plurality of first-type third external connections, and the second-type third external connections connected to the second-type second external connections. The plurality of fourth external connections include a plurality of first-type fourth external connections and a plurality of second-type fourth external connections, with the first-type fourth external connections connected to the first-type third external connections and the second-type fourth external connections connected to the second-type third external connections.

[0009] The signal acceleration module can accelerate the signal received from the first type of second external connection and then transmit it to the first type of third external connection. The number of the first type of third external connection is less than the number of the first type of second external connection, and the first type of fourth external connection can be connected to the first type of third external connection. Therefore, the number of the first type of fourth external connection is less than the number of the first type of second external connection, thereby reducing the number of the first type of fourth external connection on the packaging substrate, which in turn reduces the area occupied by the first type of fourth external connection and the area of ​​the packaging substrate. This is beneficial for the miniaturization of the semiconductor packaging structure and can improve the bandwidth of the semiconductor packaging structure per unit area.

[0010] In some embodiments, in at least a portion of the second type third external connections, one second type third external connection is connected to at least two second type second external connections; wherein, in the interconnected second type third external connections and second type second external connections, the number of second type third external connections is less than or equal to the number of second type second external connections.

[0011] With this configuration, the power signals transmitted by the at least two second type second external connections can be transmitted to a second type third external connection. Furthermore, multiple second type second external connections used to transmit power signals of the same voltage can be merged. At this time, the number of second type third external connections is less than the number of second type second external connections, thereby reducing the number of second type third external connections. The second type third external connections can also be connected to second type fourth external connections, so the number of second type fourth external connections can be reduced accordingly. This reduces the number of external connections on the packaging substrate, thereby reducing the area cost of the packaging substrate.

[0012] In some embodiments, a plurality of second external connections and a plurality of third external connections are exposed on the surface of the logic chip away from the package substrate. The semiconductor package structure also includes a plurality of first interconnects and a plurality of second interconnects, one end of the first interconnects being connected to a first external connection and the other end being connected to a second external connection, and one end of the second interconnects being connected to a third external connection and the other end being connected to a fourth external connection.

[0013] The data signals of the functional chip can be transmitted to the second external connection via the first external connection and the first connecting line. The second external connection is exposed on the surface of the logic chip facing away from the packaging substrate, thus facilitating its connection to the first external connection via the first connecting line. Furthermore, by exposing multiple third external connections on the surface of the logic chip facing away from the packaging substrate, the third external connections can be easily connected to the fourth external connection via the second connecting line.

[0014] In some embodiments, a plurality of second external connections are arranged in multiple rows and columns. A plurality of first-type third external connections and a plurality of second-type third external connections are respectively disposed on both sides of the plurality of second external connections in the column direction.

[0015] This configuration allows you to determine the type of connection based on its location. For example, second-type external connections are arranged in a row. First-type third-type external connections can be arranged in a row, and second-type third-type external connections can be arranged in a row. In this case, the external connections in the first row are second-type third-type external connections, the external connections in the second, third, fourth, and fifth rows are second-type external connections, and the external connections in the sixth row are first-type third-type external connections.

[0016] In some embodiments, a mounting position is provided between the designated third external connection and the plurality of second external connections. The semiconductor package structure further includes: a first support portion, which is disposed between the logic chip and the plurality of functional chips, and the first support portion is located on the mounting position between the designated third external connection and the plurality of second external connections, wherein the designated third external connection is a first type of third external connection or a second type of third external connection.

[0017] By providing a first support portion, space can be formed between the logic chip and multiple functional chips. Therefore, the second and third external connections on the logic chip can be left uncovered by the functional chips, thus facilitating the connection between the second and first external connections, and between the third and fourth external connections.

[0018] In some embodiments, the projection of multiple functional chips in a direction perpendicular to the packaging substrate covers multiple first-type third external connections, wherein the first-type third external connections are designated third external connections.

[0019] With this configuration, the mounting position is located between the first type of third external connection part and multiple second external connection parts, and the first support part is located between multiple second external connection parts and multiple first type of third external connection parts, thereby creating a space between the first type of third external connection part and the functional chip, which facilitates the connection between the first type of third external connection part and the first type of fourth connection part.

[0020] In some embodiments, the projection of multiple functional chips in a direction perpendicular to the packaging substrate covers multiple second-type third external connections, wherein the second-type third external connections are designated third external connections.

[0021] With this configuration, the mounting position is located between the second type third external connection part and multiple second external connection parts, and the first support part is located between the multiple second external connection parts and multiple second type third external connection parts, thereby creating a space between the second type third external connection part and the functional chip, which facilitates the connection between the second type third external connection part and the second type fourth connection part.

[0022] In some embodiments, the semiconductor packaging structure further includes a second support portion, one end of which is connected to the packaging substrate and the other end of which is connected to the functional chip closest to the packaging substrate among a plurality of functional chips. The thickness of the second support portion in the direction perpendicular to the packaging substrate is greater than the thickness of the logic chip in the direction perpendicular to the packaging substrate.

[0023] With this configuration, the second support can support multiple functional chips, and space can be formed between the multiple functional chips and the logic chip. At this time, the second and third external connections of the logic chip are not directly covered by the functional chips, which makes it easy for the second external connection to be connected to the first external connection and the third external connection to be connected to the fourth external connection.

[0024] In some embodiments, the orthographic projection of multiple functional chips on the packaging substrate covers a portion of the fourth external connection portion, and the portion of the fourth external connection portion is located within the space enclosed by the first support portion, the logic chip, the functional chip and the packaging substrate.

[0025] For example, the portion of the fourth external connection covered by the orthographic projection of multiple functional chips onto the packaging substrate can be a first-type fourth connection. In this case, the projections of the multiple functional chips in the direction perpendicular to the packaging substrate cover multiple first-type third external connections. This arrangement allows for a smaller distance between the first-type fourth connection and the first-type third external connections, facilitating their connection. Alternatively, the portion of the fourth external connection covered by the orthographic projection of multiple functional chips onto the packaging substrate can be a second-type fourth connection. In this case, the projections of the multiple functional chips in the direction perpendicular to the packaging substrate cover multiple second-type third external connections. This arrangement allows for a smaller distance between the second-type fourth connection and the second-type third external connections, facilitating their connection.

[0026] In some embodiments, the surface of the functional chip facing away from the packaging substrate includes multiple edges, and multiple first external connections are arranged along a portion of the edges of the functional chip. The multiple functional chips include at least one stacked functional chip group; the stacked functional chip group includes multiple stacked functional chips, and in two adjacent functional chips in the stacking direction, the functional chip farther from the packaging substrate avoids the first external connection of the functional chip closer to the packaging substrate. The number of logic chips is multiple, and the multiple logic chips are respectively disposed along the edges of the stacked functional chip group near the first external connections.

[0027] In this design, the upper functional chip can avoid the first external connection of the lower functional chip, allowing the first external connection of the functional chip to be exposed. Therefore, the first external connection can connect to the second external connection. The upper functional chip refers to the one farther from the packaging substrate among two adjacent functional chips, while the lower functional chip refers to the one closer to the packaging substrate among two adjacent functional chips. The logic chip can be positioned along the edge of the stacked functional chip group near the first external connection, thus minimizing the distance between the second external connection on the logic chip and the first external connection on the functional chip, facilitating connection between the second and first external connections.

[0028] In some embodiments, the functional chip includes a first edge among its plurality of edges, and a plurality of first external connections of the functional chip are disposed along the first edge. The first edges of two adjacent functional chips in the stacking direction are disposed opposite each other in a first direction, wherein the first direction is parallel to the packaging substrate. The plurality of logic chips includes a first logic chip and a second logic chip, which are spaced apart along the first direction. A stacked functional chip group is located on the side of the first logic chip and the second logic chip facing away from the packaging substrate, wherein the second external connections of the first logic chip and the second external connections of the second logic chip are respectively located on both sides of the stacked functional chip group in the first direction.

[0029] In this case, the projection of the stacked functional chipset in the stacking direction does not cover the second external connection of the first logic chip and the second external connection of the second logic chip, thereby facilitating the connection of the second external connection to the first external connection.

[0030] In some embodiments, the functional chip further includes a plurality of fifth external connections exposed on the surface of the functional chip opposite to the package substrate. The package substrate further includes a plurality of sixth external connections exposed on the first surface. The semiconductor package structure further includes a plurality of third interconnects, one end of which is connected to a fifth external connection and the other end of which is connected to a sixth external connection.

[0031] Some signals from the functional chip can be directly transmitted to the sixth external connection of the packaging substrate via the fifth external connection and the third connection line. The fifth external connection can be used to transmit power signals. In this case, the power signal received by the sixth external connection can be transmitted to the fifth external connection via the third connection line, thereby supplying power to the functional chip.

[0032] In some embodiments, the surface of the functional chip away from the logic chip includes multiple edges, including adjacent first and second edges. Multiple first external connections are disposed along the first edges, and multiple fifth external connections are disposed along the second edges. The second edges of two adjacent functional chips in the stacking direction are disposed opposite each other in a third direction, wherein the third direction is parallel to the packaging substrate and intersects with the second edges. The orthographic projections of the multiple functional chips on the first surface are offset from the multiple sixth external connections. The multiple sixth external connections are sequentially disposed along the orthographic projections of the second edges of the functional chips on the first surface, and the multiple sixth external connections are divided into two groups, with the two groups of sixth external connections located on opposite sides of the multiple functional chips in the third direction.

[0033] With this configuration, the orthographic projection of the fifth external connection of some functional chips onto the packaging substrate can be positioned adjacent to a group of sixth external connections, thereby facilitating their connection. Similarly, the orthographic projection of the fifth external connection of another set of functional chips onto the packaging substrate can be positioned adjacent to another group of sixth external connections, further facilitating their connection.

[0034] In some embodiments, the packaging substrate further includes a substrate body, multiple first traces, multiple first connection portions, and multiple eighth external connections. The multiple fourth external connections and the multiple first traces are disposed on the surface of the substrate body facing the logic chip, the multiple first connection portions are disposed within the substrate body, and the eighth external connections are disposed on the surface of the packaging substrate away from the logic chip. Each fourth external connection is connected to one end of a first connection portion via a first trace, and the other end of the first connection portion is connected to the eighth external connection portion.

[0035] The first connecting portion can penetrate the substrate body. One end of the first connecting portion is connected to the end of the first trace away from the fourth external connecting portion, and the other end of the first connecting portion is connected to the eighth external connecting portion. Therefore, the signal output from the third external connecting portion can be transmitted to the eighth external connecting portion through the fourth external connecting portion, the first trace, and the first connecting portion. The eighth external connecting portion can be electrically connected to other electronic devices. For example, the other electronic device can be a processor; or, for example, the other electronic device can be a circuit board, on which the processor and other electronic devices can be mounted. Thus, the semiconductor package structure can be electrically connected to the processor through the circuit board.

[0036] In some embodiments, the packaging substrate further includes a substrate body, a plurality of seventh external connections, a plurality of third traces, a plurality of first connections, and a plurality of eighth external connections. The plurality of seventh external connections and the plurality of third traces are exposed on the surface of the substrate body facing the logic chip, and the plurality of eighth external connections are exposed on the surface of the substrate body away from the logic chip. The first connections are disposed within the substrate body. The plurality of second and third external connections are exposed on the surface of the logic chip facing the substrate body. The semiconductor packaging structure further includes a fourth connection line, one end of which is connected to the first external connection line and the other end of which is connected to the seventh external connection line. One end of the third trace is connected to the seventh external connection line and the other end of which is connected to the second external connection line. The third external connection line is connected to one end of the first connection line, and the other end of the first connection line is connected to the eighth external connection line. The first connection line serves as the fourth external connection line, and one end of the first connection line is exposed on the surface of the substrate body facing the logic chip.

[0037] The first connecting portion can penetrate the substrate body. One end of the first connecting portion is connected to the end of the first trace away from the fourth external connecting portion, and the other end of the first connecting portion is connected to the eighth external connecting portion. Therefore, the signal output from the third external connecting portion can be transmitted to the eighth external connecting portion through the fourth external connecting portion, the first trace, and the first connecting portion. The eighth external connecting portion can be electrically connected to other electronic devices. For example, the other electronic device can be a processor; or, for example, the other electronic device can be a circuit board, on which the processor and other electronic devices can be mounted. Thus, the semiconductor package structure can be electrically connected to the processor through the circuit board.

[0038] On the other hand, an electronic device is provided, comprising: a semiconductor package structure and a processor. The semiconductor package structure includes: a package substrate, a logic chip, and a plurality of functional chips. The package substrate includes a first surface, the logic chip is disposed on the first surface, and the plurality of functional chips are disposed on a side of the logic chip facing away from the package substrate. Each functional chip includes a plurality of first external connections, which are exposed on the surface of the functional chip facing away from the logic chip. The logic chip includes a plurality of second external connections, a signal acceleration module, and a plurality of third external connections. The second external connections are connected to the first external connections, and the signal acceleration module is connected between a portion of the second external connections and a portion of the third external connections. The signal acceleration module is used to accelerate the signal transmitted by the second external connections and output it to the third external connections, wherein the number of third external connections is less than the number of second external connections. The package substrate also includes a plurality of fourth external connections, which are exposed on the first surface and connected to the third external connections. The processor is electrically connected to the fourth external connections of the package substrate.

[0039] The electronic device provided in this application includes all the structures of the semiconductor packaging structures provided in the above embodiments, and therefore has all the beneficial effects of the semiconductor packaging structures provided in the above embodiments, which will not be elaborated here. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0041] Figure 1 is a schematic diagram of the semiconductor packaging structure provided in an embodiment of this application;

[0042] Figure 2 is a top view of the semiconductor packaging structure in Figure 1;

[0043] Figure 3 is a magnified view of part A in Figure 2;

[0044] Figure 4 is another schematic diagram of the semiconductor packaging structure provided in the embodiment of this application;

[0045] Figure 5 is a magnified view of part B in Figure 4;

[0046] Figure 6 is a top view of the semiconductor package structure shown in Figure 4;

[0047] Figure 7 is another top view of the semiconductor packaging structure provided in the embodiment of this application;

[0048] Figure 8 is another top view of the semiconductor packaging structure provided in the embodiment of this application;

[0049] Figure 9 is another schematic diagram of the semiconductor packaging structure provided in the embodiment of this application;

[0050] Figure 10 is a magnified view of a portion of point C in Figure 9;

[0051] Figure 11 is a structural diagram of the electronic device provided in an embodiment of this application;

[0052] Figure 12 is another structural diagram of the electronic device provided in an embodiment of this application;

[0053] Figure 13 is another structural diagram of the electronic device provided in the embodiment of this application. Detailed Implementation

[0054] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0055] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0056] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0057] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0058] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0059] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0061] Figure 1 is a schematic diagram of the semiconductor packaging structure provided in the embodiment of this application, Figure 2 is a top view of the semiconductor packaging structure in Figure 1, and Figure 3 is a partial enlarged view of point A in Figure 2.

[0062] Referring to Figures 1 and 2, the semiconductor package structure 1000 may include a package plate 110, multiple chips 120, multiple wires 130, and a package layer 140. The multiple chips 120 are stacked and disposed on the package plate 110.

[0063] The chip 120 includes a plurality of first pins 121, wherein the first pins 121 are exposed on the surface of the chip 120 away from the package plate 110.

[0064] Please refer to Figures 1 to 3. The package board 110 includes multiple second pins 111, multiple first conductive lines 115, multiple conductive parts 113, and multiple connectors 114.

[0065] Multiple second pins 111 and multiple first conductive lines 115 are exposed on the surface of the package plate 110 facing the chip 120. A conductive portion 113 is disposed within the package plate 110. A connector 114 is disposed on the surface of the package plate 110 facing away from the chip 120. One end of the conductive portion 113 is connected to the first conductive line 115, and the other end of the conductive portion 113 is connected to the connector 114.

[0066] The second pin 111 can be located around the chip 120. For example, as shown in Figure 2, the second pin 111 can be arranged in multiple rows.

[0067] One end of wire 130 is connected to the first pin 121 of chip 120, and the other end of wire 130 is connected to the second pin 111.

[0068] One end of the first conductive wire 115 is connected to the second pin 111, and the other end is connected to one end of the conductive part 113. The other end of the conductive part 113 is connected to the connector 114.

[0069] The connector 114 can serve as an output port of the semiconductor package structure 1000. The connector 114 can be connected to other electronic devices, for example, a processor, or a circuit board.

[0070] The signal from chip 120 can be transmitted to connector 114 via first pin 121, wire 130, first conductive line 115, and conductive part 113, and then transmitted to other electronic devices via connector 114.

[0071] The encapsulation layer 140 covers the surface of the encapsulation board 110 facing the multiple chips 120 and also covers the outer surface of the multiple chips 120. The encapsulation layer 140 seals the multiple chips 120, thereby reducing the impact of external environmental factors (moisture, temperature, air pressure, pressure, etc.) on the integrated multiple chips 120, thus protecting them. In addition, the encapsulation layer 140 also serves to fix the conductive wires 130.

[0072] For example, as shown in Figure 2, multiple first pins 121 can be arranged along one edge of the chip 120. In two adjacent chips 120 in the stacking direction G, the chip 120 farther from the package board 110 can expose the pins 121 on the chip 120 closer to the package board 110. As shown in Figure 2, in the top view, the first pins 121 on the two chips 120 farthest from the package board 110 can be illustrated.

[0073] For example, chip 120 can be a memory chip. For instance, the memory chip can be dynamic random access memory (DRAM).

[0074] When the wire 130 is connected to the second pin 111, stress will be generated around the second pin 111, which is not conducive to the second pin 111 being directly connected to the connector 114 through the conductive part in the package plate 110.

[0075] In this embodiment, the second pin 111 can be connected to the conductive part 113 inside the package plate 110 via the first conductive line 115 on the package plate 110, and connected to the connector 114 via the conductive part 113. The conductive part 113 can avoid the stress around the second pin 111, thus improving the quality of the conductive part 113 and thereby improving the connection effect between the second pin 111 and the connector 114, thereby ensuring the signal transmission effect.

[0076] The bandwidth of the semiconductor package structure 1000 is related to the number of first pins 121. To increase the bandwidth of the semiconductor package structure 1000, the number of first pins 121 needs to be increased, which in turn requires increasing the number of second pins 111, conductive parts 113, and connectors 114.

[0077] For example, when the second pins 111 are arranged in two rows and the conductive parts 113 are connected to one end of the first conductive line 115 in two rows, as the number of the first pins 121 increases, the number of the first conductive lines 115 also needs to increase. This is because the first conductive lines 115 connected to the second pins 111 in the first row will pass between two adjacent second pins 111 in the second row. In addition, the first conductive lines 115 connected to the conductive parts 113 in the second row will pass between two adjacent conductive parts 113 in the first row.

[0078] With an increase in the number of second pins 111 and conductive portions 113, since the dimensions of the semiconductor package structure 1000 in the row direction are fixed, there is an upper limit to the number of second pins 111 and conductive portions 113 that can be arranged in a single row. Therefore, it is necessary to increase the number of rows of second pins 111 and conductive portions 113. This results in more first conductive lines 115 passing between adjacent second pins 111 and adjacent conductive portions 113 in the row direction. Therefore, the distance between adjacent second pins 111 and adjacent conductive portions 113 in the row direction needs to be increased to ensure that more first conductive lines 115 can pass through. In this case, the second pins 111 and conductive portions 113 require a larger area. Simultaneously, with an increase in the number of first pins 121, the number of connectors 114 also needs to increase, and more connectors 114 require a larger area.

[0079] In summary, to increase the bandwidth of the semiconductor package structure 1000, the area of ​​the package board 110 needs to be increased, resulting in a higher area cost for the semiconductor package structure 1000.

[0080] Based on this, embodiments of this application provide a semiconductor packaging structure.

[0081] Figure 4 is another schematic diagram of the semiconductor packaging structure 1000 provided in the embodiment of this application.

[0082] Please refer to Figure 4. The semiconductor package structure 1000 includes: a package substrate 200, a logic chip 300 and a plurality of functional chips 400. The package substrate 200 includes a first surface 210, the logic chip 300 is disposed on the first surface 210, and the plurality of functional chips 400 are disposed on the side of the logic chip 300 away from the package substrate 200.

[0083] The functional chip 400 includes a plurality of first external connections 410, which are exposed on the surface of the functional chip 400 away from the logic chip 300.

[0084] The logic chip 300 includes a plurality of second external connections 310, a signal acceleration module 320, and a plurality of third external connections 330. The second external connections 310 are connected to the first external connection 410. The signal acceleration module 320 is connected between at least a portion of the second external connections 310 and at least a portion of the third external connections 330. The signal acceleration module 320 is used to accelerate the signal transmitted by the second external connections 310 and output it to the third external connections 330. The number of third external connections 330 is less than the number of second external connections 310.

[0085] The packaging substrate 200 also includes a plurality of fourth external connections 220, which are exposed on the first surface 210 and connected to the third external connections 330.

[0086] For example, the functional chip 400 can be a memory chip, such as dynamic random access memory (DRAM).

[0087] Multiple functional chips 400 are located on the side of the logic chip 300 facing away from the packaging substrate 200, and the multiple functional chips 400 are stacked. For example, the multiple functional chips 400 may include at least one stacked functional chip group, in which multiple functional chips 400 can be stacked. It should be noted that the first external connection portion 410 of any functional chip 400 is not covered, that is, the first external connection portion 410 can be exposed, so as to facilitate the connection between the first external connection portion 410 and the second external connection portion 310.

[0088] For example, the second external connection 310 and the first external connection 410 can be connected by wire bonding. In this case, the second external connection 310 and the first external connection 410 can be connected by wires, and the signal output by the functional chip 400 through the first external connection 410 can be transmitted to the second external connection 310 through the wires.

[0089] The signal acceleration module 320 is connected between at least a portion of the second external connection portion 310 and at least a portion of the third external connection portion 330. For example, the signal acceleration module 320 is connected between a portion of the second external connection portion 310 and a portion of the third external connection portion 330. Or, for example, the signal acceleration module 320 is connected between all the second external connection portions 310 and all the third external connection portions 330.

[0090] The signal acceleration module 320 is connected between at least a portion of the second external connection portion 310 and at least a portion of the third external connection portion 330. Therefore, the signal received by at least a portion of the second external connection portion 310 can be transmitted to the signal acceleration module 320, and the signal acceleration module 320 can accelerate the received signal and output it to a portion of the third external connection portion 330.

[0091] For example, the bandwidth of the first external connection 410 of the functional chip 400 is 6.4 Gbps (gigabit per second), where bandwidth refers to the maximum number of bytes transmitted per second, which is the maximum data transmission rate of the first external connection 410.

[0092] The first external connection portion 410 has a bit width of 16 bits. Taking eight first external connection portions 410 as an example, the bit width of the eight first external connection portions 410 is 8 × 16 bits. The signal of the functional chip 400 can be transmitted to the signal acceleration module 320 through the first external connection portion 410 and the second external connection portion 310. The bandwidth of the second external connection portion 310 is the same as that of the first external connection portion 410, and the bit width of the second external connection portion 310 is the same as that of the first external connection portion 410.

[0093] After the signal transmitted from the second external connection unit 310 is sent to the signal acceleration module 320, the signal acceleration module 320 can accelerate the signal received from the second external connection unit 310, that is, the signal acceleration module 320 can increase the signal bandwidth. For example, the signal acceleration module 320 can increase the bandwidth to 12.8Gbps. In this case, the bandwidth of the signal output by the signal acceleration module 320 is twice the bandwidth of the signal transmitted by the first external connection unit 410. Therefore, when the bit width of the third external connection unit 330 is the same as that of the second external connection unit 310, the signal acceleration module 320 can transmit the signals received from the eight second external connection units 310 to the four third external connection units 330. For another example, the signal acceleration module 320 can increase the bandwidth to 25.6Gbps. In this case, the bandwidth of the signal output by the signal acceleration module 320 is four times the bandwidth of the signal transmitted by the first external connection unit 410. Therefore, when the bit width of the third external connection 330 is 8 bits, the signal speed-up module 320 can transmit the signals it receives from the eight second external connections 310 to the four third external connections 330.

[0094] In summary, after the signal speed-up module 320 speeds up the signal, not only can the signal bandwidth be increased, but the number of third external connections 330 can also be reduced, resulting in fewer third external connections 330 than the number of second external connections 310. Furthermore, since the fourth external connection 220 is connected to the third external connection 330, the number of fourth external connections 220 can also be reduced, thereby reducing the area occupied by the fourth connection 220, reducing the area of ​​the packaging substrate 200, lowering the area cost of the semiconductor packaging structure 1000, facilitating the miniaturization of the semiconductor packaging structure 1000, and increasing the bandwidth of the semiconductor packaging structure 1000 per unit area.

[0095] Figure 5 is a partial enlarged view of point B in Figure 4, and Figure 6 is a top view of the semiconductor package structure 1000 provided in Figure 4.

[0096] Please refer to Figures 5 and 6. In some embodiments, the plurality of first external connections 410 include a plurality of first-type first external connections 411 and a plurality of second-type first external connections 412, wherein the first-type first external connections 411 are used to transmit data signals and the plurality of second-type first external connections 412 are used to transmit power signals.

[0097] The plurality of second external connections 310 include a plurality of first-type second external connections 311 and a plurality of second-type second external connections 312, wherein the first-type second external connections 311 are connected to the first-type first external connections 411, and the second-type second external connections 312 are connected to the second-type first external connections 412.

[0098] The plurality of third external connections 330 includes a plurality of first-type third external connections 331 and a plurality of second-type third external connections 332. The signal acceleration module 320 is connected between the plurality of first-type second external connections 311 and the plurality of first-type third external connections 331, and the second-type third external connections 332 are connected to the second-type second external connections 312. In this example, the signal acceleration module 320 is connected between a portion of the second external connections 310 and a portion of the third external connections 330.

[0099] The plurality of fourth external connections 220 include a plurality of first-type fourth external connections 221 and a plurality of second-type fourth external connections 222. The first-type fourth external connections 221 are connected to the first-type third external connections 331, and the second-type fourth external connections 222 are connected to the second-type third external connections 332.

[0100] The functional chip 400 can output or receive data signals through the first type of first external connection part 411.

[0101] The second type of first external connection 412 can transmit power signals. For example, the voltage of the power signal transmitted by the second type of first external connection 412 can be 0.6V, 0.8V, and 1.2V, etc.

[0102] The first type of second external connection 311 can be connected to the first type of first external connection 411 by a lead wire, and the second type of second external connection 312 can be connected to the second type of first external connection 412 by a lead wire.

[0103] The signal acceleration module 320 can accelerate the signal received from the first type of second external connection 311 and then transmit it to the first type of third external connection 331. The number of the first type of third external connection 331 is less than the number of the first type of second external connection 311. The first type of fourth external connection 221 can be connected to the first type of third external connection 331. Therefore, the number of the first type of fourth external connection 221 is less than the number of the first type of second external connection 311, thereby reducing the number of the first type of fourth external connection 221 on the packaging substrate 200. This reduces the area occupied by the first type of fourth external connection 221 and the area of ​​the packaging substrate 200, which is beneficial to the miniaturization of the semiconductor packaging structure 1000 and can improve the bandwidth of the semiconductor packaging structure 1000 per unit area.

[0104] The second type fourth external connection 222 is connected to the second type third external connection 332, and the second type third external connection 332 is connected to the second type first external connection 412 through the second type second external connection 312. Therefore, the power signal received by the second type fourth external connection 222 can be transmitted to the second type first external connection 412, thereby powering the functional chip 400.

[0105] Referring to Figure 5, in some embodiments, in at least a portion of the second type third external connection 332, one second type third external connection 332 is connected to at least two second type second external connection 312. Wherein, in the interconnected second type third external connection 332 and second type second external connection 312, the number of second type third external connection 332 is less than or equal to the number of second type second external connection 312.

[0106] For example, in some second-type third external connections 332, one second-type third external connection 332 is connected to at least two second-type second external connections 312, and the aforementioned at least two second-type second external connections 312 may be connected to one or more second-type third external connections 332. The number of second-type third external connections 332 is less than the number of second-type second external connections 312.

[0107] In the remaining second-type third external connection parts 332, one second-type third external connection part 332 is connected to one second-type second external connection part 312. The number of second-type third external connection parts 332 is equal to the number of second-type second external connection parts 312.

[0108] For example, in all the second type of third external connections 332, one second type of third external connection 332 is connected to at least two second type of second external connections 312. The number of second type of third external connections 332 is less than the number of second type of second external connections 312.

[0109] The second type of third external connection part 332 and the second type of second external connection part 312, which are interconnected, can be used to transmit the same power signal.

[0110] For example, among the multiple second-type second external connections 312, some of the second-type second external connections 312 transmit power signals with the same voltage. For example, some of the second-type second external connections 312 transmit power signals with a voltage of 0.6V, another part of the second-type second external connections 312 transmit power signals with a voltage of 0.8V, and yet another part of the second-type second external connections 312 transmit power signals with a voltage of 1.2V.

[0111] Some of the second type of second external connection parts 312 can be connected to a second type of third external connection part 332, which can transmit a 0.6V power signal. Some of the second type of second external connection parts 312 can also be connected to two or more second type of third external connection parts 332.

[0112] Another portion of the second type of second external connection 312 can be connected to another second type of third external connection 332, which can transmit a 0.8V power signal. Furthermore, this other portion of the second type of second external connection 312 can also be connected to two or more second type of third external connection 332.

[0113] Another portion of the second type of second external connection 312 can be connected to another second type of third external connection 332, which can transmit a 1.2V power signal. Furthermore, another portion of the second type of second external connection 312 can also be connected to two or more second type of third external connection 332.

[0114] In this embodiment, a second type third external connection 332 is connected to at least two second type second external connections 312. Therefore, the power signal transmitted by the at least two second type second external connections 312 can be transmitted to a second type third external connection 332. Furthermore, multiple second type second external connections 312 used to transmit power signals of the same voltage can be merged. At this time, the number of second type third external connections 332 is less than the number of second type second external connections 312, thereby reducing the number of second type third external connections 332. The second type third external connection 332 can also be connected to a second type fourth external connection 222. Therefore, the number of second type fourth external connections 222 can be reduced accordingly, thereby reducing the number of external connections on the packaging substrate 200 and thus reducing the area cost of the packaging substrate 200.

[0115] In other embodiments, multiple first external connections 410 are used to transmit data signals, and second external connections 310 are connected to the first external connections 410. In this case, the multiple second external connections 310 are used to transmit data signals. The signal acceleration module 320 is connected between the multiple second external connections 310 and the multiple third external connections 330; that is, the signal acceleration module 320 is connected between all the second external connections 310 and all the third external connections 330.

[0116] Please continue referring to Figures 4 and 5. In some embodiments, a plurality of second external connections 310 are exposed on the surface of the logic chip 300 away from the package substrate 200. These second external connections 310 include a first type of second external connection 311 and a second type of second external connection 312.

[0117] The second external connection portion 310 and the first external connection portion 410 can be connected by wirebond technology. In this case, the semiconductor package structure 1000 may also include multiple first connection lines 510, one end of which is connected to the first external connection portion 410 and the other end is connected to the second external connection portion 310.

[0118] The data signal of the functional chip 400 can be transmitted to the second external connection 310 through the first external connection part 410 and the first connection line 510.

[0119] The second external connection portion 310 is exposed on the surface of the logic chip 300 away from the packaging substrate 200, thereby facilitating the connection of the second external connection portion 310 to the first external connection portion 410 via the first connection line 510.

[0120] In some embodiments, a plurality of third external connections 330 are exposed on the surface of the logic chip 300 away from the package substrate 200.

[0121] The third connection portion 330 and the fourth connection portion 220 can be connected via a wirebond process. For example, the semiconductor package structure 1000 may also include multiple second connection lines 520, one end of which is connected to the third external connection portion 330 and the other end of which is connected to the fourth external connection portion 220. The multiple third external connection portions 330 include first-type third external connection portions 331 and second-type third external connection portions 332, and the multiple fourth connection portions 220 include first-type fourth connection portions 221 and second-type fourth connection portions 222.

[0122] By exposing multiple third external connections 330 on the surface of the logic chip 300 away from the packaging substrate 200, the third external connections 330 can be easily connected to the fourth external connection 220 via the second connection line 520.

[0123] Please refer back to Figure 4. In some examples, the semiconductor package structure 1000 may further include a first adhesive layer 710. The first adhesive layer 710 is disposed between the logic chip 300 and the package substrate 200, and the logic chip 300 is connected to the package substrate 200 through the first adhesive layer 710. Please refer to Figure 6. In some embodiments, a plurality of second external connections 310 are arranged in multiple rows and columns, and the width of the area occupied by the plurality of second external connections 310 in the row direction X is greater than the width of the plurality of second external connections 310 in the column direction Y.

[0124] Please refer to Figure 6 and Figure 5 at the same time. Multiple first-type third external connecting parts 331 and multiple second-type third external connecting parts 332 are respectively provided on both sides of the second external connecting part 310 in the column direction Y.

[0125] With this configuration, the type of the connecting part can be determined based on its location. For example, the second connecting parts 310 are arranged in four rows. The first type of third connecting parts 331 can be arranged in one row, and the second type of third connecting parts 332 can be arranged in one row. In this case, the connecting parts located in the first row are the second type of third connecting parts 332, the connecting parts in the second, third, fourth, and fifth rows are the second connecting parts 310, and the connecting parts located in the sixth row are the first type of third connecting parts 331.

[0126] Furthermore, the second type of second external connection 312 is closer to the second type of third external connection 332 than the first type of second external connection 311. Therefore, the first connecting wire between the second type of second external connection 312 and the second type of third external connection 332 can avoid the area covered by the first type of second external connection 311, and the second connecting wire between the first type of second external connection 311 and the first type of third external connection 331 can avoid the area covered by the second type of second external connection 312 and the area covered by the second type of third external connection 332. This can prevent the first connecting wire and the second connecting wire from being interleaved, thereby reducing the short circuit between the first connecting wire and the second connecting wire.

[0127] Please refer to Figure 4 again. In some embodiments, a mounting position is provided between the designated third external connection and the plurality of second external connections 310.

[0128] The semiconductor package structure 1000 may further include a first support portion 610. The first support portion 610 is disposed between the logic chip 300 and the plurality of functional chips 400, and the first support portion 610 is located on a mounting position between a designated third external connection portion and a plurality of second external connection portions 310. The designated third external connection portion is either a first type third external connection portion 331 or a second type third external connection portion 332.

[0129] Among them, the distance between one of the first type third external connecting part 331 and the second type third external connecting part 332 and the plurality of second external connecting parts 310 is greater than the distance between the other of the first type third external connecting part 331 and the plurality of second external connecting parts 310.

[0130] For example, if the distance between the first type of third external connection 331 and the plurality of second external connection 310 is greater than the distance between the second type of third external connection 332 and the plurality of second external connection 310, then the first type of third external connection 331 is the designated third external connection.

[0131] For example, if the distance between the second type of third external connection 332 and the plurality of second external connection 310 is greater than the distance between the first type of third external connection 331 and the plurality of second external connection 310, then the second type of third external connection 332 is the designated third external connection.

[0132] The first support portion 610 is disposed on the mounting position. Therefore, the first support portion 610 can avoid the second external connection portion 310 and the third external connection portion 330 on the logic chip 300. Thus, the second external connection portion 310 and the third external connection portion 330 can be connected to other connection portions.

[0133] By providing the first support portion 610, multiple functional chips 400 can be supported to form a space between them and the logic chip 300. Therefore, the second external connection portion 310 and the third external connection portion 330 on the logic chip 300 are not directly covered by the functional chips 400. This facilitates the connection between the second external connection portion 310 and the first external connection portion 410, and the connection between the third external connection portion 330 and the fourth connection portion 220. Here, "directly covered" means that the second external connection portion 310 and the third external connection portion 330 on the logic chip 300 do not directly contact the functional chips 400.

[0134] Referring to Figures 4 and 5, in some embodiments, the projection of multiple functional chips 400 in a direction perpendicular to the packaging substrate 200 covers multiple first-type third external connections 331, where the first-type third external connections 331 are designated third external connections. In this case, a mounting position is disposed between the first-type third external connections 331 and multiple second external connections 310, and a first support portion 610 is located between the multiple second external connections 310 and multiple first-type third external connections 331, thereby creating a space between the first-type third external connections 331 and the functional chips 400. This facilitates the connection between the first-type third external connections 331 and the first-type fourth connection portion 221.

[0135] In some embodiments, the projections of the multiple functional chips 400 in a direction perpendicular to the packaging substrate 200 do not cover the second external connection portion 310 and the second type of third external connection portion 332, thereby facilitating the connection between the second external connection portion 310 and the first external connection portion 410, and the connection between the second type of third external connection portion 332 and the second type of fourth external connection portion 222. In other embodiments, the projections of the multiple functional chips 400 in a direction perpendicular to the packaging substrate 200 cover the multiple second type of third external connection portions 332, where the second type of third external connection portion 332 is a designated third external connection portion. In this case, a mounting position is provided between the second type of third external connection portion 332 and the multiple second external connection portions 310, and a first support portion 610 is located between the multiple second external connection portions 310 and the multiple second type of third external connection portions 332, thereby forming a space between the second type of third external connection portion 332 and the functional chip 400, thus facilitating the connection between the second type of third external connection portion 332 and the second type of fourth connection portion 222.

[0136] In this case, the projection of multiple functional chips 400 in the direction perpendicular to the packaging substrate 200 does not cover the second external connection portion 310 and the first type of third external connection portion 331, thereby facilitating the connection of the second external connection portion 310 to the first external connection portion 410, and the connection of the first type of third external connection portion 331 to the first type of fourth external connection portion 221.

[0137] In some examples, the semiconductor package structure 1000 may also include a third adhesive layer 730 located between the first support portion 610 and the logic chip 300, in which case the first support portion 610 is connected to the logic chip 300 through the third adhesive layer 730.

[0138] Referring to Figure 4, in some embodiments, the semiconductor package structure 1000 may further include a second support portion 620. One end of the second support portion 620 is connected to the package substrate 200, and the other end is connected between the functional chips 400 closest to the package substrate 200 among the plurality of functional chips 400. The thickness of the second support portion 620 in the direction perpendicular to the package substrate 200 may be greater than the thickness of the logic chip 300 in the direction perpendicular to the package substrate 200.

[0139] With this configuration, the second support portion 620 can support multiple functional chips 400, and a space can be formed between the multiple functional chips 400 and the logic chip 300. At this time, the second external connection portion 310 and the third external connection portion 330 of the logic chip 300 are not directly covered by the functional chips 400, which makes it easier for the second external connection portion 310 to be connected to the first external connection portion 410, and for the third external connection portion 330 to be connected to the fourth external connection portion 220.

[0140] In some examples, the semiconductor package structure 1000 may also include a fourth adhesive layer 740 located between the second support portion 620 and the package substrate 200, in which case the second support portion 620 is connected to the package substrate 200 through the fourth adhesive layer 740.

[0141] In some examples, the sum of the thicknesses of the second support portion 620 and the fourth adhesive layer 740 is equal to the sum of the thicknesses of the first support portion 610, the logic chip 300, the third adhesive layer 730, and the first adhesive layer 710. Thus, the second support portion 620 and the first support portion 610 can provide stable support for multiple functional chips 400, thereby ensuring the stability of the semiconductor package structure 1000.

[0142] Please refer to Figures 4 and 5. In some embodiments, the orthographic projection of multiple functional chips 400 on the packaging substrate 200 covers a portion of the fourth external connection portion 220. The portion of the fourth external connection portion 220 is located within the space enclosed by the first support portion 610, the logic chip 300, the functional chip 400, and the packaging substrate 200.

[0143] Please continue to refer to Figures 4 and 5. For example, the portion of the fourth external connection 220 covered by the orthographic projection of the multiple functional chips 400 on the packaging substrate 200 can be a first type of fourth connection 221. In this case, the projection of the multiple functional chips 400 in the direction perpendicular to the packaging substrate 200 covers multiple first type of third external connections 331. This arrangement allows for a smaller distance between the first type of fourth connection 221 and the first type of third external connection 331, thereby facilitating their connection.

[0144] The second type of fourth connection portion 222 is located on the side of the logic chip 300 away from the first type of fourth connection portion 221, and is not covered by the projection of the multiple functional chips 400 onto the package substrate 200. The second type of third external connection portion 332 can be located on the side of the multiple second external connection portions 310 away from the first type of third external connection portion 331, and is not covered by the projection of the multiple functional chips 400 onto the package substrate 200. This arrangement allows for a smaller distance between the second type of fourth connection portion 222 and the second type of third external connection portion 332, facilitating their connection.

[0145] For example, the portion of the fourth external connection 220 covered by the orthographic projection of multiple functional chips 400 on the packaging substrate 200 can be a second type of fourth connection 222. In this case, the projection of multiple functional chips 400 in the direction perpendicular to the packaging substrate 200 covers multiple second type of third external connections 332. This arrangement allows for a smaller distance between the second type of fourth connection 222 and the second type of third external connection 332, thereby facilitating their connection.

[0146] The first type of fourth connection portion 221 is located on the side of the logic chip 300 away from the second type of fourth connection portion 222, and is not covered by the projection of the multiple functional chips 400 onto the package substrate 200. The first type of third external connection portion 331 can be located on the side of the multiple second external connection portions 310 away from the second type of third external connection portion 332, and is not covered by the projection of the multiple functional chips 400 onto the package substrate 200. This arrangement facilitates the connection between the first type of fourth connection portion 221 and the first type of third external connection portion 331.

[0147] Referring to Figure 6, in some embodiments, the surface of the functional chip 400 facing away from the packaging substrate 200 includes multiple edges 420, and multiple first external connections 410 are arranged along a portion of the edges of the functional chip 400. The multiple functional chips 400 include at least one stacked functional chip group 401; the stacked functional chip group 401 includes multiple stacked functional chips 400, and in two adjacent functional chips 400 in the stacking direction G, the functional chip 400 farther from the packaging substrate 200 avoids the first external connection 410 of the functional chip 400 closer to the packaging substrate 200. The number of logic chips 300 is multiple, and the multiple logic chips 300 are respectively disposed along the edges 420 of the stacked functional chip group 401 near the first external connections 410.

[0148] The number of stacked functional chip groups 401 can be one, two, three, four, or even more. Figure 6 illustrates an embodiment of this application using two stacked functional chip groups 401 as an example. As shown in Figure 6, the two stacked functional chip groups 401 can be arranged sequentially along the second direction F2. The second direction F2 is parallel to the packaging substrate 200.

[0149] Please refer to Figure 4. The semiconductor package structure 1000 may also include multiple second adhesive layers 720. In the stacked functional chipset 401, two adjacent functional chips 401 in the stacking direction G can be connected through the second adhesive layers 720.

[0150] The upper functional chip 400 can avoid the first external connection portion 410 of the lower functional chip 400, thus exposing the first external connection portion 410. Therefore, the first external connection portion 410 can connect to the second external connection portion 310. The upper functional chip 400 refers to the functional chip 400 that is farther from the packaging substrate 200 among two adjacent functional chips 400, while the lower functional chip 400 refers to the functional chip 400 that is closer to the packaging substrate 200 among two adjacent functional chips 400.

[0151] The logic chip 300 can be disposed along the edge 420 of the stacked functional chip group 401 near the first external connection portion 410, so that there is a small distance between the second external connection portion 310 on the logic chip 300 and the first external connection portion 410 of the functional chip 400, thereby facilitating the connection between the second external connection portion 310 and the first external connection portion 410.

[0152] Referring to Figure 6, in some embodiments, the multiple edges 420 of the functional chip 400 include a first edge 421, and multiple first external connections 410 are disposed along the first edge 421. The first edges 421 of two adjacent functional chips 400 in the stacking direction G are disposed opposite each other in a first direction F1, wherein the first direction F1 is parallel to the packaging substrate 200.

[0153] The plurality of logic chips 300 include a first logic chip 301 and a second logic chip 302. The first logic chip 301 and the second logic chip 302 are arranged sequentially at intervals along a first direction F1. The stacked functional chip group 401 is located on the side of the first logic chip 301 and the second logic chip 302 away from the packaging substrate 200.

[0154] The second external connection portion 310 of the first logic chip 301 and the second external connection portion 310 of the second logic chip 302 are located on both sides of the stacked functional chip group 401 in the first direction F1. At this time, the projection of the stacked functional chip group 401 in the stacking direction G does not cover the second external connection portion 310 of the first logic chip 301 and the second external connection portion 310 of the second logic chip 302, thereby facilitating the connection of the second external connection portion 310 to the first external connection portion 410.

[0155] The first direction F1 can be the same as the column direction Y of the second external connection portion 310 of the first logic chip 301, while the second direction F2 can be the same as the row direction X of the second external connection portion 310 of the first logic chip 301.

[0156] In the first logic chip 301, the second type of third external connection 332 can be located on the side of the second external connection 310 away from the stacked functional chipset 401, while the first type of third external connection 331 can be located on the side of the second external connection 310 closer to the second logic chip 302. The second type of third external connection 332 is not covered by the projection of the stacked functional chipset 401 in the stacking direction G, while the first type of third external connection 331 can be covered by the projection of the stacked functional chipset 401 in the stacking direction G.

[0157] In the second logic chip 302, the second type of third external connection 332 can be located on the side of the second external connection 310 away from the stacked functional chip group 401, while the first type of third external connection 331 can be located on the side of the second external connection 310 close to the first logic chip 301.

[0158] Figure 7 is another top view of the semiconductor package structure 1000 provided in an embodiment of this application. Figure 7 illustrates an embodiment of this application using a stacked functional chipset 401 as an example.

[0159] Referring to Figure 7, in some examples, two adjacent functional chips 400 are stacked in the stacking direction G. The multiple edges 420 of the functional chip 400 may also include a second edge 422, which may be adjacent to the first edge 421. A portion of the first external connection portion 410 is sequentially disposed along the first edge 421, and another portion of the first external connection portion 410 is sequentially disposed along the second edge 422.

[0160] In the stacked functional chipset 401, the second edges 422 of two adjacent functional chips 400 in the stacking direction G are arranged opposite each other along the third direction F3.

[0161] The plurality of logic chips 300 may further include a third logic chip 303 and a fourth logic chip 304, which are disposed opposite to each other on a third direction F3. A stacked functional chipset 401 is located on the side of the third logic chip 303 and the fourth logic chip 304 facing away from the packaging substrate 200. The third direction F3 is parallel to the packaging substrate 200 and intersects with the first direction F1. For example, the third direction F3 is perpendicular to the first direction F1.

[0162] Among them, the second external connection portion 310 of the third logic chip 303 and the second external connection portion 310 of the fourth logic chip 304 are respectively located on both sides of the stacked functional chip group 401 on the third direction F3.

[0163] The third logic chip 303 is adjacent to the second edge 422 of the partial functional chip 400, which facilitates the electrical connection of the second external connection portion 310 of the third logic chip 303 with another portion of the first external connection portion 410 of the partial functional chip 400 located along the second edge 422.

[0164] The fourth logic chip 304 is adjacent to the second edge 422 of another part of the functional chip 400, which facilitates the electrical connection of the second external connection portion 310 of the fourth logic chip 304 with the other part of the first external connection portion 410 provided along the second edge 422 of the other part of the functional chip 400.

[0165] In some examples, a portion of the fourth external connection 220 is located on the side of the first logic chip 301 away from the stacked functional chipset 401, another portion of the fourth external connection 220 is located on the side of the second logic chip 302 away from the stacked functional chipset 401, yet another portion of the fourth external connection 220 is located on the side of the third logic chip 303 away from the stacked functional chipset 401, and yet another portion of the fourth external connection 220 is located on the side of the fourth logic chip 304 away from the stacked functional chipset 401.

[0166] Figure 8 is another top view of the semiconductor packaging structure 1000 provided in the embodiment of this application.

[0167] Referring to FIG8, in some embodiments, the functional chip 400 further includes a plurality of fifth external connections 430, which are exposed on the surface of the functional chip 400 away from the packaging substrate 200; the packaging substrate 200 further includes a plurality of sixth external connections 230, which are exposed on the first surface 210.

[0168] The semiconductor package structure 1000 also includes multiple third connection lines, one end of which is connected to the fifth external connection 430 and the other end is connected to the sixth external connection 230.

[0169] Among them, some signals of the functional chip 400 can be directly transmitted to the sixth external connection 230 of the packaging substrate 200 through the fifth external connection 430 and the third connection line.

[0170] The fifth external connection section 430 can be used to transmit power signals. At this time, the power signal received by the sixth external connection section 230 can be transmitted to the fifth external connection section 430 through the third connection line to power the functional chip 400.

[0171] In some embodiments, the surface of the functional chip 400 away from the logic chip 300 includes a plurality of edges 420, among which are adjacent first edges 421 and second edges 422, a plurality of first external connections 410 are disposed along the first edge 421, and a plurality of fifth external connections 430 are disposed along the second edge 422.

[0172] The second edges 422 of two adjacent functional chips 400 in the stacking direction G are disposed opposite each other in a third direction F3, wherein the third direction F3 is parallel to the package substrate 200 and intersects with the second edges 422. For example, the third direction F3 may be disposed perpendicular to the first direction F1.

[0173] In this case, the orthographic projection of multiple functional chips 400 on the first surface 210 is offset from multiple sixth external connections 230. This avoids the sixth external connections 230 being covered by the functional chips 400, thereby exposing the sixth external connections 230 and facilitating their connection with the fifth external connection 430.

[0174] Multiple sixth external connections 230 are sequentially arranged along the orthographic projection of the second edge 422 of the functional chip 400 onto the first surface 210, and the multiple sixth external connections 230 are divided into two groups, with the two groups of sixth external connections 230 located on both sides of the multiple functional chips 400 on the third direction F3.

[0175] With this configuration, the orthographic projection of the fifth external connection portion 430 of some functional chips 400 onto the packaging substrate 200 can be arranged adjacent to a group of sixth external connections 230, thereby making the distance between the fifth external connection portion 430 of some functional chips 400 and the group of sixth external connections 230 closer, thus facilitating their connection. Similarly, the orthographic projection of the fifth external connection portion 430 of another group of functional chips 400 onto the packaging substrate 200 can be arranged adjacent to another group of sixth external connections 230, thereby making the distance between the fifth external connection portion 430 of another group of sixth external connections 230 closer, thus facilitating their connection.

[0176] For example, the multiple sixth external connections 230 can be divided into a first group of sixth external connections 231 and a second group of sixth external connections 232, wherein the first group of sixth external connections 231 and the second group of sixth external connections 232 are respectively located on both sides of the multiple functional chips 400 on the third-direction F3.

[0177] The multiple functional chips 400 include multiple first-type functional chips 402 and multiple second-type functional chips 403, wherein the first-type functional chips 402 and the second-type functional chips 403 are stacked alternately, and the second edge 422 of the first-type functional chip 402 is disposed opposite to the second edge 422 of the first-type functional chip 402 on a third-direction F3.

[0178] In this configuration, the orthographic projection of the second edge 422 of the first type of functional chip 402 onto the packaging substrate 200 is adjacent to the first group of sixth external connections 231, which in turn connects to the fifth external connection 430 of the first type of functional chip 402. This arrangement allows for a shorter distance between the first group of sixth external connections 231 and the fifth external connection 430 of the first type of functional chip 402, facilitating their connection.

[0179] The second edge 422 of the second type of functional chip 403, when projected onto the packaging substrate 200, is adjacent to the second group of sixth external connections 232, which is connected to the fifth external connection 430 of the second type of functional chip 403. This arrangement allows for a shorter distance between the second group of sixth external connections 232 and the fifth external connection 430 of the second type of functional chip 403, facilitating their connection.

[0180] Furthermore, when the plurality of first external connections 410 include a plurality of second-type first external connections 412, the second-type first external connections 412 can be disposed along the first edge 421, and the plurality of fifth external connections 430 can be disposed along the second edge 422. Both the second-type first external connections 412 and the plurality of fifth external connections 430 can be used to transmit power signals. By distributing the second-type first external connections 412 and the plurality of fifth external connections 430 along different edges, the power supply uniformity of the functional chip 400 can be improved, which is beneficial to the stability of the functional chip 400.

[0181] Please refer back to Figures 4 and 5. In some embodiments, the packaging substrate 200 further includes a substrate body 240, multiple first traces 250, multiple first connection portions 260, and multiple eighth external connections 270. The multiple fourth external connections 220 and the multiple first traces 250 are all disposed on the surface of the substrate body 240 facing the logic chip 300. The multiple first connection portions 260 are disposed within the substrate body 240. The eighth external connections 270 are disposed on the surface of the packaging substrate 200 away from the logic chip 300. The fourth external connections 220 are connected to one end of the first connection portion 260 via the first traces 250, and the other end of the first connection portion 260 is connected to the eighth external connection portion 270.

[0182] The first connecting portion 260 can penetrate the substrate body 240. One end of the first connecting portion 260 is connected to the end of the first trace 250 away from the fourth external connection portion 220, and the other end of the first connecting portion 260 is connected to the eighth external connection portion 270. Therefore, the signal output by the third external connection portion 330 can be transmitted to the eighth external connection portion 270 through the fourth external connection portion 220, the first trace 250, and the first connecting portion 260.

[0183] The eighth external connection 270 can be electrically connected to other electronic devices. For example, the other electronic device can be a processor; or, for example, the other electronic device can be a circuit board, on which the processor and other electronic devices can be mounted, thereby allowing the semiconductor package structure 1000 to be electrically connected to the processor via the circuit board.

[0184] For example, the eighth external connector 270 can be a solder ball.

[0185] In some examples, among the multiple first traces 250, some of the first traces 250 are connected to the fourth external connection 220, and another portion of the first traces 250 are connected to the sixth external connection 230.

[0186] Figure 9 is another structural schematic diagram of the semiconductor packaging structure 1000 provided in the embodiment of this application, and Figure 10 is a partial enlarged view of point C in Figure 9.

[0187] Referring to Figures 9 and 10, in some embodiments, the packaging substrate 200 further includes a substrate body 240, a plurality of seventh external connections 281, a plurality of third traces 282, a plurality of first connection portions 260, and a plurality of eighth external connections 270. The plurality of seventh external connections 281 and the plurality of third traces 282 are exposed on the surface of the substrate body 240 facing the logic chip 300, and the plurality of eighth external connections 270 are exposed on the surface of the substrate body 240 away from the logic chip 300. The first connection portions 260 are disposed within the substrate body 240.

[0188] Multiple second external connections 310 and multiple third external connections 330 are exposed on the surface of the logic chip 300 facing the substrate body 240.

[0189] The semiconductor package structure 1000 also includes a fourth connection line 540, one end of which is connected to the first external connection portion 410 and the other end of which is connected to the seventh external connection portion 281.

[0190] One end of the third wiring 282 is connected to the seventh external connection part 281, and the other end is connected to the second external connection part 310.

[0191] The third external connection 330 is connected to one end of the first connection 260, and the other end of the first connection 260 is connected to the eighth external connection 270.

[0192] The first connection portion 260 serves as the fourth external connection portion 220, with one end of the first connection portion 260 exposed on the surface of the substrate body 240 facing the logic chip 300.

[0193] The surface of the substrate body 240 facing the logic chip 300 is the first surface 210.

[0194] The signal output by the functional chip 400 through the first external connection part 410 can be transmitted to the second external connection part 310 of the logic chip 300 through the fourth connection line 540, the seventh external connection part 281 and the third trace 282.

[0195] The logic chip 300 speeds up the signal received from the second external connection section 310. The speed-up signal can be output by the third external connection section 330. The signal output by the third external connection section 330 can be transmitted to the eighth external connection section 270 through the first connection section 260.

[0196] Since the logic chip 300 can speed up and merge signals, the number of third external connections 330 can be reduced. The third external connections 330 are connected to the first connection 260, thereby reducing the number of first connection 260 provided in the substrate body 240. Correspondingly, the number of eighth external connections 270 can also be reduced, thereby reducing the area of ​​the substrate body 240 and reducing the area cost of the packaging substrate 200.

[0197] The eighth external connection part 270 can be electrically connected to other electronic devices. For example, the other electronic devices can be processors; or, for example, other electronic devices can be circuit boards, on which processors and other electronic devices can be mounted, thereby allowing the semiconductor package structure 1000 to be electrically connected to the processor via the circuit board.

[0198] For example, the eighth external connector 270 can be a solder ball.

[0199] In some embodiments, as shown in Figures 4 and 9, the semiconductor package structure 1000 may further include a packaging layer 140. The packaging layer 140 covers the surface of the package substrate 200 facing the logic chip 300 and covers the outer surfaces of the logic chip 300 and the multiple functional chips 400. The packaging layer 140 can seal the logic chip 300 and the multiple functional chips 400, thereby reducing the impact of external environmental factors (moisture, temperature, air pressure, pressure, etc.) on the integrated logic chip 300 and the multiple functional chips 400, thus protecting the logic chip 300 and the multiple functional chips 400.

[0200] Figure 11 is a structural diagram of the electronic device 2000 provided in the embodiment of this application.

[0201] Referring to Figure 11, this application embodiment also provides an electronic device 2000, which includes a processor 3000 and a semiconductor package structure 1000 provided in some of the above embodiments. The processor 3000 is electrically connected to the fourth external connection portion 220 of the package substrate 200 of the semiconductor package structure 1000.

[0202] The electronic device 2000 provided in this application includes all the structures of the semiconductor packaging structure 1000 provided in the above embodiments, and therefore has all the beneficial effects of the semiconductor packaging structure 1000 provided in the above embodiments, which will not be elaborated here.

[0203] For example, processor 3000 can be a central processing unit (CPU) or a graphics processing unit (GPU).

[0204] The processor 3000 and the fourth external connection part 2000 can be indirectly connected, that is, the processor 3000 and the fourth external connection part 2000 do not directly contact each other, but are electrically connected through other structures.

[0205] For example, the bandwidth between functional chip 400 and logic chip 300 is 6.4 Gbps, and the output port width of functional chip 400 is 16 bits. After the speed-up by logic chip 300, the bandwidth of the signal output by logic chip 300 is 12.8 Gbps, and the output port width of logic chip 300 is 16 bits. Therefore, the bandwidth of the signal output by semiconductor package structure 1000 is 12.8 Gbps, and at this time, the bandwidth between processor 3000 and semiconductor package structure 1000 is 12.8 Gbps. At this time, the signal output by functional chip 400 through 8 output ports can be output by logic chip 300 through 4 output ports after the speed-up by logic chip 300. Among them, the output port of functional chip 400 is the first type of first external connection 411, and the output port of logic chip 300 is the first type of third external connection 331.

[0206] For example, the bandwidth between functional chip 400 and logic chip 300 is 6.4 Gbps, and the output port width of functional chip 400 is 16 bits. After being accelerated by logic chip 300, the bandwidth of the signal output by logic chip 300 is 25.6 Gbps, and the output port width of logic chip 300 is 8 bits. Therefore, the bandwidth of the signal output by semiconductor package structure 1000 is 25.6 Gbps, and at this time, the bandwidth between processor 3000 and semiconductor package structure 1000 is 25.6 Gbps. At this point, the signal output by functional chip 400 through its 8 output ports, after being accelerated by logic chip 300, can be output through the 4 output ports of logic chip 300.

[0207] Figure 12 is another structural diagram of the electronic device 2000 provided in the embodiments of this application.

[0208] Referring to Figure 12, in some examples, the processor 3000 may be stacked with the semiconductor package structure 1000. The processor 3000 may include a plurality of first external portions 3100 and a plurality of second external portions 3200, wherein the plurality of first external portions 3100 are exposed on the surface of the processor 3000 facing the semiconductor package structure 1000, and the plurality of second external portions 3200 are exposed on the surface of the processor 3000 away from the semiconductor package structure 1000.

[0209] The first external portion 3100 can be connected to the eighth external portion 270 of the packaging substrate 200 of the semiconductor packaging structure 1000, so that the semiconductor packaging structure 1000 can be electrically connected to the processor 3000.

[0210] Electronic device 2000 may include circuit board 4000, which may be located on the side of processor 3000 away from semiconductor package structure 1000. Circuit board 4000 is provided with a plurality of pads 4100, which may be connected to the second external part 3200 of processor 3000.

[0211] In addition, the electronic device 2000 may also include other electronic components disposed on a circuit board, which can be electrically connected to the processor 3000 and the semiconductor package structure 1000 via the circuit board 4000.

[0212] Figure 13 is another structural diagram of the electronic device 2000 provided in the embodiments of this application.

[0213] Referring to Figure 13, in some other examples, the semiconductor package structure 1000 and the processor 3000 may be arranged side by side on the circuit board 4000, in which case a plurality of eighth external connections 270 of the semiconductor package structure 1000 are connected to a portion of the pads 4100 of the circuit board 4000.

[0214] The processor 3000 can be disposed on the circuit board 4000. For example, the processor 3000 may include a plurality of third external portions 3300. The plurality of third external portions 3300 may be exposed on the surface of the processor 3000 facing the circuit board 4000. The plurality of third external portions 3300 are connected to another portion of the pads 4100 of the circuit board 4000. In this case, the processor 3000 and the semiconductor package structure 1000 can be electrically connected through the traces of the circuit board 4000.

[0215] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor packaging structure, characterized in that, include: The package substrate, logic chip, and multiple functional chips are provided. The package substrate includes a first surface, the logic chip is disposed on the first surface, and the multiple functional chips are disposed on the side of the logic chip opposite to the package substrate. The functional chip includes a plurality of first external connections, which are exposed on the surface of the functional chip away from the logic chip. The logic chip includes multiple second external connections, a signal acceleration module, and multiple third external connections. The second external connections are connected to the first external connections. The signal acceleration module is connected between at least a portion of the second external connections and at least a portion of the third external connections. The signal acceleration module is used to accelerate the signal transmitted by the second external connections and output it to the third external connections. The number of third external connections is less than the number of second external connections. The packaging substrate further includes a plurality of fourth external connections, which are exposed on the first surface and connected to the third external connection.

2. The semiconductor packaging structure according to claim 1, characterized in that, The plurality of first external connections include a plurality of first-type first external connections and a plurality of second-type first external connections, wherein the first-type first external connections are used to transmit data signals, and the plurality of second-type first external connections are used to transmit power signals; The plurality of second external connections include a plurality of first-type second external connections and a plurality of second-type second external connections, wherein the first-type second external connections are connected to the first-type first external connections, and the second-type second external connections are connected to the second-type first external connections; The plurality of third external connections include a plurality of first-type third external connections and a plurality of second-type third external connections. The signal acceleration module is connected between the plurality of first-type second external connections and the plurality of first-type third external connections. The second-type third external connections are connected to the second-type second external connections. The plurality of fourth external connections include a plurality of first-type fourth external connections and a plurality of second-type fourth external connections, wherein the first-type fourth external connections are connected to the first-type third external connections, and the second-type fourth external connections are connected to the second-type third external connections.

3. The semiconductor packaging structure according to claim 2, characterized in that, In at least a portion of the second type of third external connection, one second type of third external connection is connected to at least two second type of second external connection; wherein, in the interconnected second type of third external connection and the second type of second external connection, the number of second type of third external connection is less than or equal to the number of second type of second external connection.

4. The semiconductor packaging structure according to claim 2 or 3, characterized in that, The plurality of second external connections and the plurality of third external connections are exposed on the surface of the logic chip away from the packaging substrate; The semiconductor packaging structure further includes multiple first connecting lines and multiple second connecting lines. One end of the first connecting line is connected to the first external connection portion, and the other end is connected to the second external connection portion. One end of the second connecting line is connected to the third external connection portion, and the other end is connected to the fourth external connection portion.

5. The semiconductor packaging structure according to claim 4, characterized in that, The plurality of second external connecting parts are arranged in multiple rows and columns; The plurality of first-type third external connecting parts and the plurality of second-type third external connecting parts are respectively disposed on both sides of the plurality of second external connecting parts in the column direction.

6. The semiconductor packaging structure according to claim 5, characterized in that, A mounting position is provided between the designated third external connection and the plurality of second external connections; the semiconductor package structure further includes: a first support portion, the first support portion being disposed between the logic chip and the plurality of functional chips, and the first support portion being located on the mounting position between the designated third external connection and the plurality of second external connections, wherein the designated third external connection is either the first type of third external connection or the second type of third external connection.

7. The semiconductor packaging structure according to claim 6, characterized in that, The projection of the plurality of functional chips in a direction perpendicular to the packaging substrate covers the plurality of first-type third external connections, wherein the first-type third external connections are designated third external connections.

8. The semiconductor packaging structure according to claim 6, characterized in that, The projection of the plurality of functional chips in a direction perpendicular to the packaging substrate covers the plurality of second-type third external connections, wherein the second-type third external connections are designated third external connections.

9. The semiconductor packaging structure according to any one of claims 5-8, characterized in that, Also includes: The second support portion has one end connected to the packaging substrate and the other end connected to the functional chip closest to the packaging substrate among the plurality of functional chips. The thickness of the second support portion in the direction perpendicular to the packaging substrate is greater than the thickness of the logic chip in the direction perpendicular to the packaging substrate.

10. The semiconductor packaging structure according to any one of claims 6-9, characterized in that, The orthographic projection of the plurality of functional chips on the packaging substrate covers a portion of the fourth external connection portion, and a portion of the fourth external connection portion is located within the space enclosed by the first support portion, the logic chip, the functional chip and the packaging substrate.

11. The semiconductor packaging structure according to any one of claims 4-10, characterized in that, The surface of the functional chip away from the packaging substrate includes multiple edges, and the multiple first external connections are arranged along a portion of the edges of the functional chip. The plurality of functional chips includes at least one stacked functional chip group; the stacked functional chip group includes a plurality of stacked functional chips, wherein in two adjacent functional chips in the stacking direction, the functional chip farther from the packaging substrate avoids the first external connection portion of the functional chip closer to the packaging substrate. The number of logic chips is multiple, and the multiple logic chips are respectively arranged along the edge of the stacked functional chip group near the first external connection portion.

12. The semiconductor packaging structure according to claim 11, characterized in that, The functional chip includes a first edge among its multiple edges, and multiple first external connections of the functional chip are disposed along the first edge. The first edges of two adjacent functional chips in the stacking direction are disposed opposite each other in a first direction, wherein the first direction is parallel to the packaging substrate. The plurality of logic chips include a first logic chip and a second logic chip, which are spaced apart along the first direction. The stacked functional chip group is located on the side of the first logic chip and the second logic chip away from the packaging substrate. The second external connection portion of the first logic chip and the second external connection portion of the second logic chip are respectively located on both sides of the stacked functional chip group in the first direction.

13. The semiconductor packaging structure according to any one of claims 1-12, characterized in that, The functional chip also includes a plurality of fifth external connections, which are exposed on the surface of the functional chip away from the packaging substrate. The packaging substrate further includes a plurality of sixth external connections, which are exposed on the first surface; The semiconductor packaging structure also includes multiple third connection lines, one end of which is connected to the fifth external connection and the other end of which is connected to the sixth external connection.

14. The semiconductor packaging structure according to claim 13, characterized in that, The surface of the functional chip away from the logic chip includes multiple edges, among which are adjacent first edges and second edges. The multiple first external connections are disposed along the first edges, and the multiple fifth external connections are disposed along the second edges. The second edges of two adjacent functional chips in the stacking direction are disposed opposite each other in a third direction, wherein the third direction is parallel to the packaging substrate and intersects with the second edges; The orthographic projections of the plurality of functional chips on the first surface are offset from the plurality of sixth external connections. The plurality of sixth external connections are arranged sequentially along the orthographic projections of the second edge of the functional chip on the first surface. The plurality of sixth external connections are divided into two groups, with the two groups of sixth external connections located on both sides of the plurality of functional chips in the third direction.

15. The semiconductor packaging structure according to any one of claims 1-14, characterized in that, The packaging substrate further includes a substrate body, multiple first traces, multiple first connection portions, and multiple eighth external connections; wherein, the multiple fourth external connections and the multiple first traces are all disposed on the surface of the substrate body facing the logic chip, the multiple first connection portions are disposed in the substrate body, the eighth external connections are disposed on the surface of the packaging substrate away from the logic chip, the fourth external connections are connected to one end of the first connection portion through the first traces, and the other end of the first connection portion is connected to the eighth external connection portion.

16. The semiconductor packaging structure according to any one of claims 1-3, characterized in that, The packaging substrate further includes a substrate body, a plurality of seventh external connections, a plurality of third traces, a plurality of first connections, and a plurality of eighth external connections. The plurality of seventh external connections and the plurality of third traces are exposed on the surface of the substrate body facing the logic chip, and the plurality of eighth external connections are exposed on the surface of the substrate body away from the logic chip. The first connections are disposed within the substrate body. The plurality of second external connections and the plurality of third external connections are exposed on the surface of the logic chip facing the substrate body; The semiconductor packaging structure further includes a fourth connecting line, one end of which is connected to the first external connection portion and the other end of which is connected to the seventh external connection portion; One end of the third wiring is connected to the seventh external connection, and the other end is connected to the second external connection; The third external connection is connected to one end of the first connection, and the other end of the first connection is connected to the eighth external connection. The first connecting portion serves as the fourth external connecting portion, with one end of the first connecting portion exposed on the surface of the substrate body facing the logic chip.

17. An electronic device, characterized in that, include: Semiconductor packaging structures and processors; The semiconductor packaging structure includes: a packaging substrate, a logic chip, and multiple functional chips. The packaging substrate includes a first surface, the logic chip is disposed on the first surface, and the multiple functional chips are disposed on the side of the logic chip opposite to the packaging substrate. The functional chip includes a plurality of first external connections, which are exposed on the surface of the functional chip away from the logic chip. The logic chip includes multiple second external connections, a signal acceleration module, and multiple third external connections. The second external connections are connected to the first external connections. The signal acceleration module is connected between a portion of the second external connections and a portion of the third external connections. The signal acceleration module is used to accelerate the signal transmitted by the second external connections and output it to the third external connections. The number of third external connections is less than the number of second external connections. The packaging substrate further includes a plurality of fourth external connections, the plurality of fourth external connections being exposed on the first surface, and the fourth external connections being connected to the third external connection; The processor is electrically connected to the fourth external connection portion of the packaging substrate.

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