Base, device and method for epitaxial growth of silicon wafer, and epitaxial silicon wafer

Abstract

A base, device and method for epitaxial growth of a silicon wafer, and an epitaxial silicon wafer. The base for epitaxial growth of a silicon wafer comprises a disc-shaped bearing part used for bearing the silicon wafer; and an annular periphery extending outwards in the radial direction from the disc-shaped bearing part, wherein the annular periphery is provided with a plurality of trench areas which are spaced apart, the trench areas are uniformly distributed in the circumferential direction of the annular periphery and are fan-shaped, and each trench area is provided with a plurality of pits arranged in an array.

Description

Substrates, apparatus and methods for epitaxial growth of silicon wafers, epitaxial silicon wafers

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410508018.6, filed in China on April 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a substrate, apparatus and method for epitaxial growth of silicon wafers, and an epitaxial silicon wafer. Background Technology

[0004] Growing a single-crystal thin film on a polished single-crystal wafer is called epitaxial silicon wafer. Compared to polished wafers, epitaxial silicon wafers have fewer surface defects, better crystallinity, and controllable resistivity, and are widely used in the fabrication of highly integrated integrated circuit (IC) devices and metal-oxide-semiconductor field-effect transistors (MOS). Epitaxial growth is generally performed on wafers using chemical vapor deposition (CVD). First, the wafer is transferred to a substrate in a reaction chamber. Then, the reaction chamber is heated to a preset temperature, and a cleaning gas (such as hydrogen) is introduced to remove the native oxides on the wafer surface. Next, a silicon source gas is introduced to continuously and uniformly grow an epitaxial layer on the front side of the wafer.

[0005] The fabrication of epitaxial layers on wafers mainly consists of two stages. The first stage involves self-cleaning of the reaction chamber by introducing hydrogen (H2) and etching gas (HCl). The second stage involves epitaxial layer growth by introducing hydrogen (H2), silicon source gas (SiHCl3 / H2), and dopant gas (B2H6 / H2). In the first stage, hydrogen acts as the main gas flow, carrying the etching gas (HCl) to react with byproducts deposited in the reaction chamber, thus cleaning the chamber. In the second stage, hydrogen reacts with the natural oxide layer on the wafer surface to obtain a clean epitaxial substrate. During the deposition stage, hydrogen acts as the main gas flow, carrying the film-forming gas and dopant gas to grow an epitaxial layer with controllable resistivity on the wafer surface.

[0006] With the continuous development of semiconductor manufacturing processes, the flatness requirements for epitaxial silicon wafers are becoming increasingly stringent. Poor flatness of epitaxial silicon wafers can lead to defocusing and may even affect the Chemical Mechanical Polishing (CMP) process, impacting product yield. When the flatness of an epitaxial silicon wafer is poor in a localized area, over-polishing or under-polishing can occur; over-polishing may lead to early device breakdown, while under-polishing may result in contact errors in the devices. Summary of the Invention

[0007] To address the aforementioned technical problems, this disclosure provides a substrate, apparatus, and method for epitaxial growth of silicon wafers, as well as an epitaxial silicon wafer, which can improve the flatness of the epitaxial silicon wafer.

[0008] To achieve the above objectives, the technical solution adopted in this disclosure is as follows:

[0009] A substrate for epitaxial growth of silicon wafers, comprising:

[0010] A disk-shaped support portion for supporting the silicon wafer;

[0011] Extending radially outward from the disc-shaped support portion, the annular periphery forms a plurality of spaced groove regions. The groove regions are evenly distributed along the circumference of the annular periphery and are fan-shaped. Each groove region is provided with a plurality of arrayed pits.

[0012] In some embodiments, the central angle of the sector containing the trench region is 40-60°.

[0013] In some embodiments, four groove regions are evenly distributed circumferentially along the annular periphery.

[0014] In some embodiments, the depth of the pit is 0.1 mm to 1 mm; and / or

[0015] The area of ​​the pit is 0.1 square millimeters to 0.4 square millimeters.

[0016] This disclosure also provides an apparatus for epitaxial growth of silicon wafers, comprising:

[0017] The base as described above;

[0018] A reaction chamber for accommodating the base, wherein the base divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber;

[0019] An inlet for supplying silicon source gas to the upper reaction chamber to grow an epitaxial layer on the silicon wafer;

[0020] An exhaust port used to discharge the reaction exhaust gas generated during epitaxial growth from the reaction chamber.

[0021] This disclosure also provides a method for epitaxial growth of a silicon wafer, the method being applied to the apparatus described above, the method comprising:

[0022] The silicon wafer is placed on the base such that the silicon wafer... <100> The crystal orientation is aligned with the central axis of the groove region at the annular periphery;

[0023] Silicon source gas is delivered to the upper reaction chamber via the air inlet to grow an epitaxial layer on the silicon wafer;

[0024] The flow rate of the silicon source gas flowing through the trench region is greater than the flow rate of the silicon source gas flowing through other regions of the annular periphery, so as to make the thickness of the epitaxial layer grown on the silicon wafer uniform;

[0025] The reaction exhaust gas generated during epitaxial growth is discharged from the reaction chamber through the exhaust port.

[0026] In some embodiments, the silicon wafer is placed on the substrate such that the silicon wafer... <100> Aligning the crystal orientation with the central axis of the groove region at the annular periphery includes:

[0027] Obtain the crystal orientation corresponding to the V-groove of the silicon wafer;

[0028] If the V-groove is on the silicon wafer <110> With the crystal orientation in mind, the silicon wafer is placed on the base such that the angle between the central axis of the V-groove and the central axis of the trench region is 45°.

[0029] In some embodiments, the silicon wafer is placed on the substrate such that the silicon wafer... <100> Aligning the crystal orientation with the central axis of the groove region at the annular periphery includes:

[0030] Obtain the crystal orientation corresponding to the V-groove of the silicon wafer;

[0031] If the V-groove is on the silicon wafer <100> With the crystal orientation in mind, the silicon wafer is placed on the base such that the angle between the central axis of the V-groove and the central axis of the trench region is 0°.

[0032] This disclosure also provides an epitaxial silicon wafer, fabricated using the epitaxial growth method for silicon wafers described above.

[0033] When the epitaxial layer thickness of the epitaxial silicon wafer is no greater than 6 micrometers, the maximum value of the ESFQR value of the frontal reference least squares range at the edge of the epitaxial silicon wafer is no greater than 57.1 nanometers.

[0034] In some embodiments, when the epitaxial layer thickness of the epitaxial silicon wafer is 3-4 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 23 to 33.9 nanometers; when the epitaxial layer thickness of the epitaxial silicon wafer is 4-6 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 37.4 to 57.1 nanometers.

[0035] The beneficial effects of this disclosure are:

[0036] In this embodiment, a trench region is formed on the annular periphery, and the trench region is provided with multiple pits. When epitaxial growth is performed and silicon source gas is introduced into the reaction chamber, the presence of pits allows the flow rate of silicon source gas flowing through the trench region to be greater than the flow rate of silicon source gas flowing through other areas of the annular periphery. Since the growth rate of different crystal directions of the silicon wafer is different, during epitaxial growth, the silicon wafer can be rotated at different angles according to the crystal direction corresponding to the V-groove, so that the crystal direction of the silicon wafer matches the position of the trench region. The crystal direction with a slower epitaxial growth rate is aligned with the trench region, thereby increasing the epitaxial growth rate in that crystal direction. This can compensate for the epitaxial growth rate of different crystal directions of the silicon wafer and improve the flatness of the epitaxial silicon wafer. Attached Figure Description

[0037] Figure 1 shows a schematic diagram of gas flow in the epitaxial reaction chamber;

[0038] Figures 2 and 3 show schematic diagrams of the crystal orientation of a silicon wafer;

[0039] Figure 4 shows a schematic diagram of the edge flatness of epitaxial silicon wafers prepared by existing technology;

[0040] Figure 5 shows a schematic diagram of the existing technology for fabricating epitaxial silicon wafers;

[0041] Figure 6 shows a schematic diagram of a substrate used for epitaxial growth of silicon wafers in the prior art;

[0042] Figures 7 and 8 are schematic diagrams of a substrate used for epitaxial growth of a silicon wafer according to an embodiment of the present disclosure;

[0043] Figure 9 shows a schematic diagram of the process for preparing epitaxial silicon wafers according to an embodiment of this disclosure;

[0044] Figure 10 shows the V-groove in an embodiment of this disclosure. <100> A schematic diagram of a silicon wafer with its crystal orientation placed on a substrate;

[0045] Figures 11 and 12 illustrate the V-groove in an embodiment of this disclosure. <110> A schematic diagram of a silicon wafer with its crystal orientation placed on a substrate;

[0046] Figure 13 shows a schematic diagram of the edge flatness of the epitaxial silicon wafer prepared according to an embodiment of the present disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure are within the scope of protection of this disclosure.

[0048] The flatness of epitaxial silicon wafers typically includes flatness metrics such as Edge Site Frontsurface referenced least sQuares / Range (ESFQR), Site Frontsurface referenced least sQuares / Range (SFQR), and Global Backsurface-referenced Ideal plane / Range (GBIR). Among these, ESFQR is used to measure the edge flatness of epitaxial silicon wafers.

[0049] Figure 1 illustrates the gas flow in the epitaxial reaction chamber, where the arrows indicate the gas flow direction. After the silicon wafer is transferred to the substrate 2 in the epitaxial reaction chamber, the substrate 2 rotates the silicon wafer at a constant speed. After the reaction chamber reaches the preset temperature, a cleaning gas (H2) is introduced, passing through the preheating ring 1 and the edge of the substrate 2 to reach the silicon wafer surface and remove the native oxides on the silicon wafer surface. Then, the main gas flow carries the film-forming gas and doping gas through the preheating ring 1 and the edge of the substrate 2 to reach the silicon wafer surface to grow an epitaxial layer with controllable resistivity.

[0050] Figures 2 and 3 illustrate the crystal orientation of a silicon wafer. As shown in Figure 2, if the three o'clock direction of the silicon wafer is the radial direction of 0° / 360° and is... <110> In terms of crystal orientation, the radial directions rotated clockwise by 90°, 180°, and 270° relative to the 0° / 360° radial direction are also considered part of the silicon wafer's orientation. <110> The crystal orientation, and the radial directions of 45°, 135°, 225°, and 315° clockwise rotation relative to the 0° / 360° radial direction, are the silicon wafer's... <100> Crystal orientation. That is to say, for this silicon wafer, there are four... <110> The crystal orientation corresponds to four radial directions spaced 90° apart along the circumference of the silicon wafer. <100> The crystal orientation also corresponds to the four radial directions spaced 90° apart along the circumference of the silicon wafer, while adjacent... <110> Crystal orientation and <100> The crystal orientation is spaced 45° apart along the circumference of the silicon wafer. As shown in Figure 3, V-grooves 4 are provided on the silicon wafer 3 to position the silicon wafer. The V-grooves 4 correspond to the crystal orientation of the silicon wafer. <100> The crystal orientation can also correspond to the silicon wafer. <110> Crystal orientation.

[0051] Figure 4 illustrates the edge flatness of an epitaxial silicon wafer fabricated using existing technology. Figure 4 shows the ESFQR results for a 300mm diameter silicon wafer at a position 1mm from the radial edge, using a conventional substrate for epitaxial growth of silicon wafers. In Figure 4, the horizontal axis represents the radial angle of the silicon wafer, and the vertical axis represents the ESFQR value (in nanometers) at the corresponding angular position. As shown in Figure 4, the radial directions of 0° / 360°, 90°, 180°, and 270° correspond to the edge flatness of the silicon wafer. <100> The crystal orientation regions, with radial directions of 45°, 135°, 225°, and 315° corresponding to the silicon wafer's... <110> In the crystal orientation region, it can be seen that the edge flatness is better at the radial positions of 0° / 360°, 90°, 180°, and 270°, while the edge flatness is worse at the radial positions of 45°, 135°, 225°, and 315°. (Epiaxial silicon wafer) <100> Crystal orientation and <110> The edge flatness quality varies significantly along different crystal orientations of a single-crystal silicon wafer. This is because the physical properties differ across different crystal orientations, and the epitaxial layer growth rates also differ between these orientations. <110> The epitaxial growth rate in the crystal direction is greater than that of the silicon wafer. <100> Epitaxial layer growth rate in the crystal direction.

[0052] To address the aforementioned issues, this disclosure provides a substrate, apparatus, and method for epitaxial growth of silicon wafers, as well as an epitaxial silicon wafer, which can improve the flatness of the epitaxial silicon wafer.

[0053] This disclosure provides a substrate for epitaxial growth of silicon wafers, comprising:

[0054] A disk-shaped support portion for supporting the silicon wafer;

[0055] Extending radially outward from the disc-shaped support portion, the annular periphery forms a plurality of spaced groove regions. The groove regions are evenly distributed along the circumference of the annular periphery and are fan-shaped. Each groove region is provided with a plurality of arrayed pits.

[0056] In this embodiment, a trench region is formed on the annular periphery, and the trench region is provided with multiple pits. When epitaxial growth is performed and silicon source gas is introduced into the reaction chamber, the presence of pits allows the flow rate of silicon source gas flowing through the trench region to be greater than the flow rate of silicon source gas flowing through other areas of the annular periphery. Since the growth rate of different crystal directions of the silicon wafer is different, during epitaxial growth, the silicon wafer can be rotated at different angles according to the crystal direction corresponding to the V-groove, so that the crystal direction of the silicon wafer matches the position of the trench region. The crystal direction with a slower epitaxial growth rate is aligned with the trench region, thereby increasing the epitaxial growth rate in that crystal direction. This can compensate for the epitaxial growth rate of different crystal directions of the silicon wafer and improve the flatness of the epitaxial silicon wafer.

[0057] Figure 5 shows a schematic diagram of the existing technology for preparing epitaxial silicon wafers, and Figure 6 shows a schematic diagram of the substrate used for epitaxial growth of silicon wafers in the existing technology. As shown in Figure 6, the existing substrate 2 includes a disk-shaped support portion 21 for supporting the silicon wafer and an annular periphery 22 extending radially outward from the disk-shaped support portion 21. As shown in Figure 5, in preparing epitaxial silicon wafers, a single-crystal silicon ingot is first prepared and then cut into segments. According to product requirements, V-grooves are processed in specific crystallization directions of the segments. Then, the segments are sliced, ground, polished, cleaned, and measured to obtain the substrate silicon wafer. The substrate silicon wafers are graded and sorted. If the substrate silicon wafer is judged to be qualified (OK), the qualified substrate silicon wafer is sorted to the corresponding carrier to start the epitaxial growth process; if the substrate silicon wafer is judged to be unqualified (NG), the substrate silicon wafer is reworked or scrapped.

[0058] Figures 7 and 8 are schematic diagrams of a base for epitaxial growth of silicon wafers according to an embodiment of the present disclosure. The base 5 includes a disc-shaped support portion 51 and an annular periphery 52 extending radially outward from the disc-shaped support portion 51. As shown in Figure 7, compared with the base shown in Figure 6, the embodiment of the present disclosure adds a trench region 6 to the annular periphery 52 of the base 5. The annular periphery 52 forms a plurality of spaced trench regions 6, which are uniformly distributed circumferentially along the annular periphery 52. ​​The trench regions 6 are fan-shaped, that is, the trench regions 6 are axisymmetric, and the central axis of the trench regions 6 is radially on the base 5. Each trench region 6 is provided with a plurality of arrayed pits 61. The pits 61 are recessed downward compared to other areas of the annular periphery 52. ​​During epitaxial growth, the setting of the pits 61 can increase the amount of gas flowing through the trench region 6 to the surface of the silicon wafer, thereby increasing the epitaxial layer growth rate of the silicon wafer region corresponding to the trench region 6.

[0059] In this embodiment, during epitaxial growth, the silicon wafer can be... <100> The crystal orientation is aligned with the trench region 6 of the substrate, i.e., the silicon wafer. <100> The crystal orientation is along the central axis of trench region 6, which allows for proper epitaxial growth of the silicon wafer. <100> The epitaxial layer growth rate is increased in the region where the crystal orientation is located, reducing the silicon wafer size. <110> Epitaxial growth rate in the crystal direction and <100> The difference between the growth rates of epitaxial layers along the crystal direction improves the growth of epitaxial silicon wafers. <110> Edge flatness at the crystal orientation.

[0060] The technical solution in this embodiment is not limited to silicon wafers. <100> The crystal orientation must be located along the central axis of trench region 6, as long as the silicon wafer's orientation is guaranteed. <100> The angle between the crystal orientation and the direction of the central axis of trench region 6 should not exceed 20°, i.e., the silicon wafer's... <100> The angle between the crystal orientation and the direction of the central axis of trench region 6 can be 0°, 5°, 10°, 15°, or 20°. Additionally, due to the silicon wafer... <110> The epitaxial layer growth rate is relatively high in the crystal direction, in order to reduce the silicon wafer thickness... <110> Epitaxial layer growth rate in crystal direction and <100> The difference between the epitaxial layer growth rates in the crystal direction, preferably, is between the annular periphery 52 and the silicon wafer. <110> The groove region 6 is not provided in the radial direction corresponding to the crystal direction.

[0061] In some embodiments, as shown in Figure 7, D1, D2, D3, or D4 represent the 45° direction of the base, while the gas injection port direction, exhaust port direction, silicon wafer inlet / outlet direction, or auxiliary gas main inlet direction of the epitaxial reaction chamber represent the 0° direction of the base. Four groove regions 6 can be uniformly arranged circumferentially around the annular periphery 52, corresponding to the gas injection port direction, exhaust port direction, silicon wafer inlet / outlet direction, and auxiliary gas main inlet direction of the epitaxial reaction chamber, respectively. As shown in Figures 2 and 3, the silicon wafer includes four... <100> The crystal orientation ensures that when the silicon wafer is placed on the base 5 in this embodiment for epitaxial growth, each silicon wafer can be aligned with the crystal orientation. <100> Each crystal orientation corresponds to a trench region 6, improving the efficiency of each... <100> The growth rate of the epitaxial layer in the crystal orientation effectively improves the growth rate of the epitaxial silicon wafer. <110> Edge flatness at the crystal orientation.

[0062] In some embodiments, as shown in FIG8, the central angle α corresponding to the sector where the trench region 6 is located can be 40°-60°, for example, it can be 40°, 45°, 50°, 55° or 60°, so that when the silicon wafer is placed... <100> After aligning the crystal orientation with the central axis of the trench region 6 of the substrate, the silicon wafer can be effectively improved. <100> Crystal orientation and edge flatness of the surrounding area.

[0063] In this embodiment, the recesses 61 can be arranged radially along the base 5, and the depth of the recesses 61 can be 0.1 mm to 1 mm, such as 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm or 1 mm. When the depth of the recesses 61 adopts the above dimensions, the amount of silicon source gas flowing through the trench region 6 to the surface of the silicon wafer during epitaxial growth can be effectively increased.

[0064] The area of ​​the recess 61 can be 0.1 square millimeters to 0.4 square millimeters, for example, 0.1 square millimeters, 0.2 square millimeters, 0.3 square millimeters or 0.4 square millimeters. When the area of ​​the recess 61 adopts the above-mentioned size, the amount of silicon source gas flowing through the trench region 6 to the surface of the silicon wafer during epitaxial growth can be effectively increased.

[0065] In this embodiment, the shape of the orthographic projection of the pit 61 on the horizontal plane can be a regular shape such as a rectangle, a circle, or a parallelogram, or it can be an irregular shape.

[0066] In some embodiments, the density of the pits gradually decreases along the direction from the center of the trench region to the edge of the trench region, so that during epitaxial growth, when the silicon wafer is... <100> After aligning the crystal orientation with the central axis of the trench region 6 of the substrate, the silicon wafer can be... <100> Crystal orientation to <110> The rate of decrease in the crystal direction gradually decreases, thereby making the growth rate of the silicon wafer more uniform throughout the entire circumference and the thickness of the epitaxial layer grown on the silicon wafer more uniform, thus enabling the acquisition of epitaxial silicon wafers with better flatness.

[0067] This disclosure also provides an apparatus for epitaxial growth of silicon wafers, comprising:

[0068] The base as described above;

[0069] A reaction chamber for accommodating the base, wherein the base divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber;

[0070] An inlet for supplying silicon source gas to the upper reaction chamber to grow an epitaxial layer on the silicon wafer;

[0071] An exhaust port used to discharge the reaction exhaust gas generated during epitaxial growth from the reaction chamber.

[0072] In addition, similar to existing devices for epitaxial growth of silicon wafers, this device may also include: a base support frame, an upper quartz bell jar and a lower quartz bell jar that together enclose the reaction chamber, multiple heating bulbs, mounting components, etc., and the radial edge of the base also has a small gap with the adjacent components so that the base can rotate around its own central axis at a certain speed by the drive of the base support frame, which will not be described in detail here.

[0073] This disclosure also provides a method for epitaxial growth of a silicon wafer, the method being applied to the apparatus described above, the method comprising:

[0074] The silicon wafer is placed on the base such that the silicon wafer... <100> The crystal orientation is aligned with the central axis of the groove region at the annular periphery;

[0075] Silicon source gas is delivered to the upper reaction chamber via the air inlet to grow an epitaxial layer on the silicon wafer;

[0076] The flow rate of the silicon source gas flowing through the trench region is greater than the flow rate of the silicon source gas flowing through other regions of the annular periphery, so as to make the thickness of the epitaxial layer grown on the silicon wafer uniform;

[0077] The reaction exhaust gas generated during epitaxial growth is discharged from the reaction chamber through the exhaust port.

[0078] In this embodiment, during epitaxial growth, the silicon wafer can be rotated at different angles according to the crystal direction corresponding to the V-groove of the silicon wafer, so that the crystal direction of the silicon wafer matches the position of the trench region, and the crystal direction with a slower epitaxial layer growth rate is aligned with the trench region, thereby increasing the epitaxial layer growth rate in this crystal direction. In this way, the epitaxial layer growth rates in different crystal directions of the silicon wafer can be compensated, and the flatness of the epitaxial silicon wafer can be improved.

[0079] FIG. 9 shows a schematic flow chart of preparing an epitaxial silicon wafer according to an embodiment of the present disclosure. When preparing an epitaxial silicon wafer, a single-crystal silicon ingot is first prepared, and the single-crystal silicon ingot is segmented. According to product requirements, V-grooves are processed in a specific crystal direction of the crystal segment. Then, the crystal segment is sliced, polished, cleaned, and measured to obtain a substrate silicon wafer. The substrate silicon wafer is graded and sorted. If the substrate silicon wafer is judged to be qualified (OK), the qualified substrate silicon wafers are sorted into corresponding carriers, and the epitaxial growth process is started; if the substrate silicon wafer is judged to be unqualified (NG), the substrate silicon wafer is reworked or scrapped.

[0080] As shown in FIG. 9, the method for preparing an epitaxial silicon wafer according to an embodiment of the present disclosure further includes:

[0081] Step 101: Set the sorting rules for the substrate silicon wafers according to the V-groove direction;

[0082] The V-groove of the silicon wafer is used to determine the crystal direction of the silicon wafer. According to different product requirements, the V-grooves of some silicon wafers are in the <110> crystal direction, and the V-grooves of some silicon wafers are in the <100> crystal direction. In this embodiment, it is necessary to obtain the crystal direction corresponding to the V-groove of the silicon wafer.

[0083] Step 102: Rotate at different angles when sorting qualified substrate silicon wafers with different V-groove directions into corresponding carriers;

[0084] In the related art, when placing the silicon wafer on the base, the V-groove of the silicon wafer generally aligns with the 0° direction of the base, that is, the gas injection port direction, the exhaust port direction, the silicon wafer inlet and outlet direction, or the main auxiliary gas inlet direction of the epitaxial reaction chamber.

[0085] Step 103: Rotate the substrate silicon wafer with the V-groove in the <110> crystal direction by 45°;

[0086] If the V-groove is on the silicon wafer <110> In terms of crystal orientation, before entering the epitaxial reaction chamber, the V-groove is... <110> The substrate silicon wafer is rotated 45° in the crystal orientation so that, after the silicon wafer is placed on the base, the angle between the central axis of the V-groove and the central axis of the trench region is 45°. This allows the silicon wafer to... <100> The crystal orientation is aligned with the trench region 6 of the substrate, i.e., the silicon wafer. <100> The crystal orientation is along the central axis of trench region 6, which allows the silicon wafer to... <100> The epitaxial layer growth rate is increased in the region where the crystal orientation is located, reducing the silicon wafer size. <110> Epitaxial layer growth rate in crystal direction and <100> The difference between the growth rates of epitaxial layers along the crystal direction improves the growth of epitaxial silicon wafers. <110> Edge flatness at the crystal orientation position.

[0087] Step 104: Place the V-groove in <100> The substrate silicon wafer is rotated 0° in the crystal orientation.

[0088] If the V-groove is on the silicon wafer <100> In terms of crystal orientation, before entering the epitaxial reaction chamber, the V-groove is... <100> The substrate silicon wafer is rotated 0° (i.e., not rotated) in the crystal orientation, so that the silicon wafer is placed on the base, and the angle between the central axis of the V-groove and the central axis of the trench region is 0°. This allows the silicon wafer to... <100> The crystal orientation is aligned with the trench region 6 of the substrate, i.e., the silicon wafer. <100> The crystal orientation is along the central axis of trench region 6, which allows the silicon wafer to... <100> The epitaxial layer growth rate is increased in the region where the crystal orientation is located, reducing the silicon wafer size. <110> Epitaxial layer growth rate in crystal direction and <100> The difference between the growth rates of epitaxial layers along the crystal direction improves the growth of epitaxial silicon wafers. <110> Edge flatness at the crystal orientation position.

[0089] Figure 10 shows the V-groove in an embodiment of this disclosure. <100> A schematic diagram of a silicon wafer 3 with its crystal orientation placed on a substrate; as shown in Figure 2, the V-groove 4 of the silicon wafer... <100> Regarding the crystal orientation, the regions of the silicon wafer spaced 45° and 135° from the V-groove 4 constitute the silicon wafer's... <110> The crystal orientation of the silicon wafer is such that the regions spaced 90° and 180° apart from the V-groove 4 are the silicon wafer's... <100> Crystal orientation.

[0090] As shown in Figure 7, a trench region 6 exists at the edge of the substrate in the 0° direction. Compared to the 45° direction of the substrate, the gas flow rate in this trench region 6 in the 0° direction increases during epitaxial growth. This increased gas flow rate accelerates the epitaxial layer growth rate. Therefore, to ensure that the growth rate is the same in different regions of the silicon wafer during epitaxial growth, it is necessary to ensure that the silicon wafer... <100> The crystal orientation matches the 0° orientation of the substrate (the direction in which the trench region of the substrate is located), making the silicon wafer... <110> The crystal orientation matches the 45° orientation of the substrate, ensuring proper alignment of the silicon wafer during epitaxial growth. <100> The increased growth rate of the epitaxial layer along the crystal direction allows the epitaxial layer to grow on the silicon wafer. <100> Crystal orientation and <110> The thickness is the same along the crystal direction.

[0091] As shown in Figure 10, since the orientation of the base is fixed during installation in the epitaxial reaction chamber, the 0° direction of the groove region 6 on the edge of the base is the direction of the gas injection port, exhaust port, silicon wafer inlet / outlet, or auxiliary gas main inlet of the epitaxial reaction chamber. The V-groove is placed in... <100> The silicon wafer is rotated 0° (no rotation) in the crystal orientation, thus allowing the silicon wafer to... <100> Matching the crystal orientation with the 0° orientation of the substrate (the orientation corresponding to the substrate trench region, where gas flow on the silicon wafer surface increases) enables the silicon wafer to... <110> The crystal orientation matches the 45° orientation of the substrate, compensating for the difference in epitaxial layer growth rate caused by different crystal orientations of the silicon wafer, and improving the edge flatness of the silicon epitaxial wafer.

[0092] Figures 11 and 12 illustrate the V-groove in an embodiment of this disclosure. <110> A schematic diagram of a silicon wafer with its crystal orientation placed on a substrate. As shown in Figure 11, the V-groove 4 of the silicon wafer 3 is located on the silicon wafer. <110> Regarding the crystal orientation, the regions of the silicon wafer spaced 45° and 135° from the V-groove 4 constitute the silicon wafer's... <100> The crystal orientation of the silicon wafer is such that the regions spaced 90° and 180° apart from the V-groove 4 are the silicon wafer's... <110> Crystal orientation.

[0093] As shown in Figure 7, a trench region 6 exists at the edge of the substrate in the 0° direction. Compared to the 45° direction of the substrate, the gas flow rate in this trench region 6 in the 0° direction increases during epitaxial growth. This increased gas flow rate accelerates the epitaxial layer growth rate. Therefore, to ensure that the growth rate is the same in different regions of the silicon wafer during epitaxial growth, it is necessary to ensure that the silicon wafer... <100> The crystal orientation matches the 0° orientation of the substrate (the direction in which the trench region of the substrate is located), making the silicon wafer... <110> The crystal orientation matches the 45° orientation of the substrate, ensuring proper alignment of the silicon wafer during epitaxial growth. <100> The increased growth rate of the epitaxial layer along the crystal direction allows the epitaxial layer to grow on the silicon wafer. <100> Crystal orientation and <110> The thickness is the same along the crystal direction.

[0094] As shown in Figure 12, since the orientation of the base is fixed during installation in the epitaxial reaction chamber, the 0° direction of the groove region 6 on the edge of the base is the direction of the gas injection port, exhaust port, silicon wafer inlet / outlet, or auxiliary gas main inlet of the epitaxial reaction chamber. The V-groove is placed in... <110> Rotating the silicon wafer 45° in the crystal orientation allows the silicon wafer to... <100> Matching the crystal orientation with the 0° orientation of the substrate (the orientation corresponding to the substrate trench region, where gas flow on the silicon wafer surface increases) enables the silicon wafer to... <110> The crystal orientation matches the 45° orientation of the substrate, compensating for the difference in epitaxial layer growth rate caused by different crystal orientations of the silicon wafer, and improving the edge flatness of the silicon epitaxial wafer.

[0095] This disclosure also provides an epitaxial silicon wafer, fabricated using the epitaxial growth method for silicon wafers described above.

[0096] When the epitaxial layer thickness of the epitaxial silicon wafer is no greater than 6 micrometers, the maximum value of the ESFQR value of the frontal reference least squares range at the edge of the epitaxial silicon wafer is no greater than 57.1 nanometers.

[0097] Figure 13 shows a schematic diagram of the edge flatness of the epitaxial silicon wafer prepared according to the embodiments of this disclosure. In Figure 13, the horizontal axis represents the radial angle of the silicon wafer, and the vertical axis represents the ESFQR value (in nanometers) of the silicon wafer at the corresponding angular position. It can be seen that the phenomenon of periodic fluctuation of the edge flatness of the epitaxial silicon wafer at 45° intervals is improved, the edge flatness quality of the epitaxial silicon wafer is improved, and the ESFQR value of the epitaxial silicon wafer can be reduced by 14 nanometers, effectively improving the quality and yield of the epitaxial silicon wafer.

[0098] In some embodiments, the ESFQR value of the epitaxial silicon wafer is inversely proportional to both the depth and area of ​​the pits. With other substrate parameters remaining constant, increasing the pit depth increases the amount of gas participating in the film-forming reaction in the trench region during epitaxial growth, resulting in better compensation for differences in epitaxial layer growth rates across different crystal orientations of the silicon wafer, a smaller ESFQR value, and a more significant improvement in the edge flatness quality of the prepared epitaxial silicon wafer. Conversely, with other substrate parameters remaining constant, increasing the pit area increases the amount of gas participating in the film-forming reaction in the trench region during epitaxial growth, resulting in better compensation for differences in epitaxial layer growth rates across different crystal orientations of the silicon wafer, a smaller ESFQR value, and a more significant improvement in the edge flatness quality of the prepared epitaxial silicon wafer.

[0099] In some embodiments, when the epitaxial layer thickness of the epitaxial silicon wafer is 3-4 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 23 nanometers to 33.9 nanometers; when the epitaxial layer thickness of the epitaxial silicon wafer is 4-6 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 37.4 nanometers to 57.1 nanometers.

[0100] In specific embodiment 1, a V-groove is selected. <100> For a silicon wafer with a crystal orientation, the central angle of the sector corresponding to the trench region of the base is 40°-50°, for example, 45°; the depth of the pit is 0.1 mm-1 mm, for example, 0.48 mm-0.52 mm, and further, 0.5 mm; the area of ​​the pit is 0.1 square millimeter-0.4 square millimeter, for example, 0.18 square millimeter-0.22 square millimeter, and further, 0.2 square millimeter; when the silicon wafer is placed on the base, the angle between the central axis of the V-groove and the central axis of the trench region is 0°, so that the silicon wafer... <100> Epitaxial growth is performed by aligning the crystal orientation with the trench region of the substrate. During epitaxial growth, the flow rate of the carrier gas hydrogen (H2) is 80,000 sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6,000 sccm, the film-forming reaction temperature is 1100℃, and an epitaxial layer with a thickness of 3.3-3.5 micrometers is grown. For example, growing an epitaxial layer with a thickness of 3.5 micrometers results in an ESFQR value of 29.3 ± 4.6 nanometers for the obtained epitaxial silicon wafer. Compared with conventional techniques, this reduces the ESFQR value of the epitaxial silicon wafer by 8.6 nanometers, thus improving the quality of the epitaxial silicon wafer. This is because the pits created in the trench region increase the flow rate of the process gas in the trench region, allowing the silicon wafer to... <100> The increased growth rate of the epitaxial layer along the crystal direction compensates for the slow growth process of the epitaxial layer. <110> Crystal orientation and <100> Differences in growth rate along crystal orientation.

[0101] In specific embodiment 2, a V-groove is selected. <100> For a silicon wafer with a crystal orientation, the central angle of the sector corresponding to the trench region of the base is 40°-50°, for example, 45°; the depth of the pit is 0.78 mm-0.82 mm, for example, 0.8 mm; the area of ​​the pit is 0.38 square millimeters-0.42 square millimeters, for example, 0.4 square millimeters; when the silicon wafer is placed on the base, the angle between the central axis of the V-groove and the central axis of the trench region is 0°, so that the silicon wafer... <100> Epitaxial growth is performed by aligning the crystal orientation with the trench region of the substrate. During epitaxial growth, the flow rate of the carrier gas hydrogen (H2) is 80,000 sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6,000 sccm, the film-forming reaction temperature is 1100℃, and an epitaxial layer with a thickness of 3.3-3.5 micrometers is grown. For example, growing an epitaxial layer with a thickness of 3.5 micrometers results in an ESFQR value of 26.8 ± 3.8 nanometers for the obtained epitaxial silicon wafer. Compared with conventional techniques, this reduces the ESFQR value of the epitaxial silicon wafer by 11.1 nanometers, thus improving the quality of the epitaxial silicon wafer. This is because the pits created in the trench region increase the flow rate of the process gas in the trench region, allowing the silicon wafer to... <100> The increased growth rate of the epitaxial layer along the crystal direction compensates for the slow growth process of the epitaxial layer. <110> Crystal orientation and <100> The growth rate varies along the crystal orientation. Furthermore, compared to Specific Example 1, the increased depth and area of ​​the pits in the trench region lead to an increased amount of gas participating in the film-forming reaction during epitaxial growth. This results in better compensation for the difference in epitaxial layer growth rate across different crystal orientations of the silicon wafer, a smaller ESFQR value, and a more significant improvement in the edge flatness quality of the prepared epitaxial silicon wafer.

[0102] In specific embodiment 3, a V-groove is selected. <100> For a silicon wafer with a crystal orientation, the central angle of the sector corresponding to the trench region of the base is 40°-50°, for example, 45°; the depth of the pit is 0.1 mm-1 mm, for example, 0.48 mm-0.52 mm, and further, 0.5 mm; the area of ​​the pit is 0.1 square millimeter-0.4 square millimeter, for example, 0.18 square millimeter-0.22 square millimeter, and further, 0.2 square millimeter; when the silicon wafer is placed on the base, the angle between the central axis of the V-groove and the central axis of the trench region is 0°, so that the silicon wafer... <100> Epitaxial growth is performed by aligning the crystal orientation with the trench region of the substrate. During epitaxial growth, the flow rate of the carrier gas hydrogen (H2) is 80,000 sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6,000 sccm, the film-forming reaction temperature is 1100℃, and an epitaxial layer with a thickness of 4.8-5 micrometers is grown. For example, growing a 5-micrometer thick epitaxial layer results in an ESFQR value of 48.4 ± 8.7 nanometers for the obtained epitaxial silicon wafer. Compared with conventional techniques, this reduces the ESFQR value of the epitaxial silicon wafer, thus improving its quality. This is because the pits created in the trench region increase the flow rate of the process gas in the trench region, allowing the silicon wafer to... <100> The increased growth rate of the epitaxial layer along the crystal direction compensates for the slow growth process of the epitaxial layer. <110> Crystal orientation and <100> Differences in growth rate along crystal orientation.

[0103] In specific embodiment 4, a V-groove is selected. <100> For a silicon wafer with a crystal orientation, the central angle of the sector corresponding to the trench region of the base is 40°-50°, for example, 45°; the depth of the pit is 0.78 mm-0.82 mm, for example, 0.8 mm; the area of ​​the pit is 0.38 square millimeters-0.42 square millimeters, for example, 0.4 square millimeters; when the silicon wafer is placed on the base, the angle between the central axis of the V-groove and the central axis of the trench region is 0°, so that the silicon wafer... <100> Epitaxial growth is performed by aligning the crystal orientation with the trench region of the substrate. During epitaxial growth, the flow rate of the carrier gas hydrogen (H2) is 80,000 sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6,000 sccm, the film-forming reaction temperature is 1100℃, and an epitaxial layer with a thickness of 4.8-5 micrometers is grown. For example, growing a 5-micrometer thick epitaxial layer results in an ESFQR value of 43.8 ± 6.4 nanometers for the obtained epitaxial silicon wafer. Compared with conventional techniques, this reduces the ESFQR value of the epitaxial silicon wafer, thus improving its quality. This is because the pits created in the trench region increase the flow rate of the process gas in the trench region, allowing the silicon wafer to... <100> The increased growth rate of the epitaxial layer along the crystal direction compensates for the slow growth process of the epitaxial layer. <110> Crystal orientation and <100> The growth rate varies depending on the crystal orientation. Furthermore, compared to Specific Example 3, the increased depth and area of ​​the pits in the trench region lead to an increased amount of gas participating in the film-forming reaction during epitaxial growth. This results in better compensation for the difference in epitaxial layer growth rate across different crystal orientations of the silicon wafer, a smaller ESFQR value, and a more significant improvement in the edge flatness quality of the prepared epitaxial silicon wafer.

[0104] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0105] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0106] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0107] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0108] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A substrate for epitaxial growth of silicon wafers, comprising: A disk-shaped support portion for supporting the silicon wafer; Extending radially outward from the disc-shaped support portion, the annular periphery forms a plurality of spaced groove regions. The groove regions are evenly distributed along the circumference of the annular periphery and are fan-shaped. Each groove region is provided with a plurality of arrayed pits.

2. The base according to claim 1, wherein, The central angle of the sector containing the groove region is 40°-60°.

3. The base according to claim 1, wherein, Four groove regions are evenly distributed along the circumference of the annular perimeter.

4. The base according to claim 1, wherein, The depth of the pit is 0.1 mm to 1 mm; and / or The area of ​​the pit is 0.1 square millimeters to 0.4 square millimeters.

5. An apparatus for epitaxial growth of silicon wafers, comprising: The base as described in any one of claims 1 to 4; A reaction chamber for accommodating the base, wherein the base divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; An inlet for supplying silicon source gas to the upper reaction chamber to grow an epitaxial layer on the silicon wafer; An exhaust port used to discharge the reaction exhaust gas generated during epitaxial growth from the reaction chamber.

6. A method for epitaxial growth of a silicon wafer, the method being applied to the apparatus of claim 5, the method comprising: The silicon wafer is placed on the base such that the silicon wafer... <100> The crystal orientation is aligned with the central axis of the groove region at the annular periphery; Silicon source gas is delivered to the upper reaction chamber via the air inlet to grow an epitaxial layer on the silicon wafer; The flow rate of the silicon source gas flowing through the trench region is greater than the flow rate of the silicon source gas flowing through other regions of the annular periphery, so as to make the thickness of the epitaxial layer grown on the silicon wafer uniform; The reaction exhaust gas generated during epitaxial growth is discharged from the reaction chamber through the exhaust port.

7. The method according to claim 6, wherein, The silicon wafer is placed on the base such that the silicon wafer... <100> Aligning the crystal orientation with the central axis of the groove region at the annular periphery includes: Obtain the crystal orientation corresponding to the V-groove of the silicon wafer; If the V-groove is on the silicon wafer <110> With the crystal orientation in mind, the silicon wafer is placed on the base such that the angle between the central axis of the V-groove and the central axis of the trench region is 45°.

8. The method according to claim 6, wherein, The silicon wafer is placed on the base such that the silicon wafer... <100> Aligning the crystal orientation with the central axis of the groove region at the annular periphery includes: Obtain the crystal orientation corresponding to the V-groove of the silicon wafer; If the V-groove is on the silicon wafer <100> With the crystal orientation in mind, the silicon wafer is placed on the base such that the angle between the central axis of the V-groove and the central axis of the trench region is 0°.

9. An epitaxial silicon wafer, fabricated using the epitaxial growth method for silicon wafers as described in any one of claims 6-8. When the epitaxial layer thickness of the epitaxial silicon wafer is no greater than 6 micrometers, the maximum value of the ESFQR value of the frontal reference least squares range at the edge of the epitaxial silicon wafer is no greater than 57.1 nanometers.

10. The epitaxial silicon wafer according to claim 9, wherein when the epitaxial layer thickness of the epitaxial silicon wafer is 3 micrometers to 4 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 23 nanometers to 33.9 nanometers; and when the epitaxial layer thickness of the epitaxial silicon wafer is 4 micrometers to 6 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 37.4 nanometers to 57.1 nanometers.

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