Encoding method, decoding method, communication apparatus, storage medium, and program product

Abstract

Provided are an encoding method, a decoding method, a communication apparatus, a storage medium, and a program product. The encoding method comprises: acquiring a first bit sequence; determining a rate matching mode, and determining a first frozen bit index set on the basis of the rate matching mode; determining a second frozen bit index set on the basis of a fast decoding condition; determining a third frozen bit index set on the basis of the first frozen bit index set and the second frozen bit index set; performing polar code encoding on the first bit sequence on the basis of the third frozen bit index set, to obtain a second bit sequence; and performing rate matching on the second bit sequence on the basis of the rate matching mode, to obtain a third bit sequence.

Description

Encoding methods, decoding methods, communication devices, storage media and software products

[0001] This disclosure claims priority to Chinese patent application No. 202410520714.9, filed on April 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, a storage medium, and a program product. Background Technology

[0003] Polar coding is a channel coding technique that aims to divide the original channel into multiple polarized channels by polarization. This results in some polarized channels having high reliability, while others have low reliability. Communication devices then transmit actual information through the more reliable polarized channels to improve data transmission reliability.

[0004] Rate matching is a technique that adjusts the data rate (also known as bitrate) to balance the difference between encoded data and the actual available transmission resources, in order to ensure that the data is transmitted normally. Summary of the Invention

[0005] On one hand, this disclosure provides an encoding method applied to a first node. The encoding method includes:

[0006] Obtain the first bit sequence;

[0007] Determine the rate matching method, and based on the rate matching method, determine the first set of frozen bit indices;

[0008] Based on the fast decoding conditions, determine the second set of frozen bit indices;

[0009] Based on the first frozen bit index set and the second frozen bit index set, a third frozen bit index set is determined;

[0010] Based on the third frozen bit index set, the first bit sequence is polar-coded to obtain the second bit sequence;

[0011] Based on the rate matching method, the second bit sequence is rate matched to obtain the third bit sequence.

[0012] On the other hand, embodiments of this disclosure provide a decoding method applied to a second node. The decoding method includes:

[0013] Receive the third bit sequence from the first node;

[0014] Determine the rate matching method, and perform rate recovery on the third bit sequence based on the rate matching method to obtain the second bit sequence;

[0015] Based on the rate matching method, determine the first set of frozen bit indices;

[0016] Based on the fast decoding conditions, determine the second set of frozen bit indices;

[0017] Based on the first frozen bit index set and the second frozen bit index set, a third frozen bit index set is determined;

[0018] Based on the third frozen bit index set, the second bit sequence is polar-coded to obtain the first bit sequence.

[0019] In another aspect, embodiments of this disclosure provide a first node. The first node includes: a processing unit and a communication unit;

[0020] The communication unit is used to acquire the first bit sequence;

[0021] The processing unit is used to determine the rate matching method and, based on the rate matching method, determine the first frozen bit index set.

[0022] The processing unit is also used to determine the second set of frozen bit indices based on the fast decoding conditions;

[0023] The processing unit is further configured to determine a third frozen bit index set based on the first frozen bit index set and the second frozen bit index set;

[0024] The processing unit is further configured to perform polar code encoding on the first bit sequence based on the third frozen bit index set to obtain a second bit sequence;

[0025] The processing unit is further configured to perform rate matching on the second bit sequence based on the rate matching method to obtain a third bit sequence.

[0026] In another aspect, embodiments of this disclosure provide a second node. This second node includes: a processing unit and a communication unit;

[0027] The communication unit is used to receive a third bit sequence from the first node;

[0028] The processing unit is used to determine the rate matching method, and perform rate recovery on the third bit sequence based on the rate matching method to obtain the second bit sequence;

[0029] The processing unit is further configured to determine a first set of frozen bit indices based on the rate matching method;

[0030] The processing unit is also used to determine the second set of frozen bit indices based on the fast decoding conditions;

[0031] The processing unit is further configured to determine a third frozen bit index set based on the first frozen bit index set and the second frozen bit index set;

[0032] The processing unit is further configured to perform polar code decoding on the second bit sequence based on the third frozen bit index set to obtain the first bit sequence.

[0033] In another aspect, embodiments of this disclosure provide a communication device. The communication device includes: a memory and a processor; the memory and the processor are coupled; the memory is used to store a computer program; the processor executes the computer program to implement the method described in any of the above aspects.

[0034] In another aspect, embodiments of this disclosure provide a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the methods described in any of the above aspects.

[0035] In another aspect, embodiments of this disclosure provide a computer program product including computer program instructions that, when executed by a processor, implement the methods described in any of the above aspects. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings.

[0037] Figure 1 is an architecture diagram of a communication system according to some embodiments.

[0038] Figure 2 is a flowchart of an encoding method according to some embodiments.

[0039] Figure 3 is a performance simulation diagram according to some embodiments.

[0040] Figure 4 is another performance simulation diagram according to some embodiments.

[0041] Figure 5 is a flowchart of another encoding method according to some embodiments.

[0042] Figure 6 is a flowchart of another encoding method according to some embodiments.

[0043] Figure 7 is a flowchart of another encoding method according to some embodiments.

[0044] Figure 8 is a flowchart of a decoding method according to some embodiments.

[0045] Figure 9 is a flowchart of another decoding method according to some embodiments.

[0046] Figure 10 is a flowchart of another decoding method according to some embodiments.

[0047] Figure 11 is a flowchart of another decoding method according to some embodiments.

[0048] Figure 12 is a structural diagram of a first node according to some embodiments.

[0049] Figure 13 is a structural diagram of a second node according to some embodiments.

[0050] Figure 14 is a structural diagram of a communication device according to some embodiments. Detailed Implementation

[0051] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0052] It should be noted that in this disclosure, expressions such as "exemplarily" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of expressions such as "exemplarily" or "for example" is intended to present the relevant concepts in a detailed manner.

[0053] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0054] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can mean: only A, A and B, and only B. Furthermore, "at least one" means one or more, and "more than one" means two or more.

[0055] Polar coding is a channel coding technique that aims to divide the original channel into multiple polarized channels by polarization. This results in some polarized channels having high reliability, while others have low reliability. Communication devices then transmit actual information through the more reliable polarized channels to improve data transmission reliability.

[0056] Successive cancellation (SC) is a low-complexity decoding algorithm in polar code technology. It achieves decoding by decoding bit by bit in a serial manner. However, this serial method will result in a long decoding time and high latency, which will affect the throughput performance of the decoder.

[0057] The SC algorithm is essentially a depth-first traversal of a binary tree composed of polar code sequences. A polar code sequence of length N serves as the root node, and two subtrees of length N are partitioned from this sequence. The two subcodes correspond to the two leaf nodes of the next level, and so on. Therefore, decoding a polar code sequence can be achieved by decoding multiple subcodes. The fast successive cancellation (Fast-SC) algorithm is used to reduce decoding latency by fast decoding of specific types of subcodes, thereby improving the decoder's throughput. Specific types of subcodes include: Rate-0 codes (subcodes with a code rate of 0), REP codes (repeated codes), REP-2 codes, parity-checked repetition (PCR) codes, repeated parity check (RPC) codes, single parity check (SPC) codes, SPC-2 codes, and Rate-1 codes. Furthermore, some types of subcodes still cannot be decoded quickly.

[0058] Rate matching is a technique for adjusting the data rate (also known as bit rate) to balance the difference between encoded data and the actual available transmission resources, ensuring proper data transmission. Rate matching adjusts the length of a bit sequence by padding it with extra bits or removing certain bits to match the actual transmission capacity of the communication device.

[0059] Currently, some technologies cannot achieve rate matching while satisfying the requirements of fast polar code technology. For example, one technology involves the encoder performing polar code encoding and rate matching normally, but after the decoder performs rate recovery, the channel corresponding to the recovered bits is used as a channel with a capacity of 0 or a channel with a capacity of 1. This results in sub-codes in the bit sequence that cannot be decoded quickly.

[0060] Currently, there are contradictions between polar code technology and rate matching technology in the processing of data bits (such as the restrictions on the bit positions of actual information and the length of transmitted data by polar codes), which makes it impossible for communication devices to perform rate matching while meeting the requirements of fast polar code technology.

[0061] Therefore, in the technical solution provided in this disclosure, the first node can obtain the first bit sequence to be transmitted, determine the rate matching method to be performed subsequently, and determine the first frozen bit index set based on the rate matching method to ensure that rate matching does not affect the construction of the fast polar code. Then, the first node can determine the second frozen bit index set based on the fast decoding conditions to ensure that the subsequently constructed polar code can achieve fast decoding. Thus, the first node can simultaneously determine the third frozen bit index set based on both the first and second frozen bit index sets, and encode the first bit sequence using polar code based on the third frozen bit index set to obtain the second bit sequence. Then, the first node can perform rate matching on the second bit sequence according to the previously determined rate matching method to obtain the third bit sequence. In this way, the third bit sequence constructed by the first node can satisfy fast decoding and can also achieve free rate adjustment through rate matching, completing the rate matching required by the communication system while meeting the encoding requirements of the fast polar code technology itself.

[0062] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0063] The network architecture of the mobile communication network (including but not limited to 3G, 4G, 5G, and future mobile communication networks) in this disclosure embodiment may include at least a first communication node and a second communication node. It should be understood that, in this example, in the downlink, the first communication node may be a network-side device (e.g., including but not limited to a base station), and the second communication node may be a terminal-side device (e.g., including but not limited to a terminal). Of course, in the uplink, the first communication node may also be a terminal-side device, and the second communication node may also be a network-side device. In device-to-device communication between the two communication nodes, both the first and second communication nodes can be a base station or a terminal. The first and second communication nodes may be referred to as the first node and the second node, respectively.

[0064] For example, taking a first communication node as a terminal and a second communication node as a base station, Figure 1 is an architecture diagram of a communication system according to some embodiments. The communication system includes a terminal 101 and a base station 102. There can be one or more terminals 101 and base stations 102, and the embodiments of this disclosure do not limit the number.

[0065] Base station 102 is used to acquire the first bit sequence and encode the first bit sequence using polar code to obtain the second bit sequence.

[0066] The first bit sequence includes the information bits to be transmitted.

[0067] Base station 102 is also used to perform rate matching on the second bit sequence to obtain the third bit sequence.

[0068] For example, the rate matching method includes at least one of repetition, puncturing, and truncation. Base station 102 can determine the length of the third bit sequence according to the target rate to be achieved, and adjust the length of the second bit sequence through operations such as repetition, puncturing, and truncation to obtain the final third bit sequence.

[0069] Base station 102 is also used to modulate the third bit sequence and send a signal carrying the third bit sequence to terminal 101.

[0070] Terminal 101 is used to receive signals from base station 102 and demodulate the signals to obtain the third bit sequence.

[0071] Terminal 101 is also used to perform rate recovery and decoding on the third bit sequence to obtain the first bit sequence. Based on the above process, data information is transmitted between base station 102 and terminal 101.

[0072] The technical solutions of this disclosure can be applied to various communication systems, such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency-division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), and other systems. The term "system" can be used interchangeably with "network." CDMA systems can implement wireless technologies such as Universal Terrestrial Radio Access (UTRA) and CDMA 2000. UTRA can include wideband CDMA (WCDMA) technology and other CDMA variants. CDMA 2000 can cover interim standard (IS) 2000 (IS-2000), IS-95, and IS-856 standards. TDMA systems can implement wireless technologies such as Global System for Mobile Communication (GSM). OFDMA systems can implement wireless technologies such as Evolved Universal Radio Terrestrial Access (E-UTRA), Ultra Mobile Broadband (UMB), IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, and Flash OFDMA. UTRA and E-UTRA are UMTS and its evolved versions, respectively. 3GPP's Long Term Evolution (LTE) and various versions based on LTE are newer versions of UMTS using E-UTRA. The communication system can also be used for 5G, New Radio (NR), and 6G communication systems. Furthermore, the communication system can be adapted to future-oriented communication technologies, all of which are subject to the technical solutions provided in the embodiments of this disclosure.

[0073] Terminal 101 is a device with wireless communication capabilities that can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted, on water (such as on ships), or in the air (such as on airplanes, balloons, and satellites). Terminal 101 is also known as user equipment (UE), mobile station (MS), mobile terminal (MT), and terminal equipment, and is a device that provides voice and / or data connectivity to users. For example, Terminal 101 includes handheld devices and vehicle-mounted devices with wireless connectivity. Currently, terminal 101 can be: mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device (e.g., smartwatch, smart bracelet, pedometer, etc.), vehicle-mounted device (e.g., car, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (e.g., refrigerator, television, air conditioner, electricity meter, etc.), smart robot, workshop equipment, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flying device (e.g., smart robot, hot air balloon, drone, airplane), etc. In one application scenario of this disclosure embodiment, the terminal is a terminal that frequently operates on the ground, such as vehicle-mounted device. In this embodiment of the disclosure, for ease of description, the chip deployed in the above-mentioned device, such as a system-on-a-chip (SOC), a baseband chip, or other chip with communication functions, may also be referred to as a terminal.

[0074] Terminal 101 can be a vehicle with corresponding communication functions, or an in-vehicle communication device, or other embedded communication device, or a user's handheld communication device, including mobile phones, tablets, etc.

[0075] As an example, in this embodiment of the disclosure, the terminal 101 can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices; they achieve powerful functions through software support, data interaction, and cloud interaction. Broadly defined, wearable smart devices include those with comprehensive functions, large size, and the ability to achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those focused on a specific application function that require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0076] Base station 102 is a device located on the access network side of the aforementioned communication system and having wireless transceiver function, or a chip or chip system that can be installed in the device. Base station 102 includes, but is not limited to: access points (APs) in WiFi systems, such as home gateways, routers, servers, switches, bridges, etc.; evolved NodeBs (eNBs), radio network controllers (RNCs), NodeBs (NBs), base station controllers (BSCs), base transceiver stations (BTSs), home base stations (e.g., home evolved NodeBs, or home NodeBs (HNBs)); base band units (BBUs); radio relay nodes; radio backhaul nodes; transmission and reception points (TRPs) or transmission points (TPs); 5G base stations, such as gNBs in new radio (NR) systems, or transmission points (TRPs or TPs); one or a group of antenna panels (including multiple antenna panels) of a base station in a 5G system; or network nodes constituting gNBs or transmission points, such as base band units (BBUs), or distributed units (DUs), or roadside units with base station functions. Base station 102 also includes base stations in different networking modes, such as master evolved NodeB (MeNB) and secondary base stations (secondary eNB, SeNB, or secondary gNB, SgNB). Base station 102 also includes different types, such as terrestrial base stations, airborne base stations, and satellite base stations.

[0077] It should be noted that the various embodiments of this disclosure can be referenced or learned from each other. For example, the same or similar steps, method embodiments, system embodiments and device embodiments can be referenced from each other without limitation.

[0078] Figure 2 is a flowchart of an encoding method according to some embodiments. As shown in Figure 2, the method includes steps 201 to 206.

[0079] Step 201: Obtain the first bit sequence.

[0080] The first bit sequence includes the information bits to be transmitted. For example, the first bit sequence can be c0, c1, c2, c3, ..., c K-1 It includes K information bits (i.e., the length of the first bit sequence is K), where K is a positive integer, c0 represents the first information bit in the first bit sequence, and so on.

[0081] Step 202: Determine the rate matching method and, based on the rate matching method, determine the first frozen bit index set.

[0082] Rate matching methods include: repetition, puncturing, and shortening. The first set of frozen bit indices includes the indices corresponding to the frozen bits to be rate matched.

[0083] It should be noted that, according to the method of dividing information bits that carry the first bit sequence, polar code sequences can be divided into an information bit index set and a frozen bit index set.

[0084] The information bit index set includes the indices of the information bits carrying the first bit sequence, while the frozen bit index set includes the indices of the frozen bits carrying preset information. For example, the preset information can be uniformly set to a first value. This first value can be defined according to the actual situation. The index is used to represent the bit position of the corresponding bit.

[0085] It should be understood that after the first node (i.e. the encoding end) performs rate matching, the bits corresponding to the first frozen bit index set determined above will be removed from the second bit sequence. Therefore, the first node can use the bits to be rate matched as frozen bits when constructing the second bit sequence to avoid data transmission errors caused by the failure to correctly transmit the relevant data involving the actual information bits.

[0086] Step 203: Determine the second set of frozen bit indices based on the fast decoding conditions.

[0087] It should be noted that, in addition to the frozen bits involved in rate matching determined in step 202 above, the first node also needs to determine the frozen bits in the polar code sequence for the fast decoding conditions so that the constructed polar code can be decoded quickly.

[0088] It should be understood that during decoding (using a Fast-SC decoder), the second node (i.e., the decoder) typically divides the polar code sequence into multiple sub-codes for decoding. If a sub-code satisfies the fast decoding condition, the second node can employ the corresponding fast decoding algorithm, thereby improving decoding efficiency. The fast decoding condition can be a condition defined by the relevant fast decoding algorithm. For example, the fast decoding condition can be a sub-code that does not contain a specific code rate (i.e., the ratio of the number of information bits in the sub-code to the total number of bits in the sub-code). That is, the first node can adjust the code rate of the sub-codes in the polar code sequence based on the fast decoding condition, so that the sub-codes in the polar code sequence satisfy the fast decoding condition, and then use the frozen bit index set in the polar code sequence at this time as the second frozen bit index set.

[0089] Step 204: Determine the third frozen bit index set based on the first frozen bit index set and the second frozen bit index set.

[0090] The third set of frozen bit indices is the set of frozen bit indices in the first polar code sequence to be constructed.

[0091] In one implementation, the first node uses the union of the first frozen bit index set and the second frozen bit index set as the third frozen bit index set.

[0092] Thus, the second bit sequence obtained by the first node through polar code encoding based on the third frozen bit index set can not only perform rate matching normally, but the second node can also perform decoding through a fast decoding algorithm, thereby improving decoding efficiency.

[0093] It should be noted that since the number of information bits in the first bit sequence is fixed, and the length of the constructed first polar code sequence is also fixed, the number of frozen bits in the first polar code sequence is also fixed. However, in some cases, the number of elements in the third frozen bit index set deviates from the fixed number of frozen bits in the first polar code sequence. In this case, the first node adjusts the aforementioned third frozen bit index set.

[0094] In one implementation, if the number of elements in the third frozen bit index set is not equal to the preset number, the first node redetermines the second frozen bit index set until the number of elements in the third frozen bit index set equals the preset number.

[0095] For example, the first set of frozen bit indices is The second set of frozen bit indices is Third Frozen Bit Index Set The preset quantity can be the difference between the length of the second bit sequence and the length of the first bit sequence, which represents the number of frozen bits in the first polar code sequence.

[0096] In addition, the first node can also determine whether it is necessary to re-determine the second frozen bit index set based on the number of information bits in the first polar code sequence.

[0097] For example, if the third set of frozen bit indices is the same as the set of frozen bit indices in the first polar code sequence, then the set of information bit indices in the first polar code sequence is... It is the set of all positive integers not greater than N. This represents the difference between the set of all positive integers not greater than N and the third frozen bit index set. At this point, the information bit index set... Number of elements in

[0098] In K m In the case of K, the number of information bits in the first polar code sequence constructed based on the third frozen bit index set is the same as the number of information bits in the first bit sequence. Therefore, the first node can normally encode the first bit sequence into polar codes according to the third frozen bit index set to carry the information bits in the first bit sequence.

[0099] For example, when the rate matching method is repetitive, rate matching does not involve operations on the bits in the first polar code sequence, and the first frozen bit index set is empty. In this case, the third frozen bit index set is the same as the second frozen bit index set. Rate matching does not affect polar code encoding, and the number of information bits in the first polar code sequence constructed based on the third frozen bit index set is the same as the number of information bits in the first bit sequence.

[0100] When the rate matching method is perforation, rate matching involves operations on discontinuous bits in the first polar code sequence, which may affect the frozen bits in the second frozen bit index set determined by the first node. In this case, freezing bits only occur when the first frozen bit index set is included in the second frozen bit index set. The number of information bits in the first polar code sequence constructed based on the third frozen bit index set is the same as the number of information bits in the first bit sequence.

[0101] When the rate matching method is truncated, rate matching involves operations on consecutive bits in the first polar code sequence. These bits typically satisfy the fast decoding condition (i.e., the code rate of the subcode is 0). The first node can exclude these bits when determining the second frozen bit index set. In this case, the condition is met only when the intersection of the first and second frozen bit index sets is empty. The number of information bits in the first polar code sequence constructed based on the third frozen bit index set is the same as the number of information bits in the first bit sequence.

[0102] In K m In the case where K is not equal to K, the number of information bits in the first polar code sequence constructed based on the third frozen bit index set is inconsistent with the number of information bits in the first bit sequence. Therefore, the first node cannot properly encode the first bit sequence using polar codes based on the third frozen bit index set to carry the information bits in the first bit sequence.

[0103] When the first node redetermines the second frozen bit index set, it can add an offset to the original number of information bits. This offset can be K or K. m The difference. Thus, the number of elements in the third frozen bit index set determined by the first node based on the first frozen bit index set and the redefined second frozen bit index set is more likely to meet the preset number, thereby improving the efficiency of the first node in determining the third frozen bit index set.

[0104] Step 205: Based on the third frozen bit index set, the first bit sequence is polar-coded to obtain the second bit sequence.

[0105] In one implementation, the first node obtains a first polar code sequence based on the third frozen bit index set and the first bit sequence, and encodes the first polar code sequence based on the generator matrix (also known as the polarization transformation matrix) to obtain a second bit sequence.

[0106] For example, the first node sets the corresponding bit in the first polar code sequence to a first value (e.g., 0) according to the bit position indicated by the index in the third frozen bit index set, and sets the other bits to the values ​​of the information bits in the first bit sequence in order.

[0107] Based on the example above, the first bit sequence c = [c0, c1, c2, ..., c K-1 The first polar code sequence u = [u0 u1 u2 ... u] is given by the first polar code sequence u = [u0 u1 u2 ... u]. N-1 The third set of frozen bit indices is The set of information bit indices in the first polarization code sequence is: It is the set of all positive integers not greater than N. It represents the difference between the set of all positive integers not greater than N and the set of the third frozen bit index.

[0108] At this point, the process by which the first node determines the first polar code sequence satisfies the following:

[0109] Afterwards, the first node can be obtained through d = uG N Determine the second bit sequence. d = [d0 d1 d2 ... d N-1 [ ] represents the second bit sequence, and the generator matrix is: Generate an N*N matrix. This represents the nth power of the Kronecker power of G2.

[0110] Step 206: Based on the rate matching method, perform rate matching on the second bit sequence to obtain the third bit sequence.

[0111] Rate matching includes sub-block interleaving and bit selection. It should be noted that the rate matching method in step 206 is the same as the rate matching method determined in step 202 above.

[0112] In one implementation, the first node performs sub-block interleaving on the second bit sequence based on rate matching to obtain an interleaved bit sequence, and performs bit selection on the interleaved bit sequence to obtain a third bit sequence.

[0113] For example, the first node inputs the second bit sequence into the sub-block interleaver to obtain the interleaved bit sequence output by the sub-block interleaver, and inputs the interleaved bit sequence into a ring buffer of length N to obtain the third bit sequence.

[0114] Based on the example above, the second bit sequence is d = [d0 d1 d2 ... d N-1 The interleaved bit sequence is y = [y0 y1 y2 ... y] N-1 The process of sub-block interleaving in the first node satisfies the following:

[0115] The function J(n) = P(i) × (N / 32) + mod(n, N / 32) is the mapping function of the sub-block interleaving mapping, and the value of P(i) satisfies the following Table 1.

[0116] Table 1 Sub-block Interlacing Pattern Table

[0117] Based on the above technical solution, the first node can obtain the first bit sequence to be transmitted, determine the rate matching method to be performed, and determine the first frozen bit index set based on the rate matching method to ensure that rate matching does not affect the subsequent construction of fast polar codes. Then, the first node can determine the second frozen bit index set based on the fast decoding conditions to ensure that the subsequently constructed polar codes can achieve fast decoding. Thus, the first node can simultaneously determine the third frozen bit index set based on both the first and second frozen bit index sets, and encode the first bit sequence using polar codes based on the third frozen bit index set to obtain the second bit sequence. Then, the first node can perform rate matching on the second bit sequence according to the previously determined rate matching method to obtain the third bit sequence. In this way, the third bit sequence constructed by the first node can satisfy fast decoding and can also achieve free rate adjustment through rate matching, thus enabling rate matching while meeting the encoding requirements of the fast polar code technology itself.

[0118] For example, as shown in Table 2 below, Table 2 illustrates the code rate distribution of subcodes in multiple polar codes obtained by the above technical solution. Let the length of the smallest subcode be D, and the fast decoding condition be that the code rate of the subcode is any subcode other than 5 / 16 and 9 / 16. As shown in Table 2, the constructed polar codes (864, 756), (864, 376), (864, 173), (640, 320), (640, 220), and (640, 128) do not include subcodes with code rates of 5 / 16 and 9 / 16, thus satisfying the fast decoding condition.

[0119] Table 2. Subcode Rate Distribution of Polar Codes

[0120] The following compares the performance of polar codes (864, 756) and (864, 376) under different encoding and decoding schemes. Figure 3 shows the performance simulation of polar codes (864, 756) under different polar code algorithms. Figure 4 shows the performance simulation of polar codes (864, 376) under different polar code algorithms. Figures 3 and 4 respectively include polar code algorithms of some techniques and simulation curves corresponding to polar code algorithms based on the technical scheme proposed in this disclosure. For example, the polar code algorithms include the SC algorithm and three cyclic redundancy check-aided successive cancellation list (CA-SCL) decoding algorithms (list sizes of 2, 8, and 32, respectively). The vertical axis represents the block error rate (BLER), which is the ratio of the number of erroneous blocks to the total number of blocks. The horizontal axis represents the bit signal-to-noise ratio (Eb / N0), which is the ratio of binary bit energy to noise power spectral density. As can be seen from the figure, compared with some techniques under the SC decoding algorithm, the performance loss caused by the technical solution provided in this disclosure is within 0.1dB. Compared with some techniques under the CA-SCL algorithm, the performance loss caused by the technical solution provided in this disclosure is almost negligible. That is, the technical solution provided in this disclosure can perform rate matching normally to flexibly adjust the transmission rate without affecting the polar code encoding performance.

[0121] The following describes the process of determining the rate matching method and the first set of frozen bit indices in this disclosure.

[0122] As an embodiment of this disclosure, referring to FIG2 and FIG5, the above step 202 can also be implemented by steps 501 to 503.

[0123] Step 501: Determine the rate matching method based on the length of the first bit sequence, the length of the second bit sequence, and the length of the third bit sequence.

[0124] In one implementation, if the length of the third bit sequence is greater than the length of the second bit sequence, the first node determines the rate matching method as repetition.

[0125] If the length of the third bit sequence is less than the length of the second bit sequence, and the target rate is less than or equal to a preset rate threshold, the first node determines the rate matching method as drilling.

[0126] If the length of the third bit sequence is less than the length of the second bit sequence, and the target rate is greater than the preset rate threshold, the first node determines the rate matching method as truncation.

[0127] The target rate is the ratio of the length of the first bit sequence to the length of the third bit sequence.

[0128] It should be noted that in practical applications, since length refers to the number of bits in the sequence, which is usually an integer value, the ratio of the length of the first bit sequence to the length of the third bit sequence may deviate from the target rate. This situation does not affect the implementation of the technical solution proposed in this disclosure.

[0129] In addition, the first node can also adopt a rate matching method that combines truncation and punching. For example, if the length of the third bit sequence is less than the length of the second bit sequence and the target rate is greater than the preset rate threshold, the first node determines the rate matching method to be punching and truncation.

[0130] Step 502: When the rate matching method is repeated, determine that the first frozen bit index set is an empty set.

[0131] When the rate matching method is repetitive, the first node will repeat some bits based on the second bit sequence to obtain the third bit sequence during rate matching. In this case, there is no modification to the second bit sequence. Therefore, the first node can determine that the first frozen bit index set is empty, that is, there are no frozen bits to be rate matched.

[0132] Step 503: When the rate matching method is punching or truncating, determine the first frozen bit index set according to the corresponding rate matching algorithm.

[0133] This disclosure does not limit the rate matching algorithm; in practical applications, a suitable rate matching algorithm can be selected based on the application scenario. It should be noted that the rate matching algorithm used should correspond to the rate recovery algorithm of the second node.

[0134] Based on the above technical solution, the first node can select an appropriate rate matching method by combining the lengths of the multiple bit sequences involved to improve resource utilization efficiency. Then, based on the determined rate matching method, the frozen bits to be performed for rate matching are determined to ensure that the transmission of actual information is not affected during subsequent rate matching.

[0135] The following three examples illustrate the process of determining the rate matching method and the first frozen bit index set of the first node.

[0136] Example 1:

[0137] When the length E of the third bit sequence is greater than the length N of the second bit sequence, the rate matching method is repetition.

[0138] If the length E of the third bit sequence is less than the length N of the second bit sequence, the first node further determines the rate matching method based on the length K of the first bit sequence and the length E of the third bit sequence.

[0139] When the ratio of K to E is less than or equal to a preset rate threshold, for example, K / E ≤ 7 / 16, meaning the preset rate threshold is 7 / 16, the first node determines the rate matching method as drilling. When the ratio of K to E is greater than the preset rate threshold, the first node determines the rate matching method as truncation.

[0140] For the rate matching method of perforation, the first node can use the set obtained after mapping the first NM indices through sub-block interleaving as the first frozen bit index set. For example, the first NM indices can be represented as the set {0,1,...,NM-1}.

[0141] For the rate matching method of truncating, the first node can use the set obtained after mapping the last NM indices through sub-block interleaving as the first frozen bit index set. For example, the last NM indices can be represented as the set {M, M+1, ..., N-1}.

[0142] The length of the smallest subcode in the second bit sequence is D, and M is the smallest value that is greater than or equal to E and is an integer multiple of D, denoted as:

[0143] For example, the first node can further adjust the first frozen bit index set determined when the rate matching method is truncated, based on the length N of the second bit sequence and the length E of the third bit sequence.

[0144] If the length E of the third bit sequence is greater than or equal to a preset length threshold, for example, E≥3N / 4, the first node uses the union of the set {0,1,...,NM-1} obtained after sub-block interleaving mapping and the set {0,1,...,3N / 4-M / 2-1} as the first frozen bit index set.

[0145] If the length E of the third bit sequence is less than a preset length threshold, for example, E < 3N / 4, the first node uses the union of the set {0,1,...,NM-1} obtained after sub-block interleaving mapping and the set {0,1,...,9N / 16-M / 4-1} as the first frozen bit index set.

[0146] The sets {0,1,...,3N / 4-M / 2-1} and {0,1,...,9N / 16-M / 4-1} can be adjusted according to actual circumstances, and this disclosure does not impose any limitations on them. The number of elements in the first frozen bit index set mentioned above is an integer multiple of D. The mapping function for the sub-block interleaving mapping can be referred to the relevant description in step 206 above.

[0147] The process in Example 1 above satisfies the following conditions:

[0148] Example 2:

[0149] When the length E of the third bit sequence is greater than the length N of the second bit sequence, the rate matching method is repetition.

[0150] If the length E of the third bit sequence is less than the length N of the second bit sequence, the first node further determines the rate matching method based on the length K of the first bit sequence and the length E of the third bit sequence.

[0151] When the ratio of K to E is less than or equal to a preset rate threshold, for example, K / E ≤ 7 / 16, meaning the preset rate threshold is 7 / 16, the first node determines the rate matching method as drilling. When the ratio of K to E is greater than the preset rate threshold, the first node determines the rate matching method as truncation.

[0152] For the rate matching method of punching, the first node can use the set obtained after the first NT indices are mapped by sub-block interleaving as the first frozen bit index set. For example, the first NT indices can be represented as the set {0,1,...,NT-1}.

[0153] For the case where the rate matching method is truncated, the first node can use the union of the set obtained by sub-block interleaving mapping of the last NT indices and the set {0,1,...,ME} as the first frozen bit index set. For example, the last NT indices can be represented as the set {T,T+1,...,N-1}.

[0154] The length of the smallest subcode in the second bit sequence is D, and T is the maximum value that is less than or equal to E and is an integer multiple of D, denoted as: M is the minimum value that satisfies being greater than or equal to E and an integer multiple of D, denoted as:

[0155] For example, the first node can further adjust the first frozen bit index set determined when the rate matching method is truncated, based on the length N of the second bit sequence and the length E of the third bit sequence.

[0156] If the length E of the third bit sequence is greater than or equal to a preset length threshold, for example, E≥3N / 4, the first node uses the union of the set {0,1,...,NT-1} obtained after sub-block interleaving mapping and the set {0,1,...,3N / 4-T / 2-1} as the first frozen bit index set.

[0157] If the length E of the third bit sequence is less than a preset length threshold, for example, E < 3N / 4, the first node uses the union of the set {0,1,...,NT-1} obtained after sub-block interleaving mapping and the set {0,1,...,9N / 16-T / 4-1} as the first frozen bit index set.

[0158] The sets {0,1,...,3N / 4-T / 2-1} and {0,1,...,9N / 16-T / 4-1} can be adjusted according to actual circumstances, and this disclosure does not impose any limitations on them. The number of elements in the first frozen bit index set mentioned above is an integer multiple of D. The mapping function for the sub-block interleaving mapping can be found in the relevant description in step 206 above.

[0159] The process in Example 2 above satisfies the following:

[0160] Example 3:

[0161] When the length E of the third bit sequence is greater than the length N of the second bit sequence, the rate matching method is repetition.

[0162] If the length E of the third bit sequence is less than the length N of the second bit sequence, the first node further determines the rate matching method based on the length K of the first bit sequence and the length E of the third bit sequence.

[0163] When the ratio of K to E is less than or equal to a preset rate threshold, for example, K / E ≤ 7 / 16, meaning the preset rate threshold is 7 / 16, the first node determines the rate matching method as drilling. When the ratio of K to E is greater than the preset rate threshold, the first node determines the rate matching method as truncation.

[0164] For the rate matching method of punching, the first node can use the set obtained after the first NT indices are mapped by sub-block interleaving as the first frozen bit index set. For example, the first NT indices can be represented as the set {0,1,...,NT-1}.

[0165] For the rate matching method of truncation, the first node determines the first frozen bit index set by element offset. That is, the first node can use a rate matching method that combines truncation and perforation, using some bits as truncated bits and some bits as perforated bits.

[0166] For example, the first node can use the union of the set obtained after the last NTP indices are mapped by sub-block interleaving with the set {0,1,...,M-E+P} as the first frozen bit index set. For example, the last NT indices can be represented as the set {T+P,T+P+1,...,N-1}.

[0167] The length of the smallest subcode in the second bit sequence is D, and T is the maximum value that is less than or equal to E and is an integer multiple of D, denoted as: M is the minimum value that satisfies being greater than or equal to E and an integer multiple of D, denoted as: P is an integer multiple of D and less than or equal to NM, denoted as P = {kD|k = 0, 1, 2, ...}, and P ≤ NM.

[0168] For example, the first node can further adjust the first frozen bit index set determined when the rate matching method is truncated, based on the length N of the second bit sequence and the length E of the third bit sequence.

[0169] If the length E of the third bit sequence is greater than or equal to a preset length threshold, for example, E≥3N / 4, the first node uses the union of the set {0,1,...,NT-1} obtained after sub-block interleaving mapping and the set {0,1,...,3N / 4-T / 2-1} as the first frozen bit index set.

[0170] If the length E of the third bit sequence is less than a preset length threshold, for example, E < 3N / 4, the first node uses the union of the set {0,1,...,NT-1} obtained after sub-block interleaving mapping and the set {0,1,...,9N / 16-T / 4-1} as the first frozen bit index set.

[0171] The sets {0,1,...,3N / 4-T / 2-1} and {0,1,...,9N / 16-T / 4-1} can be adjusted according to actual circumstances, and this disclosure does not impose any limitations on them. The number of elements in the first frozen bit index set mentioned above is an integer multiple of D. The mapping function for the sub-block interleaving mapping can be found in the relevant description in step 206 above.

[0172] The process in Example 3 above satisfies the following:

[0173] It should be noted that the method by which the first node selects bits in step 206 above needs to match the method by which the first node determines the first frozen bit index set based on the rate matching method in steps 501 to 503 above.

[0174] For Examples 1 and 2 above, the first node can select bits in the following way.

[0175] When the rate matching mode is repetitive, the first node passes through a ring buffer of length N to repeatedly output a portion of the interleaved bit sequence, thus obtaining the third bit sequence.

[0176] When the rate matching method is punched, the first node uses the sequence consisting of the last E bits of the interleaved bit sequence as the third bit sequence.

[0177] When the rate matching method is truncation, the first node performs a punching operation on the smallest mod(NE,D) bits and truncates the largest NM bits to obtain the third bit sequence.

[0178] For example, the above process satisfies the following:

[0179] For Example 3 above, the first node can select bits in the following way.

[0180] When the rate matching mode is repetitive, the first node passes through a ring buffer of length N to repeatedly output a portion of the interleaved bit sequence, thus obtaining the third bit sequence.

[0181] When the rate matching method is punched, the first node uses the sequence consisting of the last E bits of the interleaved bit sequence as the third bit sequence.

[0182] When the rate matching method is truncation, the first node performs a punching operation on the smallest k = mod(NE,D) + P bits, and simultaneously performs a truncation operation on the largest NMP bits, to obtain the third bit sequence.

[0183] For example, the above process satisfies the following:

[0184] The process of determining the length of the second bit sequence in this disclosure will be described below.

[0185] As an embodiment of this disclosure, referring to FIG2 and FIG5, the method further includes step 504 before step 501 above.

[0186] Step 504: Determine the length of the second bit sequence based on the length of the third bit sequence.

[0187] The length N of the second bit sequence needs to satisfy the polar code encoding requirements, i.e., N = 2. n Here, n is a positive integer. Therefore, the first node can determine n based on the length of the third bit sequence, and thus determine the length N of the second bit sequence.

[0188] In one implementation, the first node can be obtained by taking the base-2 logarithm of the length E of the third bit sequence and rounding it up, i.e. In this way, the first node can use the length of the second bit sequence that is as close as possible to the length E of the third bit sequence and meets the polar code encoding requirements, so as to avoid additional resource consumption.

[0189] In another implementation, the first node can determine the length of the second bit sequence based on the length of the first bit sequence and the length of the third bit sequence.

[0190] For example, let the range of values ​​for n be n min ≤n≤n max The minimum speed is R min The process by which the first node determines the length of the second bit sequence satisfies the following:

[0191] Based on the above technical solution, the first node can determine the length of the second bit sequence based on the length of the third bit sequence, so as to avoid resource waste caused by unreasonable setting of the bit sequence length.

[0192] As an embodiment of this disclosure, referring to FIG2 and FIG6, the above step 203 can also be implemented by steps 601 to 604.

[0193] Step 601: Determine the number of information bits in the second polar code sequence.

[0194] In one implementation, the first node can determine the number of information bits in the second polar code sequence based on the length of the first bit sequence and the rate matching method.

[0195] In some embodiments, when the rate matching method is repetition or perforation, the first node determines the number of information bits in the second polar code sequence based on the length of the first bit sequence; or...

[0196] When the rate matching method is truncation, the first node determines the number of information bits in the second polar code sequence based on the number of truncated bits and the length of the first bit sequence.

[0197] It should be understood that for cases where the rate matching method is repetitive, rate matching will not affect the polar code encoding of the first node. Therefore, when determining the second frozen bit index set, the first node can directly use the length of the first bit sequence as the number of information bits. Let the number of information bits in the second polar code sequence be K. t Then we have K t =K.

[0198] When the rate matching method is perforation, rate matching involves operations on discontinuous bits in the first polar code sequence, which may affect the frozen bits in the second frozen bit index set determined by the first node. In this case, the first node can first use the length of the first bit sequence as the number of information bits, and then determine whether rate matching affects the final result through judgment. Therefore, the number of information bits K in the second polar code sequence is... t =K.

[0199] When the rate matching method is truncated, rate matching involves operations on consecutive bits in the first polar code sequence. These bits typically satisfy the fast decoding condition (i.e., the code rate of the subcode is 0). The first node can exclude these bits when determining the second frozen bit index set, thus ensuring that the determined first polar code sequence still satisfies the fast decoding condition. In other words, the frozen bits in the second polar code sequence do not include the first frozen bit index set at this point. The first node uses the bits in the first frozen bit index set as the information bits of the second polar code sequence. Therefore, the number of information bits in the second polar code sequence is K. t =K+(NM). NM is the number of elements in the first frozen bit index set when the rate matching method is truncated.

[0200] Furthermore, for rate matching methods such as truncation and punching, the first node can also use some bits as frozen bits and some bits as information bits, for example, the number of information bits K in the second polar code sequence. t =K+[NE-mod(NE,D)].

[0201] For example, the above process satisfies the following:

[0202] It should be noted that the scheme for the first node to re-determine the second frozen bit index set involved in step 204 above can refer to steps 601-604. The first node determines the number of information bits of the second polar code sequence in the manner described in step 204 above, that is, adds the bias amount.

[0203] Step 602: Determine the set of information bit indices in the second polar code sequence based on the number of information bits in the second polar code sequence.

[0204] The first node determines the second polarization code sequence (N, K). t The set of information bit indices in the code can be referenced from relevant polar code encoding algorithms.

[0205] For example, pre-sorted polarization sequences The largest polar code sequence defined for the relevant polar code encoding algorithm. N max The pre-sorted polar sequence is the longest compatible polar code sequence. Bit index in Arranged in ascending order of their respective reliability levels, i.e. Represents bit index The reliability of the bit index is as follows: the higher the reliability, the greater the channel capacity of the polarization channel indicated by the bit index; the lower the reliability of the bit index, the smaller the channel capacity of the polarization channel indicated by the bit index.

[0206] The first node can be derived from the pre-sorted polarization sequence based on the length of the second polarization code sequence. The corresponding subset is determined in the middle. This subset consists of preordered polarization sequences The index of the second polar code sequence is less than the length N of the index. Arranged in ascending order of their respective reliability levels, i.e.

[0207] The first node is based on Determine the set of information bit indices in the second polarization code sequence. For sequence K, the most reliable t The sequence is composed of several indices. The set of frozen bit indices in the second polar code sequence is the sequence itself. The index in.

[0208] For example, pre-sorted polarization sequences The index and corresponding reliability in the data. As shown in Table 3 below.

[0209] Table 3 Reliability List of Pre-sorted Polarization Sequence Indexes

[0210] The column represents the reliability corresponding to the bit index; the smaller the value, the lower the reliability. The column represents the bit index.

[0211] Step 603: Based on the fast decoding conditions, adjust the positions of the information bits in the second polar code sequence to obtain the adjusted information bit index set.

[0212] It should be understood that some sub-codes in the second polar code sequence determined by the first node may not be able to be decoded quickly, which leads to low decoding efficiency of the second node. Therefore, the first node can adjust the position of the information bits in the second polar code sequence based on the fast decoding condition, so that all sub-codes in the second polar code sequence can satisfy fast decoding.

[0213] In one implementation, the first node can determine, from multiple subcodes of the second polar code sequence, a first subcode that does not satisfy the fast decoding condition, and a second subcode associated with the first subcode.

[0214] The first node adjusts some information bits in the first subcode to freeze bits, and adjusts some frozen bits in the second subcode to information bits.

[0215] In some embodiments, the first node can adjust the d information bits with the lowest reliability in the first subcode to freeze bits, and adjust the d frozen bits with the highest reliability in the second subcode to information bits, where d is a positive integer.

[0216] For example, the first node can adjust the position of the information bits in the second polar code sequence according to the polarization permutation table. Taking the length of the second polar code sequence as N and the subcode length as 16 as an example, the corresponding polarization permutation table is shown in Table 4 below.

[0217] Table 4 Polarization Substitution Table

[0218] K represents the number of information bits, e I e is the index corresponding to the first subcode. F This is the index corresponding to the second subcode. The first node determines the number K of information bits less than or equal to the second polar code sequence based on the polarization permutation table. t The maximum K value corresponds to the row number L. The first node determines the first and second sub-codes in rows L-L1 to L of the polarization permutation table as the sub-codes to be detected. L1 is a preset range parameter, usually a positive integer.

[0219] The first node is the first subcode e of each line from line L-L1 to line L. I and the second subcode e F Determine if there is a subcode that cannot be quickly decoded. If not, check the next line; if it exists, set the first subcode 'e' to 'e'. IThe information bits in the middle are adjusted to the second subcode e F In, so that the first subcode e I and the second subcode e F All meet the conditions for fast decoding.

[0220] For example, the first subcode e I Represented as Second subcode e F Represented as Then the first subcode e I The set of information bit indices in the middle is Second subcode e F The set of information bit indices in the middle is The code rate of the first subcode The code rate of the second subcode

[0221] like as well as If the fast decoding condition is met, then check the first and second subcodes in the next line. If as well as If at least one of the conditions for fast decoding is not met, then... The information bits with the lowest reliability are from the information bit index set. Remove from the middle, and add the frozen bit with the highest reliability from the frozen bit index set in the second sub-code to the information bit index set. Repeat the above process until both the first and second subcodes satisfy the fast decoding conditions.

[0222] Based on the above scheme, the first node can obtain the adjusted set of information bit indices.

[0223] Step 604: Determine the second frozen bit index set based on the adjusted information bit index set.

[0224] For example, the second set of frozen bit indices is denoted as Represents a set With information bit index set The difference set.

[0225] Based on the above technical solution, the first node can determine the number of information bits in the second polar code sequence, and thus determine the set of information bit indices in the second polar code sequence based on the number of information bits. Then, the first node can adjust the positions of the information bits in the second polar code sequence according to the fast decoding condition, so that the adjusted second polar code sequence satisfies the fast decoding condition, obtaining the adjusted set of information bit indices. In this way, the first node can determine the second frozen bit index set based on the adjusted set of information bit indices. The first polar code sequence subsequently constructed by the first node based on this second frozen bit index set can then satisfy the fast decoding condition, improving decoding efficiency.

[0226] Furthermore, the number of elements in the third frozen bit index set determined by the first node based on the first frozen bit index set and the second frozen bit index set may deviate from the number of frozen bits in the first polar code sequence. Therefore, the first node can correct the number of information bits when determining the information bit index set in the second polar code sequence, thereby reducing the subsequent judgment and adjustment process and improving coding efficiency.

[0227] As an embodiment of this disclosure, referring to FIG6 and FIG7, step 602 above can be implemented by steps 701 to 704.

[0228] Step 701: Determine the first element index set.

[0229] The first element index set includes the NK code sequence with the lowest reliability in the second polar code sequence. t The indices of the elements, N is the length of the second polar code sequence, and K is the index of the element. t This represents the number of information bits in the second polar code sequence.

[0230] That is, the first element index set represents the set of frozen bit indices in the second polar code sequence determined without adjustment based on the fast decoding conditions.

[0231] Step 702: Use the union of the first element index set and the first frozen bit index set as the fourth frozen bit index set.

[0232] The fourth set of frozen bit indices That is, the set of frozen bit indices of the first polar code sequence determined based on the set of frozen bit indices of the second polar code sequence determined without adjustment based on the fast decoding conditions, and the set of frozen bit indices of the first polar code sequence.

[0233] Step 703: Based on the number of elements in the fourth frozen bit index set, correct the number of information bits in the second polar code sequence to obtain the corrected number of information bits.

[0234] For example, the number of elements in the fourth frozen bit index set can be represented as The first node can determine the amount of correction as the number of elements in the fourth frozen bit index set. And the difference between the number of frozen bits KN in the first polar code sequence.

[0235] The first node can use this correction amount to correct the number of information bits in the second polar code sequence, obtaining the corrected number of information bits.

[0236] That is, without adjustments based on the fast decoding conditions, the number of elements in the final determined fourth frozen bit index set deviates from the actual number of frozen bits in the first polar code sequence to be constructed. The deviation value is... Therefore, the first node can adjust the number of information bits in the second polar code sequence according to this deviation value, so as to reduce the number of subsequent adjustments and improve coding efficiency.

[0237] Step 704: Based on the corrected number of information bits, determine the set of information bit indices in the second polar code sequence.

[0238] The first node can determine the set of information bit indices in the second polar code sequence by referring to the above scheme, which will not be elaborated here.

[0239] Based on the above technical solution, the first node can pre-correct the number of information bits in the determined second polar code sequence before determining the second frozen bit index set, so as to reduce the problem of deviation between the number of elements in the subsequently obtained third frozen bit index set and the number of frozen bits in the first polar code sequence, thereby improving coding efficiency.

[0240] The following describes the decoding process of the second node.

[0241] Figure 8 is a flowchart of a decoding method according to some embodiments. As shown in Figure 8, the method includes steps 801 to 806.

[0242] Step 801: Receive the third bit sequence from the first node.

[0243] For example, the second node uses parameters such as the corresponding modulation scheme and channel state information to transmit the received sequence z = [z0, z1, z2, ..., z...]. E-1 The demodulated sequence is x = [x0, x1, x2, ..., x]. E-1 ].

[0244] Sequence x = [x0, x1, x2, ..., x E-1This is the third bit sequence obtained from the second node. Since the bit values ​​may change during information transmission, it is represented here by the sequence x = [x0, x1, x2, ..., x...]. E-1 ] represents the third bit sequence obtained by rate matching of the first node mentioned above.

[0245] Step 802: Determine the rate matching method, and perform rate recovery on the third bit sequence based on the rate matching method to obtain the second bit sequence.

[0246] For example, the second node can perform rate recovery on the third bit sequence by performing rate matching and corresponding rate recovery on the first node, thus obtaining the second bit sequence y′=[y′0y′1y′2...y′] N-1 ].

[0247] For example, regarding the rate matching involved in Examples 1 and 2 above, the corresponding rate recovery process satisfies the following:

[0248] The constant A is a positive number that the second node can represent.

[0249] For the rate matching with added offset P in Example 3 above, the corresponding rate recovery process satisfies the following:

[0250] The constant A is a positive number that the second node can represent.

[0251] Step 803: Determine the first set of frozen bit indices based on the rate matching method.

[0252] For related instructions, please refer to step 202 above, which will not be repeated here.

[0253] Step 804: Determine the second set of frozen bit indices based on the fast decoding conditions.

[0254] For related instructions, please refer to step 203 above, which will not be repeated here.

[0255] Step 805: Determine the third frozen bit index set based on the first frozen bit index set and the second frozen bit index set.

[0256] In one implementation, the second node uses the union of the first and second frozen bit index sets as the third frozen bit index set.

[0257] In one implementation, if the number of elements in the third frozen bit index set is not equal to the preset number, the second node redetermines the second frozen bit index set until the number of elements in the third frozen bit index set equals the preset number.

[0258] For related instructions, please refer to step 204 above, which will not be repeated here.

[0259] Step 806: Based on the third frozen bit index set, perform polar code decoding on the second bit sequence to obtain the first bit sequence.

[0260] In one implementation, the second node can determine the subcode types of multiple subcodes in the second bit sequence, and decode the multiple subcodes based on the fast decoding algorithm corresponding to the subcode types to obtain the first bit sequence.

[0261] For example, subcode types that meet the conditions for fast decoding include Rate-0 code, REP code, REP-2 code, PCR code, RPC code, SPC code, SPC-2 code, and Rate-1 code. The second node can be decoded using the corresponding fast decoding algorithm to obtain the first bit sequence.

[0262] As an embodiment of this disclosure, referring to FIG8 and FIG9, the above step 802 can also be implemented by steps 901 to 902.

[0263] Step 901: Determine the rate matching method based on the length of the first bit sequence, the length of the second bit sequence, and the length of the third bit sequence.

[0264] Rate matching methods include: repeat, truncation, and drilling.

[0265] For related instructions, please refer to step 501 above, which will not be repeated here.

[0266] Step 902: Rate recovery is performed on the third bit sequence based on rate matching to obtain the second bit sequence.

[0267] For related instructions, please refer to step 802 above, which will not be repeated here.

[0268] As an embodiment of this disclosure, in conjunction with FIG8 and FIG9, step 803 can also be implemented by steps 903 to 904.

[0269] Step 903: When the rate matching method is repeated, determine that the first frozen bit index set is an empty set.

[0270] For related instructions, please refer to step 502 above, which will not be repeated here.

[0271] Step 904: When the rate matching method is punching or truncating, determine the first frozen bit index set according to the corresponding rate matching algorithm.

[0272] For related instructions, please refer to step 503 above, which will not be repeated here.

[0273] As an embodiment of this disclosure, referring to FIG8 and FIG9, the method further includes step 905 before step 901 above.

[0274] Step 905: Determine the length of the second bit sequence based on the length of the third bit sequence.

[0275] For related instructions, please refer to step 504 above, which will not be repeated here.

[0276] As an embodiment of this disclosure, referring to FIG8 and FIG10, the above step 804 can also be implemented by steps 1001 to 1004.

[0277] Step 1001: Determine the number of information bits in the second polar code sequence.

[0278] In one implementation, the second node can determine the number of information bits in the second polar code sequence based on the length of the first bit sequence and the rate matching method.

[0279] In some embodiments, when the rate matching method is repetition or perforation, the second node determines the number of information bits of the second polar code sequence based on the length of the first bit sequence; or...

[0280] When the rate matching method is truncation, the second node determines the number of information bits in the second polar code sequence based on the number of truncated bits and the length of the first bit sequence.

[0281] For related instructions, please refer to step 601 above, which will not be repeated here.

[0282] Step 1002: Determine the set of information bit indices in the second polar code sequence based on the number of information bits in the second polar code sequence.

[0283] For related instructions, please refer to step 602 above, which will not be repeated here.

[0284] Step 1003: Based on the fast decoding conditions, adjust the positions of the information bits in the second polar code sequence to obtain the adjusted information bit index set.

[0285] In one implementation, the second node can determine, from multiple subcodes of the second polar code sequence, a first subcode that does not satisfy the fast decoding condition, and a second subcode associated with the first subcode.

[0286] The second node adjusts some information bits in the first subcode to freeze bits, and adjusts some frozen bits in the second subcode to information bits.

[0287] In some embodiments, the second node can adjust the d information bits with the lowest reliability in the first subcode to freeze bits, and adjust the d frozen bits with the highest reliability in the second subcode to information bits, where d is a positive integer.

[0288] For related instructions, please refer to step 603 above, which will not be repeated here.

[0289] Step 1004: Determine the second frozen bit index set based on the adjusted information bit index set.

[0290] For related instructions, please refer to step 604 above, which will not be repeated here.

[0291] As an embodiment of this disclosure, referring to FIG10 and FIG11, the above step 1002 can be implemented by steps 1101 to 1104.

[0292] Step 1101: Determine the first element index set.

[0293] The first element index set includes the NK code sequence with the lowest reliability in the second polar code sequence. t The indices of the elements, N is the length of the second polar code sequence, and K is the index of the element. t This represents the number of information bits in the second polar code sequence.

[0294] For related instructions, please refer to step 701 above, which will not be repeated here.

[0295] Step 1102: Use the union of the first element index set and the first frozen bit index set as the fourth frozen bit index set.

[0296] For related instructions, please refer to step 702 above, which will not be repeated here.

[0297] Step 1103: Based on the number of elements in the fourth frozen bit index set, correct the number of information bits in the second polar code sequence to obtain the corrected number of information bits.

[0298] For related instructions, please refer to step 703 above, which will not be repeated here.

[0299] Step 1104: Based on the corrected number of information bits, determine the set of information bit indices in the second polar code sequence.

[0300] For related instructions, please refer to step 704 above, which will not be repeated here.

[0301] It is understood that, in order to achieve the above-mentioned functions, the communication device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the algorithmic steps of the examples described in conjunction with the embodiments of this disclosure, this disclosure can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0302] This disclosure embodiment can divide the communication device into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one functional module. The integrated module can be implemented in hardware or software. It should be noted that the module division in this disclosure embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the example of dividing each functional module according to each function.

[0303] For example, taking a communication device as the first node in the above method embodiment as an example, Figure 12 is a schematic diagram of the structure of a first node according to some embodiments. The first node can execute the encoding method provided in the above method embodiment. As shown in Figure 12, the first node 120 includes: a processing unit 1201 and a communication unit 1202.

[0304] The communication unit 1202 is used to acquire the first bit sequence.

[0305] The processing unit 1201 is used to determine the rate matching method and, based on the rate matching method, determine the first frozen bit index set.

[0306] Processing unit 1201 is also used to determine the second set of frozen bit indices based on fast decoding conditions.

[0307] Processing unit 1201 is also used to determine a third frozen bit index set based on the first frozen bit index set and the second frozen bit index set.

[0308] The processing unit 1201 is also used to perform polar code encoding on the first bit sequence based on the third frozen bit index set to obtain the second bit sequence.

[0309] The processing unit 1201 is also used to perform rate matching on the second bit sequence based on the rate matching method to obtain the third bit sequence.

[0310] In some embodiments, rate matching methods include: repeating, truncating, and punching.

[0311] In some embodiments, the processing unit 1201 is used to determine the rate matching method based on the length of the first bit sequence, the length of the second bit sequence, and the length of the third bit sequence.

[0312] In some embodiments, the processing unit 1201 is configured to: determine the number of information bits in the second polar code sequence; determine the information bit index set in the second polar code sequence based on the number of information bits in the second polar code sequence; adjust the position of the information bits in the second polar code sequence based on the fast decoding condition to obtain the adjusted information bit index set; and determine the second frozen bit index set based on the adjusted information bit index set.

[0313] In some embodiments, the processing unit 1201 is used to determine the number of information bits of the second polar code sequence based on the length of the first bit sequence and the rate matching method.

[0314] In some embodiments, the processing unit 1201 is configured to: determine the number of information bits of the second polar code sequence based on the length of the first bit sequence when the rate matching method is repetition or punching; or, when the rate matching method is truncation, determine the number of information bits of the second polar code sequence based on the number of truncated bits and the length of the first bit sequence.

[0315] In some embodiments, the processing unit 1201 is configured to: determine a first element index set, the first element index set including the NK with the lowest reliability in the second polar code sequence. t The indices of the elements, N is the length of the second polar code sequence, and K is the index of the element. t The number of information bits in the second polar code sequence is given; the union of the first element index set and the first frozen bit index set is taken as the fourth frozen bit index set; the number of information bits in the second polar code sequence is corrected based on the number of elements in the fourth frozen bit index set to obtain the corrected number of information bits; the information bit index set in the second polar code sequence is determined based on the corrected number of information bits.

[0316] In some embodiments, the processing unit 1201 is configured to: determine a first subcode that does not meet the fast decoding condition and a second subcode associated with the first subcode from a plurality of subcodes of the second polar code sequence; adjust a portion of the information bits in the first subcode to frozen bits, and adjust a portion of the frozen bits in the second subcode to information bits.

[0317] In some embodiments, the processing unit 1201 is configured to: adjust the d information bits with the lowest reliability in the first subcode to frozen bits; and adjust the d frozen bits with the highest reliability in the second subcode to information bits, where d is a positive integer.

[0318] In some embodiments, the processing unit 1201 is used to take the union between the first frozen bit index set and the second frozen bit index set as the third frozen bit index set.

[0319] In some embodiments, the processing unit 1201 is configured to redetermine the second frozen bit index set when the number of elements in the third frozen bit index set is not equal to a preset number, until the number of elements in the third frozen bit index set is equal to the preset number.

[0320] In some embodiments, the processing unit 1201 is configured to: obtain a first polar code sequence based on a third frozen bit index set and a first bit sequence; and encode the first polar code sequence based on a generator matrix to obtain a second bit sequence.

[0321] For example, taking a communication device as the second node in the above method embodiment as an example, Figure 13 is a schematic diagram of the structure of a second node according to some embodiments. The second node can execute the decoding method provided in the above method embodiment. As shown in Figure 13, the second node 130 includes: a processing unit 1301 and a communication unit 1302.

[0322] The communication unit 1302 is used to receive the third bit sequence from the first node.

[0323] The processing unit 1301 is used to determine the rate matching mode, and to perform rate recovery on the third bit sequence based on the rate matching mode to obtain the second bit sequence.

[0324] Processing unit 1301 is also used to determine the first set of frozen bit indices based on the rate matching method.

[0325] Processing unit 1301 is also used to determine the second set of frozen bit indices based on fast decoding conditions.

[0326] Processing unit 1301 is also used to determine a third frozen bit index set based on the first frozen bit index set and the second frozen bit index set.

[0327] Processing unit 1301 is also used to perform polar code decoding on the second bit sequence based on the third frozen bit index set to obtain the first bit sequence.

[0328] In some embodiments, rate matching methods include: repeating, truncating, and punching.

[0329] In some embodiments, the processing unit 1301 is used to determine the rate matching method based on the length of the first bit sequence, the length of the second bit sequence, and the length of the third bit sequence.

[0330] In some embodiments, the processing unit 1301 is configured to: determine the number of information bits in the second polar code sequence; determine the information bit index set in the second polar code sequence based on the number of information bits in the second polar code sequence; adjust the position of the information bits in the second polar code sequence based on the fast decoding condition to obtain the adjusted information bit index set; and determine the second frozen bit index set based on the adjusted information bit index set.

[0331] In some embodiments, the processing unit 1301 is used to determine the number of information bits of the second polar code sequence based on the length of the first bit sequence and the rate matching method.

[0332] In some embodiments, the processing unit 1301 is configured to determine the number of information bits of the second polar code sequence based on the length of the first bit sequence when the rate matching method is repetition or punching; or, when the rate matching method is truncation, to determine the number of information bits of the second polar code sequence based on the number of truncated bits and the length of the first bit sequence.

[0333] In some embodiments, the processing unit 1301 is configured to: determine a first element index set, the first element index set including the NK with the lowest reliability in the second polar code sequence. t The indices of the elements, N is the length of the second polar code sequence, and K is the index of the element. t The number of information bits in the second polar code sequence is given; the union of the first element index set and the first frozen bit index set is taken as the fourth frozen bit index set; the number of information bits in the second polar code sequence is corrected based on the number of elements in the fourth frozen bit index set to obtain the corrected number of information bits; the information bit index set in the second polar code sequence is determined based on the corrected number of information bits.

[0334] In some embodiments, the processing unit 1301 is configured to: determine a first subcode that does not meet the fast decoding condition and a second subcode associated with the first subcode from a plurality of subcodes of the second polar code sequence; adjust a portion of the information bits in the first subcode to frozen bits, and adjust a portion of the frozen bits in the second subcode to information bits.

[0335] In some embodiments, the processing unit 1301 is configured to: adjust the d information bits with the lowest reliability in the first subcode to frozen bits; and adjust the d frozen bits with the highest reliability in the second subcode to information bits, where d is a positive integer.

[0336] In some embodiments, the processing unit 1301 is used to take the union between the first frozen bit index set and the second frozen bit index set as the third frozen bit index set.

[0337] In some embodiments, the processing unit 1301 is configured to redetermine the second frozen bit index set when the number of elements in the third frozen bit index set is not equal to a preset number, until the number of elements in the third frozen bit index set is equal to the preset number.

[0338] In some embodiments, the processing unit 1301 is configured to: determine the subcode types of multiple subcodes of the second bit sequence; decode the multiple subcodes based on the fast decoding algorithm corresponding to the subcode types of the multiple subcodes to obtain the first bit sequence.

[0339] In the case of implementing the functions of the integrated modules described above in hardware, this disclosure provides another structure of the communication device involved in the above embodiments. As shown in FIG14, the communication device 140 includes: a processor 1402 and a bus 1404. In some embodiments, the communication device 140 may further include a memory 1401; in some embodiments, the communication device 140 may further include a communication interface 1403.

[0340] Processor 1402 may implement or execute various exemplary logic blocks, modules, and circuits described in connection with embodiments of this disclosure. Processor 1402 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Processor 1402 may implement or execute various exemplary logic blocks, modules, and circuits described in connection with embodiments of this disclosure. Processor 1402 may also be a combination of functions implementing computation, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0341] Communication interface 1403 is used to connect to other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0342] The memory 1401 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0343] In one implementation, the memory 1401 can exist independently of the processor 1402. The memory 1401 can be connected to the processor 1402 via a bus 1404 and is used to store instructions or program code. When the processor 1402 calls and executes the instructions or program code stored in the memory 1401, it can implement the method described in any embodiment of this disclosure.

[0344] In another implementation, the memory 1401 can also be integrated with the processor 1402.

[0345] Bus 1404 can be an extended industry standard architecture (EISA) bus, etc. Bus 1404 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in Figure 14, but this does not mean that there is only one bus or one type of bus.

[0346] Some embodiments of this disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) storing computer program instructions that, when executed on a computer, cause the computer to perform the methods described in any of the above embodiments.

[0347] Exemplary examples show that the aforementioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices for storing information and / or other machine-readable storage media. The term "machine-readable storage media" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0348] This disclosure provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods described in any of the above embodiments.

[0349] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An encoding method, wherein, The method is applied to the first node and includes: Obtain the first bit sequence; Determine the rate matching method, and based on the rate matching method, determine the first set of frozen bit indices; Based on the fast decoding conditions, determine the second set of frozen bit indices; Based on the first frozen bit index set and the second frozen bit index set, a third frozen bit index set is determined; Based on the third frozen bit index set, the first bit sequence is polar-coded to obtain the second bit sequence; Based on the rate matching method, the second bit sequence is rate matched to obtain the third bit sequence.

2. The method according to claim 1, wherein, The rate matching methods include: repetition, truncation, and drilling.

3. The method according to claim 2, wherein, Determining the rate matching method includes: The rate matching method is determined based on the lengths of the first bit sequence, the second bit sequence, and the third bit sequence.

4. The method according to claim 1, wherein, The determination of the second frozen bit index set based on the fast decoding condition includes: Determine the number of information bits in the second polarization code sequence; Based on the number of information bits in the second polar code sequence, determine the set of information bit indices in the second polar code sequence; Based on the fast decoding conditions, the positions of the information bits in the second polar code sequence are adjusted to obtain the adjusted information bit index set. Based on the adjusted set of information bit indices, the second set of frozen bit indices is determined.

5. The method according to claim 4, wherein, Determining the number of information bits in the second polarization code sequence includes: The number of information bits in the second polar code sequence is determined based on the length of the first bit sequence and the rate matching method.

6. The method according to claim 5, wherein, Determining the number of information bits in the second polar code sequence based on the length of the first bit sequence and the rate matching method includes: When the rate matching method is repetition or perforation, the length of the first bit sequence is used to determine the number of information bits in the second polar code sequence; or... When the rate matching method is truncation, the number of information bits in the second polar code sequence is determined based on the number of truncated bits and the length of the first bit sequence.

7. The method according to claim 4, wherein, The step of determining the information bit index set in the second polar code sequence based on the number of information bits in the second polar code sequence includes: Determine a first set of element indices, which includes the NK element with the lowest reliability in the second polar code sequence. t The index of each element, where N is the length of the second polar code sequence, and K... t The number of information bits in the second polar code sequence; The union of the first element index set and the first frozen bit index set is used as the fourth frozen bit index set; Based on the number of elements in the fourth frozen bit index set, the number of information bits in the second polar code sequence is corrected to obtain the corrected number of information bits. Based on the corrected number of information bits, the set of information bit indices in the second polar code sequence is determined.

8. The method according to claim 4, wherein, The step of adjusting the position of information bits in the second polar code sequence based on the fast decoding condition includes: From a plurality of subcodes in the second polar code sequence, determine a first subcode that does not satisfy the fast decoding condition, and a second subcode associated with the first subcode; Some information bits in the first subcode are adjusted to be frozen bits, and some frozen bits in the second subcode are adjusted to be information bits.

9. The method according to claim 8, wherein, The step of adjusting a portion of the information bits in the first sub-code to frozen bits, and adjusting a portion of the frozen bits in the second sub-code to information bits, includes: Adjust the d information bits with the lowest reliability in the first sub-code to freeze bits; The d frozen bits with the highest reliability in the second sub-code are adjusted to information bits, where d is a positive integer.

10. The method according to claim 1, wherein, The step of determining the third frozen bit index set based on the first frozen bit index set and the second frozen bit index set includes: The third frozen bit index set is the union of the first frozen bit index set and the second frozen bit index set.

11. The method of claim 10, further comprising: If the number of elements in the third frozen bit index set is not equal to the preset number, the second frozen bit index set is redefined until the number of elements in the third frozen bit index set is equal to the preset number.

12. The method according to claim 1, wherein, The step of polar coding the first bit sequence based on the third frozen bit index set to obtain the second bit sequence includes: Based on the third frozen bit index set and the first bit sequence, the first polar code sequence is obtained; The first polar code sequence is encoded based on the generator matrix to obtain the second bit sequence.

13. A decoding method, wherein, The method is applied to the second node and includes: Receive the third bit sequence from the first node; Determine the rate matching method, and perform rate recovery on the third bit sequence based on the rate matching method to obtain the second bit sequence; Based on the rate matching method, determine the first set of frozen bit indices; Based on the fast decoding conditions, determine the second set of frozen bit indices; Based on the first frozen bit index set and the second frozen bit index set, a third frozen bit index set is determined; Based on the third frozen bit index set, the second bit sequence is polar-coded to obtain the first bit sequence.

14. The method according to claim 13, wherein, The rate matching methods include: repetition, truncation, and drilling.

15. The method according to claim 14, wherein, Determining the rate matching method includes: The rate matching method is determined based on the lengths of the first bit sequence, the second bit sequence, and the third bit sequence.

16. The method according to claim 13, wherein, The determination of the second frozen bit index set based on the fast decoding condition includes: Determine the number of information bits in the second polarization code sequence; Based on the number of information bits in the second polar code sequence, determine the set of information bit indices in the second polar code sequence; Based on the fast decoding conditions, the positions of the information bits in the second polar code sequence are adjusted to obtain the adjusted information bit index set. Based on the adjusted set of information bit indices, the second set of frozen bit indices is determined.

17. The method according to claim 16, wherein, Determining the number of information bits in the second polarization code sequence includes: The number of information bits in the second polar code sequence is determined based on the length of the first bit sequence and the rate matching method.

18. The method according to claim 17, wherein, Determining the number of information bits in the second polar code sequence based on the length of the first bit sequence and the rate matching method includes: When the rate matching method is repetition or perforation, the length of the first bit sequence is used to determine the number of information bits in the second polar code sequence; or... When the rate matching method is truncation, the number of information bits in the second polar code sequence is determined based on the number of truncated bits and the length of the first bit sequence.

19. The method of claim 16, wherein, The step of determining the information bit index set in the second polar code sequence based on the number of information bits in the second polar code sequence includes: Determine a first set of element indices, which includes the NK element with the lowest reliability in the second polar code sequence. t The index of each element, where N is the length of the second polar code sequence, and K... t The number of information bits in the second polar code sequence; The union of the first element index set and the first frozen bit index set is used as the fourth frozen bit index set; Based on the number of elements in the fourth frozen bit index set, the number of information bits in the second polar code sequence is corrected to obtain the corrected number of information bits. Based on the corrected number of information bits, the set of information bit indices in the second polar code sequence is determined.

20. The method of claim 16, wherein, The step of adjusting the position of information bits in the second polar code sequence based on the fast decoding condition includes: From a plurality of subcodes in the second polar code sequence, determine a first subcode that does not satisfy the fast decoding condition, and a second subcode associated with the first subcode; Some information bits in the first subcode are adjusted to be frozen bits, and some frozen bits in the second subcode are adjusted to be information bits.

21. The method according to claim 20, wherein, The step of adjusting a portion of the information bits in the first sub-code to frozen bits, and adjusting a portion of the frozen bits in the second sub-code to information bits, includes: Adjust the d information bits with the lowest reliability in the first sub-code to freeze bits; The d frozen bits with the highest reliability in the second sub-code are adjusted to information bits, where d is a positive integer.

22. The method according to claim 13, wherein, The step of determining the third frozen bit index set based on the first frozen bit index set and the second frozen bit index set includes: The third frozen bit index set is the union of the first frozen bit index set and the second frozen bit index set.

23. The method of claim 22, further comprising: If the number of elements in the third frozen bit index set is not equal to the preset number, the second frozen bit index set is redefined until the number of elements in the third frozen bit index set is equal to the preset number.

24. The method according to claim 13, wherein, The step of performing polar code decoding on the second bit sequence based on the third frozen bit index set to obtain the first bit sequence includes: Determine the subcode type of multiple subcodes in the second bit sequence; The first bit sequence is obtained by decoding the multiple subcodes using a fast decoding algorithm corresponding to the subcode type of the multiple subcodes.

25. A communication device, comprising: Memory and processor; The memory and the processor are coupled; The memory is used to store instructions that can be executed by the processor; When the processor executes the instructions, it performs the method according to any one of claims 1 to 12, or the method according to any one of claims 13 to 24.

26. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 12, or the method according to any one of claims 13 to 24.

27. A computer program product, wherein, The computer program product includes computer program instructions that, when executed by a processor, implement the method according to any one of claims 1 to 12, or perform the method according to any one of claims 13 to 24.

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