Solar cell and photovoltaic module

Abstract

The present disclosure is suitable for the technical field of solar power generation, and provides a solar cell and a photovoltaic module. The solar cell comprises a silicon wafer and fingers provided thereon. The fingers comprise first fingers and second fingers that are distributed alternately in a first direction. The silicon wafer has a first edge, a second edge, a third edge and a fourth edge. A first inclined edge connects the first edge and the third edge, a first connecting line being adjacent to the first inclined edge. The first connecting line is connected to the first fingers or the second fingers. The distance between the points of intersection of the first inclined edge and the first and third edges is less than or equal to 2.5 millimeters. The number of the first fingers or second fingers connected to the first connecting line is less than or equal to four. The first inclined edge is made very small, so that the first connecting line at the first inclined edge is relatively short and can only be connected to four or less of the first fingers or second fingers, ensuring the active area of the cell as much as possible so as to ensure the conversion efficiency of the cell.

Description

Solar cells and photovoltaic modules

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application No. 202420895917.1, filed on April 26, 2024, with the China National Intellectual Property Administration and entitled "Gridless Back Contact Solar Cell, Battery Module and Photovoltaic System", and Chinese patent application No. 202411028463.9, filed on July 29, 2024, with the China National Intellectual Property Administration and entitled "Solar Cell and Photovoltaic Module", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure pertains to the field of solar power generation technology, and particularly relates to a solar cell and a photovoltaic module. Background Technology

[0004] Solar cells are devices that directly convert light energy into electrical energy through the photoelectric effect. Crystalline silicon cells use silicon wafers as substrates and are classified into P-type and N-type cells based on the differences in silicon wafers. The power generation principle of these two types of cells is not fundamentally different; both rely on the separation of photogenerated carriers through a PN junction.

[0005] In the manufacturing process of solar cells, crystal pillars are cut and smoothed to obtain wafers of suitable size and shape. Subsequent etching, polishing, cleaning, and evaluation processes yield qualified silicon wafers. For silicon wafers, the size of the front side (light-receiving surface) plays a crucial role in power conversion efficiency. Using square silicon wafers is the optimal choice. Furthermore, when silicon wafers are arranged in a square array, the gaps between adjacent wafers are very small or even nonexistent, ensuring high power generation efficiency.

[0006] Existing silicon wafers all undergo chamfering, which reduces central stress at the edges, making them more robust. However, the chamfers on existing silicon wafers are typically quite large, resulting in a smaller light-receiving surface area and impacting power generation efficiency. Summary of the Invention

[0007] This disclosure provides a solar cell and a photovoltaic module, aiming to solve the problem that the small light-receiving surface area of ​​existing solar cells affects power generation efficiency.

[0008] This disclosure is implemented as follows: a solar cell includes:

[0009] A silicon wafer having a plurality of fine gates disposed thereon, the fine gates including a first fine gate and a second fine gate alternately distributed along a first direction;

[0010] Silicon wafers have:

[0011] The first edge and the second edge are arranged opposite each other along the second direction, and the third edge and the fourth edge are arranged opposite each other along the first direction, wherein the second direction is perpendicular to the first direction;

[0012] The first inclined edge connecting the first edge and the third edge; and

[0013] A first connecting line is disposed near the first inclined edge, and the first connecting line is connected to at least one first fine grid or at least one second fine grid;

[0014] The intersection of the first inclined edge and the first edge is the first intersection point, and the intersection of the first inclined edge and the third edge is the second intersection point. The distance between the first intersection point and the second intersection point is less than or equal to 2.5 mm, and the number of the first fine grid or the second fine grid connected by the first connecting line is less than or equal to four.

[0015] In some embodiments, the first inclined edge is a straight line or an arc.

[0016] In some embodiments, the first connecting line is not parallel to the first inclined edge.

[0017] In some embodiments, the first connecting line includes a first connecting portion and a second connecting portion, wherein the width of the first connecting portion is smaller than the width of the second connecting portion.

[0018] In some embodiments, the first connecting portion and the second connecting portion are connected, and the first connecting portion is a diagonal line.

[0019] In some embodiments, the second connecting portion and the first connecting portion are connected by a thin grid.

[0020] In some embodiments, the second connecting portion and the first connecting portion are parallel to the first direction.

[0021] In some embodiments, the ratio of the width of the fine grid to the width of the first connecting line is 1:1.2 to 1:2.

[0022] In some embodiments, the ratio of the width of the fine grid to the width of the first connecting line is 1:1.6-1:1.8.

[0023] In some embodiments, the distance between the first intersection point and the second intersection point is 0.7 mm to 2.5 mm.

[0024] In some embodiments, the distance between the first intersection point and the second intersection point is 1.2 mm to 1.6 mm.

[0025] In some embodiments, the silicon wafer includes a second angled edge connecting the first edge and the fourth edge;

[0026] A second connection line is provided on the silicon wafer adjacent to the second inclined edge, and the second connection line is connected to at least one first fine gate or at least one second fine gate;

[0027] The first and second connecting lines are connected to a fine grid with the same polarity.

[0028] In some embodiments, the silicon wafer includes a third inclined edge connecting the second edge and the third edge;

[0029] A third connection line is provided on the silicon wafer adjacent to the third inclined edge, and the third connection line is connected to at least one first fine gate or at least one second fine gate;

[0030] The first and third connecting lines are connected to a fine gate with opposite polarities.

[0031] In some embodiments, the angle between the first connecting line and the second direction is greater than the angle between the third connecting line and the second direction.

[0032] In some embodiments, the first connecting line is connected to the first fine gate, and along the second direction, the distance between the endpoint of the second fine gate adjacent to the first connecting line and the first connecting line is less than the distance between the first connecting line and the first inclined edge; or

[0033] The first connecting line is connected to the second fine grid. Along the second direction, the distance between the endpoint of the first fine grid adjacent to the first connecting line and the first connecting line is less than the distance between the first connecting line and the first inclined edge.

[0034] In some embodiments, along the second direction, the distance between the first connecting line and the first inclined edge is greater than the distance between the third connecting line and the third inclined edge.

[0035] In some embodiments, the first connecting line is connected to the first fine gate, and the third connecting line is connected to the second fine gate;

[0036] Along the second direction, the width of the first connecting line is less than the width of the third connecting line.

[0037] In some embodiments, the linewidth of the second fine gate is greater than the linewidth of the first fine gate.

[0038] Secondly, this disclosure also provides a photovoltaic module, including the solar cell as described above.

[0039] The beneficial effect of this disclosure is that the solar cell includes a silicon wafer and fine grids disposed on the silicon wafer (an intermediate layer may be disposed between the fine grids and the silicon wafer). The fine grids include first and second fine grids alternately distributed along a first direction. The silicon wafer has a first edge and a second edge disposed opposite to each other along a second direction, and a third edge and a fourth edge disposed opposite to each other along the first direction. The second direction is perpendicular to the first direction. A first inclined edge connects the first edge and the third edge. A first connecting line is adjacent to the first inclined edge and connects to the first or second fine grid. The intersection of the first inclined edge and the first edge is the first intersection point, and the intersection of the first inclined edge and the third edge is the second intersection point. The distance between the first intersection point and the second intersection point is less than or equal to 2.5 mm. The number of first or second fine grids connected by the first connecting line is less than or equal to four. Through the above arrangement, the first inclined edge can be made very small, thereby making the first connecting line located at the first inclined edge shorter, connecting only less than or equal to four first or second fine grids, maximizing the light-receiving area of ​​the solar cell and ensuring the conversion efficiency of the solar cell. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the modules of the photovoltaic system provided in an embodiment of this disclosure;

[0041] Figure 2 is a schematic diagram of the battery assembly provided in an embodiment of this disclosure;

[0042] Figure 3 is a schematic diagram of the back surface structure of the solar cell provided in an embodiment of this disclosure;

[0043] Figure 4 is a partially enlarged schematic diagram of the solar cell in Figure 3 at the first conductive contact structure.

[0044] Figure 5 is another enlarged schematic diagram of the solar cell in Figure 3 at the first conductive contact structure.

[0045] Figure 6 is another partially enlarged schematic diagram of the solar cell in Figure 3 at the first conductive contact structure;

[0046] Figure 7 is another partially enlarged schematic diagram of the solar cell in Figure 3 at the first conductive contact structure.

[0047] Figure 8 is a partially enlarged schematic diagram of the solar cell in Figure 3 at the second conductive contact structure;

[0048] Figure 9 is another enlarged schematic diagram of the solar cell in Figure 3 at the second conductive contact structure;

[0049] Figure 10 is another partially enlarged schematic diagram of the solar cell in Figure 3 at the second conductive contact structure;

[0050] Figure 11 is another partially enlarged schematic diagram of the solar cell in Figure 3 at the second conductive contact structure;

[0051] Figure 12 is another planar structural diagram of the back side of the solar cell provided in the embodiment of this disclosure;

[0052] Figure 13 is another planar structural diagram of the back side of the solar cell provided in the embodiment of this disclosure.

[0053] Figure 14 is a schematic diagram of the structure of a solar cell according to an embodiment of the present disclosure;

[0054] Figure 15 is an enlarged schematic diagram of part A in Figure 14;

[0055] Figure 16 is an enlarged schematic diagram of part B in Figure 14;

[0056] Figure 17 is a schematic diagram of a solar cell with an arc-shaped chamfered edge according to an embodiment of the present disclosure;

[0057] Figure 18 is a schematic diagram of a solar cell embodiment provided in this disclosure, where the chamfered edge is a combination of arc and straight lines;

[0058] Figure 19 is a schematic diagram of a stepped structure of a solar cell according to an embodiment of the present disclosure;

[0059] Figure 20 is a schematic diagram of the linewidth between the grid and the connecting lines in an embodiment of the solar cell provided in this disclosure;

[0060] Figure 21 is an enlarged schematic diagram of part C in Figure 14;

[0061] Figure 22 is a schematic diagram of the structure of the first tilted edge of a solar cell according to an embodiment of the present disclosure;

[0062] Figure 23 is a schematic diagram of the structure of the first tilted edge of an embodiment of the solar cell provided in this disclosure. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0064] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “left”, “right”, “horizontal”, “top”, “bottom”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0067] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0068] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0069] The solar cell disclosed herein includes a silicon wafer and fine grids disposed on the silicon wafer (an intermediate layer may be disposed between the fine grids and the silicon wafer). The fine grids include a first fine grid and a second fine grid alternately distributed along a first direction. The silicon wafer has a first edge and a second edge disposed opposite to each other along a second direction, and a third edge and a fourth edge disposed opposite to each other along the first direction. The second direction is perpendicular to the first direction. A first inclined edge connects the first edge and the third edge. A first connecting line is adjacent to the first inclined edge and connects to the first fine grid or the second fine grid. The intersection of the first inclined edge and the first edge is the first intersection point, and the intersection of the first inclined edge and the third edge is the second intersection point. The distance between the first intersection point and the second intersection point is less than or equal to 2.5 mm. The number of first fine grids or second fine grids connected by the first connecting line is less than or equal to four. Through the above arrangement, the first inclined edge can be made very small, thereby making the first connecting line located at the first inclined edge shorter, connecting only less than or equal to four first fine grids or second fine grids, maximizing the light-receiving area of ​​the solar cell and ensuring the conversion efficiency of the solar cell.

[0070] Example 1

[0071] Referring to Figures 1 and 2, the photovoltaic system 1000 in this embodiment may include the battery module 200 of this embodiment. The battery module 200 may include a plurality of battery strings, and the battery strings may include a plurality of gridless back-contact solar cells 100 of this embodiment. In this disclosure, the plurality of gridless back-contact solar cells 100 in the battery module 200 can be sequentially connected together by solder strips to form a battery string. The battery strings in the battery module 200 can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between the battery strings can be achieved by busbars.

[0072] Please refer to Figure 3. The gridless back contact solar cell 100 in this embodiment may include a silicon wafer 10, a plurality of first fine grids 20, a plurality of second fine grids 30, a plurality of first conductive contact structures 40 and a plurality of second conductive contact structures 50.

[0073] The silicon wafer 10 has a front side and a back side 11. The back side 11 has a plurality of first regions 111 and a plurality of second regions 112. A plurality of first grids 20 and a plurality of second grids 30 are disposed on the back side 11 of the silicon wafer 10. The plurality of first grids 20 and the plurality of second grids 30 are arranged alternately along a first direction, and both the first grids 20 and the second grids 30 extend along a second direction, which intersects the first direction. Specifically, as shown in FIG3, the first direction and the second direction can be the longitudinal direction and the transverse direction of the gridless back contact solar cell 100, respectively. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon wafer 10, and there is no specific limitation here.

[0074] A first conductive contact structure 40 is disposed within a first region 111, and is connected to a plurality of first fine gates 20. A second fine gate 30 is disconnected at the first conductive contact structure 40. A second conductive contact structure 50 is disposed within a second region 112, and is connected to a plurality of second fine gates 30. A first fine gate 20 is disconnected at the second conductive contact structure 50.

[0075] In the gridless back-contact solar cell 100, cell module 200, and photovoltaic system 1000 of this disclosure, on the back side 11 of the silicon wafer 10, in a first region 111 and a second region 112, a first conductive contact structure 40 is disposed in the first region 111 and connected to a plurality of first fine grids 20, and a second conductive contact structure 50 is disposed in the second region 112 and connected to a plurality of second fine grids 30. The first conductive contact structure 40 and the second conductive contact structure 50 can be used to contact the positive and negative electrode probes of the test equipment, respectively. Thus, by providing a plurality of first conductive contact structures 40 and a plurality of second conductive contact structures 50, the first conductive contact structures 40 and the second conductive contact structures 50 have a larger area than a single first fine grid 20 and a single fine grid 30. When performing hot spot, EL, and other tests on the gridless back-contact solar cell 100, the positive and negative electrode probes of the test equipment can form a stable contact with the first conductive contact structures 40 and the second conductive contact structures 50, reducing the difficulty of testing and improving the reliability and stability of testing. Meanwhile, during subsequent welding of the welding strip, the first conductive contact structure 40 and the second conductive contact structure 50 can serve as welding points with the welding strip. Since the first conductive contact structure 40 and the second conductive contact structure 50 are respectively connected to a number of first fine grids 20 and a number of second fine grids 30, it is not necessary to set welding points or welding layers on all the fine grids during welding, which can reduce the use of welding paste.

[0076] Specifically, it can be understood that in this disclosure, the back side 11 of the silicon wafer 10 has a plurality of first doped layers (not shown) and second doped layers (not shown), which are respectively P-type doped layers and N-type doped layers. A back passivation layer (not shown) is provided on the first doped layers and the second doped layers. A first fine gate 20 is correspondingly disposed above the first doped layer and penetrates the back passivation layer to form an ohmic contact with the first doped layer. A second fine gate 30 is correspondingly disposed on the second doped layer and penetrates the back passivation layer to form an ohmic contact with the second doped layer.

[0077] Taking hot spot testing as an example, when conducting hot spot testing on the gridless back contact solar cell 100 of this disclosure, the positive and negative probes of the testing equipment can form stable contact with the first conductive contact structure 40 and the second conductive contact structure 50, respectively. Then, the scenario of the gridless back contact solar cell 100 being shaded is simulated to observe the temperature at various points of the gridless back contact solar cell 100.

[0078] In some embodiments, the area of ​​the first region 111 can be 5-60 mm2, that is, the orthogonal projection area of ​​the first conductive contact structure 40 on the back surface 11 can be 5-60 mm2.

[0079] Thus, by setting the area of ​​the first region 111 within this reasonable range, it is possible to avoid the first conductive contact structure 40 failing to form a stable contact with the test probe if the area of ​​the first region 111 is too small, and also to avoid the current collection efficiency being affected if the area of ​​the first region 111 is too large and the area without the metal grid on the back side 11 is too small.

[0080] Specifically, in such an embodiment, the area of ​​the first region 111 can be, for example, 5mm², 10mm², 15mm², 20mm², 25mm², 30mm², 35mm², 40mm², 45mm², 50mm², 55mm², 60mm², or any value between 5mm² and 60mm², without any specific limitation.

[0081] In some embodiments, the area of ​​the second region 112 can be 5-60 mm2, that is, the orthogonal projection area of ​​the second conductive contact structure 50 on the back surface 11 can be 5-60 mm2.

[0082] Thus, by setting the area of ​​the second region 112 within this reasonable range, it is possible to avoid the second conductive contact structure 50 failing to form a stable contact with the test probe if the area of ​​the second region 112 is too small, and also to avoid the current collection efficiency being affected if the area of ​​the second region 112 is too large and the area without the metal grid on the back side 11 is too small.

[0083] Specifically, in such an embodiment, the area of ​​the second region 112 can be any value between 5mm², 10mm², 15mm², 20mm², 25mm², 30mm², 35mm², 40mm², 45mm², 50mm², 55mm², and 60mm², and no specific limitation is made here.

[0084] In some embodiments, the first conductive contact structure 40 and the second conductive contact structure 50 may both be Pad points, that is, solder points used for welding with solder strips.

[0085] Thus, the first conductive contact structure 40 and the second conductive contact structure 50 can achieve stable and reliable contact with the test probe, and can also serve as solder joints for welding, thereby reducing the number of solder joints during subsequent welding.

[0086] Please refer to Figures 3-5. In some embodiments, the first conductive contact structure 40 may include a plurality of first conductive connecting lines 41 arranged at intervals along the second direction within the first region 111. The first conductive connecting lines 41 are intersected with and connected to a plurality of first fine gates 20.

[0087] Thus, the test probe only needs to contact any one of the first conductive connection lines 41 in the mesh structure within the first region 111 to form a stable electrical contact, thereby improving the reliability of the contact.

[0088] In some embodiments, as shown in FIG5, in such an embodiment, a plurality of first conductive connection lines 41 and a plurality of first fine gates 20 form a first filling region 411; or

[0089] As shown in Figure 6, a number of first conductive connecting lines 41 intersect with a number of first fine grids 20 to form a first mesh structure 412.

[0090] Thus, the first conductive connection line 41 and several first fine grids 20 form a first filling region 411 or a first mesh structure 412. During testing, the test probe only needs to contact any one of the first conductive connection lines 41 in the first region 111 or any one of the first conductive connection lines 41 in the first mesh structure 412 and the first fine grid 20 to form a stable electrical contact, thereby improving the reliability of the contact.

[0091] Furthermore, as shown in Figures 6 and 7, in some embodiments, to further improve the contact stability of the test probe, the first conductive contact structure 40 may also include a first conductive material 413 filled in the adjacent first filling region 411 or the first mesh structure 412. This increases the area of ​​the first conductive contact structure 40, thereby enabling the first conductive contact structure 40 to form a more reliable and stable contact with the test probe during testing. In such embodiments, when the first conductive contact structure 40 acts as a solder joint, the reliability of the soldering can be improved.

[0092] Of course, in some embodiments, the first conductive contact structure 40 may not be filled with the first conductive material 413. If the first conductive contact structure 40 is required to act as a solder joint, it can be filled with conductive welding materials such as solder in the first filling area 411 or the first mesh structure 412 during subsequent welding, so as to weld with the solder strip.

[0093] Please refer to Figures 8 and 9. In some embodiments, the second conductive contact structure 50 includes a plurality of second conductive connecting lines 51 arranged at intervals along the second direction within the second region 112. The second conductive connecting lines 51 are intersected with and connected to a plurality of second fine gates 30.

[0094] Thus, the test probe only needs to contact any one of the second conductive connection lines 51 in the mesh structure within the second region 112 to form a stable electrical contact, thereby improving the reliability of the contact.

[0095] In some embodiments, as shown in FIG9, in such an embodiment, a plurality of second conductive connection lines 51 and a plurality of second fine gates 30 form a second filling region 511; or

[0096] As shown in Figure 8, a number of second conductive connecting lines 51 intersect with a number of second fine grids 30 to form a second mesh structure 512.

[0097] Thus, the second conductive connection line 51 and several second fine grids 30 form a second filling region 511 or a second mesh structure 512. During testing, the test probe only needs to contact any one of the second conductive connection lines 51 in the second region 112 or any one of the second conductive connection lines 51 in the second mesh structure 512 and the second fine grid 30 to form a stable electrical contact, thereby improving the reliability of the contact.

[0098] Furthermore, as shown in Figures 10 and 11, in some embodiments, to further improve the contact stability of the test probe, the second conductive contact structure 50 may also include a second conductive material 513 filled in the adjacent second filling region 511 or the second mesh structure 512. This increases the area of ​​the second conductive contact structure 50, thereby enabling the second conductive contact structure 50 to form a more reliable and stable contact with the test probe during testing. Furthermore, in such embodiments, when the second conductive contact structure 50 acts as a solder joint, the reliability of the soldering can be improved.

[0099] Of course, in some embodiments, the second conductive contact structure 50 may not be filled with the second conductive material 513. If the second conductive contact structure 50 is required to act as a solder joint, it can be filled with conductive welding materials such as solder in the second filling area 511 or the second mesh structure 512 during subsequent welding, so as to weld with the solder strip.

[0100] Please refer to Figures 3-5. In some embodiments, each first conductive contact structure 40 is connected to 2-7 first fine gates 20.

[0101] In this way, the first conductive contact structure 40 can have a relatively large area. When it acts as a solder joint, the number of solder joints can be reduced by 2-7, thereby reducing the use of solder paste and improving the reliability of the soldering. It can also avoid the problem of too many first fine grids 20 connected to the first conductive contact structure 40, which would result in a large transmission loss.

[0102] Specifically, in such embodiments, the number of first fine gates 20 connected to each first conductive contact structure 40 can be, for example, 2, 3, 4, 5, 6, and 7. For example, as shown in FIG3, there are 7 first fine gates 20 connected to each first conductive contact structure 40.

[0103] Please refer to Figures 3, 8 and 9. In some embodiments, each second conductive contact structure 50 is connected to 2-7 second fine grids 30.

[0104] In this way, the second conductive contact structure 50 can have a relatively large area. When it acts as a solder joint, the number of solder joints can be reduced by 2-7, thereby reducing the use of slurry and improving the reliability of the soldering. It can also avoid the excessive number of second fine grids 30 connected to the second conductive contact structure 50, which would lead to greater transmission loss.

[0105] Specifically, in such embodiments, the number of second fine gates 30 connected to each second conductive contact structure 50 can be, for example, 2, 3, 4, 5, 6, and 7. For example, as shown in FIG3, there are 7 second fine gates 30 connected to each second conductive contact structure 50.

[0106] As described above, in some embodiments, the first conductive contact structure 40 and the second conductive contact structure 50 can both be used for welding to the solder joint. Specifically, the first conductive contact structure 40 can be welded to the solder strip used for merging and outputting the current collected by the first fine grid 20, and the second conductive contact structure 50 can be welded to the solder strip used for merging and outputting the current collected by the second fine grid 30.

[0107] Thus, the first conductive contact structure 40 and the second conductive contact structure 50 can serve as solder joints for the solder strip while achieving stable contact with the test probe, thus enabling functional reuse.

[0108] Specifically, in this case, the specific structures of the first conductive contact structure 40 and the second conductive contact structure 50 can be understood with reference to the above.

[0109] Please refer to Figure 3. In some embodiments, the silicon wafer 10 has a first edge 101 and a second edge 102 along a first direction. Both the first edge 101 and the second edge 102 have a plurality of first conductive contact structures 40 and second conductive contact structures 50.

[0110] At the first edge 101, a plurality of first conductive contact structures 40 and a plurality of second conductive contact structures 50 are arranged alternately along the second direction.

[0111] At the second edge 102, a plurality of first conductive contact structures 40 and a plurality of second conductive contact structures 50 are also arranged alternately along the second direction.

[0112] Thus, by placing both the first conductive contact structure 40 and the second conductive contact structure 50 on the edge of the silicon wafer 10, it is easy to make contact with the test probe.

[0113] In some embodiments, referring to FIG3, in such embodiments, a first conductive contact structure 40 located at the first edge 101 is connected to a first fine gate 20 closest to the first edge 101, and a second conductive contact structure 50 located at the first edge 101 is connected to a second fine gate 30 closest to the first edge 101; and / or

[0114] The first conductive contact structure 40 located at the second edge 102 is connected to the first fine gate 20 closest to the second edge 102, and the second conductive contact structure 50 located at the second edge 102 is connected to the second fine gate 30 closest to the second edge 102.

[0115] Thus, the first conductive contact structure 40 and the second conductive contact structure 50 are both located at the outermost edge of the first edge 101 and the outermost edge of the second edge 102. When the first conductive contact structure 40 and the second conductive contact structure 50 act as solder joints, they can serve as the starting point and / or the ending point during welding, thereby ensuring the stability of the welding.

[0116] Please refer to Figures 3 and 12. In some embodiments, the first conductive contact structure 40 located at the first edge 101 and the first conductive contact structure 40 located at the second edge 102 are aligned in a first direction.

[0117] The second conductive contact structure 50 located at the first edge 101 and the second conductive contact structure 50 located at the second edge 102 are aligned in the first direction.

[0118] Thus, the first conductive contact structure 40 of the first edge 101 is aligned with the first conductive contact structure 40 of the second edge 102, and the second conductive contact structure 50 of the first edge 101 is aligned with the second conductive contact structure 50 of the second edge 102. The two aligned first conductive contact structures 40 can respectively serve as the starting point and the ending point for welding the solder strip that carries the current of the first fine grid 20, and the two aligned second conductive contact structures 50 can respectively serve as the starting point and the ending point for welding the solder strip that carries the current of the second fine grid 30, thereby ensuring the reliability of the welding, and at the same time, there is no need to set additional starting points and ending points.

[0119] Referring to Figure 12, in some embodiments, between two first conductive contact structures 40 aligned in a first direction, there is also at least one first conductive contact structure 40 aligned with the first conductive contact structure 40 located at the first edge 101 and the second edge 102; and / or

[0120] Between the two second conductive contact structures 50 aligned in the first direction, there is also at least one second conductive contact structure 50 aligned with the second conductive contact structure 50 located at the first edge 101 and the second edge 102.

[0121] Thus, at least one first conductive contact structure 40 is provided between two first conductive contact structures 40 aligned in opposite directions. When the first conductive contact structure 40 acts as a solder joint, it can be welded to the solder joint by at least three first conductive contact structures 40, further ensuring the reliability of the welding. Similarly, at least one second conductive contact structure 50 is provided between two second conductive contact structures 50 aligned in opposite directions. When the second conductive contact structure 50 acts as a solder joint, it can be welded to the solder joint by at least three second conductive contact structures 50, further ensuring the reliability of the welding.

[0122] Please refer to Figures 3 and 4. In some embodiments, the silicon wafer 10 also has a third edge 103 and a fourth edge 104 opposite to each other along the second direction, and a first edge busbar 60 is provided at the third edge 103.

[0123] When the conductive contact structure closest to the third edge 103 along the first direction is the first conductive contact structure 40, the first edge busbar 60 connects the portion of the second fine gate 30 that is broken at the first conductive contact structure 40 located at the third edge 103 and at least one second fine gate 30 that is not broken at the first conductive contact structure 40.

[0124] When the conductive contact structure closest to the third edge 103 along the first direction is the second conductive contact structure 50, the first edge busbar 60 connects the portion of the first fine gate 20 that is broken at the second conductive contact structure 50 located at the third edge 103 and at least one first fine gate 20 that is not broken at the first conductive contact structure 40.

[0125] Specifically, the conductive contact structure closest to the third edge 103 along the first direction is the first conductive contact structure 40. When the first conductive contact structure 40 closest to the third edge 103 acts as a solder joint for welding with the solder strip, the second fine gate 30 needs to be disconnected at the first conductive contact structure 40. In this case, the current of the portion of the second fine gate 30 located between the first conductive contact structure 40 and the third edge 103 cannot be collected and converged. In this embodiment, by setting the first edge busbar 60, the current collected by this portion of the second fine gate 30 can be converged to at least one unbroken second fine gate 30, thereby realizing the convergence of the current of this portion of the fine gate and reducing efficiency loss.

[0126] The conductive contact structure closest to the third edge 103 along the first direction is the second conductive contact structure 50. When the second conductive contact structure 50 closest to the third edge 103 acts as a solder joint for welding with the solder strip, the first fine gate 20 needs to be disconnected at the second conductive contact structure 50. In this case, the current of the portion of the first fine gate 20 located between the second conductive contact structure 50 and the third edge 103 cannot be collected and combined. In this embodiment, by setting the first edge busbar 60, the current collected by this portion of the first fine gate 20 can be combined to at least one unbroken first fine gate 20, thereby realizing the current of this portion of the fine gate and reducing efficiency loss.

[0127] Please refer to Figures 3 and 8. In some embodiments, a second edge busbar 70 is provided at the fourth edge 104.

[0128] When the conductive contact structure closest to the fourth edge 104 along the first direction is the first conductive contact structure 40, the second edge busbar 70 connects the portion of the second fine gate 30 that is broken at the first conductive contact structure 40 located at the fourth edge 104 and at least one second fine gate 30 that is not broken at the first conductive contact structure 40.

[0129] When the conductive contact structure closest to the fourth edge 104 along the first direction is the second conductive contact structure 50, the second edge busbar 70 connects the portion of the first fine gate 20 that is broken at the second conductive contact structure 50 located at the fourth edge 104 and at least one first fine gate 20 that is not broken at the first conductive contact structure 40.

[0130] Specifically, the conductive contact structure closest to the fourth edge 104 along the first direction is the first conductive contact structure 40. When the first conductive contact structure 40 closest to the fourth edge 104 acts as a solder joint for welding with the solder strip, the second fine gate 30 needs to be disconnected at the first conductive contact structure 40. In this case, the current of the portion of the second fine gate 30 located between the first conductive contact structure 40 and the fourth edge 104 cannot be collected and combined. In this embodiment, by setting the second edge busbar 70, the current collected by this portion of the second fine gate 30 can be combined to at least one unbroken second fine gate 30, thereby realizing the current of this portion of the fine gate and reducing efficiency loss.

[0131] The conductive contact structure closest to the fourth edge 104 along the first direction is the second conductive contact structure 50. When the second conductive contact structure 50 closest to the fourth edge 104 acts as a solder joint for welding with the solder strip, the first fine gate 20 needs to be disconnected at the second conductive contact structure 50. In this case, the current of the portion of the first fine gate 20 located between the second conductive contact structure 50 and the fourth edge 104 cannot be collected and combined. In this embodiment, by setting the second edge busbar 70, the current collected by this portion of the first fine gate 20 can be combined to at least one unbroken first fine gate 20, thereby realizing the current of this portion of the fine gate and reducing efficiency loss.

[0132] Please refer to Figure 13. In some embodiments, the silicon wafer 10 has a first center line L1 and a second center line L2 that are perpendicular to each other. The first center line L1 is parallel to a second direction, and the second center line L2 is parallel to the first direction. In the first direction, the silicon wafer 10 is symmetrical about the first center line L1, and in the second direction, the silicon wafer 10 is symmetrical about the second center line L2.

[0133] Both the first conductive contact structure 40 and the second conductive contact structure 50 are disposed on the first center line L1. In the first direction, the portions of the first conductive contact structure 40 located on both sides of the first center line L1 are symmetrically arranged about the first center line L1, and the portions of the second conductive contact structure 50 located on both sides of the first center line L1 are also symmetrically arranged about the first center line L1.

[0134] Among them, the first fine grids 20 on both sides of the first center line L1 are symmetrical about the first center line L1, and the second fine grids 30 on both sides of the first center line L1 are also symmetrical about the first center line L1.

[0135] A first conductive contact structure 40 and a second conductive contact structure 50 are provided on both sides of the second center line L2. The first conductive contact structures 40 on both sides of the second center line L2 are symmetrically arranged about the second center line L2, and the second conductive contact structures 50 on both sides of the second center line L2 are also symmetrically arranged about the second center line L2.

[0136] In this way, rotational symmetry of the first conductive contact structure 40 and the second conductive contact structure 50 can be achieved. Thus, during the manufacturing process, after the first conductive contact structure 40 is printed and the first fine grid 20 and the second fine grid 30 are set, the gridless back contact solar cell 100 can be moved and replaced at will without the need for alignment and calibration.

[0137] Specifically, as shown in Figure 13, in this embodiment, the same number of first conductive contact structures 40 (e.g., 1, 2, or 3) are provided on both sides of the second center line L2. The first conductive contact structures 40 on both sides are symmetrical about the second center line L2. The same number of second conductive contact structures 50 are also provided, and the second conductive contact structures 50 on both sides are also symmetrical about the second center line L2. Furthermore, for each conductive contact structure, its center point is located on the first center line L1, and the portions of each conductive contact structure located on both sides of the first center line L1 are symmetrical about the first center line L1.

[0138] In some embodiments, in such embodiments, no additional fine gate may be provided at the first centerline L1. Of course, in order to maximize the utilization of the area of ​​the silicon wafer 10, a central fine gate 80 may also be provided at the first centerline L1. The central fine gate 80 has the same polarity as the fine gates (first fine gate 20 or second fine gate 30, FIG. 13 shows the second fine gate 30) of the two edges (i.e., the first edge 101 and the second edge 102) closest to the silicon wafer 10 in the first direction.

[0139] Thus, by setting a central fine gate 80 with the same polarity as the fine gates closest to the first edge 101 and the second edge 102, all fine gates on both sides of the center gate line can be symmetrical about the central fine gate 80, thereby achieving the purpose of being able to move and interchange during the setting of the fine gates. It is easy to understand that in such an embodiment, a doped layer corresponding to its polarity can be present below the central fine gate 80, and the central fine gate 80 penetrates the passivation layer and contacts the underlying doped layer, thereby improving area utilization and current collection capability.

[0140] Specifically, as shown in Figure 13, when the fine gates closest to the first edge 101 and the second edge 102 are both second fine lines 30, the central fine gate 80 is the same gate line as the second fine gate 30. This is equivalent to the first fine gate 20 and the second fine gate 30 being evenly spaced and alternately arranged on the silicon wafer 10, with the fine gates located at the upper and lower edges in the first direction being both second fine gates 30. There are N second fine gates 30, and N-1 first fine gates 20. The extra second gate line 30 is the central fine gate 80 that coincides with the first center line L1. Similarly, when the fine gates closest to the first edge 101 and the second edge 102 are both first fine lines 20, the central fine gate 80 is a fine gate with the same polarity as the first fine gate 20. The specifics will not be elaborated here.

[0141] Please continue referring to Figure 13. In this embodiment, the first conductive contact structure 40 may include a first Pad point 401 located on the first center line L1 and two first connecting lines 402 connected to the two ends of the first Pad point and extending along the first direction. The first connecting lines 402 are connected to at least one first fine gate 20. The second conductive contact structure 50 may include a second Pad point 501 located on the first center line L1 and two second connecting lines 502 connected to the two ends of the second Pad point 501 and extending along the first direction. The second connecting lines 502 are connected to at least one second fine gate 30.

[0142] In this way, stable contact with the probe can be achieved through the pad point, and then a portion of the fine grid can be connected through the connecting wire, thereby achieving stable testing of electrical performance and hot spots.

[0143] In some embodiments, the width of the first connecting line 402 may be greater than the width of the first fine gate 20, and the width of the second connecting line 502 may be greater than the width of the second fine gate 30. The widths of the first connecting line 402 and the second connecting line 502 refer to their lengths in a second direction, while the widths of the first fine gate 20 and the second fine gate 30 refer to their lengths in a first direction.

[0144] Example 2

[0145] As shown in Figures 14 to 23, one embodiment of this disclosure provides a solar cell, comprising:

[0146] A silicon wafer 100 is provided with a plurality of fine gates, the fine gates including a first fine gate 200 and a second fine gate 300 that are alternately distributed along a first direction;

[0147] Silicon wafer 100 has:

[0148] The first edge 111 and the second edge 112 are arranged opposite each other along the second direction, and the third edge 113 and the fourth edge 114 are arranged opposite each other along the first direction, wherein the second direction is perpendicular to the first direction;

[0149] The first inclined edge 121 connecting the first edge 111 and the third edge 113; and

[0150] A first connecting line 410 is disposed adjacent to the first inclined edge 121, and the first connecting line 410 is connected to at least one first fine grid 200 or at least one second fine grid 300:

[0151] The intersection of the first inclined edge 121 and the first edge 111 is the first intersection point J2, and the intersection of the first inclined edge 121 and the third edge 113 is the second intersection point J1. The distance between the first intersection point J2 and the second intersection point J1 is less than or equal to 2.5 mm, and the number of the first fine grid 200 or the second fine grid 300 connected by the first connecting line 410 is less than or equal to four.

[0152] In implementation, the silicon wafer 100, the first fine gate 200, and the second fine gate 300 can refer to the silicon wafer 10, the first fine gate 20, and the second fine gate 30 in the above embodiment 1, respectively. The silicon wafer 100 is the silicon substrate, which can be an N-type silicon wafer or a P-type silicon wafer. The N-type silicon wafer is obtained by adding a pentavalent element (such as phosphorus, arsenic, or bismuth) to intrinsic semiconductor silicon, and the P-type silicon wafer is obtained by adding a trivalent element (such as boron, gallium, or indium) to intrinsic semiconductor silicon. Further details are omitted.

[0153] The silicon wafer 100 has a front side and a back side. The front side of the silicon wafer 100 corresponds to the light-receiving surface of the solar cell, and similarly, the back side of the silicon wafer 100 corresponds to the back-lighting surface of the solar cell.

[0154] In some embodiments, the fine gate can be disposed on the front or back side of the silicon wafer 100. The fine gate refers to a metal fine gate, including a first fine gate 200 and a second fine gate 300, which are alternately distributed along a first direction. For example, taking the first direction as vertical, the first fine gate 200 and the second fine gate 300 are alternately distributed from top to bottom on the silicon wafer 100. A second fine gate 300 is disposed between two adjacent first fine gates 200, and similarly, a first fine gate 200 is disposed between two adjacent second fine gates 300. Further details are omitted.

[0155] The silicon wafer 100 is in the form of a sheet or plate and has four edges, namely a third edge 113 and a fourth edge 114 arranged opposite to each other along a first direction, and a first edge 111 and a second edge 112 arranged opposite to each other along a second direction, the second direction being perpendicular to the first direction.

[0156] For example, taking the first direction as vertical, the second direction is horizontal. In this case, the first edge 111 and the second edge 112 can be regarded as the left and right edges of the silicon wafer 100. Similarly, the third edge 113 and the fourth edge 114 can be regarded as the top and bottom edges of the silicon wafer 100. In some other embodiments, when the first direction is horizontal, the second direction is vertical. In this case, the first edge 111 and the second edge 112 can be regarded as the top and bottom edges of the silicon wafer 100. Similarly, the third edge 113 and the fourth edge 114 can be regarded as the left and right edges of the silicon wafer 100. Further details are omitted.

[0157] The silicon wafer 100 has a first inclined edge 121, which connects a first edge 111 and a third edge 113. A first connecting line 410 is provided adjacent to the first inclined edge 121. The first connecting line 410 can connect to a first fine gate 200 or a second fine gate 300. Since the distance between the first intersection point J2 and the second intersection point J1 is less than 2.5 mm, by designing the first inclined edge 121 as a small chamfered area, the number of first fine gates 200 or second fine gates 300 that the first connecting line 410 can connect to is less than or equal to four. For example, taking the first connecting line 410 connecting to the first fine gate 200 as an example, the first connecting line 410 can connect to four first fine gates 200, or three first fine gates 200, or two first fine gates 200, or one first fine gate 200.

[0158] Optionally, the distance between the first intersection point J2 and the second intersection point J1 is less than or equal to 2.5 mm. For example, the distance between the first intersection point J2 and the second intersection point J1 can be designed to be any value from 0.9 mm, 1.1 mm, 1.2 mm, 1.5 mm, 1.6 mm, 1.8 mm, 2.0 mm, 2.4 mm, or 0.7 mm to 2.5 mm. Preferably, the distance between the first intersection point J2 and the second intersection point J1 is 1.2 mm to 1.6 mm. For example, the preset threshold is any value from 1.3 mm, 1.4 mm, 1.45 mm, 1.5 mm, or 1.2 mm to 1.6 mm, without limitation.

[0159] In some possible embodiments, the silicon wafer 100 includes a second tilted edge 122, a third tilted edge 123, and a fourth tilted edge 124, wherein the second tilted edge 122 connects the first edge 111 and the fourth edge 114, the third tilted edge 123 connects the second edge 112 and the third edge 113, and the fourth tilted edge 124 connects the second edge 112 and the fourth edge 114.

[0160] The silicon wafer 100 is also provided with a second connection line 420, a third connection line 430 and a fourth connection line 440, wherein the second connection line 420 is adjacent to the second inclined edge 122, the third connection line 430 is adjacent to the third inclined edge 123, and the fourth connection line 440 is adjacent to the fourth inclined edge 124. The second connection line 420, the third connection line 430 and the fourth connection line 440 are all connected to at least one first fine gate or at least one second fine gate.

[0161] In implementation, the first connecting line 410 and the second connecting line 420 are connected to the fine gate with the same polarity, and the first connecting line 410 and the third connecting line 430 are connected to the fine gate with opposite polarities. For example, when the first connecting line 410 is connected to the first fine gate 200, the second connecting line 420 is also connected to the first fine gate 200, the third connecting line 430 is connected to the second fine gate 300, and the fourth connecting line 430 is also connected to the second fine gate 300.

[0162] It should be noted that the above-mentioned intersection points J1 and J2 of the first inclined edge 121 and the corresponding edge are illustrative examples of the present disclosure, and not specific limitations of the present disclosure. In some other embodiments, the second inclined edge 122, the third inclined edge 123 and the fourth inclined edge 124 can refer to the first inclined edge 121 described above, and will not be repeated.

[0163] In some possible embodiments, taking the first connecting line 410 connecting the first fine gate 200 as an example, the first connecting line 410 can connect two first fine gates 200, the third connecting line 430 connects one second fine gate 300, the second connecting line 420 connects two first fine gates 200, and the fourth connecting line 440 connects one second fine gate 300.

[0164] Optionally, the first connecting line 410 can connect three first fine gates 200, the third connecting line 430 can connect two second fine gates 300, the second connecting line 420 can connect three first fine gates 200, and the fourth connecting line 440 can connect two second fine gates 300. Optionally, the first connecting line 410 can connect four first fine gates 200, the third connecting line 430 can connect three second fine gates 300, the second connecting line 420 can connect four first fine gates 200, and the fourth connecting line 440 can connect three second fine gates 300.

[0165] It should be noted that the number of fine gates connected by the connecting lines at each inclined edge is an example of one embodiment of this disclosure, and not a specific limitation of this disclosure. In other embodiments, the number of fine gates connected by the connecting lines at each inclined edge can be set according to needs and is not limited.

[0166] The solar cell disclosed herein includes a silicon wafer 100 and fine grids disposed on the silicon wafer 100. The fine grids include first fine grids 200 and second fine grids 300 alternately distributed along a first direction. The silicon wafer 100 has a first edge 111 and a second edge 112 disposed opposite to each other along a second direction, and a third edge 113 and a fourth edge 114 disposed opposite to each other along the first direction. The second direction is perpendicular to the first direction. A first inclined edge 121 connects the first edge 111 and the third edge 113. A first connecting line 410 is disposed adjacent to the first inclined edge 121. The first connecting line 410 is connected to at least one first fine grid 200 or at least one second fine grid 300. The intersection of the first inclined edge 121 and the first edge 111 is the first intersection point J2. The intersection of the first inclined edge 121 and the third edge 113 is the second intersection point J1. The distance between the first intersection point J2 and the second intersection point J1 is less than or equal to 2.5 mm. The number of first fine grids 200 or second fine grids 300 connected by the first connecting line 410 is less than or equal to four. With the above settings, the first inclined edge 121 can be made very small, which in turn makes the first connecting line 410 located at the first inclined edge 121 shorter, and can only connect less than or equal to four first fine grids 200 or second fine grids 300, so as to maximize the light-receiving area of ​​the solar cell and ensure the conversion efficiency of the solar cell.

[0167] In some alternative embodiments, the first inclined edge 121 is a straight line or an arc.

[0168] In implementation, each inclined edge can be a straight line, as shown in Figures 14, 15, and 16, taking the first inclined edge 121 as an example. In some possible embodiments, each inclined edge can also be curved, as shown in Figure 17, taking the first inclined edge 121 as an example. Of course, each inclined edge can also be a combination of straight lines and curves, as shown in Figure 18.

[0169] In some alternative embodiments, the connecting lines are not parallel to the corresponding inclined edges. For example, the first connecting line 410 is not parallel to the first inclined edge 121, the second connecting line 420 is not parallel to the second inclined edge 122, the third connecting line 430 is not parallel to the third inclined edge 123, and the fourth connecting line 440 is not parallel to the fourth inclined edge 124, as shown in FIG21, which will not be described in detail.

[0170] In some alternative embodiments, the first connecting line 410 includes a first connecting portion 450 and a second connecting portion 460, wherein the first connecting portion 450 is used to connect two fine gates of the same polarity, and the second connecting portion 460 is connected to the first connecting portion 450.

[0171] The connecting lines can be designed in a stepped shape, as shown in Figure 19. For example, taking the first connecting line 410 connecting the first fine gate 200 and the second connecting line 420 connecting the second fine gate 300 as an example, the silicon wafer 100 is arranged from top to bottom as follows: the first first fine gate 200, the first second fine gate 300, the second first fine gate 200, the second second fine gate 300, ..., the Nth first fine gate 200 and the Nth second fine gate 300. The first end of the first connecting portion 450 of the first connecting line 410 is connected to the first first fine gate 200, and the second end of the first connecting portion 450 of the first connecting line 410 is connected to the second first fine gate 200. The second connecting portion 460 of the first connecting line 410 is perpendicular or substantially perpendicular to the first connecting portion 450 of the first connecting line 410. Similarly, the first end of the first connecting portion 450 of the second connecting line 420 is connected to the first second fine grid 300, the second end of the first connecting portion 450 of the second connecting line 420 is connected to the second second fine grid 300, and the second connecting portion 460 of the second connecting line 420 is perpendicular or substantially perpendicular to the first connecting portion 450 of the second connecting line 420.

[0172] In implementation, the second connecting portion 460 and the first connecting portion 450 are connected by a thin grid. Optionally, the second connecting portion 460 and the first connecting portion 450 are parallel to the first direction, and optionally, the first connecting portion 450 is an oblique line. The first connecting portion 450 and the second connecting portion 460 are distributed along the current direction. That is, the first end of the first connecting portion 450 is connected to the first thin grid 200, and the second end of the first connecting portion 450 is connected to the second thin grid 200. At this time, the current flowing through the first connecting portion 450 is the current of the first thin grid 200. The second connecting portion 460 is connected to the first connecting portion 450, and at this time, the current flowing through the second connecting portion 460 is the sum of the currents of the first and second thin grids 200. By designing the width of the first connecting portion 450 to be smaller than the width of the second connecting portion 460, the line resistance of the second connecting portion 460 can be effectively reduced, thereby reducing the overall power loss of the connecting wire and improving the power generation efficiency of the solar cell.

[0173] In some alternative embodiments, the width of the connecting line 400 is greater than the width of the fine gate. In practice, the width of the connecting line 400 is related to the line resistance; generally, a larger line width results in lower line resistance. Connecting lines with different line widths have different line resistance losses. For example, when the line width of the connecting line 400 is 150µm, the line resistance loss is 0.0095W. When the line width of the connecting line 400 is 300µm, the line resistance loss is 0.0048W. When the line width of the connecting line 400 is gradually increased, for example, when the width of the connecting line 400 gradually increases from 150µm to 300µm, the line resistance loss is 0.0062W, as shown in Figure 20. Therefore, using a wider connecting line 400 can effectively reduce the line resistance of the connecting line 400, thereby reducing the current loss when current flows through the connecting line 400.

[0174] Optionally, a wider connecting line 400 can effectively reduce its line resistance. However, a wider connecting line 400 can also obstruct the light-receiving area of ​​the solar cell, leading to a decrease in the solar cell's power generation efficiency. In this case, the ratio of the width of the grid to the width of the connecting line 400 can be designed to be 1:1.2 to 1:2. For example, the ratio can be 1:1:3, 1:1.5, or 1:1.9. Preferably, the ratio is 1:1.6 to 1:1.8. For example, the ratio can be 1:1:7 or 1:1.75, etc., without limitation. Through the above design, both the line resistance of the connecting line 400 and the power generation efficiency of the solar cell can be effectively balanced.

[0175] In some alternative embodiments, the angle between the first connecting line 410 and the second direction is greater than the angle between the third connecting line 420 and the second direction. Similarly, the angle between the second connecting line 420 and the second direction is greater than the angle between the fourth connecting line 440 and the second direction.

[0176] In implementation, the second direction refers to the direction parallel to the fine grid. Taking the alternating longitudinal arrangement of the first fine grid 200 and the second fine grid 300 as an example, the second direction is the transverse direction, meaning that the first fine grid 200 and the second fine grid 300 extend laterally. For example, if the angle between the first connecting line 410 and the second direction is Z1, and the angle between the third connecting line 430 and the second direction is Z2, then Z1 > Z2. Similarly, if the angle between the second connecting line 420 and the second direction is Z3, and the angle between the fourth connecting line 440 and the second direction is Z4, then Z3 > Z4.

[0177] In some alternative embodiments, the first connecting line 410 and the second connecting line 420 are both used to connect the first fine gate 200, and the third connecting line 430 and the fourth connecting line 440 are both used to connect the second fine gate 300.

[0178] Along the second direction, when the first connecting line 410 connects to the first fine gate 200, the distance between the endpoint of the second fine gate 300 adjacent to the first connecting line 410 and the first connecting line 410 is less than the distance between the first connecting line 410 and the first inclined edge 121; or when the first connecting line 410 connects to the second fine gate 300, the distance between the endpoint of the first fine gate 200 adjacent to the first connecting line 410 and the first connecting line 410 is less than the distance between the first connecting line 410 and the first inclined edge 121.

[0179] Optionally, taking the first connecting line 410 connecting the first fine grid 200 as an example, as shown in Figure 22, the first connecting line 410 and the second fine grid 300 are spaced apart. The distance between the ends of the first connecting line 410 and the second fine grid 300 is considered as D1, and the distance between the first connecting line 410 and the first inclined edge 121 is considered as D2. Then D1 < D2.

[0180] In some possible embodiments, when the connecting line is spaced apart from multiple fine grids, taking the first fine grid 200, the first second fine grid 300, the second first fine grid 200, and the second second fine grid 300 distributed sequentially from top to bottom as an example, as shown in Figure 23. The first connecting line 410 connects the first first fine grid 200 and the second first fine grid 200. In this case, the first connecting line 410 is spaced apart from the first second fine grid 300 and the second second fine grid 300. The fine grid closest to the connecting line is selected to determine the distance. For example, if the distance between the end of the first connecting line 410 and the end of the first second fine grid 300 is less than the distance between the end of the first connecting line 410 and the end of the second second fine grid 300, then the distance between the end of the first connecting line 410 and the end of the first second fine grid 300 is considered as D1, and the distance between the first connecting line 410 and the first inclined edge 121 is considered as D2. Then D1 < D2.

[0181] Similarly, in some other embodiments, the second connecting line 420, the third connecting line 430 and the fourth connecting line 440 can refer to the design of the first connecting line 410 described above, and will not be repeated here.

[0182] In some alternative embodiments, along the second direction, the distance between the first connecting line 410 and the first inclined edge 121 is greater than the distance between the third connecting line 430 and the third inclined edge 123.

[0183] Taking the second direction as horizontal as an example, the first inclined edge 121 is located at the upper left corner of the silicon wafer 100, the second inclined edge 122 is located at the lower left corner of the silicon wafer 100, the third inclined edge 123 is located at the upper right corner of the silicon wafer 100, and the fourth inclined edge 124 is located at the lower right corner of the silicon wafer 100. The distance between the first connecting line 410 and the edge of the first inclined edge 121 is greater than the distance between the edges of the third connecting line 430 and the third inclined edge 123. Similarly, the distance between the edges of the second connecting line 420 and the second inclined edge 122 is greater than the distance between the edges of the fourth connecting line 440 and the fourth inclined edge 124.

[0184] Optionally, the connecting line is not parallel to the corresponding inclined edge. For example, the first connecting line 410 is not parallel to the first inclined edge 121, and similarly, the second connecting line 420 is not parallel to the second inclined edge 122. The third connecting line 430 and the fourth connecting line 440 are similar and will not be elaborated further. The point closest to the inclined edge of the connecting line can be selected to determine the distance. Taking the first connecting line 410 as an example, the distance between the upper endpoint of the first connecting line 410 and the first inclined edge 121 is greater than the distance between the lower endpoint of the first connecting line 410 and the first inclined edge 121. Therefore, the distance between the lower endpoint of the first connecting line 410 and the first inclined edge 121 can be considered as the distance between the first connecting line 410 and the first inclined edge 121. Alternatively, the average distance between the two ends of the first connecting line 410 and the first inclined edge 121 can be used as the distance between the first connecting line 410 and the first inclined edge 121, which will not be elaborated further.

[0185] In some alternative embodiments, the first connecting line 410 is connected to the first fine gate 200, the third connecting line 430 is connected to the second fine gate 300, and the width of the first connecting line 410 is smaller than the width of the third connecting line 430 along the second direction. Similarly, the second connecting line 420 is connected to the first fine gate 200, and the fourth connecting line 440 is connected to the second fine gate 300, and the width of the second connecting line 420 is smaller than the width of the fourth connecting line 440 along the second direction.

[0186] In some alternative embodiments, the linewidth of the second fine gate 300 is greater than the linewidth of the first fine gate 200.

[0187] In some optional embodiments, taking the first direction as the longitudinal direction as an example, the second direction is the transverse direction. The second fine gate 300 and the first fine gate 200 are alternately distributed on the silicon wafer 100 along the first direction, so that the first fine gate 200 and the second fine gate 300 are symmetrically distributed vertically. For example, when the first fine gate 200 is closest to the third edge 113, the first fine gate is also closest to the fourth edge 114. In addition, the first fine gate 200 and the second fine gate 300 are asymmetrical horizontally.

[0188] Example 2

[0189] In some alternative embodiments, this disclosure provides a photovoltaic module including the solar cell as described above.

[0190] A photovoltaic module consists of at least one solar cell. The first grid 200 of the solar cell is connected by a positive electrode solder strip 500, and the second grid 300 is connected by a negative electrode solder strip 600. The solder strips of adjacent solar cells can be connected in series or in parallel, which will not be elaborated further.

[0191] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the structure and implementation principle of the photovoltaic module described above can be referred to the corresponding structure and implementation principle in the aforementioned Embodiment 1, and will not be repeated here.

[0192] The solar cell disclosed herein includes a silicon wafer 100 and fine grids disposed on the silicon wafer 100. The fine grids include first fine grids 200 and second fine grids 300 alternately distributed along a first direction. The silicon wafer 100 has a first edge 111 and a second edge 112 disposed opposite to each other along a second direction, and a third edge 113 and a fourth edge 114 disposed opposite to each other along the first direction. The second direction is perpendicular to the first direction. A first inclined edge 121 connects the first edge 111 and the third edge 113. A first connecting line 410 is disposed adjacent to the first inclined edge 121. The first connecting line 410 is connected to at least one first fine grid 200 or at least one second fine grid 300. The intersection of the first inclined edge 121 and the first edge 111 is the first intersection point J2. The intersection of the first inclined edge 121 and the third edge 113 is the second intersection point J1. The distance between the first intersection point J2 and the second intersection point J1 is less than or equal to 2.5 mm. The number of first fine grids 200 or second fine grids 300 connected by the first connecting line 410 is less than or equal to four. With the above settings, the first inclined edge 121 can be made very small, which in turn makes the first connecting line 410 located at the first inclined edge 121 shorter, and can only connect less than or equal to four first fine grids 200 or second fine grids 300, so as to maximize the light-receiving area of ​​the solar cell and ensure the conversion efficiency of the solar cell.

[0193] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. Solar cells, wherein, include: A silicon wafer having a plurality of fine gates disposed thereon, the fine gates including first fine gates and second fine gates alternately distributed along a first direction; The silicon wafer has: A first edge and a second edge arranged opposite to each other along a second direction, and a third edge and a fourth edge arranged opposite to each other along a first direction, wherein the second direction is perpendicular to the first direction; A first inclined edge connecting the first edge and the third edge; as well as A first connecting line is disposed adjacent to the first inclined edge, and the first connecting line is connected to at least one of the first fine grids or at least one of the second fine grids; The intersection of the first inclined edge and the first edge is the first intersection point, the intersection of the first inclined edge and the third edge is the second intersection point, the distance between the first intersection point and the second intersection point is less than or equal to 2.5 mm, and the number of the first fine grid or the second fine grid connected by the first connecting line is less than or equal to four.

2. The solar cell as claimed in claim 1, wherein, The first inclined edge is either a straight line or an arc.

3. The solar cell as described in claim 2, wherein, The first connecting line is not parallel to the first inclined edge.

4. The solar cell according to any one of claims 1 to 2, wherein, The first connecting line includes a first connecting portion and a second connecting portion, wherein the width of the first connecting portion is smaller than the width of the second connecting portion.

5. The solar cell as claimed in claim 4, wherein, The first connecting part and the second connecting part are connected, and the first connecting part is a diagonal line.

6. The solar cell of claim 4, wherein, The second connecting part and the first connecting part are connected by a thin grid.

7. The solar cell of claim 6, wherein, The second connecting portion and the first connecting portion are parallel to the first direction.

8. The solar cell of claim 4, wherein, The ratio of the width of the fine grid to the width of the first connecting line is 1:1.2 to 1:

2.

9. The solar cell of claim 8, wherein, The ratio of the width of the fine grid to the width of the first connecting line is 1:1.6-1:1.

8.

10. The solar cell of claim 1, wherein, The distance between the first intersection point and the second intersection point is 0.7 mm to 2.5 mm.

11. The solar cell of claim 10, wherein, The distance between the first intersection point and the second intersection point is 1.2 mm to 1.6 mm.

12. The solar cell of claim 1, wherein, The silicon wafer includes a second inclined edge connecting the first edge and the fourth edge; The silicon wafer is provided with a second connection line adjacent to the second inclined edge, and the second connection line is connected to at least one of the first fine gates or at least one of the second fine gates; The first connecting line and the second connecting line are connected to a fine gate having the same polarity.

13. The solar cell of claim 12, wherein, The silicon wafer includes a third inclined edge connecting the second edge and the third edge; The silicon wafer is provided with a third connection line adjacent to the third inclined edge, and the third connection line is connected to at least one of the first fine gates or at least one of the second fine gates; The first connecting line and the third connecting line are connected to a fine gate with opposite polarities.

14. The solar cell of claim 13, wherein, The angle between the first connecting line and the second direction is greater than the angle between the third connecting line and the second direction.

15. The solar cell of claim 1, wherein, The first connecting line is connected to the first fine grid. Along the second direction, the distance between the endpoint of the second fine grid adjacent to the first connecting line and the first connecting line is less than the distance between the first connecting line and the first inclined edge; or The first connecting line is connected to the second fine grid. Along the second direction, the distance between the first fine grid and the endpoint of the first connecting line is less than the distance between the first connecting line and the first inclined edge.

16. The solar cell of claim 13, wherein, Along the second direction, the distance between the first connecting line and the first inclined edge is greater than the distance between the third connecting line and the third inclined edge.

17. The solar cell of claim 13, wherein, The first connecting line is connected to the first fine gate, and the third connecting line is connected to the second fine gate; Along the second direction, the width of the first connecting line is smaller than the width of the third connecting line.

18. The solar cell of claim 1, wherein, The linewidth of the second fine gate is greater than the linewidth of the first fine gate.

19. A photovoltaic module, wherein, Including the solar cell as described in any one of claims 1 to 18.

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