Drive circuit, drive module, drive method and display apparatus

Abstract

A drive circuit, a drive module, a drive method and a display apparatus. The drive circuit comprises a first control node control circuit (11), a first node control circuit (12), a second control node control circuit (13) and a second node control circuit (14). Under the control of a control clock signal, the first control node control circuit (11) controls a first control node (Q1) and an input terminal (I1) to be connected; under the control of a first voltage signal, the first node control circuit (12) controls the first control node (Q1) and a first node (Q) to be connected; under the control of a signal provided by a node control terminal, the second control node control circuit (13) controls the potential of a second control node (QB1); and under the control of the second control node (QB1), the second node control circuit (14) controls the potential of a second node (QB) on the basis of the control clock signal. The present application achieves more complete reset of the second control node (QB1), thus eliminating potential distortions of drive signals outputted by drive circuits.

Description

Drive circuit, drive module, drive method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202410518951.1, filed in China on April 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving module, driving method and display device. Background Technology

[0004] In the display field, especially in OLED (Organic Light Emitting Diode) displays, oxides are currently widely used in medium and large-sized OLED displays due to their good uniformity. Internal compensation has attracted widespread attention due to its low cost and good compensation effect. However, the related internal compensation driving circuit does not completely reset the second control node, and cannot eliminate the potential distortion of the driving signal output by the driving circuit. Summary of the Invention

[0005] The main objective of this disclosure is to provide a driving circuit, driving module, driving method, and display device to solve the problem in the prior art where the reset of the second control node is incomplete and the potential distortion of the driving signal output by the driving circuit cannot be eliminated.

[0006] In one aspect, embodiments of this disclosure provide a driving circuit, including a first control node control circuit, a first node control circuit, a second control node control circuit, and a second node control circuit.

[0007] The first control node control circuit is electrically connected to the control clock signal terminal, the input terminal and the first control node respectively, and is used to control the connection between the first control node and the input terminal under the control of the control clock signal provided by the control clock signal terminal;

[0008] The first node control circuit is electrically connected to the first voltage terminal, the first control node, and the first node, respectively, and is used to control the connection between the first control node and the first node under the control of the first voltage signal provided by the first voltage terminal;

[0009] The second control node control circuit is electrically connected to the node control terminal and the second control node, respectively, and is used to control the potential of the second control node under the control of the signal provided by the node control terminal; the node control terminal is the first node in the adjacent upper m-level drive circuit or the first control node in the adjacent upper m-level drive circuit; m is a positive integer;

[0010] The second node control circuit is electrically connected to the second control node, the control clock signal terminal, and the second node, respectively, and is used to control the potential of the second node according to the control clock signal provided by the control clock signal terminal under the control of the second control node.

[0011] Optionally, the second control node control circuit is also electrically connected to the second voltage terminal or the adjacent upper-level intermediate node, and is used to control the connection between the second control node and the second voltage terminal or the adjacent upper-level intermediate node under the control of the signal provided by the node control terminal.

[0012] Optionally, the control circuit of the second control node includes a first transistor;

[0013] The gate of the first transistor is electrically connected to the node control terminal, the first terminal of the first transistor is electrically connected to the second voltage terminal or the adjacent intermediate node of the previous stage, and the second terminal of the first transistor is electrically connected to the second control node.

[0014] Optionally, the second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit;

[0015] The first control circuit is electrically connected to the node control terminal, the third voltage terminal and the intermediate node respectively, and is used to control the connection between the intermediate node and the third voltage terminal under the control of the signal provided by the node control terminal;

[0016] The second control circuit is electrically connected to the node control terminal, the intermediate node, and the second control node, respectively, and is used to control the connection between the intermediate node and the second control node under the control of the signal provided by the node control terminal;

[0017] The third control circuit is electrically connected to the second control node, the intermediate node, and the fourth voltage terminal, respectively, and is used to control the connection between the intermediate node and the fourth voltage terminal under the control of the second control node.

[0018] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor;

[0019] The gate of the first transistor is electrically connected to the node control terminal, the first terminal of the first transistor is electrically connected to the third voltage terminal, and the second terminal of the first transistor is electrically connected to the intermediate node.

[0020] The gate of the second transistor is electrically connected to the node control terminal, the first terminal of the second transistor is electrically connected to the intermediate node, and the second terminal of the second transistor is electrically connected to the second control node.

[0021] The gate of the third transistor is electrically connected to the second control node, the first terminal of the third transistor is electrically connected to the fourth voltage terminal, and the second terminal of the third transistor is electrically connected to the intermediate node.

[0022] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes an output circuit and an output reset circuit;

[0023] The output circuit is electrically connected to the first node, the drive signal output terminal and the first voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the first node.

[0024] The output reset circuit is electrically connected to the second node, the drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the second voltage terminal under the control of the second node.

[0025] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit, a carry reset circuit, an output circuit, and an output reset circuit;

[0026] The carry output circuit is electrically connected to the first node, the carry signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry signal output terminal and the first voltage terminal under the control of the first node.

[0027] The carry reset circuit is electrically connected to the second node, the carry signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the carry signal output terminal and the second voltage terminal under the control of the second node.

[0028] The output circuit is electrically connected to the first node, the drive signal output terminal and the fifth voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the fifth voltage terminal under the control of the first node.

[0029] The output reset circuit is electrically connected to the second node, the drive signal output terminal, and the sixth voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the sixth voltage terminal under the control of the second node.

[0030] Optionally, the second node control circuit is also electrically connected to the first control node, and is used to control the potential of the second node under the control of the first control node;

[0031] The drive circuit also includes a control energy storage circuit;

[0032] The control energy storage circuit is electrically connected to the control clock signal terminal and the second control node, respectively, and is used to control the potential of the second control node according to the control clock signal.

[0033] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0034] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output terminal. The first energy storage circuit is used to store electrical energy.

[0035] The second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to maintain the potential of the second node.

[0036] Optionally, the driving circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0037] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the carry signal output terminal. The first energy storage circuit is used to store electrical energy.

[0038] The second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to maintain the potential of the second node.

[0039] Optionally, the first control node control circuit includes a fourth transistor, and the first node control circuit includes a fifth transistor.

[0040] The gate of the fourth transistor is electrically connected to the control clock signal terminal, the first terminal of the fourth transistor is electrically connected to the input terminal, and the second terminal of the fourth transistor is electrically connected to the first control node.

[0041] The gate of the fifth transistor is electrically connected to the first voltage terminal, the first terminal of the fifth transistor is electrically connected to the first control node, and the second terminal of the fifth transistor is electrically connected to the first node.

[0042] Optionally, the second node control circuit includes a sixth transistor and a seventh transistor;

[0043] The gate of the sixth transistor is electrically connected to the second control node, the first terminal of the sixth transistor is electrically connected to the control clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0044] The gate of the seventh transistor is electrically connected to the first control node, the first terminal of the seventh transistor is electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

[0045] Optionally, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0046] The gate of the output transistor is electrically connected to the first node, the first terminal of the output transistor is electrically connected to the first voltage terminal, and the second terminal of the output transistor is electrically connected to the drive signal output terminal.

[0047] The gate of the output reset transistor is electrically connected to the second node, the first terminal of the output reset transistor is electrically connected to the drive signal output terminal, and the second terminal of the output reset transistor is electrically connected to the second voltage terminal.

[0048] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a carry reset transistor, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor.

[0049] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the first voltage terminal, and the second terminal of the carry output transistor is electrically connected to the carry signal output terminal.

[0050] The gate of the carry reset transistor is electrically connected to the second node, the first terminal of the carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the carry reset transistor is electrically connected to the second voltage terminal.

[0051] The gate of the output transistor is electrically connected to the first node, the first terminal of the output transistor is electrically connected to the fifth voltage terminal, and the second terminal of the output transistor is electrically connected to the drive signal output terminal.

[0052] The gate of the output reset transistor is electrically connected to the second node, the first terminal of the output reset transistor is electrically connected to the drive signal output terminal, and the second terminal of the output reset transistor is electrically connected to the sixth voltage terminal.

[0053] In a second aspect, embodiments of this disclosure provide a drive module including multiple stages of the drive circuits described above.

[0054] Optionally, the node control terminal of the a-th stage driving circuit is the first node in the am-th stage driving circuit or the first control node in the am-th stage driving circuit.

[0055] Both a and m are positive integers.

[0056] Optionally, the second control node control circuit in the nth stage drive circuit includes an nth stage first control circuit, an nth stage second control circuit, and an nth stage third control circuit; n is a positive integer;

[0057] The second control node control circuit in the (n+1)th stage drive circuit is electrically connected to the (n+1)th node control terminal, the (n+1)th stage second control node, and the nth stage intermediate node, respectively, and is used to control the (n+1)th stage second control node to connect with the adjacent previous stage intermediate node under the control of the signal provided by the (n+1)th node control terminal.

[0058] The first control circuit of the nth level is electrically connected to the control terminal of the nth node, the third voltage terminal and the intermediate node of the nth level respectively, and is used to control the connection between the intermediate node of the nth level and the third voltage terminal under the control of the signal provided by the control terminal of the nth node;

[0059] The nth-level second control circuit is electrically connected to the nth-node control terminal, the nth-level intermediate node, and the nth-level second control node, respectively, and is used to control the connection between the nth-level intermediate node and the nth-level second control node under the control of the signal provided by the nth-node control terminal;

[0060] The nth-level third control circuit is electrically connected to the nth-level second control node, the nth-level intermediate node, and the fourth voltage terminal, respectively, and is used to control the connection between the nth-level intermediate node and the fourth voltage terminal under the control of the nth-level second control node.

[0061] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving circuit, the driving method comprising:

[0062] The first control node control circuit controls the connection between the first control node and the input terminal under the control of the control clock signal;

[0063] The first node control circuit controls the connection between the first control node and the first node under the control of the first voltage signal;

[0064] The second control node control circuit controls the potential of the second control node under the control of the potential of the first node in the adjacent upper m-level drive circuit or the control of the first control node in the adjacent upper m-level drive circuit; m is a positive integer.

[0065] The second node control circuit, under the control of the second control node, controls the potential of the second node according to the control clock signal.

[0066] Optionally, the step of controlling the potential of the second control node under the control of the potential of the first node in the adjacent upper m-stage drive circuit or the control of the first control node in the adjacent upper m-stage drive circuit includes:

[0067] The second control node control circuit controls the connection between the second control node and the second voltage terminal or the adjacent upper-level intermediate node under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

[0068] Optionally, the second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit; the step of controlling the potential of the second control node under the control of the potential of the first node in the adjacent upper m-stage drive circuit or the control of the first control node in the adjacent upper m-stage drive circuit includes:

[0069] The first control circuit controls the connection between the intermediate node and the third voltage terminal under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

[0070] The second control circuit controls the connection between the intermediate node and the second control node under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

[0071] Under the control of the second control node, the third control circuit controls the connection between the intermediate node and the fourth voltage terminal.

[0072] Optionally, the driving circuit further includes an output circuit and an output reset circuit; the driving method further includes:

[0073] Under the control of the first node, the output circuit controls the connection between the drive signal output terminal and the first voltage terminal;

[0074] Under the control of the second node, the output reset circuit controls the connection between the drive signal output terminal and the second voltage terminal;

[0075] The second node control circuit controls the potential of the second node under the control of the first node.

[0076] In a fourth aspect, at least one embodiment of the present disclosure provides a display device including the driving module described above.

[0077] The driving circuit, driving module, driving method, and display device described in this embodiment provide a more complete reset of the second control node, eliminating potential distortion of the driving signal output by the driving circuit. Attached Figure Description

[0078] Figure 1 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0079] Figure 2 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0080] Figure 3 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0081] Figure 4 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0082] Figure 5 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0083] Figure 6 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0084] Figure 7 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0085] Figure 8 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0086] Figure 9 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0087] Figure 10 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0088] Figure 11 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0089] Figure 12 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0090] Figure 13 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0091] Figure 14 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0092] Figure 15 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0093] Figure 16 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0094] Figure 17 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0095] Figure 18 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 17;

[0096] Figure 19 is a circuit diagram of the (n-1)th stage drive circuit and the nth stage drive circuit in the drive module according to at least one embodiment of the present disclosure;

[0097] Figure 20 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 19;

[0098] Figure 21 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0099] Figure 22 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0100] Figure 23 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 22 of this disclosure;

[0101] Figure 24 is a circuit diagram of the (n-1)th stage drive circuit and the nth stage drive circuit in the drive module according to at least one embodiment of the present disclosure;

[0102] Figure 25 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0103] Figure 26 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0104] Figure 27 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 26;

[0105] Figure 28 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. Detailed Implementation

[0106] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0107] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0108] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0109] The driving circuit described in this embodiment includes a first control node control circuit, a first node control circuit, a second control node control circuit, and a second node control circuit.

[0110] The first control node control circuit is electrically connected to the control clock signal terminal, the input terminal and the first control node respectively, and is used to control the connection between the first control node and the input terminal under the control of the control clock signal provided by the control clock signal terminal;

[0111] The first node control circuit is electrically connected to the first voltage terminal, the first control node, and the first node, respectively, and is used to control the connection between the first control node and the first node under the control of the first voltage signal provided by the first voltage terminal;

[0112] The second control node control circuit is electrically connected to the node control terminal and the second control node, respectively, and is used to control the potential of the second control node under the control of the signal provided by the node control terminal; the node control terminal is the first node in the adjacent upper m-level drive circuit or the first control node in the adjacent upper m-level drive circuit; m is a positive integer;

[0113] The second node control circuit is electrically connected to the second control node, the control clock signal terminal, and the second node, respectively, and is used to control the potential of the second node according to the control clock signal provided by the control clock signal terminal under the control of the second control node.

[0114] In at least one embodiment of this disclosure, the second control node control circuit controls the potential of the second control node at the potential of the node control terminal. The node control terminal is either the first node in the adjacent upper m-level drive circuit or the first control node in the adjacent upper m-level drive circuit. When the adjacent upper m-level drive circuit outputs a drive signal, the potential of the first node in the adjacent upper m-level drive circuit and the potential of the first control node in the adjacent upper m-level drive circuit will self-boost. The second control node control circuit can better control the reset of the potential of the second control node under the control of the potential of the first node in the adjacent upper m-level drive circuit and the first control node in the adjacent upper m-level drive circuit, and the reset of the second control node is more complete, eliminating the potential distortion of the drive signal output by the drive circuit.

[0115] Optionally, the first voltage terminal can be a high voltage terminal, but is not limited thereto.

[0116] In at least one embodiment of this disclosure, m can be equal to 1, but is not limited thereto. In actual operation, m can also be an integer greater than 1.

[0117] As shown in Figure 1, the driving circuit described in this embodiment includes a first control node control circuit 11, a first node control circuit 12, a second control node control circuit 13, and a second node control circuit 14.

[0118] The first control node control circuit 11 is electrically connected to the control clock signal terminal CKC, the input terminal I1 and the first control node Q1 respectively, and is used to control the connection between the first control node Q1 and the input terminal I1 under the control of the control clock signal provided by the control clock signal terminal CKC.

[0119] The first node control circuit 12 is electrically connected to the first voltage terminal V1, the first control node Q1 and the first node Q respectively, and is used to control the connection between the first control node Q1 and the first node Q under the control of the first voltage signal provided by the first voltage terminal V1.

[0120] The second control node control circuit 13 is electrically connected to the first node Q(n-1) and the second control node QB1 in the adjacent upper-level drive circuit, respectively, and is used to control the potential of the second control node QB1 under the control of the first node Q(n-1) in the adjacent upper-level drive circuit.

[0121] The second node control circuit 14 is electrically connected to the second control node QB1, the control clock signal terminal CKC, and the second node QB, respectively, and is used to control the potential of the second node QB according to the control clock signal provided by the control clock signal terminal CKC under the control of the second control node QB1.

[0122] As shown in Figure 2, the driving circuit described in this embodiment includes a first control node control circuit 11, a first node control circuit 12, a second control node control circuit 13, and a second node control circuit 14.

[0123] The first control node control circuit 11 is electrically connected to the control clock signal terminal CKC, the input terminal I1 and the first control node Q1 respectively, and is used to control the connection between the first control node Q1 and the input terminal I1 under the control of the control clock signal provided by the control clock signal terminal CKC.

[0124] The first node control circuit 12 is electrically connected to the first voltage terminal V1, the first control node Q1 and the first node Q respectively, and is used to control the connection between the first control node Q1 and the first node Q under the control of the first voltage signal provided by the first voltage terminal V1.

[0125] The second control node control circuit 13 is electrically connected to the first control node Q1(n-1) and the second control node QB1 in the adjacent upper-level drive circuit, respectively, and is used to control the potential of the second control node QB1 under the control of the first control node Q1(n-1) in the adjacent upper-level drive circuit.

[0126] The second node control circuit 14 is electrically connected to the second control node QB1, the control clock signal terminal CKC, and the second node QB, respectively, and is used to control the potential of the second node QB according to the control clock signal provided by the control clock signal terminal CKC under the control of the second control node QB1.

[0127] In at least one embodiment of this disclosure, the second control node control circuit is also electrically connected to the second voltage terminal or the adjacent upper-level intermediate node, and is used to control the connection between the second control node and the second voltage terminal or the adjacent upper-level intermediate node under the control of the signal provided by the node control terminal.

[0128] In specific implementation, the second control node control circuit can also control the second control node to be electrically connected to the second voltage terminal or the adjacent upper-level intermediate node under the control of the signal provided by the node control terminal, so as to control the potential of the second control node.

[0129] Optionally, the second voltage terminal can be a low voltage terminal, but is not limited thereto.

[0130] As shown in Figure 3, based on at least one embodiment of the driving circuit shown in Figure 1, the second control node control circuit 13 is also electrically connected to the second voltage terminal V2, and is used to control the connection between the second control node and the second voltage terminal under the control of the first node Q(n-1) in the adjacent upper-level driving circuit.

[0131] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 2, the second control node control circuit 13 is also electrically connected to the second voltage terminal V2, and is used to control the connection between the second control node and the second voltage terminal under the control of the first control node Q1(n-1) in the adjacent upper-level driving circuit.

[0132] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 1, the second control node control circuit 13 is also electrically connected to the adjacent upper-level intermediate node P(n-1) for controlling the connection between the second control node and the adjacent upper-level intermediate node P(n-1) under the control of the first node Q(n-1) in the adjacent upper-level driving circuit.

[0133] As shown in Figure 6, based on at least one embodiment of the driving circuit shown in Figure 2, the second control node control circuit 13 is also electrically connected to the adjacent upper-level intermediate node P(n-1) for controlling the connection between the second control node and the adjacent upper-level intermediate node P(n-1) under the control of the first control node Q1(n-1) in the adjacent upper-level driving circuit.

[0134] In at least one embodiment shown in Figures 1-6, the driving circuit is an nth-stage driving circuit, where n is a positive integer.

[0135] Optionally, the control circuit of the second control node includes a first transistor;

[0136] The gate of the first transistor is electrically connected to the node control terminal, the first terminal of the first transistor is electrically connected to the second voltage terminal or the adjacent intermediate node of the previous stage, and the second terminal of the first transistor is electrically connected to the second control node.

[0137] In at least one embodiment of this disclosure, the second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit;

[0138] The first control circuit is electrically connected to the node control terminal, the third voltage terminal and the intermediate node respectively, and is used to control the connection between the intermediate node and the third voltage terminal under the control of the signal provided by the node control terminal;

[0139] The second control circuit is electrically connected to the node control terminal, the intermediate node, and the second control node, respectively, and is used to control the connection between the intermediate node and the second control node under the control of the signal provided by the node control terminal;

[0140] The third control circuit is electrically connected to the second control node, the intermediate node, and the fourth voltage terminal, respectively, and is used to control the connection between the intermediate node and the fourth voltage terminal under the control of the second control node.

[0141] Optionally, the third voltage terminal can be a first low voltage terminal, and the fourth voltage terminal can be a first high voltage terminal or a second high voltage terminal.

[0142] In specific implementation, the second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit. When the third control circuit is controlled by the second control node, it controls the electrical connection between the intermediate node and the fourth voltage terminal. The fourth voltage terminal can be a first high voltage terminal or a second high voltage terminal, so that the potential of the second control node will not decrease due to leakage.

[0143] As shown in Figure 7, based on at least one embodiment of the driving circuit shown in Figure 1, the second control node control circuit includes a first control circuit 71, a second control circuit 72, and a third control circuit 73.

[0144] The first control circuit 71 is electrically connected to the first node Q(n-1), the third voltage terminal V3 and the intermediate node P in the adjacent upper-level driving circuit, respectively, and is used to control the intermediate node P and the third voltage terminal V3 to be connected under the control of the first node Q(n-1) in the adjacent upper-level driving circuit.

[0145] The second control circuit 72 is electrically connected to the first node Q(n-1), the intermediate node P and the second control node QB1 in the adjacent upper-level drive circuit, respectively, and is used to control the intermediate node P and the second control node QB1 to communicate under the control of the first node Q(n-1) in the adjacent upper-level drive circuit.

[0146] The third control circuit 73 is electrically connected to the second control node QB1, the intermediate node P, and the fourth voltage terminal V4, respectively, and is used to control the connection between the intermediate node P and the fourth voltage terminal V4 under the control of the second control node QB1.

[0147] In at least one embodiment shown in Figure 7, the driving circuit is an nth-level driving circuit, and the intermediate node P is an nth-level intermediate node P(n).

[0148] As shown in Figure 8, based on at least one embodiment of the driving circuit shown in Figure 2, the second control node control circuit includes a first control circuit 71, a second control circuit 72, and a third control circuit 73.

[0149] The first control circuit 71 is electrically connected to the first control node Q1(n-1), the third voltage terminal, and the intermediate node P in the adjacent upper-level drive circuit, respectively, and is used to control the intermediate node P and the third voltage terminal V3 to be connected under the control of the first control node Q1(n-1) in the adjacent upper-level drive circuit.

[0150] The second control circuit 72 is electrically connected to the first control node Q1(n-1), the intermediate node P and the second control node QB1 in the adjacent upper-level drive circuit, respectively, and is used to control the intermediate node P and the second control node QB1 to connect under the control of the first control node Q1(n-1) in the adjacent upper-level drive circuit.

[0151] The third control circuit 73 is electrically connected to the second control node QB1, the intermediate node P, and the fourth voltage terminal V4, respectively, and is used to control the connection between the intermediate node P and the fourth voltage terminal V4 under the control of the second control node QB1.

[0152] In at least one embodiment shown in Figure 8, the driving circuit is an nth-level driving circuit, and the intermediate node P is an nth-level intermediate node P(n).

[0153] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor;

[0154] The gate of the first transistor is electrically connected to the node control terminal, the first terminal of the first transistor is electrically connected to the third voltage terminal, and the second terminal of the first transistor is electrically connected to the intermediate node.

[0155] The gate of the second transistor is electrically connected to the node control terminal, the first terminal of the second transistor is electrically connected to the intermediate node, and the second terminal of the second transistor is electrically connected to the second control node.

[0156] The gate of the third transistor is electrically connected to the second control node, the first terminal of the third transistor is electrically connected to the fourth voltage terminal, and the second terminal of the third transistor is electrically connected to the intermediate node.

[0157] The driving circuit described in at least one embodiment of this disclosure further includes an output circuit and an output reset circuit;

[0158] The output circuit is electrically connected to the first node, the drive signal output terminal and the first voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the first node.

[0159] The output reset circuit is electrically connected to the second node, the drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the second voltage terminal under the control of the second node.

[0160] In a specific implementation, the driving circuit may further include an output circuit and an output reset circuit. Under the control of the first node, the output circuit controls the connection between the driving signal output terminal and the first voltage terminal to output a driving signal. Under the control of the second node, the output reset circuit controls the connection between the driving signal output terminal and the second voltage terminal to reset the driving signal.

[0161] Optionally, the first voltage terminal can be a high voltage terminal and the second voltage terminal can be a low voltage terminal, but this is not a limitation.

[0162] As shown in Figure 9, based on at least one embodiment of the driving circuit shown in Figure 3, the driving circuit of at least one embodiment of this disclosure further includes an output circuit 91 and an output reset circuit 92.

[0163] The output circuit 91 is electrically connected to the first node Q, the drive signal output terminal GT, and the first voltage terminal V1, respectively, and is used to control the connection between the drive signal output terminal GT and the first voltage terminal V1 under the control of the first node Q.

[0164] The output reset circuit 92 is electrically connected to the second node QB, the drive signal output terminal GT, and the second voltage terminal V2, respectively, and is used to control the connection between the drive signal output terminal GT and the second voltage terminal V2 under the control of the second node QB.

[0165] As shown in Figure 10, based on at least one embodiment of the driving circuit shown in Figure 4, the driving circuit of at least one embodiment of this disclosure further includes an output circuit 91 and an output reset circuit 92.

[0166] The output circuit 91 is electrically connected to the first node Q, the drive signal output terminal GT, and the first voltage terminal V1, respectively, and is used to control the connection between the drive signal output terminal GT and the first voltage terminal V1 under the control of the first node Q.

[0167] The output reset circuit 92 is electrically connected to the second node QB, the drive signal output terminal GT, and the second voltage terminal V2, respectively, and is used to control the connection between the drive signal output terminal GT and the second voltage terminal V2 under the control of the second node QB.

[0168] The driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit, a carry reset circuit, an output circuit, and an output reset circuit;

[0169] The carry output circuit is electrically connected to the first node, the carry signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry signal output terminal and the first voltage terminal under the control of the first node.

[0170] The carry reset circuit is electrically connected to the second node, the carry signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the carry signal output terminal and the second voltage terminal under the control of the second node.

[0171] The output circuit is electrically connected to the first node, the drive signal output terminal and the fifth voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the fifth voltage terminal under the control of the first node.

[0172] The output reset circuit is electrically connected to the second node, the drive signal output terminal, and the sixth voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the sixth voltage terminal under the control of the second node.

[0173] Optionally, the first voltage terminal can be a first high voltage terminal, the second voltage terminal can be a first low voltage terminal, the fifth voltage terminal can be a second high voltage terminal, and the sixth voltage terminal can be a second low voltage terminal, but this is not a limitation.

[0174] As shown in Figure 11, based on at least one embodiment of the driving circuit shown in Figure 7, the driving circuit described in at least one embodiment of this disclosure further includes a carry output circuit 111, a carry reset circuit 112, an output circuit 91, and an output reset circuit 92.

[0175] The carry output circuit 111 is electrically connected to the first node Q, the carry signal output terminal CR, and the first voltage terminal V1, respectively, and is used to control the connection between the carry signal output terminal CR and the first voltage terminal V1 under the control of the first node Q.

[0176] The carry reset circuit 112 is electrically connected to the second node QB, the carry signal output terminal CR, and the second voltage terminal V2, respectively, and is used to control the connection between the carry signal output terminal CR and the second voltage terminal V2 under the control of the second node QB.

[0177] The output circuit 91 is electrically connected to the first node Q, the drive signal output terminal GT, and the fifth voltage terminal V5, respectively, and is used to control the connection between the drive signal output terminal GT and the fifth voltage terminal V5 under the control of the first node Q.

[0178] The output reset circuit 92 is electrically connected to the second node QB, the drive signal output terminal GT, and the sixth voltage terminal V6, respectively, and is used to control the connection between the drive signal output terminal GT and the sixth voltage terminal V6 under the control of the second node QB.

[0179] As shown in Figure 12, based on at least one embodiment of the driving circuit shown in Figure 8, the driving circuit of at least one embodiment of this disclosure further includes a carry output circuit 111, a carry reset circuit 112, an output circuit 91, and an output reset circuit 92.

[0180] The carry output circuit 111 is electrically connected to the first node Q, the carry signal output terminal CR, and the first voltage terminal V1, respectively, and is used to control the connection between the carry signal output terminal CR and the first voltage terminal V1 under the control of the first node Q.

[0181] The carry reset circuit 112 is electrically connected to the second node QB, the carry signal output terminal CR, and the second voltage terminal V2, respectively, and is used to control the connection between the carry signal output terminal CR and the second voltage terminal V2 under the control of the second node QB.

[0182] The output circuit 91 is electrically connected to the first node Q, the drive signal output terminal GT, and the fifth voltage terminal V5, respectively, and is used to control the connection between the drive signal output terminal GT and the fifth voltage terminal V5 under the control of the first node Q.

[0183] The output reset circuit 92 is electrically connected to the second node QB, the drive signal output terminal GT, and the sixth voltage terminal V6, respectively, and is used to control the connection between the drive signal output terminal GT and the sixth voltage terminal V6 under the control of the second node QB.

[0184] In at least one embodiment of this disclosure, the second node control circuit is also electrically connected to the first control node, and is used to control the potential of the second node under the control of the first control node;

[0185] The drive circuit also includes a control energy storage circuit;

[0186] The control energy storage circuit is electrically connected to the control clock signal terminal and the second control node, respectively, and is used to control the potential of the second control node according to the control clock signal.

[0187] In specific implementation, the second node control circuit, under the control of the first control node, controls the potential of the second node and resets the potential of the second node. The control energy storage circuit controls the potential of the second control node according to the control clock signal.

[0188] The driving circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0189] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output terminal. The first energy storage circuit is used to store electrical energy.

[0190] The second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to maintain the potential of the second node.

[0191] As shown in Figure 13, based on at least one embodiment of the driving circuit shown in Figure 9, the second node control circuit 14 is also electrically connected to the first control node Q1, and is used to control the potential of the second node QB under the control of the first control node Q1.

[0192] The driving circuit described in at least one embodiment of this disclosure may further include a control energy storage circuit 130, a first energy storage circuit 131, and a second energy storage circuit 132.

[0193] The first terminal of the control energy storage circuit 130 is electrically connected to the control clock signal terminal CKC, and the second terminal of the control energy storage circuit 130 is electrically connected to the second control node QB1. The control energy storage circuit 130 is used to control the potential of the second control node QB1 according to the control clock signal provided by the control clock signal terminal CKC.

[0194] The first terminal of the first energy storage circuit 131 is electrically connected to the first node Q, and the second terminal of the first energy storage circuit 131 is electrically connected to the drive signal output terminal GT. The first energy storage circuit 131 is used to store electrical energy.

[0195] The first terminal of the second energy storage circuit 132 is electrically connected to the second node QB, and the second terminal of the second energy storage circuit 132 is electrically connected to the second voltage terminal V2. The second energy storage circuit 132 is used to maintain the potential of the second node QB.

[0196] As shown in Figure 14, based on at least one embodiment of the driving circuit shown in Figure 10, the second node control circuit 14 is also electrically connected to the first control node Q1, and is used to control the potential of the second node QB under the control of the first control node Q1.

[0197] The driving circuit described in at least one embodiment of this disclosure may further include a control energy storage circuit 130, a first energy storage circuit 131, and a second energy storage circuit 132.

[0198] The first terminal of the control energy storage circuit 130 is electrically connected to the control clock signal terminal CKC, and the second terminal of the control energy storage circuit 130 is electrically connected to the second control node QB1. The control energy storage circuit 130 is used to control the potential of the second control node QB1 according to the control clock signal provided by the control clock signal terminal CKC.

[0199] The first terminal of the first energy storage circuit 131 is electrically connected to the first node Q, and the second terminal of the first energy storage circuit 131 is electrically connected to the drive signal output terminal GT. The first energy storage circuit 131 is used to store electrical energy.

[0200] The first terminal of the second energy storage circuit 132 is electrically connected to the second node QB, and the second terminal of the second energy storage circuit 132 is electrically connected to the second voltage terminal V2. The second energy storage circuit 132 is used to maintain the potential of the second node QB.

[0201] The driving circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit and a second energy storage circuit;

[0202] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the carry signal output terminal. The first energy storage circuit is used to store electrical energy.

[0203] The second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to maintain the potential of the second node.

[0204] As shown in Figure 15, based on at least one embodiment of the driving circuit shown in Figure 11, the second node control circuit 14 is also electrically connected to the first control node Q1, and is used to control the potential of the second node QB under the control of the first control node Q1.

[0205] The driving circuit described in at least one embodiment of this disclosure may further include a control energy storage circuit 130, a first energy storage circuit 131, and a second energy storage circuit 132.

[0206] The first terminal of the control energy storage circuit 130 is electrically connected to the control clock signal terminal CKC, and the second terminal of the control energy storage circuit 130 is electrically connected to the second control node QB1. The control energy storage circuit 130 is used to control the potential of the second control node QB1 according to the control clock signal provided by the control clock signal terminal CKC.

[0207] The first terminal of the first energy storage circuit 131 is electrically connected to the first node Q, and the second terminal of the first energy storage circuit 131 is electrically connected to the carry signal output terminal CR. The first energy storage circuit 131 is used to store electrical energy.

[0208] The first terminal of the second energy storage circuit 132 is electrically connected to the second node QB, and the second terminal of the second energy storage circuit 132 is electrically connected to the second voltage terminal V2. The second energy storage circuit 132 is used to maintain the potential of the second node QB.

[0209] As shown in Figure 16, based on at least one embodiment of the driving circuit shown in Figure 12, the second node control circuit 14 is also electrically connected to the first control node Q1, and is used to control the potential of the second node QB under the control of the first control node Q1.

[0210] The driving circuit described in at least one embodiment of this disclosure may further include a control energy storage circuit 130, a first energy storage circuit 131, and a second energy storage circuit 132.

[0211] The first terminal of the control energy storage circuit 130 is electrically connected to the control clock signal terminal CKC, and the second terminal of the control energy storage circuit 130 is electrically connected to the second control node QB1. The control energy storage circuit 130 is used to control the potential of the second control node QB1 according to the control clock signal provided by the control clock signal terminal CKC.

[0212] The first terminal of the first energy storage circuit 131 is electrically connected to the first node Q, and the second terminal of the first energy storage circuit 131 is electrically connected to the carry signal output terminal CR. The first energy storage circuit 131 is used to store electrical energy.

[0213] The first terminal of the second energy storage circuit 132 is electrically connected to the second node QB, and the second terminal of the second energy storage circuit 132 is electrically connected to the second voltage terminal V2. The second energy storage circuit 132 is used to maintain the potential of the second node QB.

[0214] Optionally, the first control node control circuit includes a fourth transistor, and the first node control circuit includes a fifth transistor.

[0215] The gate of the fourth transistor is electrically connected to the control clock signal terminal, the first terminal of the fourth transistor is electrically connected to the input terminal, and the second terminal of the fourth transistor is electrically connected to the first control node.

[0216] The gate of the fifth transistor is electrically connected to the first voltage terminal, the first terminal of the fifth transistor is electrically connected to the first control node, and the second terminal of the fifth transistor is electrically connected to the first node.

[0217] Optionally, the second node control circuit includes a sixth transistor and a seventh transistor;

[0218] The gate of the sixth transistor is electrically connected to the second control node, the first terminal of the sixth transistor is electrically connected to the control clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0219] The gate of the seventh transistor is electrically connected to the first control node, the first terminal of the seventh transistor is electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

[0220] Optionally, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor;

[0221] The gate of the output transistor is electrically connected to the first node, the first terminal of the output transistor is electrically connected to the first voltage terminal, and the second terminal of the output transistor is electrically connected to the drive signal output terminal.

[0222] The gate of the output reset transistor is electrically connected to the second node, the first terminal of the output reset transistor is electrically connected to the drive signal output terminal, and the second terminal of the output reset transistor is electrically connected to the second voltage terminal.

[0223] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a carry reset transistor, the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor.

[0224] The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the first voltage terminal, and the second terminal of the carry output transistor is electrically connected to the carry signal output terminal.

[0225] The gate of the carry reset transistor is electrically connected to the second node, the first terminal of the carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the carry reset transistor is electrically connected to the second voltage terminal.

[0226] The gate of the output transistor is electrically connected to the first node, the first terminal of the output transistor is electrically connected to the fifth voltage terminal, and the second terminal of the output transistor is electrically connected to the drive signal output terminal.

[0227] The gate of the output reset transistor is electrically connected to the second node, the first terminal of the output reset transistor is electrically connected to the drive signal output terminal, and the second terminal of the output reset transistor is electrically connected to the sixth voltage terminal.

[0228] As shown in Figure 17, based on at least one embodiment of the driving circuit shown in Figure 13,

[0229] The control circuit of the second control node includes a first transistor T1;

[0230] The gate of the first transistor T1 is electrically connected to the first node Q(n-1) in the adjacent previous stage driving circuit, the drain of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the source of the first transistor T1 is electrically connected to the second control node QB1.

[0231] The first control node control circuit includes a fourth transistor T4, and the first node control circuit includes a fifth transistor T5;

[0232] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the drain of the fourth transistor T4 is electrically connected to the input terminal I1, and the source of the fourth transistor T4 is electrically connected to the first control node Q1.

[0233] The gate of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, the drain of the fifth transistor T5 is electrically connected to the first control node Q1, and the source of the fifth transistor T5 is electrically connected to the first node Q.

[0234] The second node control circuit includes a sixth transistor T6 and a seventh transistor T7;

[0235] The gate of the sixth transistor T6 is electrically connected to the second control node QB1, the drain of the sixth transistor T6 is electrically connected to the first clock signal terminal CK1, and the source of the sixth transistor T6 is electrically connected to the second node QB.

[0236] The gate of the seventh transistor T7 is electrically connected to the first control node Q1, the drain of the seventh transistor T7 is electrically connected to the low voltage terminal VGL, and the source of the seventh transistor T7 is electrically connected to the second node QB.

[0237] The output circuit includes an output transistor TS, and the output reset circuit includes an output reset transistor TF.

[0238] The gate of the output transistor TS is electrically connected to the first node Q, the drain of the output transistor TS is electrically connected to the high voltage terminal VGH, and the source of the output transistor TS is electrically connected to the drive signal output terminal GT.

[0239] The gate of the output reset transistor TF is electrically connected to the second node QB, the drain of the output reset transistor TF is electrically connected to the drive signal output terminal GT, and the source of the output reset transistor TF is electrically connected to the low voltage terminal VGL.

[0240] The first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, and the control energy storage circuit includes a third capacitor C3;

[0241] The first end of the first capacitor C1 is electrically connected to the first node Q, and the second end of the first capacitor C1 is electrically connected to the drive signal output terminal GT.

[0242] The first terminal of the second capacitor C2 is electrically connected to the second node QB, and the second terminal of the second capacitor C2 is electrically connected to the low voltage terminal VGL.

[0243] The first terminal of the third capacitor C3 is electrically connected to the first clock signal terminal CK1, and the second terminal of the third capacitor C3 is electrically connected to the second control node QB.

[0244] In at least one embodiment of the driving circuit shown in Figure 17, the control clock signal terminal is a first clock signal terminal, the first voltage terminal is a high voltage terminal, and the second voltage terminal is a low voltage terminal.

[0245] In at least one embodiment of the driving circuit shown in Figure 17, all transistors are n-type transistors and all transistors are oxide transistors, but are not limited thereto.

[0246] As shown in FIG18, when at least one embodiment of the driving circuit shown in FIG17 of this disclosure is in operation, the display cycle may include a first stage t1, a second stage t2 and a third stage t3 set sequentially.

[0247] In the first stage t1, I1 provides a high voltage signal, CK1 provides a high voltage signal, T4 is turned on, the potentials of Q1 and Q are high voltage, at this time, the potential of Q(n-1) is higher than the potential of the input signal provided by I1, so T1 can be fully turned on, the potential of QB1 is low voltage, T7 is turned on, the potential of QB is low voltage, TS is turned on, and GT provides a high voltage signal.

[0248] In the second stage t2, I1 provides a low voltage signal, CK1 provides a low voltage signal, T4 and T6 are both turned off, the potential of Q is maintained at a high voltage, the potential of QB is maintained at a low voltage, and GT outputs a high voltage signal.

[0249] In the third stage t3, CK1 provides a high voltage signal, I1 provides a low voltage signal, T4 is turned on, Q1 is at a low voltage, Q is at a low voltage, QB1 is coupled to a high voltage by C3, controlling T6 to conduct, QB is at a high voltage, TS is turned off, TF is turned on, and GT provides a low voltage signal.

[0250] In at least one embodiment of the driving circuit shown in Figure 17, the gate of T1 is electrically connected to Q(n-1). The potential of Q(n-1) will be bootstrap when the adjacent upstream driving circuit outputs a driving signal. The potential of Q(n-1) is higher than the potential of the driving signal output by the adjacent upstream driving circuit. For example, the potential of Q(n-1) can reach 22V, and the potential of the driving signal output by the adjacent upstream driving circuit can reach 15V. This allows T1 to reset the potential of QB1 more completely, eliminating the potential distortion of the driving signal output by GT.

[0251] As shown in Figure 19, the (n-1)th stage driving circuit includes a first first transistor T11, a first fourth transistor T14, a first fifth transistor T15, a first sixth transistor T16, a first seventh transistor T17, a first output transistor TS1, a first output reset transistor TF1, a first first capacitor C11, a first second capacitor C12, and a first third capacitor C13.

[0252] The gate of the first transistor T11 is electrically connected to the first node Q(n-2) of the (n-2)th stage, the drain of the first transistor T11 is electrically connected to the low voltage terminal VGL, and the source of the first transistor T11 is electrically connected to the second control node QB1(n-1) of the (n-1)th stage.

[0253] The gate of the first fourth transistor T14 is electrically connected to the second clock signal terminal CK2, the drain of the first fourth transistor T14 is electrically connected to the (n-2)th stage drive signal output terminal GT(n-2), and the source of the first fourth transistor T14 is electrically connected to the (n-1)th stage first control node Q1(n-1).

[0254] The gate of the first fifth transistor T15 is electrically connected to the high voltage terminal VGH, the drain of the first fifth transistor T15 is electrically connected to the first control node Q1(n-1) of the (n-1)th stage, and the source of the first fifth transistor T15 is electrically connected to the first node Q(n-1) of the (n-1)th stage.

[0255] The gate of the first sixth transistor T16 is electrically connected to the second control node QB1(n-1) of the (n-1)th stage, the drain of the first sixth transistor T16 is electrically connected to the second clock signal terminal CK2, and the source of the first sixth transistor T16 is electrically connected to the second node QB(n-1) of the (n-1)th stage.

[0256] The gate of the first seventh transistor T17 is electrically connected to the first control node Q1(n-1) of the (n-1)th stage, the drain of the first seventh transistor T17 is electrically connected to the low voltage terminal VGL, and the source of the first seventh transistor T17 is electrically connected to the second node QB(n-1) of the (n-1)th stage.

[0257] The gate of the first output transistor TS1 is electrically connected to the first node Q(n-1) of the (n-1)th stage, the drain of the first output transistor TS1 is electrically connected to the high voltage terminal VGH, and the source of the first output transistor TS1 is electrically connected to the drive signal output terminal GT(n-1) of the (n-1)th stage.

[0258] The gate of the first output reset transistor TF1 is electrically connected to the second node QB(n-1) of the (n-1)th stage, the drain of the first output reset transistor TF1 is electrically connected to the drive signal output terminal GT(n-1) of the (n-1)th stage, and the source of the first output reset transistor TF1 is electrically connected to the low voltage terminal VGL.

[0259] The first terminal of the first capacitor C11 is electrically connected to the first node Q(n-1) of the (n-1)th stage, and the second terminal of the first capacitor C11 is electrically connected to the drive signal output terminal GT(n-1) of the (n-1)th stage.

[0260] The first terminal of the first second capacitor C12 is electrically connected to the second node QB(n-1) of the (n-1)th stage, and the second terminal of the first second capacitor C12 is electrically connected to the low voltage terminal VGL.

[0261] The first terminal of the first third capacitor C13 is electrically connected to the second clock signal terminal CK2, and the second terminal of the first third capacitor C13 is electrically connected to the second control node QB(n-1) of the (n-1)th level.

[0262] The nth stage drive circuit includes a second first transistor T21, a second fourth transistor T24, a second fifth transistor T25, a second sixth transistor T26, a second seventh transistor T27, a second output transistor TS2, a second output reset transistor TF2, a second first capacitor C21, a second second capacitor C22, and a second third capacitor C23.

[0263] The gate of the second first transistor T21 is electrically connected to the first node Q(n-1) of the (n-1)th stage, the drain of the second first transistor T21 is electrically connected to the low voltage terminal VGL, and the source of the second first transistor T21 is electrically connected to the second control node QB1(n) of the nth stage.

[0264] The gate of the second fourth transistor T24 is electrically connected to the first clock signal terminal CK1, the drain of the second fourth transistor T24 is electrically connected to the (n-1)th stage drive signal output terminal GT(n-1), and the source of the second fourth transistor T24 is electrically connected to the nth stage first control node Q1(n).

[0265] The gate of the second fifth transistor T25 is electrically connected to the high voltage terminal VGH, the drain of the second fifth transistor T25 is electrically connected to the first control node Q1(n) of the nth stage, and the source of the second fifth transistor T25 is electrically connected to the first node Q(n) of the nth stage.

[0266] The gate of the second sixth transistor T26 is electrically connected to the nth level second control node QB1(n), the drain of the second sixth transistor T26 is electrically connected to the first clock signal terminal CK1, and the source of the second sixth transistor T26 is electrically connected to the nth level second node QB(n).

[0267] The gate of the second seventh transistor T27 is electrically connected to the first control node Q1(n) of the nth stage, the drain of the second seventh transistor T27 is electrically connected to the low voltage terminal VGL, and the source of the second seventh transistor T27 is electrically connected to the second node QB(n) of the nth stage.

[0268] The gate of the second output transistor TS2 is electrically connected to the first node Q(n) of the nth stage, the drain of the second output transistor TS2 is electrically connected to the high voltage terminal VGH, and the source of the second output transistor TS2 is electrically connected to the nth stage drive signal output terminal GT(n).

[0269] The gate of the second output reset transistor TF2 is electrically connected to the second node QB(n) of the nth stage, the drain of the second output reset transistor TF2 is electrically connected to the drive signal output terminal GT(n) of the nth stage, and the source of the second output reset transistor TF is electrically connected to the low voltage terminal VGL.

[0270] The first terminal of the second first capacitor C21 is electrically connected to the first node Q(n) of the nth stage, and the second terminal of the second first capacitor C21 is electrically connected to the drive signal output terminal GT(n) of the nth stage.

[0271] The first terminal of the second capacitor C22 is electrically connected to the second node QB(n) of the nth stage, and the second terminal of the second capacitor C22 is electrically connected to the low voltage terminal VGL.

[0272] The first terminal of the second third capacitor C23 is electrically connected to the first clock signal terminal CK1, and the second terminal of the second third capacitor C23 is electrically connected to the nth level second control node QB(n).

[0273] n is a positive integer.

[0274] In at least one embodiment of the driving circuit shown in Figure 19, in the (n-1)th stage driving circuit, the control clock signal terminal is the second clock signal terminal, and in the nth stage driving circuit, the control clock signal terminal is the first clock signal terminal.

[0275] In at least one embodiment of the driving circuit shown in Figure 19, all transistors are n-type transistors and all transistors are oxide transistors, but are not limited thereto.

[0276] Figure 20 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 19.

[0277] The difference between at least one embodiment of the driving circuit shown in Figure 21 and at least one embodiment of the driving circuit shown in Figure 17 is that:

[0278] The gate of the first transistor T1 is electrically connected to the first control node Q1(n-1) in the adjacent previous stage driving circuit.

[0279] In at least one embodiment of the drive circuit shown in Figure 21 of this disclosure, when the potential of Q1 is high, the potential of Q1 is 22V when CK1 provides a high voltage signal, and the potential of Q1 is 15V when CK1 provides a low voltage signal, so as to reduce the PBTS (Positive Bias Temperature Stabilization) of T1.

[0280] As shown in Figure 22, based on at least one embodiment of the driving circuit shown in Figure 15, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the third control circuit includes a third transistor T3.

[0281] The gate of the first transistor T1 is connected to the first node Q(n-1) in the adjacent previous stage driving circuit, the drain of the first transistor T1 is electrically connected to the first low voltage terminal VGL1, and the source of the first transistor T1 is electrically connected to the intermediate node P.

[0282] The gate of the second transistor T2 is electrically connected to the first node Q(n-1) in the adjacent previous stage driving circuit, the drain of the second transistor T2 is electrically connected to the intermediate node P, and the source of the second transistor T2 is electrically connected to the second control node QB1.

[0283] The gate of the third transistor T3 is electrically connected to the second control node QB1, the drain of the third transistor T3 is electrically connected to the second high voltage terminal VGH2, and the source of the third transistor T3 is electrically connected to the intermediate node P.

[0284] The first control node control circuit includes a fourth transistor T4, and the first node control circuit includes a fifth transistor T5;

[0285] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the drain of the fourth transistor T4 is electrically connected to the input terminal I1, and the source of the fourth transistor T4 is electrically connected to the first control node Q1.

[0286] The gate of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, the drain of the fifth transistor T5 is electrically connected to the first control node Q1, and the source of the fifth transistor T5 is electrically connected to the first node Q.

[0287] The second node control circuit includes a sixth transistor T6 and a seventh transistor T7;

[0288] The gate of the sixth transistor T6 is electrically connected to the second control node QB1, the drain of the sixth transistor T6 is electrically connected to the first clock signal terminal CK1, and the source of the sixth transistor T6 is electrically connected to the second node QB.

[0289] The gate of the seventh transistor T7 is electrically connected to the first control node Q1, the drain of the seventh transistor T7 is electrically connected to the low voltage terminal VGL, and the source of the seventh transistor T7 is electrically connected to the second node QB.

[0290] The carry output circuit includes a carry output transistor TR, and the carry reset circuit includes a carry reset transistor TRF; the output circuit includes an output transistor TS, and the output reset circuit includes an output reset transistor TF.

[0291] The gate of the carry output transistor TR is electrically connected to the first node Q, the drain of the carry output transistor TR is electrically connected to the first high voltage terminal VGH1, and the source of the carry output transistor TR is electrically connected to the carry signal output terminal CR.

[0292] The gate of the carry reset transistor TRF is electrically connected to the second node QB, the drain of the carry reset transistor TRF is electrically connected to the carry signal output terminal CR, and the source of the carry reset transistor TRF is electrically connected to the first low voltage terminal VGL1.

[0293] The gate of the output transistor TS is electrically connected to the first node Q, the drain of the output transistor TS is electrically connected to the second high voltage terminal VGH2, and the source of the output transistor TS is electrically connected to the drive signal output terminal GT.

[0294] The gate of the output reset transistor TF is electrically connected to the second node QB, the drain of the output reset transistor TF is electrically connected to the drive signal output terminal GT, and the source of the output reset transistor TF is electrically connected to the second low voltage terminal VGL2.

[0295] The control energy storage circuit includes a third capacitor C3, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2.

[0296] The first terminal of the third capacitor C3 is electrically connected to the first clock signal terminal CK1, and the second terminal of the third capacitor C3 is electrically connected to the second control node QB1.

[0297] The first terminal of the first capacitor C1 is electrically connected to the first node Q, and the second terminal of the first capacitor C1 is electrically connected to the carry signal output terminal CR.

[0298] The first end of the second capacitor C2 is electrically connected to the second node QB, and the second end of the second capacitor C2 is electrically connected to the first low voltage terminal VGL1.

[0299] In at least one embodiment of the driving circuit shown in Figure 22, all transistors are n-type transistors and all transistors are oxide transistors, but are not limited thereto.

[0300] In at least one embodiment of the driving circuit shown in Figure 22, I1 is electrically connected to the carry signal output terminal in the adjacent previous stage driving circuit.

[0301] In at least one embodiment of the drive circuit shown in Figure 22 of this disclosure, when the potential of QB1 is high, T3 is turned on, VGH2 is connected to P, and the potential of P is high, which can improve the problem of potential drop of QB1 due to leakage.

[0302] Figure 23 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 22 of this disclosure.

[0303] As shown in Figure 24, the nth stage driving circuit includes a first transistor T11, a first second transistor T12, a first third transistor T13, a first fourth transistor T14, a first fifth transistor T15, a first sixth transistor T16, a first seventh transistor T17, a first carry output transistor TR1, a first carry reset transistor TRF1, a first output transistor TS1, a first output reset transistor TF1, a first first capacitor C11, a first second capacitor C12, and a first third capacitor C13;

[0304] The gate of the first transistor T11 is connected to the first node Q(n-1) of the (n-1)th stage, the drain of the first transistor T11 is electrically connected to the first low voltage terminal VGL1, and the source of the first transistor T11 is electrically connected to the intermediate node P(n) of the nth stage.

[0305] The gate of the first second transistor T12 is electrically connected to the first node Q(n-1) of the (n-1)th stage, the drain of the first second transistor T12 is electrically connected to the intermediate node P(n) of the nth stage, and the source of the first second transistor T12 is electrically connected to the second control node QB1(n) of the nth stage.

[0306] The gate of the first third transistor T13 is electrically connected to the second control node QB1(n) of the nth stage, the drain of the first third transistor T13 is electrically connected to the second high voltage terminal VGH2, and the source of the first third transistor T13 is electrically connected to the intermediate node P(n) of the nth stage.

[0307] The gate of the first fourth transistor T14 is electrically connected to the first clock signal terminal CK1, the drain of the first fourth transistor T14 is electrically connected to the carry signal output terminal CR(n-1) of the (n-1)th stage, and the source of the first fourth transistor T14 is electrically connected to the first control node Q1(n) of the nth stage.

[0308] The gate of the first fifth transistor T15 is electrically connected to the first high voltage terminal VGH1, the drain of the first fifth transistor T15 is electrically connected to the first control node Q1(n) of the nth stage, and the source of the first fifth transistor T15 is electrically connected to the first node Q(n) of the nth stage.

[0309] The gate of the first sixth transistor T16 is electrically connected to the second control node QB1(n) of the nth stage, the drain of the first sixth transistor T16 is electrically connected to the first clock signal terminal CK1, and the source of the first sixth transistor T16 is electrically connected to the second node QB(n) of the nth stage.

[0310] The gate of the first seventh transistor T17 is electrically connected to the first control node Q1(n) of the nth stage, the drain of the first seventh transistor T17 is electrically connected to the first low voltage terminal VGL1, and the source of the first seventh transistor T17 is electrically connected to the second node QB(n) of the nth stage.

[0311] The gate of the first carry output transistor TR1 is electrically connected to the first node Q(n) of the nth stage, the drain of the first carry output transistor TR1 is electrically connected to the first high voltage terminal VGH1, and the source of the first carry output transistor TR1 is electrically connected to the carry signal output terminal CR(n) of the nth stage.

[0312] The gate of the first carry reset transistor TRF1 is electrically connected to the second node QB(n) of the nth stage, the drain of the first carry reset transistor TRF1 is electrically connected to the carry signal output terminal CR(n) of the nth stage, and the source of the first carry reset transistor TRF1 is electrically connected to the first low voltage terminal VGL1.

[0313] The gate of the first output transistor TS1 is electrically connected to the first node Q(n) of the nth stage, the drain of the first output transistor TS1 is electrically connected to the first high voltage terminal VGH1, and the source of the first output transistor TS1 is electrically connected to the nth stage drive signal output terminal GT(n).

[0314] The gate of the first output reset transistor TF1 is electrically connected to the second node QB(n) of the nth stage, the drain of the first output reset transistor TF1 is electrically connected to the drive signal output terminal GT(n) of the nth stage, and the source of the first output reset transistor TF1 is electrically connected to the first low voltage terminal VGL1.

[0315] The first terminal of the first third capacitor C13 is electrically connected to the first clock signal terminal CK1, and the second terminal of the first third capacitor C13 is electrically connected to the nth level second control node QB1(n).

[0316] The first terminal of the first capacitor C11 is electrically connected to the first node Q(n) of the nth stage, and the second terminal of the first capacitor C11 is electrically connected to the carry signal output terminal CR(n) of the nth stage.

[0317] The first terminal of the first second capacitor C12 is electrically connected to the second node QB(n) of the nth stage, and the second terminal of the first second capacitor C12 is electrically connected to the first low voltage terminal VGL1.

[0318] n is a positive integer;

[0319] The (n+1)th stage drive circuit includes a second first transistor T21, a second fourth transistor T24, a second fifth transistor T25, a second sixth transistor T26, a second seventh transistor T27, a second carry output transistor TR2, a second carry reset transistor TRF2, a second output transistor TS2, a second output reset transistor TF2, a second first capacitor C21, a second second capacitor C22, and a second third capacitor C23;

[0320] The gate of the second first transistor T21 is connected to the first node Q(n) of the nth stage, the drain of the second first transistor T21 is electrically connected to the intermediate node P(n) of the nth stage, and the source of the second first transistor T21 is electrically connected to the second control node QB1(n+1) of the n+1th stage.

[0321] The gate of the second fourth transistor T24 is electrically connected to the second clock signal terminal CK2, the drain of the second fourth transistor T24 is electrically connected to the nth stage carry signal output terminal CR(n), and the source of the second fourth transistor T24 is electrically connected to the n+1th stage first control node Q1(n+1).

[0322] The gate of the second fifth transistor T25 is electrically connected to the first high voltage terminal VGH1, the drain of the second fifth transistor T25 is electrically connected to the first control node Q1(n+1) of the (n+1)th stage, and the source of the second fifth transistor T25 is electrically connected to the first node Q(n+1) of the (n+1)th stage.

[0323] The gate of the second sixth transistor T26 is electrically connected to the second control node QB1(n+1) of the (n+1)th stage, the drain of the second sixth transistor T26 is electrically connected to the second clock signal terminal CK2, and the source of the second sixth transistor T26 is electrically connected to the second node QB(n+1) of the (n+1)th stage.

[0324] The gate of the second seventh transistor T27 is electrically connected to the first control node Q1(n+1) of the (n+1)th stage, the drain of the second seventh transistor T27 is electrically connected to the first low voltage terminal VGL1, and the source of the second seventh transistor T27 is electrically connected to the second node QB(n+1) of the (n+1)th stage.

[0325] The gate of the second carry output transistor TR2 is electrically connected to the first node Q(n+1) of the (n+1)th stage, the drain of the second carry output transistor TR2 is electrically connected to the first high voltage terminal VGH1, and the source of the second carry output transistor TR2 is electrically connected to the carry signal output terminal CR(n+1) of the (n+1)th stage.

[0326] The gate of the second carry reset transistor TRF2 is electrically connected to the second node QB(n+1) of the (n+1)th stage, the drain of the second carry reset transistor TRF2 is electrically connected to the carry signal output terminal CR(n+1) of the (n+1)th stage, and the source of the second carry reset transistor TRF2 is electrically connected to the first low voltage terminal VGL1.

[0327] The gate of the second output transistor TS2 is electrically connected to the first node Q(n+1) of the (n+1)th stage, the drain of the second output transistor TS2 is electrically connected to the first high voltage terminal VGH1, and the source of the second output transistor TS2 is electrically connected to the drive signal output terminal GT(n+1) of the (n+1)th stage.

[0328] The gate of the second output reset transistor TF2 is electrically connected to the second node QB(n+1) of the (n+1)th stage, the drain of the second output reset transistor TF2 is electrically connected to the drive signal output terminal GT(n+1) of the (n+1)th stage, and the source of the second output reset transistor TF2 is electrically connected to the first low voltage terminal VGL1.

[0329] The first terminal of the second third capacitor C23 is electrically connected to the second clock signal terminal CK2, and the second terminal of the second third capacitor C23 is electrically connected to the second control node QB1(n+1) of the (n+1)th level.

[0330] The first terminal of the second first capacitor C21 is electrically connected to the first node Q(n+1) of the (n+1)th stage, and the second terminal of the second first capacitor C21 is electrically connected to the carry signal output terminal CR(n+1) of the (n+1)th stage.

[0331] The first terminal of the second capacitor C22 is electrically connected to the second node QB(n+1) of the (n+1)th stage, and the second terminal of the second capacitor C22 is electrically connected to the first low voltage terminal VGL1.

[0332] In at least one embodiment of the driving circuit shown in Figure 24, in the nth stage driving circuit, the control clock signal terminal is the first clock signal terminal, and in the (n+1)th stage driving circuit, the control clock signal terminal is the second clock signal terminal.

[0333] In at least one embodiment of the driving circuit shown in Figure 24, the nth stage driving circuit and the (n+1)th stage driving circuit share the nth stage intermediate node P(n).

[0334] The difference between at least one embodiment of the driving circuit shown in Figure 25 and at least one embodiment of the driving circuit shown in Figure 22 is that:

[0335] The gates of T1 and T2 are both electrically connected to the first control node Q1(n-1) in the adjacent previous stage drive circuit.

[0336] The difference between at least one embodiment of the driving circuit shown in Figure 26 and at least one embodiment of the driving circuit shown in Figure 17 is that all transistors are p-type transistors.

[0337] Figure 27 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 26.

[0338] The difference between at least one embodiment of the driving circuit shown in Figure 28 and at least one embodiment of the driving circuit shown in Figure 26 is that the gate of T1 is electrically connected to the first control node Q1(n-1) in the (n-1)th stage driving circuit.

[0339] The driving module described in this embodiment includes multiple stages of the aforementioned driving circuits.

[0340] In at least one embodiment of this disclosure, the node control terminal of the a-th stage driving circuit is the first node in the am-th stage driving circuit or the first control node in the am-th stage driving circuit.

[0341] Both a and m are positive integers.

[0342] Optionally, the second control node control circuit in the nth stage drive circuit includes an nth stage first control circuit, an nth stage second control circuit, and an nth stage third control circuit; n is a positive integer;

[0343] The second control node control circuit in the (n+1)th stage drive circuit is electrically connected to the (n+1)th node control terminal, the (n+1)th stage second control node, and the nth stage intermediate node, respectively, and is used to control the (n+1)th stage second control node to connect with the adjacent previous stage intermediate node under the control of the signal provided by the (n+1)th node control terminal.

[0344] The first control circuit of the nth level is electrically connected to the control terminal of the nth node, the third voltage terminal and the intermediate node of the nth level respectively, and is used to control the connection between the intermediate node of the nth level and the third voltage terminal under the control of the signal provided by the control terminal of the nth node;

[0345] The nth-level second control circuit is electrically connected to the nth-node control terminal, the nth-level intermediate node, and the nth-level second control node, respectively, and is used to control the connection between the nth-level intermediate node and the nth-level second control node under the control of the signal provided by the nth-node control terminal;

[0346] The nth-level third control circuit is electrically connected to the nth-level second control node, the nth-level intermediate node, and the fourth voltage terminal, respectively, and is used to control the connection between the nth-level intermediate node and the fourth voltage terminal under the control of the nth-level second control node.

[0347] The driving method described in this embodiment is applied to the above-mentioned driving circuit, and the driving method includes:

[0348] The first control node control circuit controls the connection between the first control node and the input terminal under the control of the control clock signal;

[0349] The first node control circuit controls the connection between the first control node and the first node under the control of the first voltage signal;

[0350] The second control node control circuit controls the potential of the second control node under the control of the potential of the first node in the adjacent upper m-level drive circuit or the control of the first control node in the adjacent upper m-level drive circuit; m is a positive integer.

[0351] The second node control circuit, under the control of the second control node, controls the potential of the second node according to the control clock signal.

[0352] In at least one embodiment of this disclosure, the step of controlling the potential of the second control node under the control of the potential of the first node in the adjacent upper m-level driving circuit or the control of the first control node in the adjacent upper m-level driving circuit includes:

[0353] The second control node control circuit controls the connection between the second control node and the second voltage terminal or the adjacent upper-level intermediate node under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

[0354] Optionally, the second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit; the step of controlling the potential of the second control node under the control of the potential of the first node in the adjacent upper m-stage drive circuit or the control of the first control node in the adjacent upper m-stage drive circuit includes:

[0355] The first control circuit controls the connection between the intermediate node and the third voltage terminal under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

[0356] The second control circuit controls the connection between the intermediate node and the second control node under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

[0357] Under the control of the second control node, the third control circuit controls the connection between the intermediate node and the fourth voltage terminal.

[0358] In at least one embodiment of this disclosure, the driving circuit further includes an output circuit and an output reset circuit; the driving method further includes:

[0359] Under the control of the first node, the output circuit controls the connection between the drive signal output terminal and the first voltage terminal;

[0360] Under the control of the second node, the output reset circuit controls the connection between the drive signal output terminal and the second voltage terminal;

[0361] The second node control circuit controls the potential of the second node under the control of the first node.

[0362] The display device described in this disclosure includes the driving module described above.

[0363] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving circuit, comprising a first control node control circuit, a first node control circuit, a second control node control circuit, and a second node control circuit; The first control node control circuit is electrically connected to the control clock signal terminal, the input terminal and the first control node respectively, and is used to control the connection between the first control node and the input terminal under the control of the control clock signal provided by the control clock signal terminal; The first node control circuit is electrically connected to the first voltage terminal, the first control node, and the first node, respectively, and is used to control the connection between the first control node and the first node under the control of the first voltage signal provided by the first voltage terminal; The second control node control circuit is electrically connected to the node control terminal and the second control node respectively, and is used to control the potential of the second control node under the control of the signal provided by the node control terminal; The node control terminal is the first node in the adjacent upper m-level drive circuit or the first control node in the adjacent upper m-level drive circuit. m is a positive integer; The second node control circuit is electrically connected to the second control node, the control clock signal terminal, and the second node, respectively, and is used to control the potential of the second node according to the control clock signal provided by the control clock signal terminal under the control of the second control node.

2. The driving circuit as described in claim 1, wherein, The second control node control circuit is also electrically connected to the second voltage terminal or the adjacent upper-level intermediate node, and is used to control the connection between the second control node and the second voltage terminal or the adjacent upper-level intermediate node under the control of the signal provided by the node control terminal.

3. The driving circuit as described in claim 2, wherein, The control circuit of the second control node includes a first transistor; The gate of the first transistor is electrically connected to the node control terminal, the first terminal of the first transistor is electrically connected to the second voltage terminal or the adjacent intermediate node of the previous stage, and the second terminal of the first transistor is electrically connected to the second control node.

4. The driving circuit as described in claim 1, wherein, The second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit; The first control circuit is electrically connected to the node control terminal, the third voltage terminal and the intermediate node respectively, and is used to control the connection between the intermediate node and the third voltage terminal under the control of the signal provided by the node control terminal; The second control circuit is electrically connected to the node control terminal, the intermediate node, and the second control node, respectively, and is used to control the connection between the intermediate node and the second control node under the control of the signal provided by the node control terminal; The third control circuit is electrically connected to the second control node, the intermediate node, and the fourth voltage terminal, respectively, and is used to control the connection between the intermediate node and the fourth voltage terminal under the control of the second control node.

5. The driving circuit as described in claim 4, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; The gate of the first transistor is electrically connected to the node control terminal, the first terminal of the first transistor is electrically connected to the third voltage terminal, and the second terminal of the first transistor is electrically connected to the intermediate node. The gate of the second transistor is electrically connected to the node control terminal, the first terminal of the second transistor is electrically connected to the intermediate node, and the second terminal of the second transistor is electrically connected to the second control node. The gate of the third transistor is electrically connected to the second control node, the first terminal of the third transistor is electrically connected to the fourth voltage terminal, and the second terminal of the third transistor is electrically connected to the intermediate node.

6. The driving circuit according to any one of claims 1 to 5, wherein, It also includes an output circuit and an output reset circuit; The output circuit is electrically connected to the first node, the drive signal output terminal and the first voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the first node. The output reset circuit is electrically connected to the second node, the drive signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the second voltage terminal under the control of the second node.

7. The driving circuit according to any one of claims 1 to 5, wherein, It also includes a carry-out circuit, a carry-reset circuit, an output circuit, and an output-reset circuit; The carry output circuit is electrically connected to the first node, the carry signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry signal output terminal and the first voltage terminal under the control of the first node. The carry reset circuit is electrically connected to the second node, the carry signal output terminal, and the second voltage terminal, respectively, and is used to control the connection between the carry signal output terminal and the second voltage terminal under the control of the second node. The output circuit is electrically connected to the first node, the drive signal output terminal and the fifth voltage terminal respectively, and is used to control the connection between the drive signal output terminal and the fifth voltage terminal under the control of the first node. The output reset circuit is electrically connected to the second node, the drive signal output terminal, and the sixth voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the sixth voltage terminal under the control of the second node.

8. The driving circuit according to any one of claims 1 to 3, wherein, The second node control circuit is also electrically connected to the first control node, and is used to control the potential of the second node under the control of the first control node; The drive circuit also includes a control energy storage circuit; The control energy storage circuit is electrically connected to the control clock signal terminal and the second control node, respectively, and is used to control the potential of the second control node according to the control clock signal.

9. The driving circuit as described in claim 7, wherein, It also includes a first energy storage circuit and a second energy storage circuit; The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output terminal. The first energy storage circuit is used to store electrical energy. The second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to maintain the potential of the second node.

10. The driving circuit as claimed in claim 7, wherein, It also includes a first energy storage circuit and a second energy storage circuit; The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the carry signal output terminal. The first energy storage circuit is used to store electrical energy. The second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is used to maintain the potential of the second node.

11. The driving circuit as claimed in claim 1, wherein, The first control node control circuit includes a fourth transistor, and the first node control circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the control clock signal terminal, the first terminal of the fourth transistor is electrically connected to the input terminal, and the second terminal of the fourth transistor is electrically connected to the first control node. The gate of the fifth transistor is electrically connected to the first voltage terminal, the first terminal of the fifth transistor is electrically connected to the first control node, and the second terminal of the fifth transistor is electrically connected to the first node.

12. The driving circuit as described in claim 8, wherein, The second node control circuit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is electrically connected to the second control node, the first terminal of the sixth transistor is electrically connected to the control clock signal terminal, and the second terminal of the sixth transistor is electrically connected to the second node. The gate of the seventh transistor is electrically connected to the first control node, the first terminal of the seventh transistor is electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the second node.

13. The driving circuit as described in claim 6, wherein, The output circuit includes an output transistor, and the output reset circuit includes an output reset transistor; The gate of the output transistor is electrically connected to the first node, the first terminal of the output transistor is electrically connected to the first voltage terminal, and the second terminal of the output transistor is electrically connected to the drive signal output terminal. The gate of the output reset transistor is electrically connected to the second node, the first terminal of the output reset transistor is electrically connected to the drive signal output terminal, and the second terminal of the output reset transistor is electrically connected to the second voltage terminal.

14. The driving circuit as described in claim 7, wherein, The carry output circuit includes a carry output transistor, and the carry reset circuit includes a carry reset transistor; the output circuit includes an output transistor, and the output reset circuit includes an output reset transistor. The gate of the carry output transistor is electrically connected to the first node, the first terminal of the carry output transistor is electrically connected to the first voltage terminal, and the second terminal of the carry output transistor is electrically connected to the carry signal output terminal. The gate of the carry reset transistor is electrically connected to the second node, the first terminal of the carry reset transistor is electrically connected to the carry signal output terminal, and the second terminal of the carry reset transistor is electrically connected to the second voltage terminal. The gate of the output transistor is electrically connected to the first node, the first terminal of the output transistor is electrically connected to the fifth voltage terminal, and the second terminal of the output transistor is electrically connected to the drive signal output terminal. The gate of the output reset transistor is electrically connected to the second node, the first terminal of the output reset transistor is electrically connected to the drive signal output terminal, and the second terminal of the output reset transistor is electrically connected to the sixth voltage terminal.

15. A drive module comprising multiple stages of drive circuits as described in any one of claims 1 to 14.

16. The drive module as described in claim 15, wherein, The node control terminal of the a-th stage drive circuit is the first node in the am-th stage drive circuit or the first control node in the am-th stage drive circuit. Both a and m are positive integers.

17. The drive module as described in claim 15 or 16, wherein, The second control node control circuit in the nth stage drive circuit includes the nth stage first control circuit, the nth stage second control circuit, and the nth stage third control circuit; n is a positive integer; The second control node control circuit in the (n+1)th stage drive circuit is electrically connected to the (n+1)th node control terminal, the (n+1)th stage second control node, and the nth stage intermediate node, respectively, and is used to control the (n+1)th stage second control node to connect with the adjacent previous stage intermediate node under the control of the signal provided by the (n+1)th node control terminal. The first control circuit of the nth level is electrically connected to the control terminal of the nth node, the third voltage terminal and the intermediate node of the nth level respectively, and is used to control the connection between the intermediate node of the nth level and the third voltage terminal under the control of the signal provided by the control terminal of the nth node; The nth-level second control circuit is electrically connected to the nth-node control terminal, the nth-level intermediate node, and the nth-level second control node, respectively, and is used to control the connection between the nth-level intermediate node and the nth-level second control node under the control of the signal provided by the nth-node control terminal; The nth-level third control circuit is electrically connected to the nth-level second control node, the nth-level intermediate node, and the fourth voltage terminal, respectively, and is used to control the connection between the nth-level intermediate node and the fourth voltage terminal under the control of the nth-level second control node.

18. A driving method applied to a driving circuit as described in any one of claims 1 to 14, the driving method comprising: The first control node control circuit controls the connection between the first control node and the input terminal under the control of the control clock signal; The first node control circuit controls the connection between the first control node and the first node under the control of the first voltage signal; The second control node control circuit controls the potential of the second control node under the control of the potential of the first node in the adjacent upper m-level drive circuit or the control of the first control node in the adjacent upper m-level drive circuit. m is a positive integer; The second node control circuit, under the control of the second control node, controls the potential of the second node according to the control clock signal.

19. The driving method as described in claim 18, wherein, The steps for the second control node control circuit to control the potential of the second control node under the control of the potential of the first node in the adjacent upper m-stage drive circuit or the control of the first control node in the adjacent upper m-stage drive circuit include: The second control node control circuit controls the connection between the second control node and the second voltage terminal or the adjacent upper-level intermediate node under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit.

20. The driving method as described in claim 18, wherein, The second control node control circuit includes a first control circuit, a second control circuit, and a third control circuit; the second control node control circuit controls the potential of the second control node under the control of the potential of the first node in the adjacent upper m-stage drive circuit or the control of the first control node in the adjacent upper m-stage drive circuit, and the steps include: The first control circuit controls the connection between the intermediate node and the third voltage terminal under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit. The second control circuit controls the connection between the intermediate node and the second control node under the potential of the first node in the adjacent upper m-level drive circuit or under the control of the first control node in the adjacent upper m-level drive circuit. Under the control of the second control node, the third control circuit controls the connection between the intermediate node and the fourth voltage terminal.

21. The driving method according to any one of claims 18 to 20, wherein, The driving circuit further includes an output circuit and an output reset circuit; the driving method further includes: Under the control of the first node, the output circuit controls the connection between the drive signal output terminal and the first voltage terminal; Under the control of the second node, the output reset circuit controls the connection between the drive signal output terminal and the second voltage terminal; The second node control circuit controls the potential of the second node under the control of the first node.

22. A display device comprising the driving module as described in any one of claims 15 to 17.

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