Amplifier circuit

Abstract

In an example, an amplifier circuit comprising a differential amplifier stage (102) and a biasing circuit is provided. The differential amplifier stage (102) comprises a first p-type transistor (202) with a drain connected to a first output node of the amplifier circuit, and a gate of the first p-type transistor (202) is configured to receive a first component of a differential input signal. The differential amplifier stage (102) also comprises a first n-type transistor (210) with a drain connected to the first output node of the amplifier circuit, and a gate of the first n-type transistor (210) is configured to receive the first component of the differential input signal. The differential amplifier stage (102) also comprises a second p-type transistor (214) with a drain connected to a second output node of the amplifier circuit, and a gate of the second p-type transistor (214) is configured to receive a second component of the differential input signal. The differential amplifier stage (102) also comprises a second n-type transistor (220) with a drain connected to the second output node of the amplifier circuit, and a gate of the second n-type transistor (220) is configured to receive the second component of the differential input signal.

Description

[0001] AMPLIFIER CIRCUIT

[0002] Technical Field

[0003] Example embodiments of this disclosure relate to an amplifier circuit, for example including a differential amplifier stage and a biasing circuit.

[0004] Background

[0005] A transmitter or receiver in a wireless communications device includes one or more amplifier. An ideal differential amplifier is linear and has the following relation between the input (comprising the pair of signals Vjnpand Vjnn) and the output (comprising the pair of signals VoutPand Voutn):

[0006] VoutP—Voutn=(VjnP—Vjnn)*G

[0007] G is the constant gain of the ideal amplifier. For an amplifier based on a transistor differential pair and a current source, the effective gain G is not constant independent of the input amplitude Vjnp- jnn. The higher the input amplitude is, the lower becomes the effective gain G. This reduction in effective gain at a higher input amplitude causes nonlinearity or distortion in the output signal VoutP-outn. This non-linearity causes unwanted spurs and other emissions in the output signal spectrum.

[0008] One way to make a differential amplifier based on a transistor differential pair and a current source more linear (i.e. linearization of the amplifier) is to increase the bias current of transistors in the differential pair. However, this results in increased power consumption. A variant is to sense the input signal envelope and increase the bias current from the current source when the envelope amplitude increases.

[0009] Both of these methods increase power consumption and can cause electromigration. Electromigration is the transport of material in a conductor under the influence of an applied electric field. Electromigration is a more severe problem with finer transistor geometries.

[0010] A third variant to achieve linearization is disclosed in WO 2020 / 143934 A1. This discloses a bias circuit for a power amplifier (PA), which tracks the envelope of the input signal to the PA. Summary

[0011] In embodiments of this disclosure, an input signal is fed forward by a biasing circuit to provide more bias current in a differential amplifier stage, for example to improve the linearity of the circuit and / or to overcome compression or distortion in the output signal.

[0012] In the proposed linearizer solution, a source signal is feed forward (a source follower signal). Example embodiments have a DC current consumption that is independent of temperature and process.

[0013] One aspect of the present disclosure provides an amplifier circuit comprising a differential amplifier stage. The differential amplifier stage comprises a first p-type transistor with a source connected to a first node, wherein a drain of the first p-type transistor is connected to a first output node of the amplifier circuit, and a gate of the first p-type transistor is configured to receive a first component of a differential input signal. The differential amplifier stage also comprises a first n-type transistor with a source connected to a second node, wherein a drain of the first n-type transistor is connected to the first output node of the amplifier circuit, and a gate of the first n-type transistor is configured to receive the first component of the differential input signal. The differential amplifier stage also comprises a second p-type transistor with a source connected to the first node, wherein a drain of the second p-type transistor is connected to a second output node of the amplifier circuit, and a gate of the second p-type transistor is configured to receive a second component of the differential input signal. The differential amplifier stage also comprises a second n-type transistor with a source connected to the second node, wherein a drain of the second n-type transistor is connected to the second output node of the amplifier circuit, and a gate of the second n-type transistor is configured to receive the second component of the differential input signal. The amplifier circuit further comprises a biasing circuit. The biasing circuit comprises a third p-type transistor with a source connected to a third node, wherein a gate of the third p-type transistor is configured to receive the first component of the differential input signal. The biasing circuit also comprises a third n-type transistor with a source connected to a fourth node, wherein a drain of the third n-type transistor is connected to a drain of the third p-type transistor, and wherein a gate of the third n-type transistor is configured to receive the first component of the differential input signal. The biasing circuit also comprises a fourth p-type transistor with a source connected to the third node, wherein a gate of the fourth p-type transistor is configured to receive the second component of the differential input signal. The biasing circuit also comprises a fourth n-type transistor with a source connected to the fourth node, wherein a drain of the fourth n-type transistor is connected to a drain of the fourth p-type transistor, and wherein a gate of the fourth n-type transistor is configured to receive the second component of the differential input signal. The biasing circuit also comprises a fifth p-type transistor with a gate connected to the third node, a source connected to a first supply voltage and a drain connected to the first node. The biasing circuit also comprises a fifth n-type transistor with a gate connected to the fourth node, a source connected to a second supply voltage and a drain connected to the second node.

[0014] Another aspect of the present disclosure provides an integrated circuit comprising the amplifier circuit of the above aspect.

[0015] A further aspect of the present disclosure provides an electronic apparatus comprising the amplifier circuit of the above aspect.

[0016] Brief Description of the Drawings

[0017] For a better understanding of examples of the present disclosure, and to show more clearly how the examples may be carried into effect, reference will now be made, by way of example only, to the following drawings in which:

[0018] Figure 1 illustrates an example of an amplifier circuit;

[0019] Figure 2 is a circuit diagram of an example of a differential amplifier stage of the amplifier circuit of Figure 1 ;

[0020] Figure 3 is a circuit diagram of an example of a biasing circuit of the amplifier circuit of Figure 1 ;

[0021] Figure 4 is a circuit diagram of a bias voltage generating circuit;

[0022] Figure 5 illustrates an example of an integrated circuit comprising an amplifier circuit according to examples of this disclosure; and

[0023] Figure 6 illustrates an example of an electronic apparatus comprising an amplifier circuit according to examples of this disclosure.

[0024] Detailed Description

[0025] The following sets forth specific details, such as particular embodiments or examples for purposes of explanation and not limitation. It will be appreciated by one skilled in the art that other examples may be employed apart from these specific details. Examples of this disclosure provide an amplifier circuit comprising a differential amplifier stage and a biasing circuit. Such amplifier circuits may be suitable for use for example in transmitter or receiver in a wireless communications device, or in other types of electronic device that use an amplifier circuit.

[0026] Figure 1 is a circuit diagram of an example of an amplifier circuit 100 according to examples of this disclosure. The amplifier circuit 100 comprises a differential amplifier stage 102 and a biasing circuit 104 that provides biasing to the differential amplifier stage 102.

[0027] Figure 2 is a circuit diagram of an example of a differential amplifier stage 102 of the amplifier circuit 100. The differential amplifier stage 102 comprises a first p-type transistor 202 with a source connected to a first node 204. A drain of the first p-type transistor 202 is connected to a first output node 206 (RFoutn) of the amplifier circuit, and a gate of the first p- type transistor 202 is configured to receive a first component (RFjnp) of a differential input signal at node 208.

[0028] The differential amplifier stage 102 also comprises a first n-type transistor 210 with a source connected to a second node 212. A drain of the first n-type transistor 210 is connected to the first output node 206 (RFoutn) of the amplifier circuit, and a gate of the first n-type transistor 210 is configured to receive the first component (RFjnp) of the differential input signal at node 208.

[0029] The differential amplifier stage 102 also comprises a second p-type transistor 214 with a source connected to the first node 204. A drain of the second p-type transistor 214 is connected to a second output node 216 (RFoutP) of the amplifier circuit, and a gate of the second p-type transistor 214 is configured to receive a second component (RFjnn) of the differential input signal at node 218. In some examples, a first component (RFoutn) and a second component (RFoutP) of a differential output signal from the differential amplifier stage 102 (and hence from the amplifier circuit 100) are provided by the first output node 206 and the second output node 216 respectively.

[0030] The differential amplifier stage 102 also comprises a second n-type transistor 220 with a source connected to the second node 212. A drain of the second n-type transistor 220 is connected to the second output node 216 (RFoutP) of the amplifier circuit, and a gate of the second n-type transistor is configured to receive the second component (RFjnn) of the differential input signal at node 218. In some examples, such as that shown in Figure 2, the differential amplifier stage 102 comprises a first capacitor 222 connected between the first output node 206 (RFoutn) and a fifth node 224 (vcm), and a second capacitor 226 connected between the second output node 216 (RFoutP) and the fifth node (vcm). Additionally or alternatively, in some examples, such as that shown in Figure 2, the differential amplifier stage 102 comprises a first resistor 228 connected between the first output node 206 (RFoutn) and the fifth node 224 (vcm), and a second resistor 230 connected between the second output node 216 (RFoutP) and the fifth node 224 (vcm).

[0031] In some examples, the differential amplifier stage 102 also comprises a common mode differential amplifier 232 (vcm amp) configured to receive a voltage at the fifth node (vcm) at one of its inputs 234, and a voltage between a first supply voltage (e.g. Vdd) and a second supply voltage (e.g. OV or Gnd) at another one of its inputs 236. An output of the common mode differential amplifier is connected to the second node 212, as shown in Figure 2, or may alternatively in other examples be connected to a different node such as the first node 204. In some examples, the voltage between the first supply voltage and the second supply voltage may be half way between the two supply voltages. Therefore, for example, the voltage between the first supply voltage and the second supply voltage may be Vdd / 2 or substantially Vdd / 2 where the first supply voltage is Vdd and the second supply voltage is 0V or Gnd.

[0032] Figure 3 is a circuit diagram of an example of a biasing circuit 104. The biasing circuit 104 comprises a third p-type transistor 302 with a source connected to a third node 304. A gate of the third p-type transistor 302 is configured to receive the first component (RFjnp) of the differential input signal. The gate of the third p-type transistor 302 is configured to configured to be biased by a first bias voltage (VcaSp). In the example shown in Figure 3, this is achieved by connecting a resistor 306 between the first bias voltage and the gate of the third p-type transistor 302, and a capacitor 308 between the gate of the third p-type transistor 302 and the first component (RFjnp) of the differential input signal.

[0033] The biasing circuit 104 also comprises a third n-type transistor 310 with a source connected to a fourth node 312. A drain of the third n-type transistor 310 is connected to a drain of the third p-type transistor 302. A gate of the third n-type transistor 310 is configured to receive the first component (RFjnp) of the differential input signal. The gate of the third n-type transistor 310 is configured to be biased by a second bias voltage (VcaSn). In the example shown in Figure 3, this is achieved by connecting a resistor 314 between the second bias voltage and the gate of the third n-type transistor 310, and a capacitor 316 between the gate of the third n-type transistor 310 and the first component (RFjnp) of the differential input signal.

[0034] The biasing circuit 104 also comprises a fourth p-type transistor 318 with a source connected to the third node 304. A gate of the fourth p-type transistor 318 is configured to receive the second component (RFjnn) of the differential input signal. The gate of the fourth p-type transistor 318 is configured to be biased by the first bias voltage (VCaSp). In the example shown in Figure 3, this is achieved by connecting a resistor 320 between the first bias voltage and the gate of the fourth p-type transistor 318, and a capacitor 322 between the gate of the fourth p-type transistor 318 and the second component (RFjnn) of the differential input signal.

[0035] The biasing circuit 104 also comprises a fourth n-type transistor 324 with a source connected to the fourth node 312. A drain of the fourth n-type transistor 324 is connected to a drain of the fourth p-type transistor 318. A gate of the fourth n-type transistor 324 is configured to receive the second component (RFjnn) of the differential input signal. The gate of the fourth n-type transistor 324 is configured to be biased by the second bias voltage (Vcasn). In the example shown in Figure 3, this is achieved by connecting a resistor 326 between the first bias voltage and the gate of the fourth n-type transistor 324, and a capacitor 328 between the gate of the fourth n-type transistor 324 and the second component (RFjnn) of the differential input signal.

[0036] The biasing circuit 104 also comprises a fifth p-type transistor 330 with a gate connected to the third node 304, a source connected to a first supply voltage (e.g. Vdd) and a drain connected to the first node 204 shown in Figure 2. Thus, a bias current ( ) may be provided to the first node 204 by the fifth p-type transistor 330. The biasing circuit 104 also comprises a fifth n-type transistor 332 with a gate connected to the fourth node 312, a source connected to a second supply voltage (e.g. 0V or Gnd) and a drain connected to the second node 212 shown in Figure 2. Thus, a bias current (I2) may be drawn from the second node 212 by the fifth n-type transistor 332.

[0037] In some examples, such as the example shown in Figure 3, the biasing circuit 104 may also comprise a sixth p-type transistor 334 with a source connected to the first supply voltage (e.g. Vdd), a drain connected to the third node 304, and a gate configured to be biased by a third bias voltage (Vbiasp). In some examples, such as the example shown in Figure 3, the biasing circuit 104 may also comprise a sixth n-type transistor 336 with a source connected to the second supply voltage (e.g. 0V or Gnd), a drain connected to the fourth node 312, and a gate configured to be biased by a fourth bias voltage (Vbiasn). Thus, in some examples, the transistors 334 and / or 336 may provide bias current to the transistors 302, 310, 318 and 324.

[0038] In some examples, such as the example shown in Figure 3, the biasing circuit 104 may also comprise a seventh p-type transistor 338 with a source connected to the first supply voltage (e.g. Vdd) and a gate connected to the third node 304. A seventh n-type transistor 340 has a source connected to the second supply voltage (e.g. 0V or Gnd). A drain of the seventh n- type transistor 340 is connected to a gate of the seventh n-type transistor 340 and a drain of the seventh p-type transistor 338. An eighth n-type transistor 342 has a source connected to the second supply voltage (e.g. 0V or Gnd), a drain connected to the second node 212 shown in Figure 2, and a gate connected to the gate of the seventh n-type transistor 340. Thus, a bias current (h) may be drawn from the second node 212 by the eighth n-type transistor 342.

[0039] In some examples, such as the example shown in Figure 3, the biasing circuit 104 may also comprise a ninth n-type transistor 344 with a source connected to the second supply voltage (e.g. 0V or Gnd) and a gate connected to the fourth node 312. An eighth p-type transistor 346 has a source connected to the first supply voltage (e.g. Vdd). A drain of the eighth p- type transistor 346 is connected to a gate of the eighth p-type transistor 346 and a drain of the ninth n-type transistor 344. A ninth p-type transistor 348 has a source connected to the first supply voltage (e.g. Vdd), a drain connected to the first node 204 shown in Figure 2, and a gate connected to the gate of the eighth p-type transistor 346. Thus, a bias current (I4) may be provided to the first node 204 by the ninth p-type transistor 348. In some examples, the bias currents , I2, I3 and I4 are identical or substantially identical. Thus, in some examples, the total bias current provided to the first node 204 of the differential amplifier stage by the transistors 330 and 348 of the biasing circuit 104 is 2*h. Also, when the bias currents , I2, I3 and I4 are identical or substantially identical, the biasing circuit 104 may be insensitive to common mode signals.

[0040] In some examples, the drain of the third p-type transistor 302, the drain of the third n-type transistor 310, the drain of the fourth p-type transistor 318 and the drain of the fourth n-type transistor 324 are connected to a voltage between the first supply voltage (e.g. Vdd) and the second supply voltage (e.g. Gnd). In some examples, the voltage between the first supply voltage and the second supply voltage may be half way between the two supply voltages. Therefore, for example, the voltage between the first supply voltage and the second supply voltage may be Vdd / 2 or substantially Vdd / 2 where the first supply voltage is Vdd and the second supply voltage is OV or Gnd. As a result, in some examples, differential pairs of the biasing circuit 104 that comprise the transistors 302, 310, 318 and 324 may be forced to a common mode voltage such as Vdd / 2.

[0041] In operation, when the differential input signal magnitude (e.g. RFinp - RFinn) increases, the bias current from the biasing circuit 104 will increase momentarily. The momentarily increased bias current ensures that the transistors 202, 210, 214 and 220in the differential amplifier stage 102 provide a linear differential output signal (e.g. RFoutp - RFoutn) that is not compressed or distorted, even with the increased differential input signal magnitude, and thus linearizes the differential amplifier stage 102. However, when the differential input signal magnitude decreases, the bias current also decreases. Thus for example the bias current for the differential amplifier stage 102 responds to the instantaneous magnitude of the input signal and not the envelope of the input signal. As a result, the differential amplifier uses less power than a solution that may use the input signal envelope to adjust bias current for the differential amplifier stage. In addition, as the biasing circuit 104 responds as soon as a signal is applied at the input of the amplifier circuit, the biasing circuit also linearizes small input signal levels.

[0042] Figure 4 is a circuit diagram of a bias voltage generating circuit 400 that may in some examples be used in the amplifier circuit 100 to generate the first, second, third and fourth bias voltages referred to above. The bias voltage generating circuit 400 comprises a tenth p-type transistor 402 with a source connected to the first supply voltage (e.g. Vdd). The drain and gate of the tenth p-type transistor 402 are connected together. An eleventh p-type transistor 404 has a source connected to the drain of the tenth p-type transistor 402 and a gate and drain connected together. A bias current (bias) is drawn from the drain of the eleventh p-type transistor 404. The first bias voltage (VCaSp) is generated at the gate of the eleventh p-type transistor 404, and the third bias voltage (Vbiasp) is generated at the gate of the tenth p-type transistor 402.

[0043] The bias voltage generating circuit 400 also comprises a tenth n-type transistor 406. The drain and gate of the tenth p-type transistor 402 are connected together. An eleventh n-type transistor 408 has a drain connected to the gate of the eleventh n-type transistor 408 and also to the source of the tenth n-type transistor 406. The eleventh n-type transistor 408 has a source connected to the second supply voltage (e.g. 0V or Gnd). A bias current (bias) is provided to the drain of the tenth n-type transistor 406. The second bias voltage ( casn) is provided by the gate of the tenth n-type transistor 406, and the fourth bias voltage ( biasn) is provided by the gate of the eleventh n-type transistor 408. In some examples, for example where the bias currents h, I2, I3 and I4 are identical or substantially identical, the bias current may be c*lbias, where c is a constant factor.

[0044] In some examples, the transistors may be sized as follows. Transistor 336 may be 2k times the size of transistor 408, transistors 310 and 324 may each be k times the size of transistor 406, transistors 302 and 318 may each be k times the size of transistor 404, and transistor 334 may be 2k times the size of transistor 402, where k is a constant factor. Therefore, examples of this disclosure may have a DC current consumption that is independent of temperature and process. In general, the sizes of any of the transistors or other components may be chosen by the skilled person to achieve the required level of performance.

[0045] In the examples described herein, “connected to” may mean connected directly, with no additional components in between, or alternatively may mean connected via one or more additional components not shown in Figures 1-4, such as for example cascode transistors, other transistors, resistors, capacitors, inductors and / or other electronic components.

[0046] Figure 5 illustrates an example of an integrated circuit 500 comprising an amplifier circuit 502 according to examples of this disclosure, such as for example the amplifier circuit 100 shown in Figure 1 . Figure 6 illustrates an example of an electronic apparatus 600 comprising an amplifier circuit 602 according to examples of this disclosure, such as for example the amplifier circuit 100 shown in Figure 1 . The electronic apparatus may in some examples be a communication apparatus. For example, the communication apparatus may be a wireless communication device for a cellular communications system. Alternatively, for example, the communication apparatus may be a base station for a cellular communications system.

[0047] An amplifier circuit according to examples of this disclosure may be used for example in a circuit where there is a need for a differential stage amplifier with improved linearity and low extra power consumption due to the linearization. As an example, an ampolifier circuit according to examples of this disclosure can be used in a wideband communication transceiver. In the receiver, for example, the amplifier circuit can be used in the receiver front end analog to digital converter (FE ADC) driver. The ADC driver has a relatively high input signal level and therefore needs a relatively high linearity not to distort the received radio signal. In the transmitter, for example, the digital to analog converter (DAC) can be a resistive DAC (RDAC), and after the RDAC comes a power amplifier (PA) pre driver, in the transmitter front end, that may include the amplifier circuit according to examples of this disclosure.

[0048] Simulations of an amplifier circuit according to examples of this disclosure in a 7nm Fin FET process show that a receiver ADC driver achieves 7dB extra Input related IP3, 11 P3, at 6 GHz frequency when a biasing circuit according to examples of this disclosure is used, for example as compared to constant biasing.

[0049] It should be noted that the above-mentioned examples illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative examples without departing from the scope of the appended statements. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the statements below. Where the terms, “first”, “second” etc. are used they are to be understood merely as labels for the convenient identification of a particular feature. In particular, they are not to be interpreted as describing the first or the second feature of a plurality of such features (i.e. , the first or second of such features to occur in time or space) unless explicitly stated otherwise. Steps in the methods disclosed herein may be carried out in any order unless expressly otherwise stated. Any reference signs in the statements shall not be construed so as to limit their scope.

Claims

Claims1 . An amplifier circuit (100) comprising: a differential amplifier stage (102) comprising: a first p-type transistor (202) with a source connected to a first node (204), wherein a drain of the first p-type transistor is connected to a first output node (2oe) of the amplifier circuit, and a gate of the first p-type transistor is configured to receive a first component (RFjnp) of a differential input signal; a first n-type transistor (210) with a source connected to a second node (212), wherein a drain of the first n-type transistor is connected to the first output node of the amplifier circuit, and a gate of the first n-type transistor is configured to receive the first component of the differential input signal; a second p-type transistor (214) with a source connected to the first node (204), wherein a drain of the second p-type transistor is connected to a second output node (2ie) of the amplifier circuit, and a gate of the second p-type transistor is configured to receive a second component (RFjnn) of the differential input signal; and a second n-type transistor (220) with a source connected to the second node (212), wherein a drain of the second n-type transistor is connected to the second output node of the amplifier circuit, and a gate of the second n-type transistor is configured to receive the second component of the differential input signal; wherein the amplifier circuit further comprises a biasing circuit (104) comprising: a third p-type transistor (302) with a source connected to a third node (304), wherein a gate of the third p-type transistor is configured to receive the first component of the differential input signal; a third n-type transistor (310) with a source connected to a fourth node (312), wherein a drain of the third n-type transistor is connected to a drain of the third p-type transistor, and wherein a gate of the third n-type transistor is configured to receive the first component of the differential input signal; a fourth p-type transistor (318) with a source connected to the third node (304), wherein a gate of the fourth p-type transistor is configured to receive the second component of the differential input signal; a fourth n-type transistor (324) with a source connected to the fourth node (312), wherein a drain of the fourth n-type transistor is connected to a drain of the fourth p- type transistor, and wherein a gate of the fourth n-type transistor is configured to receive the second component of the differential input signal; a fifth p-type transistor (330) with a gate connected to the third node (304), a source connected to a first supply voltage and a drain connected to the first node (204); anda fifth n-type transistor (332) with a gate connected to the fourth node (312), a source connected to a second supply voltage and a drain connected to the second node (212).

2. The amplifier circuit of claim 1 , wherein: the gate of the third p-type transistor (302) is configured to be biased by a first bias voltage (VCasP); the gate of the third n-type transistor (310) is configured to be biased by a second bias voltage (V casn), the gate of the fourth p-type transistor (318) is configured to be biased by the first bias voltage (VCaSp); and / or the gate of the fourth n-type transistor (324) is configured to be biased by the second bias voltage (V casn)-3. The amplifier circuit of claim 1 or 2, wherein the biasing circuit comprises: a sixth p-type transistor (334) with a source connected to the first supply voltage, a drain connected to the third node (304), and a gate configured to be biased by a third bias voltage (Vbiasp); and / or a sixth n-type transistor (336) with a source connected to the second supply voltage, a drain connected to the fourth node (312), and a gate configured to be biased by a fourth bias voltage (Vbiasn).

4. The amplifier of any of claims 1 to 3, wherein the biasing circuit comprises: a seventh p-type transistor (338) with a source connected to the first supply voltage and a gate connected to the third node (304); a seventh n-type transistor (340) with a source connected to the second supply voltage, wherein a drain of the seventh n-type transistor is connected to a gate of the seventh n-type transistor and a drain of the seventh p-type transistor; and an eighth n-type transistor (342) with a source connected to the second supply voltage, a drain connected to the second node (212), and a gate connected to the gate of the seventh n-type transistor.

5. The amplifier of any of claims 1 to 4, wherein the biasing circuit comprises: a ninth n-type transistor (344) with a source connected to the second supply voltage and a gate connected to the fourth node (312);a eighth p-type transistor (346) with a source connected to the first supply voltage, wherein a drain of the eighth p-type transistor is connected to a gate of the eighth p-type transistor and a drain of the ninth n-type transistor; and a ninth p-type transistor (348) with a source connected to the first supply voltage, a drain connected to the first node (204), and a gate connected to the gate of the eighth p-type transistor.

6. The amplifier circuit of any of claims 1 to 5, wherein the drain of the third p-type transistor (302), the drain of the third n-type transistor (310), the drain of the fourth p-type transistor (318) and the drain of the fourth n-type transistor (324) are connected to a voltage between the first supply voltage and the second supply voltage.

7. The amplifier circuit of any of claims 1 to 6, wherein the differential amplifier stage comprises: a first capacitor (222) connected between the first output node (206) and a fifth node (224), and a second capacitor (226) connected between the second output node (216) and the fifth node (224); and / or a first resistor (228) connected between the first output node (206) and the fifth node (224), and a second resistor (230) connected between the second output node (216) and the fifth node (224).

8. The amplifier circuit of claim 7, wherein the differential amplifier stage comprises a common mode differential amplifier (232) configured to receive a voltage at the fifth node (224) and a voltage between the first supply voltage and the second supply voltage, wherein an output of the common mode differential amplifier is connected to the first node (204) or the second node (212).

9. An integrated circuit (500) comprising the amplifier circuit (100, 502) of any one of claims 1 to 8.

10. An electronic apparatus (600) comprising the amplifier circuit (100, 602) of any one of claims 1 to 8.

11. The electronic apparatus of claim 10, wherein the electronic apparatus is a communication apparatus.

12. The electronic apparatus of claim 11 , wherein the communication apparatus is a wireless communication device for a cellular communications system.

13. The electronic apparatus of claim 11, wherein the communication apparatus is a base station for a cellular communications system.

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