Hermetically sealed cover for an electronic device

Abstract

A hermetically sealed cover for one or more electronic devices is disclosed. The hermetically sealed cover includes at least two or more encapsulating components made of diamond. Each encapsulating component includes a first surface, a second surface, and at least one mating surface. The first surface is configured to face towards the one or more electronic devices. The second surface is configured to face away from the one or more electronic devices. The at least one mating surface extends between the first surface and the second surface. The at least one mating surface of each encapsulating component is configured to be joined with at least one mating surface of the other encapsulating component via welding to hermetically enclose the one or more electronic devices between the at least two encapsulating components.

Description

HERMETICALLY SEALED COVER FOR AN ELECTRONIC DEVICE Technical field

[0001] The present disclosure relates to a hermetically sealed cover for an electronic device and a method for making a hermetically sealed cover for an electronic device. More specifically, the present disclosure relates to a hermetically sealed cover made from engineered diamond for electronic devices and a method for creating said hermetically sealed cover. Background

[0002] Diamonds offer superior properties, such as high thermal conductivity, mechanical strength, and chemical stability, required in electronic applications, for example, for encapsulating delicate electronic components. However, encapsulating electronic components within a diamond presents significant challenges, such as thermal management during high-temperature growth, stress mitigation, protection of sensitive electronics in reactive environments, and achieving uniform, high- quality diamond growth around integrated components. Existing methods inadequately address these issues, particularly for sensitive electronic components like Complementary Metal Oxide Semiconductor (CMOS) chips, power devices, and Micro Electromechanical System (MEMS) components. Additionally, the size of artificially engineered diamonds is restricted, which in turn limits their use for packaging larger electronic devices.

[0003] In addition, certain applications require secure feedthroughs or interfaces between internal electronic components and external systems. Existing methods such as metallization of diamond surfaces or doping-based conduction paths can be prone to delamination, stress fractures, or inadequate vacuum sealing. Furthermore, many industries including biomedical, quantum computing, aerospace, fusion energy, and high-power electronics, demand endurance at extreme temperatures, vibrations, and radiation.Summary

[0004] In an aspect, the present disclosure relates to a hermetically sealed cover for one or more electronic devices. The hermetically sealed cover includes at least two or more encapsulating components made of diamond. Each encapsulating component includes a first surface, a second surface, and at least one mating surface. The first surface is configured to face towards the one or more electronic devices. The second surface is configured to face away from the one or more electronic devices. The at least one mating surface extends between the first surface and the second surface. The at least one mating surface of each encapsulating component is configured to be joined with at least one mating surface of the other encapsulating component via welding to hermetically enclose the one or more electronic devices between the at least two encapsulating components.

[0005] In another aspect, the present disclosure relates to a method for creating a hermetically sealed cover for one or more electronic devices. The method comprises obtaining at least two encapsulating components fabricated using a diamond deposition technique. Each encapsulating component includes a first surface, a second surface and at least one mating surface. The first surface is configured to face towards the one or more electronic devices. The second surface is configured to face away from the one or more electronic devices. The at least one mating surface extends between the first surface and the second surface. The method further includes assembling the one or more electronic devices between the at least two encapsulating components. Furthermore, the method includes hermetically sealing the one or more electronic devices within the encapsulating components by sealably joining together the mating surfaces of the two or more encapsulating components via welding. The welding is done by a laser source selected from a group consisting of a femtosecond laser, a picosecond laser, or a combination thereof. Brief Description of the Drawings

[0006] FIG.1 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with an embodiment of the present disclosure;

[0007] FIG.2 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with another embodiment of the present disclosure;

[0008] FIG.3 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with yet another embodiment of the present disclosure;

[0009] FIG.4 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with yet another embodiment of the present disclosure;

[0010] FIG.5 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with yet another embodiment of the present disclosure;

[0011] FIG.6A-6G are exemplary illustrations of an encapsulating component of the hermetically sealed cover, in accordance with various embodiments of the present disclosure;

[0012] FIG.7A is an expanded view of a portion of the hermetically sealed cover for an electronic device illustrated in FIG 1;

[0013] FIG.7B and 7C are expanded views of a portion of the hermetically sealed cover for an electronic device, in accordance with an embodiment of the present disclosure;

[0014] FIG.7D and 7E are expanded views of a portion of the hermetically sealed cover for an electronic device, in accordance with an embodiment of the present disclosure;

[0015] FIG.8 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with an embodiment of the present disclosure; and

[0016] FIG.9 is an exemplary illustration of the sectional view of a hermetically sealed cover for an electronic device, in accordance with an embodiment of the present disclosure.Detailed Description

[0017] Reference will now be made in detail to specific embodiments or features, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or the like parts.

[0018] Referring to FIG.1 through 5, an exemplary hermetically sealed cover 100 for an electronic device 114 is disclosed. The hermetically sealed cover 100 is configured to enclose electronic devices that require protection from mechanical shocks, thermal shocks, thermal fluctuations and other harsh operating conduction. Such electronic devices include, but are not limited to, integrated circuits (ICs) such as CMOS chips, high-power semiconductor devices (e.g., GaN or SiC power modules), drug delivery micro-implants, micro-electromechanical systems (MEMS), optoelectronic sensors (e.g., photodiodes, LED arrays), quantum computing elements (e.g., superconducting qubits or nitrogen-vacancy (NV) centers in diamond), and microfluidic devices requiring an inert environment.

[0019] The hermetically sealed cover 100 may have any suitable shape and size, and can be configured to enclose electronic devices of different sizes and shapes. Non limiting examples of the shape of the hermetically sealed cover 100 includes spherical, hemispherical, ellipsoidal, cubical, cuboidal, prism-shaped, and tubelike.

[0020] Referring again to FIG. 1 through 5, the hermetically sealed cover 100 comprises two or more encapsulating components 102a, 102b, 102c, 102d, each made of diamond. Each encapsulating component includes a mating surface integrally formed thereon and is weldable to at least one other encapsulating component. The hermetically sealed cover 100 may include two encapsulating components 102a, 102b as exemplified in FIG.1, or three encapsulating components 102a 102b, 102c as exemplified in FIG. 2 and FIG. 3, or four encapsulating components 102a, 102b, 102c, 102d as exemplified in FIG.4 and FIG.5. However, the hermetically sealed cover 100 may be formed of any number of encapsulating components as required for encapsulating the electronic device 114.

[0021] The encapsulating components 102a, 102b, 102c, 102d may be suitably sized and shaped so that when they are welded with each other via their matingsurfaces 108a, 108b, 108c, 108d, the entire electronic device 114 is encapsulated. The encapsulating components 102a, 102b, 102c, 102d may be made in a series of standard sizes and shapes such that two or more such encapsulating components 102a, 102b, 102c, 102d may be selected to form the hermetically sealed cover 100 of different sizes and shapes. Referring to FIGS.6E to 6G, depending on the size of the hermetically sealed cover 100 required, an encapsulating component (out of encapsulating components 102a, 102b, 102c, 102d) having different radius of curvature may be selected to form the hermetically sealed cover 100. Similarly, referring to FIGS. 6A to 6D, multiple encapsulating components, such as those shown in FIG 6A and 6B, could be joined to form different sizes and shapes of the hermetically sealed cover 100. The encapsulating components can be used as modular building blocks to form size and shapes of covers as desired.

[0022] The encapsulating component, may be shaped as a box, semi-spherical, curved, cuboidal, planar or any other shape that is capable of welding with at least one other encapsulating component to form the hermetically sealed cover. For example, two box shaped encapsulating components can be joined to form a cuboidal hermetically sealed cover. Similarly, two or more hemispherical or curved shaped encapsulating components may form a spherical hermetically sealed cover. Alternatively, a plane encapsulating component and a curved encapsulating component may form a hemispherical cover, such as the hermetically sealed cover 100, as shown in FIG. 1. In some embodiments, each of the two or more encapsulating component 102a, 102b has a different shape as illustrated in FIGS.1, 2 and 3. In alternate embodiments, each of the one and more encapsulating components has the same shape and size i.e., all the encapsulating components are identical as illustrated in FIG.4..

[0023] In an aspect, at least one encapsulating components, for example, the encapsulating components 102a, 102b are adapted to house the electronic device 114, as shown in FIG. 1. In another aspect, more than two encapsulating components, such as the encapsulating components 102a, 102b, 102c may be joined together to house the electronic device 114, as shown in FIGS.2 and 3.

[0024] Each of the two or more encapsulating components 102a, 102b, 102c, 102d are made of engineered diamond selected from a group consisting of a monolithic diamond, a polycrystalline diamond, a doped monolithic diamond, a doped polycrystalline diamond and a combination thereof. In some embodiments, encapsulating components 102a, 102b, 102c, 102d are made of the doped monolithic diamond or doped polycrystalline diamond, wherein the doping agents includes, but may not be limited to, boron, nitrogen, phosphorus, or a combination thereof. The encapsulating components 102a, 102b, 102c, 102d are doped to tailor electrical, optical, or thermal properties, for example, boron doping imparts p-type conductivity for enhancing thermal conductivity or enabling electrochemical sensing features, nitrogen doping introduces specific optical centers (e.g., nitrogen-vacancy (NV) centers) and modulates thermal properties, and phosphorus doping enables n-type conductivity, potentially enhancing integration with semiconductor devices.

[0025] In some embodiments, the dopant concentration ranges from about 1015atoms / cm³ to about 1021atoms / cm³, which balances the desired electrical or optical properties with mechanical and thermal stability. However, other dopant concentrations may also be used and will depending on the desired electrical conductivity or other performance parameters.

[0026] In some embodiments, the encapsulating component 102a 102b, 102c, 102d is a single-layer diamond structure that is uniformly doped. In other embodiments, the encapsulating component 102a 102b, 102c, 102d is made of multiple layers of diamond, wherein each layer has a different dopant concentration or a different type of dopant to achieve gradient properties. In some embodiments, doping concentrations or crystal morphologies vary from the outermost layer (i.e., the layer that faces away from the electronic device) to the innermost layer (i.e., the layer that faces the electronic device). Such variations are done to optimize properties like mechanical strength near the interface with the electronic device 114 and improved durability or chemical inertness away from the electronic device 114 interface. By way of an example, the encapsulating component 102a, 102b, 102c, 102d is doped such that it has more conductive inner layer (i.e., the layer that faces the electronic device) and a mechanically stronger higher-purity outer layer (i.e., thelayer that faces away from the electronic device). Other permutations and combinations, depending on the requirement may be made. In embodiments where the encapsulating component 102a, 102b, 102c, 102d is made of multiple layers of diamond, the thickness of each layer may vary from sub-micrometer for fine-tuning surface conductivity or optical features to several millimeters (for robust mechanical protection).

[0027] In some embodiments, each of the two or more encapsulating components 102a 102b, 102c, 102d has an identical composition. In other embodiments, the encapsulating components 102a 102b, 102c, 102d may be different with respect to the doping type and doping level. Various doping strategies and layer configurations provide significant flexibility in designing hermetically sealed covers that optimize mechanical strength, thermal conductivity, chemical inertness, and / or electrical functionality, while reliably protecting the enclosed electronic device from harsh environmental conditions.

[0028] The dimensions of the encapsulating components 102a 102b, 102c, 102d may vary and will depend on the dimensions and requirements of the electronic device 114 to be encapsulated. For example, in some embodiments, the encapsulating components 102a 102b, 102c, 102d may have a minimal thickness or characteristic dimension such that the electronic device 114 of 50 micrometers thickness is to be encapsulated. Examples of such electronic device 114 may include, but not limited to, small-scale microelectronic or MEMS devices, biosensors, and the like. In other embodiments, the size (e.g., length, breadth, height, etc.,) of the encapsulating components 102a 102b, 102c, 102d may extend up to about 100 millimeters (mm) or more when used for encapsulating larger power electronics or multi-chip modules. This range accommodates various applications, ranging from precision micro-scale packaging to robust macro-scale enclosures, without compromising the hermetic integrity and protective advantages afforded by engineered diamond encapsulation.

[0029] Each of the two or more encapsulating components 102a 102b, 102c, 102d includes a first surface, a second surface and at least one mating surface extending between the first surface and the second surface. As exemplified in FIG. 1, theencapsulating components 102a, 102b include first surfaces 104a, 104b and second surfaces 106a, 106b. Further, the encapsulating component 102a includes mating surfaces 108a extending between the first surface 104a and the second surface 106a, whereas the encapsulating component 102b includes mating surfaces 108b extending between the first surface 104b and the second surface 106b.

[0030] The first surfaces 104a, 104b of the encapsulating components 102a, 102b are configured to face towards the electronic device 114 and form an inner surface of the hermetically sealed cover 100. In various embodiments, the first surfaces 104a, 104b may exhibit specific crystallographic orientation. For example, the first surfaces 104a, 104b, 104c, 104d (of the encapsulating components 102a, 102b, 102c, 102d) may have a 100 or 111 orientation of diamond grains. Such orientations are chosen to enhance certain properties such as wear resistance, thermal conductivity, or optical clarity. In some embodiments, the first surfaces 104a, 104b of the hermetically sealed cover 100, shown in FIG. 1, may be doped. In some embodiments, the first surfaces 104a, 104b of the hermetically sealed cover 100 may be doped with one or more material, for example, boron to improve thermal conductivity thereof; or nitrogen to create optically active centres; or phosphorus to enable localized electrical conductivity for sensor integration or electrostatic discharge (ESD) protection; or combinations thereof. In some embodiments, the first surfaces 104a, 104b may be shaped as per the specific topography of the electronic device 114, for example, to reduce stress concentrations, improve thermal contact, or ensure accurate alignment with any bonding pads or electrical interconnections. In other embodiments, the first surfaces 104a, 104b may be polished or textured. In some embodiments, the first surfaces 104a, 104b of the hermetically sealed cover 100 may further include microchannels or microcavities. Such microchannels may enhance cooling (by circulating a fluid or gas), facilitate vacuum pulls during electronic device 114 assembly, or allow housing of additional sensors or circuit elements. It may be contemplated that one or more characteristics of the first surfaces 104a, 104b, as discussed above and in following paragraphs, may be applicable to the first surfaces 104c and 104d of the encapsulating components 102c and 102d as well.

[0031] The second surfaces 106a, 106b of the encapsulating component 102a, 102b are configured to face away from the electronic device 114 and form an outer surface of the hermetically sealed cover 100. In some embodiments, the second surfaces 106a, 106b may be customised by selecting / modifying surface orientation and doping to optimize properties such as hardness, thermal conductivity, or optical transparency. In some embodiments, the second surfaces 106a, 106b may be grown or polished to expose desired diamond facets. In some embodiments, the second surfaces 106a, 106b may be undoped (pure diamond) for maximum chemical inertness. In other embodiments, the second surfaces 106a, 106b may be doped with dopants including, but not limited to, boron or nitrogen to enhance thermal dissipation, or electrical conductivity. In some embodiments, the second surfaces 106a, 106b may include texturing or microstructures, such as micro channels or nano structures, to facilitate heat dissipation, and reduce reflection. Such hermitically sealed cover 100 that include the second surfaces 106a, 106b with texturing or microstructures, may be used for encapsulating electronic device 114 such as sensors that require management of radiative heat transfer. In some other embodiments, the second surfaces 106a, 106b may be a polished surface having high-clarity and optical smoothness. Such hermitically sealed cover 100 that includes the smooth second surfaces106a, 106b may find applications requiring minimal scattering (e.g., optical sensors, laser-based devices). In yet other embodiments, the second surfaces 106a, 106b may include embedded cooling channels, for augmenting heat exchange with ambient air or a cooling medium. By carefully tailoring the orientation, doping, coatings, and structural features of the second surfaces 106a, 106b, of the encapsulating components 102a, 102b, the hermetically sealed cover 100 can be engineered for superior mechanical robustness, thermal management, chemical resistance, and depending on application, optical performance, while maintaining a reliable hermetic seal around the enclosed electronic device 114.

[0032] In some embodiments, the second surfaces 106a 106b of the encapsulating components 102a 102b may be provided with a hydrophobic or oleophobic coatings to minimize contamination or fouling in harsh environments, particularly for medical or industrial applications.

[0033] In some other embodiments, the second surfaces 106a 106b of the encapsulating components 102a 102b may be provided with a protective barrier layer such as an additional transparent or semi-transparent coating of diamond-like carbon or a functional film deposited to reinforce scratch resistance or to provide an anti- reflective function (where optical access is needed). It may be contemplated that one or more characteristics of the second surfaces 106a, 106b, as discussed above and in following paragraphs, may be applicable to the second surfaces 106c and 106d of the encapsulating components 102c and 102d as well.

[0034] Referring again to FIGS. 1 through 6, at least one mating surface of the encapsulating component is sealably joined with at least one mating surface of at least one other encapsulating component, such that the two or more encapsulating components are welded at the mating surfaces to obtain the hermetically sealed cover 100. For instance, as illustrated in FIG. 1, the mating surfaces 108a of the encapsulating component 102a are sealably joined with the corresponding mating surfaces 108b of the encapsulating component 102b to form the hermetically sealed cover 100.

[0035] Referring to FIGS. 2 and 3, another exemplary hermetically sealed cover 100 having three encapsulating components 102a, 102b, 102c is shown, in which the mating surfaces 108a, 108a’ extend between the first surface 104a and the second surface 106a of the encapsulating component 102a, the mating surfaces 108b, 108b’, extend between the first surface 104b and the second surface 106b of the encapsulating component 102b, and the mating surfaces 108c, 108c’ extend between the first surface 104c and the second surface 106c of the encapsulating component 102c. In FIGS. 2 and 3, the mating surface 108a of the encapsulating component 102a is sealably joined with its complementary mating surface 108b’ of the encapsulating component 102b; the mating surface 108a’ of the encapsulating component 102a is sealably joined with the mating surface 108c of the encapsulating component 102c; and the mating surface 108c’ of the encapsulating component 102c is sealably joined with the mating surface 108b of the encapsulating component 102b.

[0036] Referring to FIG. 4, another exemplary hermetically sealed cover 100 having four encapsulating components 102a, 102b, 102c, 102d is shown. The mating surface 108a of the encapsulating component 102a is sealably joined with its complementary mating surface 108b’ of the encapsulating component 102b; the mating surface 108a’ of the encapsulating component 102a is sealably joined with the mating surface 108d of the encapsulating component 102d; the mating surface 108c’ of the encapsulating component 102c is sealably joined with the mating surface 108b of the encapsulating component 102b, the mating surface 108c of the encapsulating component 102c is sealably joined with the mating surface 108d of the encapsulating component 102d.

[0037] Referring to FIG.5, each encapsulating component 102a, 102b, 102c, 102d, are shaped in a manner that when they are welded together, a cuboidal shaped hermetically sealed cover 100 is formed. In the embodiment illustrated in FIG. 5, each of the four mating surfaces of the encapsulating component mates with one mating surface of another encapsulating component. For example, the mating surface 108a of encapsulating component 102a is sealably joined with the mating surface 108b’ of the encapsulating component 102b, the mating surface 108a’ of encapsulating component 102a is sealably joined with the mating surface 108d of the encapsulating component 102d, the mating surface 108c of encapsulating component 102c is sealably joined with the mating surface 108d’ of the encapsulating component 102d, the mating surface 108c’ of encapsulating component 102c is sealably joined with the mating surface 108b of the encapsulating component 102b, so as to form the cuboid shaped hermetically sealed cover 100 of FIG.5.

[0038] With reference to FIG. 6 examples of encapsulating components in standard sizes and shapes is described. FIG 6A provides a perspective view of one of the encapsulating components, e.g., the encapsulating component 102c of the hermetically sealed cover 100 of FIG.5. As illustrated in FIG.6A the encapsulating component 102c has the first surface 104c, the second surface 106c, and a series of lateral faces that define four mating surfaces, a first mating surface 108c, a second mating surface 108c’, a third mating surface 108c’’ and a fourth mating surface 108c’’’, each extending from the first surface 104c to the second surface 106c.Further, the first mating surface 108c may be located opposite to the second mating surface 108c’, and the third mating surface 108c’’ may be located opposite to the fourth mating surface 108c’’’. Referring again to FIG. 5, the encapsulating component 102a has the first surface 104a, the second surface 106a, and four mating surfaces – only two mating surfaces 108a and 108a’are shown; the encapsulating component 102b has the first surface 104b, the second surface 106b, and four mating surfaces – only two mating surfaces 108b and 108b’are shown; the encapsulating component 102c has the first surface 104c, the second surface 106c, and four mating surfaces – only two mating surfaces 108c and 108c’are shown; and the encapsulating component 102d has the first surface 104d, the second surface 106d, and four mating surfaces – only two mating surfaces 108d and 108d’are shown.

[0039] In some embodiments, at least one mating surface of at least one of the encapsulating components is provided with a chamfered surface. In an example, as shown in FIG.6A, each of the mating surfaces of the encapsulating component 102c is provided with a chamfered surface. In other embodiments, one or more mating surfaces of an encapsulating component is flat. For example, as shown in FIG.6B, the encapsulating component 102c has each mating surface as flat. In yet other embodiments, the encapsulating component may have mating surfaces that are a combination of chamfered, flat or fillet or any other suitable shape. FIG.6C and 6D illustrate encapsulating components with a combination of flat and chamfered mating surfaces. In an example, the mating surfaces 108a, 108b (of the encapsulating components 102a, 102b) are provided with respective chamfered surfaces 116a, 116b as illustrated in FIGS.7B and 7C. In some other embodiments, the mating surface of each of the two or more encapsulating components is provided with a fillet surface. In an example the encapsulating components 102a, 102b are provided with fillet surfaces 116a’, 116b’ as illustrated in FIGS.7D and 7E. In some embodiments, by providing the chamfered or fillet surface significantly extends the operational lifetime in high-vibration environments, such as automotive or aerospace applications.

[0040] The types and choice of mating surfaces of the encapsulating component allow the encapsulating component to be manufactured in standard shapes and sizesand to be used as modular building blocks to form size and shapes of hermetically sealed covers as desired. For example, mating surfaces as illustrated in FIG 6A and 6C are suitable for corner pieces that form the hermitically sealed cover 100.

[0041] In some embodiments, the mating surfaces 108a, 108b of the encapsulating components 102a, 102b may include at least one alignment feature for enabling a precise fit and facilitating laser welding to form the hermetically sealed cover 100. In some embodiments, the alignment feature includes interlocking protrusions and recesses where small protrusions on the mating surfaces 108a, 108b of one of the encapsulating components 102a, 102b, may fit into the complementary recesses on the mating surfaces 108a, 108b of the other of the encapsulating component 102a, 102b, ensuring correct orientation and minimizing lateral or rotational misalignment. In other embodiments, the alignment feature includes guide rails or ridges formed along the mating surfaces 108a, 108b of one encapsulating component 102a, 102b, which slots into a corresponding groove on the mating surfaces 108a, 108b, of the other of the encapsulating component 102a, 102b, to maintain a uniform welding gap. In yet another embodiment, the alignment feature includes reference notches or markers (etched or machined) that allow robotic or manual assembly systems to accurately position the mating surfaces 108a, 108b of the two encapsulating components 102a, 102b prior to coupling via welding. In yet another embodiment, the alignment feature may be an integrally formed spacers comprising slightly raised areas or studs that define a controlled distance between the mating surfaces 108a, 108b of the two encapsulating components 102a, 102b for optimal weld penetration or outgassing channels before sealing. These alignment features may result in a consistently accurate mating interface that simplifies assembly and enhances the robustness of the hermetically sealed cover 100. It may be contemplated that the mating surfaces of the encapsulating components 102c, 102d may have one or more alignment features similar to the alignment features of the mating surfaces 108a, 108b of the encapsulating components 102a, 102b as discussed above.

[0042] In some embodiments, the hermetically sealed cover 100 includes at least one intermediate layer adjacent to the first surface of at least one of the two or more encapsulating components. FIG.5 illustrates an example of the hermetically sealedcover 100 that includes the intermediate layer 118, adjacent to the first surface 104a, 104b, 104c, 104d of the encapsulating components 102a, 102b,102c, 102d. The intermediate layer 118 may be composed of any suitable material including but not limited to a thermally conductive material, an electrically insulating material, a vibration-dampening material and a combination thereof. In some embodiments, the intermediate layer 118 is provided to reduce thermal, mechanical, or vibrational impact on the electronic device 114 during the sealing process.

[0043] Thermally conductive material includes but is not limited to high- conductivity ceramics, metals, or composite materials that can efficiently dissipate heat away from the encapsulated electronic device 114. By way of an example, the thermally conductive material is selected from aluminium nitride, boron nitride, and silicon carbide. Other examples of the thermally conductive material include metals such as copper, silver, and tungsten provided as a thin foil or sputtered film for rapid heat spreading. In some embodiments, where the intermediate layer 118 is made of metal, such metal-based layers can be combined with insulating coatings, if necessary, to maintain overall electrical isolation. Yet another example of the thermally conductive material includes one or more composite layers comprising of polymer matrices loaded with nano- or micro-diamond particles. Such layers may be applied via various processes, including vacuum deposition (physical vapor deposition, PVD; chemical vapor deposition, CVD), lamination of preformed foils, or spin-coating. The thickness of the thermically conductive material may range from a few micrometres (e.g., 10–50 µm for sputtered metallic or ceramic films) up to several hundred micrometres (e.g., 100–500 µm for laminated foils or composite layers). Selecting the appropriate thickness and composition ensures effective heat dissipation while maintaining a secure mechanical interface between the diamond encapsulating component 102a, 102b and the enclosed electronic device 114.

[0044] The electrically insulating material includes but is not limited to ceramics, polymers, or composite materials that offer high dielectric strength and chemical stability. Examples include aluminium oxide (Al₂O₃), silicon nitride (Si₃N₄), boron nitride (BN) or aluminium nitride (AlN), polyimide films (e.g., Kapton), epoxy based or silicone-based insulating layers. These materials can be deposited or bonded tothe inner surface of the diamond encapsulating component via methods such as sputtering, spin-coating, chemical vapor deposition, or adhesive lamination. The thickness of the electrically insulating material may range from a few micrometers (e.g., thin-film ceramic coatings) up to hundreds of micrometers (e.g., laminated polymer films or composite layers), providing sufficient electrical isolation without compromising the device’s thermal performance.

[0045] The vibration-dampening material includes but is not limited to elastomers, polymers, or composite layers that mitigate mechanical shocks and vibrations transmitted to the electronic device. Examples include but is not limited to silicone elastomers such as polydimethylsiloxane, PDMS, polyurethane foams, butyl rubbers, nitrile rubbers, viscoelastic polymers such as 3M™ VHB™ adhesives, or specialized damping tapes, composite layers such as polymer-based matrices loaded with micro- inclusions or nanofillers. Such vibration-dampening layers can be applied through molding, adhesive lamination, or spin-coating processes, depending on the chosen material and desired layer thickness. The thickness of the vibration-dampening material may range from a few micrometres (for thin, high-precision damping coatings) to several millimetres for robust shock-absorption.

[0046] In some embodiments, a single intermediate layer 118 is provided. The single intermediate layer 118 may be composed of a single material or may be composed of a combination of two or more different materials. For example, a first part of the intermediate layer 118 may be composed of the thermally conductive material and a second part of the intermediate layer 118 may be composed of the electrically insulating material. In such embodiments, for example, one of more of the encapsulating components may have an intermediate layer 118 composed of one material, (for e.g., the thermally conductive material) and one or more encapsulating components may have an intermediate layer 118 composed of another material (for e.g., the electrically insulating material). In an alternate embodiment, two or more intermediate layers 118 are provided wherein each intermediate layer 118 is composed of a different material, placed one on top of the other.

[0047] The intermediate layer 118 may have a thickness in the range from about 1 micrometer (µm) to about 5 millimeters (mm), depending on the specific functionalrequirements (e.g., thermal conductivity, electrical insulation, or vibration dampening). Preferably, the thickness of the intermediate layer 118 is in the range from 50 micrometers to 1 millimeter. More preferably, the thickness of the intermediate layer 118 is in the range from 25 micrometers to 500 micrometers, which provides a practical balance between providing sufficient protective functionality and preserving a compact overall form factor for the hermetically sealed cover 100.

[0048] In some embodiments, one or more encapsulating components 102a, 102b may further includes integrally formed mechanical coupling features (not shown) on the second surfaces 106a, 106b, to help secure the encapsulated device into a larger assembly or a heat sink. In some other embodiments, the one or more encapsulating components 102a, 102b may further include reinforcing ribs or thicker regions on their second surfaces 106a, 106b, to enhance mechanical rigidity and resilience to external shocks. In yet other embodiments, one or more encapsulating components 102a, 102b, may further include integrated heat sink regions such as extending protrusions, fins or thermal vias to increase surface area and to dissipate heat from the electronic device 114 to the external environment.

[0049] In some embodiments, the hermetically sealed cover 100 further comprises at least one feedthrough member in at least one encapsulating component. As illustrated in FIG. 8, a feedthrough member 120 is provided in the encapsulating component 102b of the hermetically sealed cover 100. The feedthrough member 120 is hermetically sealed to the encapsulating component 102b via a brazed alloy layer. Said feedthrough member 120 is configured for providing electrical or optical communication between an interior portion of the hermetically sealed cover 100 and an external environment. The feedthrough member 120 is selected from a group comprising molybdenum, tantalum, niobium, platinum, nickel, and copper. In yet other embodiments, the feedthrough member 120 may be fabricated by using any electrically conductive material known in the art.

[0050] As illustrated in FIG. 9, in some embodiments, at least one strain- compensating interlayer 124 may be disposed at an interface between encapsulating component and the feedthrough member 120 to mitigate thermal expansionmismatches. The strain-compensating interlayer 124 may be fabricated using a material selected from a group consisting of Titanium Carbide (TiC), Molybdenum Carbide (MoC), and Niobium Nitride (NbN), or a combination thereof.

[0051] With continued reference to FIGS 1 through 5, a method for creating the hermetically sealed cover 100 for the electronic device 114 is described. The method comprises obtaining two or more encapsulating components 102a, 102b, 102c, 102d, using a diamond deposition technique. The diamond deposition technique that may be used for fabricating the encapsulating components 102a, 102b, 102c, 102d include, but is not limited to, chemical vapor deposition (CVD) technique, high pressure high temperature (HPHT) technique, and a combination thereof. Other known process of synthesizing diamonds as is now known or in the future developed may also be used for fabricating the encapsulating components 102a, 102b, 102c, 102d.

[0052] In an exemplary embodiment, the fabrication of the encapsulating component 102a, 102b, 102c, 102d is carried out by chemical vapor deposition (CVD) technique. The method comprises providing a support structure including a seed layer inside a CVD reactor. The support structure may be one of a mold or a template, which can be custom-machined or formed to mirror the desired final geometry of the encapsulating component 102. For instance, the mold could have a concave or convex surface to produce hemispherical or domed diamond layers, or multiple facets / shapes to facilitate more complex geometries. The support structure may be made of any suitable material, including but not limited to, semiconductors such as silicon and silicon carbide, metals such as molybdenum and tungsten, ceramics such as alumina, silicon nitride or glass / insulator materials such as silicon dioxide. The support structure is selected such that there is minimized mismatches in the coefficient of thermal expansion (CTE) which helps reduce stress at the diamond-substrate interface during high-temperature CVD processes, mechanical stability for maintaining dimensional accuracy under vacuum or high-temperature conditions to preserve shape fidelity, chemical inertness to ensure the mold or template material does not contaminate the diamond growth surface or degrade under hydrogen plasma, releasability for facilitating subsequent debonding steps (e.g.,through etch stops, sacrificial layers, or specialized surface coatings that prevent permanent bonding).

[0053] In some embodiments, the seed layer is deposited on the support structure. The seed layer includes a thin layer of diamond deposited on the support structure using known techniques for example, microwave plasma CVD or hot filament CVD. In other embodiments, one or more nanodiamonds or microdiamonds may be deposited onto the support structure via seeding techniques such as ultrasonic agitation or spin-coating to ensure uniform distribution of diamond nuclei to form the seed layer.

[0054] A feed gas comprising a mixture of gases is fed into the CVD reactor. The feed gas comprises one or more carbon containing gases (e.g., methane (CH4)) diluted in a high concentration of hydrogen (H2) gas. In some embodiments, feed gas comprises methane in the range from 1% to 5% and hydrogen in the range from 95% to 99%. In some embodiments, the feed gas further comprises a dopant-containing gas selected from boron (e.g., diborane (B2H6)), nitrogen (N2), phosphorus molecules or mixtures thereof.

[0055] Next, the feed gas is ionized and dissociated using a microwave plasma (plasma-enhanced chemical vapor deposition (PECVD)) or a hot filament (hot- filament chemical vapor deposition) activation technique, thereby providing a reactive environment for promoting diamond growth on the substrate. The temperature and pressure inside the reactor and the ratio of dopant-containing gases (if added) to the one or more carbon containing gases in the feed gas are maintained at predetermined level. The temperature is typically maintained between 700°C and 1200°C, depending on the specific CVD process, to enable optimized nucleation and growth rates. The pressure ranges from 10 Torr to several hundred Torr, ensuring sufficient partial pressures of reactive species for stable, high-quality diamond growth. The flow rates of the feed gas and ratios of its components is adjusted to control growth rates, crystal size, dopant incorporation, and uniformity. For instance, methane concentration can range from about 0.5% to 5% (v / v) in hydrogen, while dopant gases may be introduced at significantly lower concentrations (e.g., ppm to percent levels) to fine-tune doping profiles. The doping with boron, nitrogen, orphosphorus is done to tailor the electrical or optical properties of the encapsulating component 102. Gradients in dopant concentration may be introduced to modulate conductivity or enhance mechanical toughness at specific layers of the encapsulating component.

[0056] In the next step, the encapsulating component 102a, 102b, 102c, 102d is debonded from the supporting structure. Any known method for debonding the engineered diamond from the support structure may be used to debond the encapsulating component 102a, 102b, 102c, 102d from the support structure. Such methods for debonding diamond include, but are not limited to, chemical etching, plasma or ion beam processes, thermal or mechanical fracturing, laser-based lift-off, adhesive and temporary bonded layer removal.

[0057] Chemical etching involves selectively removing the support structure using acid or alkaline solutions. For instance, substrates made of silicon can be dissolved by Potassium hydroxide (KOH) or Potassium hydride (HF), while certain metals can be etched with appropriate acid solutions. If a sacrificial release layer, such as a metal or oxide film, is placed between the substrate and the engineered diamond, chemical reagents can dissolve or undercut this layer, enabling the diamond to lift off. The plasma or ion beam processes involve reactive ion etching (RIE) or focused ion beam (FIB) milling that locally removes or weakens the interface at the support structure, enabling separation. Said method of debonding is especially useful when conventional wet etchants are not suitable or would cause undesired damage. The thermal or mechanical fracturing is the process of exploiting thermal expansion mismatch, wherein rapid changes in temperature (thermal shock) can cause the substrate to crack or debond along the interface, freeing the diamond. Careful mechanical wedge or blade insertion at the perimeter of the interface may gently lift off the diamond if the bond is weak enough. The laser-based lift-off is a process where a pulsed laser (e.g., excimer or femtosecond) is focused on the interface to induce localised ablation or heating, thus releasing the diamond layer from the substrate. The adhesive or temporary bonded layer removal may be done if the support structure was coated with an adhesive or polymer release layer prior todiamond deposition. In such methods, solvents or mild heat can dissolve or soften that layer, allowing the diamond to be peeled away.

[0058] The method for debonding is selected based on substrate composition, diamond thickness, and the desired final surface quality, of the encapsulating component 102a, 102b, 102c, 102d. The debonding step completes the formation of the free-standing diamond encapsulating components 102a, 102b, 102c, 102d, ready for subsequent assembly and welding into the hermetically sealed cover 100.

[0059] Referring now to FIG. 7B through 7E, in some embodiments, the process further comprises of providing on the mating surface of the encapsulating component, a chamfer surface or a fillet surface, such as the chamfered surface 116a, 116b on the mating surfaces 108a, 108b of the encapsulating components 102a, 102b; or the fillet surfaces 116a’, 116b’ on the mating surfaces 108a, 108b of the encapsulating components 102a, 102b. In some other embodiments, the chamfer surface or the fillet surface may be formed during the fabrication of the encapsulating components, i.e., during the diamond growth. In some other embodiments, the chamfer surface or the fillet surface may be formed after the encapsulating components are formed via post-growth processes such as laser micromachining or selective etching.

[0060] In some embodiments, the process further comprises making alignment features on the mating surfaces of the encapsulating components. In some embodiments, the alignment features can be formed during diamond growth (by shaping the growth template or mold). In some other embodiments, the alignment features may be formed after the encapsulating components are formed via post- growth processes such as laser micromachining or selective etching.

[0061] In some embodiments, the method further comprises providing at least one feedthrough (e.g., the feedthrough member 120) in at least one encapsulating component. FIG 8 illustrates an embodiment of the hermetically sealed cover 100 that includes the feedthrough member 120 in the encapsulating component 102b. In the first step of the method, a cavity is machined in one (or more) of the diamond encapsulating components (e.g., the encapsulating component 102b) using a laser- assisted or ultrasonic micro-machining process. The cavity dimensions are tailoredto the diameter or cross-section of the feedthrough member 120. The feedthrough member 120 is then passed though the cavity. The feedthrough member 120 may be cleaned before passing it through the cavity. The feedthrough member 120 maybe metal or diamond or any other suitable material. In some embodiments, the feedthrough member 120 may optionally be coated with graphene, a carbide forming layer or an ion-implanted surface to enhance wettability. A brazing alloy 122 (for example, Ni-based or Ag-Ti-based) is added to the cavity either before passing the feedthrough member 120 or after passing the feedthrough member 120. The encapsulating component 102b with the feedthrough member 120 and the brazing alloy 122 may be placed in a high-vacuum chamber. In some embodiments, the high vacuum chamber has a pressure of more than ≤103mbars. The temperature of the chamber is them raised such that the brazing filler melts to hermitically seal the feedthrough member 120 to the encapsulating component 102b. The brazing is carried at a temperature in a range from 850°C to 1300°C depending on the brazing alloy.

[0062] In some embodiments, a strain-compensating layer is provided at an interface between the diamond material of the encapsulating component (e.g., the encapsulating component 102b) and the feedthrough member 120. FIG 9 illustrates an embodiment of the hermetically sealed cover 100 that includes strain- compensating layer 124. The strain-compensating layer 124 may be selected from a group consisting of TiC, MoC, and NbN. In some embodiments, the strain- compensating layer 124 may mitigate differences in the coefficient of thermal expansion between the feedthrough member 120 and the diamond encapsulating component 102b to reduce thermal stress during subsequent cooling or operational cycles.

[0063] Once the encapsulating components 102a, 102b, 102c, 102d are fabricated, the electronic device 114 is assembled or placed within the two or more of the encapsulating components 102a, 102b, 102c, 102d such that the electronic device 114 is encapsulated within the two or more encapsulating components 102a, 102b, 102c, 102d in a manner that the two or more encapsulating components 102a, 102b, 102c, 102d are integral and seamlessly contiguous to each other.

[0064] In an example, the encapsulating components 102a, 102b are placed such that at least one mating surface 108a, 108b of one of the encapsulating components 102a, 102b is in contact with at least one other mating surface 108a, 108b of at least one other encapsulating component102a, 102b. In some embodiments, before the electronic device 114 is assembled and the encapsulating components 102a, 102b are placed together to form the hermetically sealed cover 100, the mating surfaces 108a, 108b of the encapsulating components 102a 102b are smoothened. The smoothening of the mating surfaces 108a, 108b may be done by polishing such as mechanical lapping with diamond-based slurries or chemical-mechanical planarization (CMP). Other suitable techniques may include laser ablation (using ultrafast lasers to selectively remove micro-roughness) or reactive plasma etching (to isotropically remove surface irregularities). In some embodiments, the smoothening of the mating surfaces 108a, 108b before welding allows for precision alignment of the encapsulating components 102a, 102b.

[0065] In some embodiments, before the electronic device 114 is placed within the encapsulating components 102a, 102b an intermediate layer 118 is provided between the electronic device 114 and the first surface 104a, 104b of at least one of the encapsulating components 102a, 102b. The intermediate layer 118 is selected from a group consisting of a thermally conductive layer, an electrically insulating layer and a vibration-dampening substance. In some embodiments, the intermediate layer 118, is applied to absorb any vibrations or mechanical stress that may be experienced by the electronic device 114 during the sealing process to protect the fragile components from potential damage. Such an intermediate layer 118 is provided to facilitate damping capacity across a range of frequencies, reducing resonance-related damage, adhesion and layer integration. In some other embodiments, the intermediate layer 118 is applied to allow thermal conductivity between the electronic device 114 and the encapsulating component, allowing heat to dissipate from the electronic device 114 to the outside environment. In yet other embodiments, the intermediate layer 118 is applied to provide electric insulation to the electronic device 114. The intermediate layer 118 may be composed of any suitable material including, but not limited to, a thermally conductive material, anelectrically insulating material, a vibration-dampening material and a combination thereof.

[0066] Thermally conductive material includes, but is not limited to, high- conductivity ceramics, metals, or composite materials that can efficiently dissipate heat away from the encapsulated electronic device 114. By way of an example, the thermally conductive material is selected from aluminium nitride, boron nitride, and silicon carbide. Other examples of the thermally conductive material include metals such as copper, silver, and tungsten provided as a thin foil or sputtered film for rapid heat spreading. In some embodiments, where the intermediate layer 118 is made of metal, such metal-based layers can be combined with insulating coatings, if necessary, to maintain overall electrical isolation. Yet another example of the thermally conductive material includes one or more composite layers comprising of polymer matrices loaded with nano- or micro-diamond particles. Such layers may be applied via various processes, including vacuum deposition (physical vapor deposition, PVD; chemical vapor deposition, CVD), lamination of preformed foils, or spin-coating.

[0067] The electrically insulating material includes but is not limited to ceramics, polymers, or composite materials that offer high dielectric strength and chemical stability. Examples include aluminium oxide (Al₂O₃), silicon nitride (Si₃N₄), boron nitride (BN) or aluminium nitride (AlN), polyimide films (e.g., Kapton), epoxy based or silicone-based insulating layers. These materials can be deposited or bonded to the inner surface of the diamond encapsulating component via methods such as sputtering, spin-coating, chemical vapor deposition, or adhesive lamination. The thickness of the electrically insulating material may range from a few micrometers (e.g., thin-film ceramic coatings) up to hundreds of micrometers (e.g., laminated polymer films or composite layers), providing sufficient electrical isolation without compromising the device’s thermal performance.

[0068] The vibration-dampening material includes but is not limited to elastomers, polymers, or composite layers that mitigate mechanical shocks and vibrations transmitted to the electronic device. Examples include but is not limited to silicone elastomers such as polydimethylsiloxane, PDMS, polyurethane foams, butyl rubbers,nitrile rubbers, viscoelastic polymers such as 3M™ VHB™ adhesives, or specialized damping tapes, composite layers such as polymer-based matrices loaded with micro- inclusions or nanofillers. Such vibration-dampening layers can be applied through moulding, adhesive lamination, or spin-coating processes, depending on the chosen material and desired layer thickness. The thickness of the vibration-dampening material may range from a few micrometres (for thin, high-precision damping coatings) to several millimetres for robust shock-absorption.

[0069] In some embodiments, the thickness of the intermediate layer 118 is chosen to maintain a compact form factor while ensuring adequate thermal, electrical, and mechanical performance. The intermediate layer 118 is applied such that it has a thickness in a range from 1 micrometer (µm) to 5 millimeters (mm), depending on the specific functional requirements (e.g., thermal conductivity, electrical insulation, or vibration dampening). Preferably, the intermediate layer 118 is applied such that it has a thickness in a range from 50 micrometers to 1 millimeter, which strikes a practical balance between providing sufficient protective functionality and preserving a compact overall form factor for the hermetically sealed cover.

[0070] In some embodiments, optionally the process further comprises carrying out surface treatment of the first surface 104a, 104b, of the encapsulating component 102a, 102b, before applying the intermediate layer 118. The surface treatments may be selected from a chemical functionalization treatment or a plasma treatment to enhance bonding between the first surface 104a, 104b, of the encapsulating component 102a, 102b and the intermediate layer 118, improving mechanical integrity.

[0071] In the next step, the electronic device 114 is hermetically sealed within the encapsulating components 102a, 102b by welding together the mating surfaces 108a, 108b of the encapsulating components 102a, 102b that are in contact with each other. The welding of the encapsulating components 102a, 102b may be done via a laser source selected from a group consisting of a femtosecond laser and a picosecond laser.

[0072] In accordance with an embodiment, the welding is done by the femtosecond laser. The femtosecond laser has at least one pulse width in the range from 50femtoseconds to 500 femtoseconds depending on the thickness of the diamond pieces that is to be joined. Preferably, the femtosecond laser has at least one pulse width in the range from 80 femtoseconds to 200 femtoseconds. In accordance with an aspect, the femtosecond laser has a pulse repetition rate from50 kHz to a few MHz. Preferably, the femtosecond laser has a pulse repetition rate from 50 kHz to 2 MHz, and more preferably, the femtosecond laser has a pulse repetition rate from 50 kHz to 1 MHz. The pulse repetition rate of the femtosecond laser is selected such that it maintains sufficient average power while preventing excessive heat accumulation. In accordance with an aspect, the average power of the femtosecond laser that is used is of the order of a few watts (W) to tens of watts, depending on the thickness of the two or more diamond pieces that to be joined and desired weld depth. In some embodiments, the average power of the femtosecond laser is in the range from 0.5 W to 50 W. Preferably, the average power of the femtosecond laser is in the range from 1 W to 20 W.

[0073] In an alternate embodiment, the welding is done by the picosecond laser. In an aspect, the picosecond laser has at least one pulse width in the range from 1 picosecond to 100 picoseconds. Preferably, the picosecond laser has at least one pulse width in the range from 2 picoseconds to 50 picoseconds. In an aspect, the picosecond laser has a pulse repetition rate of at least 50 kHz, depending on required processing speed and thermal management. Preferably, the pulse repetition rate is in a range from 50 kHz to 1 MHz. More preferably, the pulse repetition rate is in a range from 50 kHz to 500 kHz. The energy per pulse is in a range from microjoules (µJ) to millijoules (mJ), ensuring localised melting / fusion without over-penetration. Preferably, the energy per pulse is in a range from 5 µJ to 2 mJ and more preferably in a range from 20 µJ to 1 mJ.

[0074] In some embodiments, precise control of power and pulse energy is done to avoid crack formation or thermal damage. Short pulse durations (fs-ps range) reduce heat-affected zones and enable high-quality weld seams.

[0075] In accordance with an aspect, the welding is carried out with a tightly focused beam having a spot size in the range from a few micrometres to tens of micrometres to ensure high-intensity interaction at an interface of the mating surfacesof the encapsulating components, enabling localised melting and fusion of the mating surfaces. In an aspect, the spot size is in a range from 1 µm to 100 µm. Preferably, the spot size is in a range from 5 µm to 30 µm.

[0076] The welding paths may be rastered, spiral-scanned, or follow a contour of the mating surface to achieve continuous seam welds. In some embodiments, the welding is carried out with overlapping passes (e.g., 50–90% overlap) to ensure full coverage and minimize porosity. For example, the welding is carried out with an overlap of 50 % to 90%. In some other embodiments, the welding of the mating surfaces 108a, 108b comprises passing the laser at least two times over the mating surfaces 108a, 108b of the encapsulating component 102a, 102b. In some embodiments, passing the laser two or more times over the mating surfaces 108a, 108b of the encapsulating component 102a, 102b ensures robust hermeticity, compensates for minor surface irregularity and manages stress distribution. In addition, passing the laser beam twice over the mating surfaces with approximately 70% overlap decreased weld porosity by over 40%, as confirmed via helium leak detection.

[0077] In some embodiments the welding is carried out in a controlled atmosphere. The controller atmosphere under which the welding is carried out includes but is not limited to a vacuum, inert gas atmosphere including a nitrogen atmosphere to minimize oxidation or contamination at high temperatures. Certain embodiments require slight overpressure of inert gas to help expel debris or molten material.

[0078] In accordance with an aspect, the welding of the mating surfaces 108a, 108b is carried out under real-time sensors (e.g., pyrometers, optical sensors) for detection of weld pool formation and temperature to dynamically adjust laser parameters. Closed loop feedback helps avoid defects such as cracks voids or insufficient weld penetration.

[0079] Once the mating surfaces 108a, 108b, of the two or more encapsulating components 102a, 102b, are welded together, the hermetically sealed cover 100 is cooled. The cooling is carried out in a predetermined manner to prevent thermal shocks and to reduce the likelihood of damage to internal components of the electrical device. The controlled cooling protocol, includes protocols such as slowthermal ramp-downs or staged cooling. The slow thermal ramp-down is a process wherein the cooling is carried out at a continuous cooling rate of about 1°C to 10°C per minute, gradually lowering the temperature from the welding zone (which may locally reach several hundred degrees Celsius) down to near-ambient levels. This approach reduces the risk of microcracks or delamination caused by abrupt temperature gradients. The staged cooling is a process wherein the cooling is performed in discrete steps. In some embodiments, the staged cooling is carried out in two stages, in a first stage, the temperature is reduced from about 300°C to 150°C at 5°C / min, and in a second stage, temperature is reduced from 150°C to room temperature at 2°C / min. Each stage is typically followed by a soak period (e.g., holding the hermetically sealed cover 100 at an intermediate temperature for 10 to 30 minutes), allowing internal stresses to relax uniformly before further temperature reductions. In some embodiments, cooling occurs under inert gas flow (argon, nitrogen) or in a vacuum to eliminate oxidation or contamination during the cooldown phase. A precisely regulated environment further prevents thermal gradients and maintains consistent material properties.

[0080] In some embodiments, once all the encapsulating components (e.g., the encapsulating components 102a, 102b, 102c, 102d) are welded together, a further reinforcing process is carried out to stabilize the seal, reduce residual stresses, and enhance the durability and functionality of the hermetically sealed cover 100. The reinforcing process includes, but is not limited to, heat treatment, annealing, coating the second surfaces 106a, 106b of the encapsulating components 102a, 102b, laser or ion-beam peening and providing secondary structural reinforcement on the second surface of the encapsulating components 102a 102b after welding.

[0081] The heat treatment or annealing involves high-temperature treatment, and stress relief. In other embodiments, annealing may be done at lower temperatures of 350 to 600°C. The high-temperature treatment (e.g., 600°C–1200°C) is conducted in a controlled atmosphere such as high vacuum or inert gas (argon, nitrogen) to eliminate oxidation. Stress relief happens when elevated temperatures allow microstructural relaxation in the diamond encapsulating components and at the weld interface, reducing the risk of cracks or delamination. The duration may range froma few minutes to several hours, depending on thickness of the encapsulating components 102a, 102b and desired relaxation level. In some embodiments, annealing the sealed assembly at 800°C to 1000°C for about 10 to 120 minutes in an inert or vacuum atmosphere allows reduction in residual stress at the weld interface by approximately 30%. In certain embodiments, the annealing may be time limited to 5 to 10 minutes. The post-weld annealing step can significantly bolster the hermetic seal and improve long-term reliability. In other embodiments, the annealing may be carried out pre-weld or in multiple stages.

[0082] In some embodiments, the reinforcement process further comprises coating the second surfaces 106a, 106b, of the encapsulating components 102a 102b, after the encapsulating components 102a 102b are welded together. In other embodiments, the coating may be carried out pre-weld. In some embodiments, the coating includes a coating of a diamond-like carbon (DLC) or of additional diamond layers. Such coating offers extra scratch resistance, chemical inertness, and can serve as a protective interface for high-wear or corrosive environments. In other embodiments, coating includes a coating of metal film or a ceramic film (for e.g., films of Titanium, Aluminium oxide (Al₂O₃), or Silicon nitride (Si₃N₄)) applied via physical vapor deposition (PVD), chemical vapor deposition (CVD), or sputtering to improve surface properties (such as reflectivity, thermal dissipation, or electrical isolation). In yet other embodiments, the coating includes polymeric overcoats for example fluoropolymer-based coating, or silicone-based coating that provide hydrophobicity / oleophobicity, dampening, or insulation benefits while maintaining external hermeticity.

[0083] In some embodiments, reinforcing process comprises providing at least one secondary structural reinforcement on the second surface 106a, 106b, of the encapsulating components 102a 102b. The secondary structural reinforcement can be provide by adhesive bonding of the reinforcing structures including but not limited to additional diamond or ceramic rings, fins, or frames to the second surfaces 106a, 106b of the encapsulating components 102a, 102b to enhance mechanical stiffness or improve heat dissipation. In some embodiments, the secondary structuralreinforcements include reinforcing collars or rib-like structures provided over vulnerable weld seams to distribute stress more uniformly.

[0084] In yet other embodiments, the reinforcing process may include carrying out processes like laser or ion-beam peening, surface treatment techniques that impart compressive stresses, diminishing crack propagation at or near the weld seams, controlled cooling extensions where extended soak time is provided at intermediate temperatures, paired with slow ramp-down protocols after annealing, to ensure full stress equilibration. These reinforcement processes are applied to stabilize the seal and relieve any residual mechanical stresses and to further enhance the durability and functionality of the hermetically sealed encapsulated cover 100.

[0085] In certain embodiments, the hermetically sealed cover 100 may be purged, evacuated, or back-filled with a controlled atmosphere prior to final laser welding or sealing. This internal environment (vacuum, inert, or specially formulated) may be selected to optimize the performance and longevity of the enclosed electronic or electromechanical devices, such as the electronic device 114.

[0086] As an additional step, the hermetically sealed cover 100 may be verified by using a technique selected from a group consisting of helium leak detection, and high-resolution X-ray tomography.

[0087] In accordance with an aspect, sensors or monitoring systems (such as thermocouples, infrared cameras, or spectrometers) are used to provide real-time data on temperature, energy input, and mechanical stress, allowing for dynamic adjustments during the process. During diamond deposition process thermocouples are placed near or on the support structure to monitor reactor temperature, ensuring that the CVD growth environment remains within specified ranges (e.g., 700°C– 1200°C). Spectrometers may be used to analyze plasma composition (e.g., methane / hydrogen ratios, dopant gas concentrations) in real time, enabling precise control over doping levels and diamond growth rates. Also, during the step of smoothing the mating surfaces 108a, 108b of the encapsulating components 102a, 102b, infrared cameras may be used to track localized heating or friction zones during polishing or laser ablation, to moderate polishing pressure, laser power, or feed rates to avoid surface damage. Acoustic emission sensors (optional) may alsobe used to detect microcracking or delamination in the diamond while smoothing the mating surfaces 108a, 108b. Further, during laser welding thermocouples or pyrometers may be used to provide temperature feedback at or near the weld interface to prevent overheating and subsequent diamond cracking, high-speed infrared cameras may be used to capture thermal profiles of the weld zone in real time, verifying consistent weld penetration and identifying potential hot spots. Spectrometers or photodiodes may be used to monitor plasma emissions or reflected laser signals during ultrafast (femtosecond / picosecond) welding, guiding power modulation and pulse overlap. During the cooling phase thermocouples are used to measure ramp-down temperature at the weld site and within the sealed enclosure, ensuring uniform cooling rates and preventing thermal shock. Strain gauges (optional) can be embedded on the second surfaces 106a, 106b of the encapsulating components 102a, 102b, to detect residual stress development in real time, allowing for staged cooling adjustments. Industrial Applicability

[0088] Exemplary applications of the hermetically sealed cover 100 for an electronic device 114 of the present invention will now be explained in detail. The flexibility of the hermetically sealed cover 100 allows it to be used for sealing a diverse array of high-value or sensitive electronic or electrical devices, in a simple and efficient manner.

[0089] To this end, the hermetically sealed cover 100 may be used to encapsulate electronic devices that require precise environmental control such as advanced semiconductor components like CMOS chips such as microprocessors, ASICs, and other integrated circuits.

[0090] Hermetically sealed cover 100 may also be used to encapsulate electronic or similar devices which operate at high temperatures and demanding operational conditions necessitating robust packaging. Such electronic devices may include power devices like high-voltage IGBTs, MOSFETs, GaN / SiC transistors for power conversion and motor drives.

[0091] Other type of electronic devices that can be encapsulated with the hermetically sealed cover 100 are those requiring contamination-free and sterile conditions, such as biomedical and pharmaceutical microdevices like implantable pumps or micro-reservoir devices. Additionally, the hermetically sealed cover 100 is suitable for devices needing biocompatible, chemically inert protective barriers such as biosensors, including enzymatic or MEMS-based sensors for in vivo applications.

[0092] Another application of the hermetically sealed cover 100 is to encapsulate electronic devices, including MEMS components such as accelerometers and gyroscopes, used in navigation, automotive safety, and consumer electronics, where environmental isolation enhances reliability. Additionally, the hermetically sealed cover 100 is used for encapsulating pressure sensors critical in aerospace or industrial processes, which require hermetic encapsulation to prevent drift and damage. Yet another application of the hermetically sealed cover 100 is for the encapsulation of electronic devices which require an ultra-clean, moisture-free environment to maintain sensitivity such as optical and photonic devices like optoelectronic sensors like photodiodes, avalanche photodiodes, or CCD / CMOS imaging sensors. Yet another application of the hermetically sealed cover 100 is for the encapsulation of electronic devices sensitive to temperature and humidity fluctuations. Examples of such electronic devices include laser diodes and quantum cascade lasers, which benefit from diamond’s superior thermal dissipation.

[0093] Moreover, the hermetically sealed cover 100 may also be used to encapsulate quantum computing and sensing elements such as superconducting qubits where extremely low temperatures and vacuum conditions necessitate a stable and contamination-free enclosure.

[0094] The hermetically sealed cover 100 may also be used for encapsulating automotive electronics like engine control modules that are exposed to extreme temperature cycles and vibration, requiring robust packaging. Additionally, the hermetically sealed cover 100 also find application in aerospace electronics such as satellite or spacecraft systems where harsh vacuum, radiation, and wide temperature fluctuations demand highly durable hermetic sealing.

[0095] These examples illustrate the versatility of the hermetically sealed cover 100 in safeguarding sensitive electronics from mechanical shocks, thermal fluctuations, and harsh operating conditions, thereby enhancing overall reliability and extending service life.

[0096] Moreover, the hybrid brazing-plus-laser-welding method provides a reliable feedthrough for powering enclosed electronics, routing signals (e.g., quantum or sensor leads), or delivering fluids in microfluidic implants. Testing has shown that the resulting feedthrough exhibits leak rates below 1×10^-9 mbar·L / s under repeated thermal cycling from –40°C to +150°C, indicating superior hermetic integrity.

[0097] It will be apparent to those skilled in the art that various modifications and variations can be made to the method and / or system of the present disclosure without departing from the scope of the disclosure. Other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the method and / or system disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalent.List of Elements exemplary hermetically sealed covera encapsulating component b encapsulating component c encapsulating component d encapsulating component a first surface b first surface c first surface d first surface a second surface b second surface c second surface d second surface third mating surface a-108a’ mating surfaces b-108b’ mating surfaces c-108c’ mating surfaces d-108d’ mating surfaces electronic device a chamfered surface b chamfered surface intermediate layer feedthrough member brazing alloy strain-compensating interlayer

Claims

We Claim:

1. A hermetically sealed cover for one or more electronic devices, the hermetically sealed cover comprising: at least two encapsulating components made of diamonds, each encapsulating component including: a first surface configured to face towards the one or more electronic devices; a second surface configured to face away from the one or more electronic devices; and at least one mating surface extending between the first surface and the second surface, wherein at least one mating surface of each encapsulating component is configured to be joined with at least one mating surface of the other encapsulating component via welding to hermetically enclose the one or more electronic devices between the at least two encapsulating components.

2. The hermetically sealed cover of claim 1, wherein the encapsulating component is made of engineered diamond selected from a group consisting of a monolithic diamond, a polycrystalline diamond, a doped monolithic diamond, a doped polycrystalline diamond and a combination thereof.

3. The hermetically sealed cover of claim 1, wherein the at least one mating surface of the encapsulating component has a chamfer surface or a fillet surface.

4. The hermetically sealed cover of claim 1, wherein the at least one mating surface of the encapsulating component include alignment features selected from a group comprising interlocking protrusions and recesses, guide rails, guide ridges, reference notches, reference markers, integrally formed spacers,and combinations thereof, wherein each of the alignment features is configured to facilitate alignment of the encapsulating components prior to the welding.

5. The hermetically sealed cover of claim 1, further comprising at least one intermediate layer adjacent to the first surface of at least one encapsulating component, wherein the intermediate layer is selected from a group consisting of a thermally conductive layer, an electrically insulating layer, a vibration- dampening layer and a combination thereof.

6. The hermetically sealed cover of claim 1, further comprising at least one feedthrough member in at least one encapsulating component to facilitate electrical or optical communication between an interior portion of the hermetically sealed cover and an external environment, and wherein the feedthrough member is hermetically sealed to the encapsulating component.

7. The hermetically sealed cover of claim 6, wherein the feedthrough member is made of at least one of a metal, a diamond, or combinations thereof.

8. The hermetically sealed cover of claim 1, further comprising at least one strain- compensating interlayer disposed at an interface between the hermetically sealed cover and the feedthrough member and configured to mitigate thermal expansion mismatches, the strain-compensating interlayer is selected from a group consisting of TiC, MoC, and NbN.

9. The hermetically sealed cover of claim 1, wherein the second surface of the encapsulating component includes texturing, microstructures, micro-channels or nano structures to facilitate heat dissipation or reflection.

10. A method for creating a hermetically sealed cover for one or more electronic devices, the method comprising:obtaining at least two encapsulating components fabricated using a diamond deposition technique, each encapsulating component including: a first surface configured to face towards the one or more electronic devices; a second surface configured to face away from the one or more electronic devices; and at least one mating surface extending between the first surface and the second surface; assembling the one or more electronic devices between the at least two encapsulating components; and hermetically sealing the one or more electronic devices within the encapsulating components by sealably joining together the mating surfaces of the two or more encapsulating components via welding, wherein the welding is done by a laser source selected from a group consisting of a femtosecond laser, a picosecond laser, or a combination thereof.

11. The method of claim 10, wherein the encapsulating components are fabricated using the diamond deposition technique selected from a group consisting of chemical vapor deposition (CVD), High Pressure High Temperature (HPHT) technique, and combinations thereof.

12. The method of claim 10, wherein fabricating the encapsulating component includes: providing a support structure including a seed layer inside a CVD reactor, wherein the support structure is one of a mold or a template; forming one or more layers of diamonds on the seed layer by exposing the seed layer to a feed gas comprising of a mixture of gases in the CVD reactor and ionizing the feed gas to provide a reactive environment for promoting diamond growth; anddebonding the formed diamond layers from the support structure to form the encapsulating component.

13. The method of claim 12, wherein the feed gas is doped with at least one of boron, nitrogen, phosphorous and mixture thereof.

14. The method of claim 10, further comprising providing at least one feedthrough in at least one encapsulating component for providing electrical or optical communication between an interior portion of the hermetically sealed encapsulating cover and an external environment, wherein the feedthrough is provided by a method comprising: machining a cavity in the encapsulating cover; passing a feedthrough through the cavity so formed; providing a brazing alloy in the cavity with the feedthrough; and performing brazing in a vacuum or inert gas environment, such that the feedthrough is hermetically sealed to said encapsulating component.

15. The method of claim 14, further comprising deposing at least one strain- compensating interlayer selected from TiC, MoC, or NbN in an interface between the encapsulating component and the feedthrough.

16. The method of claim 10, wherein the femtosecond laser has at least one pulse width in the range from 50 femtoseconds to 500 femtoseconds and a pulse repetition rate in a range from 50 kHz to 10 MHz 17. The method of claim 10, wherein the picosecond laser has at least one pulse width in the range from 1 picosecond to 50 picoseconds and a pulse repetition rate of at least 50 kHz.

18. The method of claim 10, further comprising smoothening the mating surface of the encapsulating component prior to welding, by a process selected frompolishing, chemical-mechanical planarization (CMP), laser ablation and reactive plasma etching.

19. The method of claim 10, wherein the welding is carried out in a controlled atmosphere selected from a group consisting of a vacuum, a nitrogen atmosphere, and an argon atmosphere.

20. The method of claim 10, further comprising a second welding step that covers 50 % to 100% of the weld coupling the mating surfaces of the two or more encapsulating components.

21. The method of claim 10, further comprising forming at least one additional diamond layer over the welded together mating surfaces of the two or more encapsulating components.

22. The method of claim 10, wherein the hermetically sealed cover is cooled at a continuous cooling rate of 1°C to 10°C per minute.

23. The method of claim 22, wherein the cooling is carried out at in stages, wherein, in a first stage, the hermetically sealed encapsulation is cooled from 300°C to 150°C at a rate of 5°C per minute, and wherein, in a second stage, the hermetically sealed encapsulation is cooled from 150°C to room temperature at a rate of 2°C per min.

24. The method of claim 10, further comprising providing at least one intermediate layer between the electronic device and the first surface of at least one encapsulating component, wherein the intermediate layer is selected from a group consisting of a thermally conductive layer, an electrically insulating layer, a vibration-dampening layer and a combination thereof.

25. The method of claim 10, further comprising carrying out at reinforcing process after welding the mating surfaces of the at least two encapsulating components, the reinforcing process includes at least one of heat treatment, annealing or coating the second surface of the encapsulating components.

26. The method of claim 10, further comprising testing the hermetic sealed cover using a technique selected from a group consisting of helium leak detection, and high-resolution X-ray tomography.

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