Light detection device

Abstract

The present technology relates to a light detection device with which effects caused by flare can be reduced. The present invention comprises: pixels having a multiplication region for multiplying a carrier by means of a high electric field region; an inter-pixel separation part for separating one pixel from another adjacent pixel on a semiconductor substrate on which the pixels are formed; and lenses disposed on a light incident surface side of the pixels, the lenses being disposed so as to be shifted by a half pitch in an up-down direction or a left-right direction from an adjacent lens. The present technology can be applied to, for example, a single photon avalanche diode (SPAD) element, and an imaging device or distance measuring device including a SPAD element.

Description

Photodetector

[0001] The present technology relates to a light detection device, and more particularly to a light detection device that can detect light while suppressing the occurrence of flare and ghosts, for example.

[0002] Avalanche photodiodes (APDs) are available in two modes: Geiger mode, which operates at a bias voltage higher than the breakdown voltage, and linear mode, which operates at a bias voltage slightly higher than the breakdown voltage. Geiger mode avalanche photodiodes are also called single photon avalanche diodes (SPADs).

[0003] A SPAD is a device that can detect a single photon for each pixel by multiplying carriers generated by photoelectric conversion in a high-electric field PN junction region provided for each pixel (see, for example, Patent Document 1).

[0004] Japanese Patent Application Publication No. 2019-145702

[0005] When flare or ghosting occurs, the accuracy of light detection decreases, so measures to suppress the occurrence of flare or ghosting, or to reduce the effects of flare or ghosting if they do occur, have been desired.

[0006] The present technology has been made in view of such circumstances, and is intended to suppress the occurrence of flare and ghosting, or to reduce the effects thereof.

[0007] A first photodetector according to one aspect of the present technology is a photodetector including: a pixel having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separator that separates the pixel from another adjacent pixel on a semiconductor substrate on which the pixel is formed; and a lens arranged on the light incident surface side of the pixel, wherein the lenses are arranged with a half-pitch offset in the vertical or horizontal direction from adjacent lenses.

[0008] A second photodetector according to one aspect of the present technology is a photodetector including: a pixel having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separation section that separates the pixel from another adjacent pixel on a semiconductor substrate on which the pixel is formed; and a region in which a fine concave-convex shape is formed in a cross-sectional view, wherein, in a planar view, the concave or convex portion in the region is formed in a shape that is oblique to the inter-pixel separation section.

[0009] A third photodetector according to one aspect of the present technology is a photodetector including: a pixel having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separator that separates the pixel from another adjacent pixel on a semiconductor substrate on which the pixel is formed; a lens arranged on the light incident surface side of the pixel; and a light-shielding film arranged between the lenses and sized to separate the lenses.

[0010] According to a first aspect of the present technology, a photodetector includes a pixel having a multiplication region that multiplies carriers by a high electric field region, an inter-pixel separator that separates the pixel from an adjacent pixel on a semiconductor substrate on which the pixel is formed, and a lens disposed on a light incident surface side of the pixel, the lenses being shifted by half a pitch in the vertical or horizontal direction from adjacent lenses.

[0011] According to a second aspect of the present technology, a photodetector includes a pixel having a multiplication region that multiplies carriers by a high electric field region, an inter-pixel isolation portion that isolates the pixel from an adjacent pixel on a semiconductor substrate on which the pixel is formed, and a region in which a fine concave and convex shape is formed in a cross-sectional view, wherein the concave or convex portion in the region is formed in a shape that is oblique to the inter-pixel isolation portion in a plan view.

[0012] A third photodetector according to one aspect of the present technology includes a pixel having a multiplication region that multiplies carriers by a high electric field region, an inter-pixel separator that separates the pixel from adjacent pixels on a semiconductor substrate on which the pixel is formed, a lens arranged on the light incident surface side of the pixel, and a light-shielding film arranged between the lenses and sized to separate the lenses.

[0013] The photodetector may be an independent device or an internal block constituting a single device.

[0014] FIG. 1 is a diagram showing a cross-sectional configuration of an embodiment of a SPAD element to which the present technology is applied. FIG. 2 is a diagram for explaining a stacked structure of a SPAD element. FIG. 3 is a diagram showing an example of a planar configuration of a SPAD element. FIG. 4 is a diagram for explaining a stacked structure of a SPAD element in a second embodiment. FIG. 5 is a diagram showing an example of a planar configuration of a SPAD element in a third embodiment. FIG. 6 is a diagram showing an example of a planar configuration of a SPAD element in a fourth embodiment. FIG. 7 is a diagram showing an example of a planar configuration of a SPAD element in a fifth embodiment. FIG. 8 is a diagram showing an example of a planar configuration of a SPAD element in a sixth embodiment. FIG. 9 is a diagram showing an example of a planar configuration of a SPAD element in a seventh embodiment. FIG. 10 is a diagram showing an example of a cross-sectional configuration of a SPAD element in the eighth embodiment. FIG. 11 is a diagram showing an example of a cross-sectional configuration of a SPAD element in the ninth embodiment. FIG. 12 is a diagram showing an example of a cross-sectional configuration of a SPAD element in the ninth embodiment. FIG. 13 is a diagram showing an example of a cross-sectional configuration of a SPAD element in the ninth embodiment. It is a block diagram showing an example of a schematic configuration of a vehicle control system.It is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0015] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0016] The technology described below can be applied to photodetectors. Since it is particularly applicable to avalanche photodiodes (APDs), we will use APDs as an example. APDs operate in either Geiger mode, where they are operated at a bias voltage higher than the breakdown voltage, or in linear mode, where they are operated at a slightly higher bias voltage close to the breakdown voltage. Geiger-mode avalanche photodiodes are also called single-photon avalanche diodes (SPADs).

[0017] A SPAD is a device that can detect a single photon for each pixel by multiplying carriers generated by photoelectric conversion in a high-electric field PN junction region provided for each pixel.This technology can be more effective when applied to a SPAD, a type of APD, so the following explanation will use a SPAD as an example.

[0018] <Example of Cross-Sectional Configuration of SPAD> An example of the cross-sectional configuration of a SPAD element 11 formed on a sensor chip will be described with reference to Fig. 1. As shown in Fig. 1, the sensor chip has a layered structure in which a sensor substrate 31, a sensor-side wiring layer 32, and a logic circuit 33 are layered. The SPAD pixel circuit 21 has a configuration in which the sensor substrate 31 and the sensor-side wiring layer 32 are layered, and the SPAD element 11 has a configuration in which the SPAD pixel circuit 21 and the logic circuit 33 are layered.

[0019] The sensor substrate 31 is, for example, a semiconductor substrate obtained by thinly slicing single-crystal silicon, with a controlled p-type or n-type impurity concentration, and has the SPAD elements 11 formed thereon. In Fig. 1, the surface of the sensor substrate 31 facing upward is the light-receiving surface that receives light, and a sensor-side wiring layer 32 is laminated on the surface opposite the light-receiving surface.

[0020] The sensor side wiring layer 32 and the wiring layer of the logic circuit 33 are formed with wiring for supplying voltage to be applied to the SPAD element 11 and wiring for extracting electrons generated in the SPAD element 11 from the sensor substrate 31.

[0021] The SPAD element 11 is composed of an N-well 51, a P-type diffusion layer 52, an N-type diffusion layer 53, and a high-concentration P-type diffusion layer 54 formed on the sensor substrate 31. In the SPAD element 11, an avalanche multiplication region 55 is formed by a depletion layer formed in the region where the P-type diffusion layer 52 and the N-type diffusion layer 53 are connected.

[0022] The N-well 51 is formed by controlling the impurity concentration of the sensor substrate 31 to be n-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the SPAD element 11 to the avalanche multiplication region 55. Note that instead of the N-well 51, a P-well may be formed by controlling the impurity concentration of the sensor substrate 31 to be p-type.

[0023] The P-type diffusion layer 52 is a dense P-type diffusion layer (P+) formed near the surface of the sensor substrate 31 on the back side (upper side in Figure 1) of the N-type diffusion layer 53, and is formed so as to cover almost the entire surface of the SPAD element 11.

[0024] The N-type diffusion layer 53 is a dense N-type diffusion layer (N+) formed near the surface of the sensor substrate 31 and on the surface side (lower side in FIG. 1 ) of the P-type diffusion layer 52, and is formed in the center of the SPAD element 11. The N-type diffusion layer 53 may also be configured to be formed to have approximately the same size as the P-type diffusion layer 52. An electrode 56 (cathode electrode 56) is formed in the N-type diffusion layer 53 to connect to a contact electrode 71 that supplies a negative voltage to form the avalanche multiplication region 55.

[0025] The high-concentration P-type diffusion layer 54 is a high-concentration P-type diffusion layer (P++) formed in the vicinity of the surface of the sensor substrate 31 so as to surround the outer periphery of the N-well 51, and is used for connecting to a contact electrode 72 for electrically connecting to the anode of the SPAD element 11.

[0026] The avalanche multiplication region 55 is a high electric field region formed at the boundary surface between the P-type diffusion layer 52 and the N-type diffusion layer 53 by a large negative voltage applied to the N-type diffusion layer 53, and multiplies the electrons (e-) generated by one photon incident on the SPAD element 11.

[0027] In the sensor substrate 31, the SPAD elements 11 are insulated and separated from each other by inter-pixel separation sections 63 having a double structure made of a metal film 61 and an insulating film 62 formed between adjacent SPAD elements 11. For example, the inter-pixel separation sections 63 are formed so as to penetrate the sensor substrate 31 from its rear surface to its front surface.

[0028] The metal film 61 is a film made of a metal (for example, tungsten) that reflects light, and the insulating film 62 is a film having insulating properties such as SiO2. For example, the inter-pixel isolation portion 63 is formed by embedding the metal film 61 in the sensor substrate 31 so that the surface of the metal film 61 is covered with the insulating film 62, and the inter-pixel isolation portion 63 electrically and optically isolates adjacent SPAD elements 11.

[0029] An on-chip lens 34 is formed on the light incident surface side of the N well 51. A light-shielding film 64 is formed between the SPAD elements 11 on the on-chip lens 34 side of the inter-pixel isolation portion 63. The light-shielding film 64 is provided between the SPAD elements 11 so as to prevent light incident via the on-chip lens 34 from leaking into adjacent SPAD elements 11. The light-shielding film 64 can be formed from the same material as the metal film 61.

[0030] The contact electrode 71 (cathode electrode 56 ) of the sensor-side wiring layer 32 is connected to a metal wiring 74 , and the contact electrode 72 (anode electrode) is connected to a metal wiring 75 .

[0031] A recessed region 57 having a fine uneven structure for scattering incident light is provided on the light incident surface side of the N well 51. The incident light is scattered by the recessed region 57, thereby extending the optical path length and enabling more light to be trapped in the N well 51, thereby improving sensitivity.

[0032] A convex region 58 having a fine uneven structure is also provided on the surface of the N well 51 opposite to the light incident surface (the surface on the sensor-side wiring layer 32 side). Of the incident light, some reaches the bottom surface of the N well 51 and escapes to the sensor-side wiring layer 32 side. By forming the convex region 58 on the wiring layer side, the light that reaches the wiring layer side can be reflected by the convex region 58 and returned to the N well 51. This makes it possible to increase the amount of light that can be trapped in the photoelectric conversion region.

[0033] As shown in FIG. 1, the configuration may include both the recessed region 57 and the raised region 58, or may include only one of the recessed region 57 or the raised region 58, or may include neither the recessed region 57 nor the raised region 58.

[0034] <Stacked Structure of SPAD Pixels and Logic Circuits> Fig. 2 is a diagram for explaining the stacked structure of the SPAD pixel circuits 21 and the logic circuit 33. In Fig. 2, the stacked structure will be explained using as an example four SPAD pixel circuits 21 (2 x 2) out of the SPAD pixel circuits 21 arranged in an array in the pixel array section.

[0035] The logic circuits 33-1 to 33-4 are each rectangular. The SPAD pixel circuits 21-1 to 21-4 are each rectangular. The logic circuits 33 and the SPAD pixel circuits 21 are formed to have approximately the same shape and approximately the same size.

[0036] The SPAD element 11 has a configuration in which the SPAD pixel circuit 21 is stacked on the logic circuit 33, and the logic circuit 33 and the SPAD pixel circuit 21 are electrically connected.

[0037] <Arrangement of Recessed Regions> Fig. 3 is a diagram showing an example of the planar configuration of four SPAD pixel circuits 21 in a 2 × 2 arrangement. Fig. 3 mainly shows the surface on which the recessed regions 57 are arranged. The SPAD pixel circuits 21 are separated by inter-pixel separation portions 63. An on-chip lens 34 is arranged above each SPAD pixel circuit 21 so as to cover it.

[0038] When viewed from above, each recess in the recessed region 57 is formed in a quadrangular shape. When viewed in cross section, as shown in Fig. 1, each recess in the recessed region 57 is formed in a triangular shape. When viewed three-dimensionally, each recess in the recessed region 57 is formed in a quadrangular pyramid shape. Note that each recess may also be formed in a rectangular parallelepiped shape.

[0039] 3, each recess in recess region 57 is formed in the same direction as inter-pixel separation portions 63. The horizontal sides of each rectangular recess in recess region 57 are parallel to inter-pixel separation portions 63 arranged in the horizontal direction, and the vertical sides of each recess are parallel to inter-pixel separation portions 63 arranged in the vertical direction.

[0040] <Arrangement of Convex Regions> Fig. 4 is a diagram showing an example of the planar configuration of four 2 x 2 SPAD pixel circuits 21. Fig. 4 mainly illustrates the surface on which the convex regions 58 are arranged. A cathode electrode 56 is arranged in the center of each SPAD pixel circuit 21, and an N-type diffusion layer 53 is formed around the cathode electrode 56.

[0041] When viewed from above, each convex portion of the convex region 58 is formed in a quadrangular shape. When viewed in cross section, as shown in Fig. 1, each convex portion of the convex region 58 is formed in a quadrangular shape. When viewed three-dimensionally, each convex portion of the convex region 58 is formed in a rectangular parallelepiped shape. Note that each convex portion may also be formed in a quadrangular pyramid shape.

[0042] 4, each convex portion of the convex region 58 is formed in the same direction as the inter-pixel separation portions 63. The horizontal sides of each rectangular convex portion of the convex region 58 are positioned parallel to the inter-pixel separation portions 63 arranged in the horizontal direction, and the vertical sides of each convex portion are positioned parallel to the inter-pixel separation portions 63 arranged in the vertical direction.

[0043] 2 to 4, the SPAD pixel circuits 21 are arranged in a square. Because the SPAD pixel circuits 21 are arranged in a square, flare tends to propagate in the vertical and horizontal directions, and the flare may degrade the performance of the imaging device including the SPAD elements 11. If the imaging device is a distance measurement device, the distance measurement performance may degrade.

[0044] An imaging device (range-finding device) having a pixel array section in which SPAD elements 11 are arranged in a matrix can be applied to a line-scan type LIDAR (Laser Imaging Detection and Ranging).

[0045] Line-scan LIDAR scans a one-dimensional laser beam extending horizontally in the vertical direction to obtain a two-dimensional image. Because of this type of scanning, if flare runs horizontally, it can cause mixed signals, which can degrade ranging performance. Similarly, in line-scan LIDAR that is configured to scan a one-dimensional laser beam extending vertically in the left-right direction, if flare runs vertically, it can cause mixed signals, which can degrade ranging performance.

[0046] In such line-scan LIDARs, by making the flare extend outside the laser irradiation area, it is possible to prevent degradation of distance measurement performance.

[0047] The following will explain the configuration of the SPAD element 11 that suppresses the occurrence of flare in the vertical and horizontal directions.

[0048] <Second embodiment> Figure 5 is a diagram for explaining the configuration of a SPAD element 11b in a second embodiment. In the following explanation, parts that are the same as those in the SPAD element 11 in the first embodiment explained with reference to Figures 1 to 4 (hereinafter, the SPAD element 11 in the first embodiment will be referred to as SPAD element 11a) will be given the same reference numerals, and explanations thereof will be omitted as appropriate.

[0049] 5 is a diagram for explaining the stacked structure of the SPAD pixel circuits 21b and the logic circuit 33, as in the case explained with reference to Fig. 2. As in Fig. 2, Fig. 5 explains the stacked structure using an example of four SPAD elements 11 arranged in a 2 × 2 array in the pixel array section.

[0050] The logic circuits 33-1 to 33-4 are each rectangular. The SPAD pixel circuits 21b-1 to 21b-4 are each rectangular. The logic circuit 33 and the SPAD pixel circuit 21b are formed to have approximately the same shape and approximately the same size. This is the same as the case shown in FIG. 2.

[0051] The SPAD pixel circuits 21b in the second embodiment are arranged with a half-pitch offset. The SPAD pixel circuit 21b-2, which is arranged to the right of the SPAD pixel circuit 21b-1, is arranged at a position offset by half a pitch in the upward direction. Similarly, the SPAD pixel circuit 21b-4, which is arranged to the right of the SPAD pixel circuit 21b-3, is arranged at a position offset by half a pitch in the upward direction. In this way, SPAD pixel circuits 21b adjacent in the horizontal direction are arranged at positions offset by half a pitch in the vertical direction.

[0052] The logic circuits 33 are arranged without any misalignment, as shown in the left diagram of Fig. 5. When such logic circuits 33 and SPAD pixel circuits 21 are stacked, as shown in the right diagram of Fig. 5, the SPAD pixel circuit 21b-1 is arranged without any misalignment above the logic circuit 33-1, but the SPAD pixel circuit 21b-2 is arranged above the logic circuit 33-2 at a position misaligned by half a pitch in the vertical direction relative to the logic circuit 33-2.

[0053] In Figure 5, an example is shown in which the logic circuits 33 are arranged without any offset (square arrangement), but like the SPAD pixel circuits 21b, the logic circuits 33 may also be configured so that adjacent logic circuits 33 in the left and right direction are arranged at positions offset by half a pitch in the up and down direction.

[0054] When the SPAD pixel circuits 21b are arranged with a misalignment in this way, the on-chip lenses 34 are also arranged at misaligned positions, as shown in Figure 6. Figure 6 shows seven SPAD pixel circuits 21, SPAD pixel circuits 21b-1 to 21b-7. The on-chip lens 34b-2 arranged on the SPAD pixel circuit 21b-2 is arranged at a position that is misaligned by half a pitch upward from the on-chip lens 34b-1 arranged on the SPAD pixel circuit 21b-1. The on-chip lens 34b-3 arranged on the SPAD pixel circuit 21b-3 is arranged at a position that is misaligned by half a pitch downward from the on-chip lens 34b-2 arranged on the SPAD pixel circuit 21b-2.

[0055] The on-chip lens 34b-5 arranged on the SPAD pixel circuit 21b-5 is positioned at a half pitch upward shift relative to the on-chip lens 34b-4 arranged on the SPAD pixel circuit 21b-4. The on-chip lens 34b-6 arranged on the SPAD pixel circuit 21b-6 is positioned at a half pitch downward relative to the on-chip lens 34b-5 arranged on the SPAD pixel circuit 21b-5.

[0056] The on-chip lens 34b-7 arranged on the SPAD pixel circuit 21b-7 is shifted downward by half a pitch from the on-chip lens 34b-4 arranged on the SPAD pixel circuit 21b-4. The on-chip lens 34b-6 arranged on the SPAD pixel circuit 21b-6 is shifted upward by half a pitch from the on-chip lens 34b-7 arranged on the SPAD pixel circuit 21b-7.

[0057] In this way, by disposing the SPAD pixel circuits 21b adjacent to each other in the horizontal direction so that they are shifted by half a pitch in the vertical direction, the on-chip lenses 34b arranged to cover the SPAD pixel circuits 21b are also shifted by half a pitch in the vertical direction. By arranging the on-chip lenses 34b in an oblique structure in this way, it is possible to suppress flare from running in the horizontal and vertical directions.

[0058] For example, if an imaging device including the SPAD element 11b is applied to a LIDAR that scans a one-dimensional laser extending horizontally in an up-and-down direction, flare that occurs horizontally can be suppressed, the effect of flare on the SPAD element 11 on the scanning line can be reduced, and a decrease in ranging accuracy can be prevented.

[0059] 5 and 6 have been described as an example in which adjacent SPAD pixel circuits 21b in the left-right direction are arranged with a half-pitch offset in the up-down direction, but a configuration in which adjacent SPAD pixel circuits 21b in the up-down direction are arranged with a half-pitch offset in the left-right direction is also possible. Referring to Fig. 7, a description will now be given of a case in which adjacent SPAD pixel circuits 21b in the up-down direction are arranged with a half-pitch offset in the left-right direction.

[0060] 7, the SPAD pixel circuit 21b-3 is disposed below the SPAD pixel circuit 21b-1 and shifted half a pitch to the left. The on-chip lens 34b-3 disposed on the SPAD pixel circuit 21b-3 is disposed leftwardly and shifted half a pitch to the left relative to the on-chip lens 34b-1 disposed on the SPAD pixel circuit 21b-1. The SPAD pixel circuit 21b-6 is disposed below the SPAD pixel circuit 21b-3 and shifted half a pitch to the right relative to the SPAD pixel circuit 21b-3. The on-chip lens 34b-6 disposed on the SPAD pixel circuit 21b-6 is disposed rightwardly and shifted half a pitch to the right relative to the on-chip lens 34b-3 disposed on the SPAD pixel circuit 21b-3.

[0061] Relative to the SPAD pixel circuit 21b-2, the SPAD pixel circuit 21b-4 is disposed below the SPAD pixel circuit 21b-2 and shifted by half a pitch to the left. Relative to the on-chip lens 34b-2 disposed on the SPAD pixel circuit 21b-2, the on-chip lens 34b-4 disposed on the SPAD pixel circuit 21b-4 is shifted by half a pitch to the left. Relative to the SPAD pixel circuit 21b-4, the SPAD pixel circuit 21b-7 is disposed below the SPAD pixel circuit 21b-4 and shifted by half a pitch to the right. Relative to the on-chip lens 34b-4 disposed on the SPAD pixel circuit 21b-4, the on-chip lens 34b-7 disposed on the SPAD pixel circuit 21b-7 is shifted by half a pitch to the right.

[0062] The SPAD pixel circuit 21b-5 is disposed below the SPAD pixel circuit 21b-2 and shifted by half a pitch to the right. The on-chip lens 34b-5 disposed on the SPAD pixel circuit 21b-5 is disposed by half a pitch to the right relative to the on-chip lens 34b-2 disposed on the SPAD pixel circuit 21b-2.

[0063] In this way, by arranging the SPAD pixel circuits 21b adjacent to each other in the vertical direction with a half pitch offset in the horizontal direction, the on-chip lenses 34b arranged to cover the SPAD pixel circuits 21b are also arranged with a half pitch offset in the horizontal direction. By arranging the on-chip lenses 34b in an oblique structure in this way, it is possible to suppress flare from running in the horizontal and vertical directions.

[0064] For example, if an imaging device including the SPAD element 11b is applied to a LIDAR that scans a one-dimensional laser extending vertically in the left-right direction, flare that occurs vertically can be suppressed, the effect of flare on the SPAD element 11 on the scanning line can be reduced, and a decrease in ranging accuracy can be prevented.

[0065] It is also possible to combine the second embodiment with the first embodiment. For example, in the second embodiment, the arrangement of the SPAD pixel circuits 21b and the arrangement of the on-chip lenses 34b arranged on the SPAD pixel circuits 21b have been described, but the configurations of the recessed regions 57 and the protruding regions 58 can be the same as those of the recessed regions 57 and the protruding regions 58 in the first embodiment described with reference to FIGS. 3 and 4.

[0066] <Third embodiment> Fig. 8 is a diagram for explaining the configuration of a SPAD element 11c according to a third embodiment. Like Fig. 3, Fig. 8 is a diagram showing an example of the planar configuration of four SPAD pixel circuits 21c in a 2 × 2 arrangement, and illustrates the surface on which the recessed region 57 is arranged and the on-chip lens 34.

[0067] The SPAD element 11c in the third embodiment differs from the SPAD elements 11a and 11b in the first and second embodiments in that the SPAD element 11c is configured by rotating the SPAD element 11a shown in Figure 3 at an angle of 45 degrees, but is otherwise similar.

[0068] Since the SPAD element 11c is arranged obliquely, the recesses of the recessed region 57 and the protrusions of the protrusion region 58 formed in the SPAD pixel circuit 21c are also arranged obliquely.

[0069] An oblique arrangement is, for example, when the substrate including the pixel array section on which the SPAD element 11c is formed is rectangular, and the sides of the substrate and the sides of the SPAD element 11c are not parallel to each other, in this case forming an angle of 45 degrees.

[0070] Note that the numerical value such as 45 degrees is an example and is not a description that indicates limitation. In the following description, the numerical values ​​are also an example and are not a description that indicates limitation, so other numerical values ​​are also within the scope of application of the present technology.

[0071] In this way, by arranging the SPAD element 11c so that it is rotated at an angle of 45 degrees, it is possible to disperse the generated flare in an oblique direction, and it is possible to suppress flare that runs in the vertical and horizontal directions.

[0072] The third embodiment can also be implemented in combination with the first embodiment and / or the second embodiment.

[0073] 9 is a diagram for explaining the configuration of a SPAD element 11d according to a fourth embodiment. Like Fig. 3, Fig. 9 is a diagram showing an example of the planar configuration of four SPAD pixel circuits 21d arranged in a 2 × 2 array in a pixel array section, and illustrates the surface on which the recessed region 57d is arranged and the on-chip lens 34.

[0074] 9, each recess in recess region 57d is formed in a direction oblique to inter-pixel separation portion 63. The sides of each rectangular recess in recess region 57 are positioned such that they form an angle of approximately 45 degrees with inter-pixel separation portion 63 arranged in the horizontal direction and inter-pixel separation portion 63 arranged in the vertical direction.

[0075] In this way, by arranging the recessed region 57d included in the SPAD element 11d so that it is rotated at an angle of 45 degrees, the flare that occurs can be dispersed in an oblique direction, and flare that runs in all directions can be suppressed.

[0076] The fourth embodiment can also be implemented in combination with any one or more of the first to third embodiments.

[0077] Fifth Embodiment Fig. 10 is a diagram for explaining the configuration of a SPAD element 11d according to a fifth embodiment. Fig. 9, like Fig. 3, is a diagram showing an example of the planar configuration of four SPAD pixel circuits 21e in a 2 × 2 array arranged in a pixel array section, and illustrates the surface on which the convex region 58e is arranged and the on-chip lens 34.

[0078] 9, each convex portion of convex region 58e is formed in a direction oblique to inter-pixel separation portions 63. The sides of each rectangular convex portion of convex region 58e are positioned such that they form an angle of approximately 45 degrees with inter-pixel separation portions 63 arranged in the horizontal direction and inter-pixel separation portions 63 arranged in the vertical direction.

[0079] In this way, by arranging the convex region 58e included in the SPAD element 11d so that it is rotated at an angle of 45 degrees, the flare that occurs can be dispersed in an oblique direction, and flare that runs in all directions can be suppressed.

[0080] The fifth embodiment can also be implemented in combination with any one or more of the first to fourth embodiments.

[0081] Sixth Embodiment Fig. 11 is a diagram for explaining the configuration of a SPAD element 11f according to a sixth embodiment. Like Fig. 3, Fig. 11 is a diagram showing an example of the planar configuration of four SPAD pixel circuits 21f in a 2 × 2 arrangement, and illustrates the surface on which recessed regions 57f are arranged and on-chip lenses 34f.

[0082] In the example shown in FIG. 11, the on-chip lenses 34f provided on the SPAD pixel circuit 21f are arranged in a zigzag pattern, which is different from the SPAD element 11a in the first embodiment, but other points are the same.

[0083] The SPAD pixel circuit 21f-1 is covered with an on-chip lens 34f-1, and the SPAD pixel circuit 21f-3 is covered with an on-chip lens 34f-3. The upper half of the SPAD pixel circuit 21f-2 is covered with an on-chip lens 34f-2, and the lower half of the SPAD pixel circuit 21f-2 is covered with an on-chip lens 34f-4. The upper half of the SPAD pixel circuit 21f-4 is covered with an on-chip lens 34f-4, and the lower half of the SPAD pixel circuit 21f-4 is covered with an on-chip lens 34f-5.

[0084] With respect to the on-chip lens 34b-1 arranged on the SPAD pixel circuit 21f-1, the on-chip lens 34f-2 arranged on the SPAD pixel circuit 21f-2 is arranged at a position shifted by half a pitch upward, and the on-chip lens 34f-4 is arranged at a position shifted by half a pitch downward. With respect to the on-chip lens 34f-3 arranged on the SPAD pixel circuit 21f-3, the on-chip lens 34f-4 arranged on the SPAD pixel circuit 21f-4 is arranged at a position shifted by half a pitch upward, and the on-chip lens 34f-5 is arranged at a position shifted by half a pitch downward.

[0085] In this way, by disposing the on-chip lenses 34f arranged on the SPAD pixel circuits 21f adjacent in the left-right direction so as to be shifted by half a pitch in the up-down direction, it is possible to suppress flare from running in the left-right and up-down directions.

[0086] The sixth embodiment can also be implemented in combination with any one or more of the first to fifth embodiments.

[0087] Seventh Embodiment Fig. 12 is a diagram for explaining the configuration of a SPAD element 11g according to a seventh embodiment. Like Fig. 3, Fig. 12 is a diagram showing an example of the planar configuration of four SPAD pixel circuits 21g in a 2 × 2 arrangement, and illustrates the surface on which the recessed region 57 is arranged and the on-chip lens 34g.

[0088] The example shown in Figure 12 differs from the SPAD element 11a in the first embodiment in that multiple small on-chip lenses 34g are arranged in a zigzag pattern on one SPAD pixel circuit 21g, but is otherwise similar.

[0089] The arrangement of the on-chip lenses 34g will be described using the SPAD pixel circuit 21g-1 as an example. Ten on-chip lenses 34g, 34g-1 to 34g-10, are arranged on the SPAD pixel circuit 21g-1.

[0090] The on-chip lenses 34g-1 to 34g-3 are arranged horizontally above the SPAD pixel circuit 21g-1. The on-chip lenses 34g-4 to 34g-7 are arranged horizontally in the center of the SPAD pixel circuit 21g-1. The on-chip lenses 34g-4 to 34g-7 are arranged at positions shifted by half a pitch in the horizontal direction from the on-chip lenses 34g-1 to 34g-3. For example, the on-chip lens 34g-4 is arranged at a position shifted by half a pitch to the left of the on-chip lens 34g-1.

[0091] The on-chip lenses 34g-8 to 34g-10 are arranged side by side below the SPAD pixel circuit 21g-1. The on-chip lenses 34g-8 to 34g-10 are arranged at positions shifted by half a pitch in the horizontal direction from the on-chip lenses 34g-4 to 34g-7. For example, the on-chip lens 34g-8 is arranged at a position shifted by half a pitch to the right of the on-chip lens 34g-4.

[0092] In the SPAD pixel circuit 21f in the sixth embodiment described with reference to FIG. 11, for example, the SPAD pixel circuit 21f-2 has portions that are not covered by the on-chip lens 34f-2 and the on-chip lens 34f-4, and therefore the light-collecting ability may be reduced compared to the SPAD pixel circuit 21f-1, which is entirely covered by the on-chip lens 34f-1.

[0093] In the SPAD pixel circuit 21g according to the seventh embodiment described with reference to Fig. 12, the area not covered by the on-chip lens 34g is smaller than the area not covered by the on-chip lens 34f in the SPAD pixel circuit 21f shown in Fig. 11. Furthermore, in the SPAD pixel circuits 21g according to the seventh embodiment described with reference to Fig. 12, the area not covered by the on-chip lens 34g is the same size for each SPAD pixel circuit 21g, which prevents differences in light-collecting ability from occurring.

[0094] In this way, by arranging a plurality of small on-chip lenses 34g on one SPAD pixel circuit 21g with a half-pitch offset in the left-right direction, it is possible to suppress flare from running in the left-right and up-down directions.

[0095] Although not shown in the figure, it is also possible to arrange multiple small on-chip lenses 34g on one SPAD pixel circuit 21g with a half-pitch offset in the vertical direction, and even in such a configuration, it is possible to suppress flare from running in the left-right and up-down directions.

[0096] The seventh embodiment can also be implemented in combination with any one or more of the first to sixth embodiments.

[0097] Eighth Embodiment Fig. 13 is a diagram showing an example of a cross-sectional configuration of a SPAD element 11h according to an eighth embodiment, and Fig. 14 is a diagram showing an example of a planar configuration. In the SPAD element 11h according to the eighth embodiment, parts that are the same as those in the SPAD element 11a according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0098] The SPAD element 11h shown in Figure 13 differs from the SPAD element 11a in the first embodiment shown in Figure 1 in that the light-shielding film 64h formed between the SPAD elements 11h is formed on the on-chip lens 34, but is otherwise similar.

[0099] 13, a light-shielding film 64h is provided between the on-chip lenses 34. Referring to the planar configuration example shown in Fig. 14, the light-shielding film 64h is formed between the SPAD pixel circuits 21 and between the on-chip lenses 34. The light-shielding film 64h is formed on the raised portion of the on-chip lens 34, and is formed to a size that separates the on-chip lens 34 from the interface between the SPAD pixel circuit 21h and the on-chip lens 34.

[0100] By disposing the light-shielding film 64h between the on-chip lenses 34, flare propagating inside the on-chip lenses 34 can be suppressed.

[0101] The eighth embodiment can also be implemented in combination with any one or more of the first to seventh embodiments.

[0102] 15 is a diagram showing an example of a cross-sectional configuration of a SPAD element 11i according to a ninth embodiment, and FIG. 16 is a diagram showing an example of a planar configuration. In the SPAD element 11i according to the ninth embodiment, parts that are the same as those in the SPAD element 11a according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0103] The SPAD element 11i shown in Figure 15 differs from the SPAD element 11a in the first embodiment shown in Figure 1 in that a light-shielding film 64i and a light absorption layer 101 are formed between the SPAD elements 11h and the on-chip lenses 34, but is otherwise similar.

[0104] 15, a light-shielding film 64i is provided between the on-chip lenses 34, and a light-absorbing layer 101 is provided on the light incident side of the light-shielding film 64i. Referring to the planar configuration example shown in Fig. 16, the light-shielding film 64i and the light-absorbing layer 101 are formed between the SPAD pixel circuits 21, between the on-chip lenses 34, and in the raised portions of the on-chip lenses 34.

[0105] The light-shielding film 64i can be made of metal. If the light-shielding film 64i is made of metal, there is a possibility that light will be reflected by the light-shielding film 64i. In order to suppress this reflection, a light-absorbing layer 101 made of a material that absorbs light, such as an organic material, is laminated on the light-shielding film 64i.

[0106] By disposing the light-shielding film 64i and the light-absorbing layer 101 between the on-chip lenses 34, it is possible to suppress flare propagating inside the on-chip lenses 34 and flare due to reflection of incident light.

[0107] The ninth embodiment can also be implemented in combination with any one or more of the first to eighth embodiments.

[0108] 17 is a diagram showing an example of a cross-sectional configuration of a SPAD element 11j according to a tenth embodiment. In the SPAD element 11j according to the tenth embodiment, parts that are the same as those in the SPAD element 11a according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0109] The SPAD element 11j shown in Figure 17 differs from the SPAD element 11a in the first embodiment shown in Figure 1 in that an anti-reflection film 111 is provided in the sensor side wiring layer 32 of the SPAD element 11j, but is otherwise similar.

[0110] 17, an anti-reflection film 111 is provided in the sensor-side wiring layer 32 that constitutes the SPAD pixel circuit 21. The anti-reflection film 111 is formed of, for example, an organic material or metal that has the function of absorbing light, and has the function of absorbing reflected components that are not absorbed by the sensor substrate 31 (silicon substrate) and suppressing reflection.

[0111] By providing the anti-reflection film 111, flare caused by reflected components not absorbed by the sensor substrate 31 can be suppressed.

[0112] The tenth embodiment can also be implemented in combination with any one or more of the first to ninth embodiments.

[0113] 18 is a diagram showing an example of a cross-sectional configuration of a SPAD element 11k according to an eleventh embodiment. In the SPAD element 11k according to the eleventh embodiment, parts that are the same as those in the SPAD element 11a according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0114] The SPAD element 11k shown in Figure 18 differs from the SPAD element 11a in the first embodiment shown in Figure 1 in that the on-chip lens 34k arranged on the SPAD pixel circuit 21k is configured as a gapless lens, but is similar in other respects.

[0115] Referring again to the SPAD element 11a shown in FIG. 1, the on-chip lens 34 of the SPAD element 11a has a structure with a raised portion. The raised portion is a rectangular portion in cross section that exists from the interface between the SPAD pixel circuit 21 and the on-chip lens 34 to the point where the surface of the on-chip lens 34 becomes curved. In the SPAD element 11a shown in FIG. 1, the light-shielding film 64 is formed on the raised portion of the on-chip lens 34. There is a possibility that light will leak in from this raised portion, causing flare.

[0116] The on-chip lens 34k shown in Fig. 18 is an elliptical lens without a raised portion (a structure in which the raised portion is minimized as much as possible). Here, an on-chip lens 34 without a raised portion is referred to as a gapless lens. By using an on-chip lens 34k with such a shape, it is possible to minimize light leakage and prevent flare from worsening.

[0117] The eleventh embodiment may be implemented in combination with any one or more of the first to tenth embodiments.

[0118] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0119] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0120] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0121] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0122] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0123] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0124] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0125] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0126] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0127] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0128] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0129] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0130] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0131] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0132] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0133] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0134] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0135] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0136] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0137] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0138] In this specification, a system refers to an entire device made up of multiple devices.

[0139] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0140] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0141] The present technology can also be configured as follows. (1) A photodetector including a pixel having a multiplication region that multiplies carriers by a high electric field region, an inter-pixel separator that separates the pixel from adjacent pixels on a semiconductor substrate on which the pixel is formed, and a lens arranged on a light incident surface side of the pixel, wherein the lenses are arranged such that adjacent lenses are shifted by a half pitch in the vertical or horizontal direction. (2) The photodetector according to (1), wherein the pixels are arranged such that adjacent pixels are shifted by a half pitch in the vertical or horizontal direction. (3) The photodetector according to (1) or (2), wherein the lenses that are adjacent in the horizontal direction are shifted by a half pitch in the vertical direction, or the lenses that are adjacent in the vertical direction are shifted by a half pitch in the horizontal direction. (4) The photodetector according to any one of (1) to (3), wherein a plurality of the lenses are arranged in one pixel, and adjacent lenses in the horizontal direction among the plurality of lenses are arranged with a half pitch offset in the vertical direction, or adjacent lenses in the vertical direction are arranged with a half pitch offset in the horizontal direction. (5) The photodetector according to any one of (1) to (3), comprising: a pixel having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separation section that separates adjacent pixels in a semiconductor substrate on which the pixel is formed; and a region in which a fine uneven shape is formed in a cross-sectional view, wherein, in a plan view, recesses or protrusions in the region are formed in a shape that is oblique to the inter-pixel separation section. (6) The photodetector according to (5), wherein the region has a plurality of recesses on the light incident surface side of the pixel, and, in a plan view, the recesses are formed in a shape that is oblique to the inter-pixel separation section. (7) The photodetector according to (5) or (6), wherein the region has a plurality of convex portions on the wiring layer side of the pixel, and the convex portions are formed in a shape that is oblique to the inter-pixel separation portion in a plan view. (8) The photodetector according to any one of (5) to (7), wherein the concave portion or the convex portion is in a quadrangular pyramid shape.(9) A photodetector comprising: a pixel having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separator that separates the pixel from another adjacent pixel on a semiconductor substrate on which the pixel is formed; a lens arranged on the light incident surface side of the pixel; and a light-shielding film arranged between the lenses and having a size that separates the lenses. (10) The photodetector according to (9), in which a light-absorbing layer made of a material that absorbs light is stacked on the light incident side of the light-shielding film. (11) The photodetector according to (9) or (10), further comprising an anti-reflection film that prevents reflection of light that has transmitted through the semiconductor substrate, in a wiring layer stacked on the semiconductor substrate. (12) The photodetector according to any of (9) to (11), in which the lens has an elliptical shape and is structured so that there is no raised portion between the semiconductor substrate and the lens.

[0142] REFERENCE SIGNS LIST 11 SPAD element, 21 SPAD pixel circuit, 31 sensor substrate, 32 sensor-side wiring layer, 33 logic circuit, 34 on-chip lens, 51 N-well, 52 P-type diffusion layer, 53 N-type diffusion layer, 54 high-concentration P-type diffusion layer, 55 avalanche multiplication region, 56 cathode electrode, 57 recessed region, 58 raised region, 61 metal film, 62 insulating film, 63 inter-pixel isolation portion, 64 light-shielding film, 71 contact electrode, 72 contact electrode, 74 metal wiring, 75 metal wiring, 101 light-absorbing layer, 111 light-absorbing layer

Claims

1. A photodetector comprising: pixels each having a multiplication region that multiplies carriers by a high electric field region; inter-pixel separators that separate the pixels from adjacent pixels on a semiconductor substrate on which the pixels are formed; and lenses arranged on the light incident surface side of the pixels, wherein the lenses are arranged such that adjacent lenses are offset by half a pitch in the vertical or horizontal direction.

2. The photodetector according to claim 1, wherein the pixels are arranged such that adjacent pixels are shifted by half a pitch in the vertical or horizontal direction.

3. The optical detection device according to claim 1, wherein the lenses adjacent in the horizontal direction are arranged with a half pitch offset in the vertical direction, or the lenses adjacent in the vertical direction are arranged with a half pitch offset in the horizontal direction.

4. The photodetector device according to claim 1, wherein a plurality of lenses are arranged in one pixel, and adjacent lenses in the horizontal direction are arranged with a half-pitch offset in the vertical direction, or adjacent lenses in the vertical direction are arranged with a half-pitch offset in the horizontal direction.

5. A photodetector comprising: pixels each having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separation section that separates each pixel from adjacent pixels on a semiconductor substrate on which the pixels are formed; and a region in which a fine concave-convex shape is formed in a cross-sectional view, wherein, in a plan view, the concave or convex portions in the region are formed in a shape that is oblique to the inter-pixel separation section.

6. The photodetector according to claim 5, wherein the region has a plurality of recesses on the light incident surface side of the pixel, and the recesses are formed in a shape that is oblique to the inter-pixel separation portion in a plan view.

7. The photodetector according to claim 5, wherein the region has a plurality of convex portions on the wiring layer side of the pixel, and the convex portions are formed in a shape that is oblique to the inter-pixel separation portion in a plan view.

8. The light detection device according to claim 5, wherein the recess or the protrusion has a quadrangular pyramid shape.

9. A photodetector comprising: a pixel having a multiplication region that multiplies carriers by a high electric field region; an inter-pixel separator that separates the pixel from adjacent pixels on a semiconductor substrate on which the pixel is formed; a lens arranged on the light incident surface side of the pixel; and a light-shielding film arranged between the lenses and sized to separate the lenses.

10. The photodetector according to claim 9, wherein a light absorbing layer made of a material that absorbs light is laminated on the light incident side of the light blocking film.

11. The photodetector according to claim 9, further comprising an anti-reflection film formed in a wiring layer stacked on the semiconductor substrate, for preventing reflection of light transmitted through the semiconductor substrate.

12. The photodetector according to claim 9, wherein the lens has an elliptical shape and is structured so that there is no raised portion between the semiconductor substrate and the lens.

Images