Smart IC substrate, smart IC module, and IC card comprising same

Abstract

A smart IC substrate according to an embodiment comprises: a substrate including an upper surface and the other surface opposite to one surface; a first adhesive layer disposed on the one surface of the substrate; a second adhesive layer disposed on the other surface of the substrate; a first conductive pattern part attached to the first adhesive layer on the one surface of the substrate; and a second conductive pattern part attached to the second adhesive layer on the other surface of the substrate, wherein the thickness of the first adhesive layer and the thickness of the second adhesive layer are different, and the thickness of the first conductive pattern part and the thickness of the second conductive pattern part are different.

Description

Smart IC substrate, smart IC module and IC card including the same

[0001] The embodiments relate to a smart IC substrate, a smart IC module, and an IC card including the same.

[0002] An IC card is a plastic card with an integrated circuit chip capable of storing and processing information. An IC card contains an IC chip that stores the necessary information and transmits this information to a reader in the form of an electrical signal. These IC cards are manufactured by inserting a smart IC module into the card body.

[0003] Smart IC modules are classified into single and dual types depending on the arrangement of the metal layers. The single type has the metal and plating layers arranged on only one side of the substrate. The dual type has the metal and plating layers arranged on both sides of the substrate.

[0004] Additionally, smart IC modules are categorized into contact, contactless, hybrid, and combi cards, depending on how the card is used. Contact cards transmit and receive information through physical contact. Contactless cards transmit and receive information without physical contact. Furthermore, hybrid and combi cards incorporate both contact and contactless functions.

[0005] Contact-type smart IC modules transmit and receive information through physical contact. Contactless smart IC modules use wireless communication capabilities (e.g., Near Field Communication (NFC)) to transmit and receive information without physical contact. Combi-type smart IC modules and hybrid smart IC modules incorporate both physical contact and contactless wireless communication capabilities.

[0006] Meanwhile, combination or hybrid IC cards offering wireless communication capabilities are increasingly being used. To implement wireless communication capabilities in IC cards, signal exchange between the card module and the smart IC module is required. To achieve this, the card module and smart IC module can be equipped with antenna patterns, enabling information exchange via wireless communication.

[0007] Additionally, in order to provide wireless communication functionality, the smart IC substrate may be provided with an antenna pad connected to an antenna pattern. In this case, the antenna pad may be formed on the bonding side of the smart IC substrate in the same manner as the metal pattern provided on the contact side of the smart IC substrate.

[0008] However, the smart IC substrate according to the conventional technology has a complex process for forming an antenna pad for implementing an antenna function on the bonding side, which causes a decrease in product yield or an increase in manufacturing cost.

[0009] Therefore, a new structure of a smart IC substrate, a smart IC module, and an IC card including the same that can solve the above problems is required.

[0010] The embodiment provides a smart IC substrate providing a wireless communication function, a smart IC module, and an IC card including the same.

[0011] In addition, the embodiment provides a smart IC substrate, a smart IC module, and an IC card including the same, which can simplify the manufacturing process.

[0012] In addition, the embodiment provides a smart IC substrate, a smart IC module, and an IC card including the same, which can improve design freedom.

[0013] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0014] A smart IC substrate according to an embodiment comprises a substrate including an upper surface and a second surface opposite to the first surface; a first adhesive layer disposed on one surface of the substrate; a second adhesive layer disposed on the second surface of the substrate; a first conductive pattern portion attached to the first adhesive layer on the first surface of the substrate; and a second conductive pattern portion attached to the second adhesive layer on the second surface of the substrate, wherein a thickness of the first adhesive layer and a thickness of the second adhesive layer are different from each other, and a thickness of the first conductive pattern portion and a thickness of the second conductive pattern portion are different from each other.

[0015] Additionally, the smart IC substrate includes a plurality of through holes spaced apart from each other and penetrating the substrate and the first adhesive layer, the first conductive pattern portion includes a plurality of upper pads overlapping each of the plurality of through holes along a vertical direction, and the second conductive pattern portion includes a plurality of lower pads that do not overlap the plurality of through holes along the vertical direction.

[0016] Additionally, the thickness of the second adhesive layer is greater than the thickness of the first adhesive layer.

[0017] Additionally, the thickness of the second conductive pattern portion is greater than the thickness of the first conductive pattern portion.

[0018] Additionally, the width of the second conductive pattern portion is greater than the width of at least one through hole among the plurality of through holes.

[0019] Additionally, each of the plurality of lower pads includes a first portion disposed adjacent to one of the plurality of through holes, a second portion disposed adjacent to the periphery of the other surface of the substrate than the first portion, and a third portion connecting the second portions.

[0020] In addition, the first portion of the lower pad is a bonding area connected to a terminal of the chip, the second portion of the lower pad is a bonding area connected to an antenna pattern, and the third portion of the lower pad is a connection area connecting the bonding area and the bonding area.

[0021] Additionally, each of the plurality of lower pads further includes a fourth portion extending from the third portion to the outside of the plurality of through holes and provided along the circumferential direction of the area where the plurality of through holes are arranged.

[0022] In addition, the second conductive pattern portion further includes a dummy portion provided along the circumferential direction of the area where the plurality of through holes are arranged on the outside of the plurality of through holes, and spaced apart from the lower pad.

[0023] Additionally, the dummy portion includes a plurality of dummy patterns spaced apart from each other along the circumferential direction.

[0024] In addition, the first adhesive layer is provided to entirely cover one surface of the substrate, and the second adhesive layer is provided to partially cover the other surface of the substrate.

[0025] The smart IC substrate of the embodiment includes a first conductive pattern portion arranged on one surface of a substrate, and a second conductive pattern portion arranged on the other surface of the substrate. In this case, the embodiment may form the first conductive pattern portion and the second conductive pattern portion on the one surface and the other surface of the substrate, respectively, in different ways. For example, the first conductive pattern portion may be formed by etching a metal layer attached to the substrate, and the second conductive pattern portion may be formed by attaching a pre-manufactured conductive pattern to the other surface of the substrate. Therefore, the embodiment may solve the problem of the double-sided wiring structure having a complicated manufacturing process due to the product structure characteristics of the smart IC substrate, and the problem of the manufacturing cost increasing as the product yield decreases. That is, the embodiment may simplify the manufacturing process of the smart IC substrate by forming an antenna pattern by attaching a pre-manufactured second conductive pattern portion to the substrate.

[0026] Furthermore, the embodiment facilitates the adjustment of the attachment location of the second conductive pattern portion according to various product designs, and is applicable to products of various designs, thereby improving design freedom. Furthermore, the embodiment can reduce manufacturing costs by simplifying the process, thereby further improving product yield.

[0027] At this time, the smart IC substrate may include a first adhesive layer disposed between one surface of the substrate and the first conductive pattern portion, and a second adhesive layer disposed between the other surface of the substrate and the second conductive pattern portion. At this time, the second adhesive layer may be selectively provided on the other surface of the substrate. For example, the first adhesive layer may be provided to cover the entire one surface of the substrate. In contrast, the second adhesive layer may be selectively provided only in an area on the other surface of the substrate where the second conductive pattern portion is to be disposed. Through this, the embodiment can reduce the planar area of ​​the second adhesive layer, and further reduce the manufacturing cost by reducing the amount of the second adhesive layer. Through this, the other surface of the substrate may include a portion covered by the second adhesive layer and a portion not covered by the second adhesive layer. In addition, the portion not covered by the second adhesive layer can provide a space for a separate adhesive material to be disposed in a later process of assembling the smart IC card. Therefore, in the embodiment, it is possible to increase the thickness of the above-described adhesive material in a smart IC substrate having the same thickness as the comparative example, thereby improving process characteristics in the assembly process and enabling the smart IC substrate to be more stably bonded.

[0028] In addition, the second adhesive layer may have a thickness greater than that of the first adhesive layer. Therefore, the embodiment can enable the second conductive pattern portion to be more stably attached to the other surface of the substrate, thereby improving product reliability. Furthermore, the embodiment can reduce the height difference between the terminal of the chip and the second conductive pattern portion by the amount of the above-described thickness difference by making the thickness (T2) of the second adhesive layer greater than that of the first adhesive layer. Therefore, the embodiment can improve the process characteristics in the process of wire-bonding the second conductive pattern portion and the terminal of the chip, thereby further improving the wire bonding reliability.

[0029] At this time, the embodiment can form the second conductive pattern portion by attaching the conductive pattern manufactured in advance as described above, and thus, formation is possible without restrictions on the width of the second conductive pattern portion. To this end, the embodiment makes the width of the second conductive pattern portion larger than the width of the through hole. The embodiment makes the width of the second conductive pattern portion larger than the width of the first conductive pattern portion, thereby increasing the contact area between the second conductive pattern portion and the second adhesive layer, and increasing their bonding strength, thereby allowing the second conductive pattern portion to be more stably attached to the other surface of the substrate. Through this, the embodiment can further improve product reliability. In addition, the embodiment makes the width of the second conductive pattern portion larger than the width of the first conductive pattern portion, thereby increasing the allowable current of the second conductive pattern portion, and thus improving the antenna characteristics.

[0030] In addition, the thickness of the second conductive pattern portion may be different from the thickness of the first conductive pattern portion. Preferably, the thickness of the second conductive pattern portion may be greater than the thickness of the first conductive pattern portion. Through this, the embodiment can improve the allowable current of the second conductive pattern portion, and thereby further improve the antenna characteristics. In addition, the embodiment can reduce the step between the second conductive pattern portion and the terminal of the chip, and thereby improve the wire bonding process characteristics. Therefore, the embodiment can improve the product reliability of the smart IC substrate.

[0031] In addition, the second conductive pattern portion has an extension portion arranged outside the plurality of through holes. For example, the second conductive pattern portion may be an antenna pad including a first portion connected to a terminal of the chip, a second portion connected to an antenna pattern, and a third portion arranged between the first portion and the second portion. In addition, the extension portion may further include a fourth portion extending from the third portion of the antenna pad toward the outside of the through hole and arranged along the circumferential direction of the other surface of the substrate. In this case, the fourth portion may be provided while being connected to the antenna pad, or may be provided as a plurality of dummy patterns spaced apart from the antenna pad and spaced apart from each other. In addition, the fourth portion of the antenna pad corresponding to the above-described extension portion may prevent the molding member from flowing outward from the area where the through holes are arranged during the molding process of the chip. For example, the fourth portion may function as a dam that prevents the molding member of the chip from flowing outward from the area while ensuring that it is arranged only in the area designated by the substrate. Through this, the embodiment can ensure that the chip and the connecting member (to be described later) connecting the chip and the pads are stably molded through the molding member, thereby improving the operating characteristics of the chip. Accordingly, the embodiment can prevent external moisture or foreign substances from penetrating into the molding area of ​​the chip, thereby further improving operational reliability.

[0032] FIG. 1 is a plan view of one side of a smart IC substrate according to the first embodiment.

[0033] Figure 2 is a plan view of the other surface of the smart IC substrate according to the first embodiment.

[0034] Figure 3 is a cross-sectional view taken along the AA' direction of Figure 2.

[0035] Figure 4 is a cross-sectional view taken along the BB' direction of Figure 2.

[0036] Figure 5 is a plan view of the other surface of the smart IC substrate according to the second embodiment.

[0037] Figure 6 is a plan view of the other surface of a smart IC substrate according to the third embodiment.

[0038] Fig. 7 is a plan view showing a smart IC module according to an embodiment.

[0039] Fig. 8 is a cross-sectional view showing a smart IC module according to an embodiment.

[0040] Fig. 9 is a perspective view showing a smart IC card according to an embodiment.

[0041] Fig. 10 is a cross-sectional view schematically showing the smart IC card of Fig. 9.

[0042] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0043] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0044] In addition, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (or at least one) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0045] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0046] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0047] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0048] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0049]

[0050] Hereinafter, a smart IC substrate, a smart IC module, and a smart IC card including the same according to an embodiment will be described with reference to the drawings.

[0051]

[0052] FIG. 1 is a plan view of one side of a smart IC substrate according to a first embodiment, FIG. 2 is a plan view of the other side of the smart IC substrate according to the first embodiment, FIG. 3 is a cross-sectional view taken along the AA' direction of FIG. 2, and FIG. 4 is a cross-sectional view taken along the BB' direction of FIG. 2.

[0053] Referring to FIGS. 1 to 4, a smart IC substrate (100) includes a substrate (110), a first conductive pattern portion (120), and a second conductive pattern portion (130, 135). The substrate (110) includes one side (110S1) and a second side (110S2) opposite to the first side (110S1). In addition, the first conductive pattern portion (120) is disposed on the first side (110S1) of the substrate (110). In addition, the second conductive pattern portion (130, 135) is disposed on the second side (110S2) of the substrate (110). Here, the arrangement on one side (110S1) and the other side (110S2) should not be understood only as a configuration in which the first conductive pattern portion (120) and the second conductive pattern portion (130, 135) are in direct contact with the one side (110S1) and the other side (110S2) of the substrate (110), but should be understood as another configuration between the one side (110S1) of the substrate (110) and the first conductive pattern portion (120), and between the other side (110S2) of the substrate (110) and the second conductive pattern portion (130, 135).

[0054] One side (110S1) of the substrate (110) and the other side (110S2) of the substrate (110) mean opposite sides. The one side (110S1) of the substrate (110) may be defined as a contact surface. For example, the one side (110S1) of the substrate (110) may mean a surface that can recognize information of a smart IC module through direct or indirect contact. In addition, the other side (110S2) of the substrate (110) may be defined as a bonding surface. For example, the other side (110S2) of the substrate (110) may mean a surface for bonding with a mounted chip when a chip (to be described later) is mounted.

[0055] The substrate (110) comprises a resin material. The substrate (110) may have a certain strength. The substrate (110) may include a reinforcing member. For example, the substrate (110) may be provided as a prepreg having a reinforcing member such as glass fiber. Specifically, the substrate (110) may be provided by dispersing glass fiber and silicon-based filler (Si filler) within an epoxy resin.

[0056] The substrate (110) may be rigid or flexible. For example, the substrate (110) may include glass or plastic. For example, the substrate (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the substrate (110) may include polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0057] The substrate (110) may include an optically isotropic film. For example, the substrate (110) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0058] Alternatively, the substrate (110) may be bent while having a partially curved surface. That is, the substrate (110) may be bent while having a partially flat surface and a partially curved surface. In detail, the ends of the substrate (110) may be bent while having a curved surface. Alternatively, the substrate (110) may be bent while having a random curvature.

[0059] The substrate (110) may have a thickness within a set range. For example, the thickness of the substrate (110) may be 80 μm to 150 μm, 90 μm to 140 μm, or 100 μm to 120 μm. If the thickness of the substrate (110) is less than 80 μm, the support force and / or rigidity of the substrate (110) may be reduced, and thus, the first conductive pattern portion (120) and the second conductive pattern portions (130, 135) may be difficult to stably position. If the thickness of the substrate (110) exceeds 150 μm, the thickness of the smart IC substrate may increase, and thereby, the thickness of the smart IC card including the smart IC substrate (100) may increase, making it difficult to make it thin.

[0060] The substrate (110) has insulating properties. For example, the substrate (110) can be provided for insulation between the first conductive pattern portion (120) and the second conductive pattern portion (130, 135), and can prevent short circuiting between the first conductive pattern portion (120) and the second conductive pattern portion (130, 135). In addition, the substrate (110) serves to stably support the first conductive pattern portion (120) and / or the second conductive pattern portion (130, 135) during the process of forming the first conductive pattern portion (120) and the second conductive pattern portion (130, 135).

[0061] The substrate (110) may have through holes. For example, the substrate (110) may include a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) spaced apart from each other in the horizontal direction. At this time, although the drawing illustrates that the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in eight numbers, the present invention is not limited thereto. For example, the number of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may increase or decrease depending on the type of chip mounted on the smart IC substrate (100). For example, the number of terminals of a chip mounted on a smart IC substrate (100) may be less than 8 or more than 8, and accordingly, the number of a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may be less than 8 or more than 8. The plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be an area for electrically connecting the terminals of the chip and the first conductive pattern portion (120) arranged on one surface (110S1) of the substrate (110). Preferably, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be an area for wire bonding of the terminals of the chip and the first conductive pattern portion (120).

[0062] Each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) has a width (W1) of a set range. The width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may mean a diameter of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). Alternatively, the width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be defined as a minimum distance between inner walls of the through holes passing through the central axis in the horizontal direction of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0063] The width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be 500 µm to 1000 µm, 600 µm to 900 µm, or 700 µm to 800 µm. If the width (W1) of at least one through hole among the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) is less than 500 µm, it may be difficult to secure a wire bonding space, and thus, process characteristics in the wire bonding process may deteriorate. In addition, when the width (W1) of at least one of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) exceeds 1000 μm, the planar area of ​​the substrate (110) may decrease and the rigidity of the substrate (110) may decrease accordingly, or it may be difficult to stably place the first conductive pattern portion (120) and / or the second conductive pattern portion (130, 135) on the substrate (110).

[0064] A first adhesive layer (140) may be disposed on one side (110S1) of the substrate (110). The first adhesive layer (140) may be provided for bonding strength between the first conductive pattern portion (120) and the substrate (110). The first adhesive layer (140) may be referred to as a bonding sheet. The first adhesive layer (140) may be provided for bonding a copper foil layer (not shown), which is a metal layer before implementing a circuit such as the first conductive pattern portion (120), to one side (110S1) of the substrate (110).

[0065] The first adhesive layer (140) comprises a resin material. For example, the first adhesive layer (140) may comprise at least one of an epoxy resin, an acrylic resin, and a polyimide resin. In addition, the first adhesive layer (140) may comprise at least one additive selected from the group consisting of natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. In this case, the flexibility of the first adhesive layer (140) may be improved.

[0066] The first adhesive layer (140) may have a thickness (T1) within a set range. For example, the thickness (T1) of the first adhesive layer (140) may be 8 μm to 35 μm, 10 μm to 30 μm, or 12 μm to 25 μm. If the thickness (T1) of the first adhesive layer (140) is less than 8 μm, the adhesive strength of the first adhesive layer (140) may decrease, thereby causing the first conductive pattern portion (120) to be separated from the first adhesive layer (140). In addition, if the thickness (T1) of the first adhesive layer (140) exceeds 35 μm, the thickness of the smart IC substrate or the thickness of the smart IC card may increase.

[0067] At this time, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the substrate (110) and the first adhesive layer (140). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate from one surface of the first adhesive layer (140) to the other surface (110S2) of the substrate (110). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be formed through a process such as punching while the first adhesive layer (140) is disposed on the substrate (110), thereby commonly penetrating the substrate (110) and the first adhesive layer (140).

[0068] The planar area of ​​the first adhesive layer (140) may correspond to the planar area of ​​the substrate (110). For example, the first adhesive layer (140) may entirely cover one side (110S1) of the substrate (110). Accordingly, the rigidity of the substrate (110) may be further improved.

[0069] The first conductive pattern portion (120) may be disposed on one surface (110S1) of the substrate (110). Preferably, the first conductive pattern portion (120) may be disposed on the substrate (110) by adhesive force provided through the first adhesive layer (140). For example, the first conductive pattern portion (120) may refer to a pattern disposed on the contact surface of the substrate (110).

[0070] The first conductive pattern portion (120) has a plurality of pads spaced apart from each other along a horizontal direction. For example, the first conductive pattern portion (120) may include a plurality of pads. At this time, the number of the plurality of pads of the first conductive pattern portion (120) may correspond to the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be eight, and accordingly, the first conductive pattern portion (120) may include first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) spaced apart from each other along a horizontal direction. One surface of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a contact surface that makes contact or does not make contact with an external terminal to transmit information of the smart IC substrate (100) to the outside. In addition, the other surface of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a bonding surface that is wire-bonded to a terminal of a chip mounted on the smart IC substrate (100). The first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be referred to as upper pads.

[0071] Each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be provided with multiple layers. For example, each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may include a metal layer (120a) disposed on a first adhesive layer (140), a first plating layer (120b) disposed on the metal layer (120a), and a second plating layer (120c) disposed on the first plating layer (120b).

[0072] The metal layer (120a) is disposed on a first adhesive layer (140) disposed on one surface (110S1) of the substrate (110). The metal layer (120a) may include at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the metal layer (120a) may be a copper foil layer attached to the substrate (110) via the first adhesive layer (140), and thus may include copper.

[0073] The metal layer (120a) may have a thickness within a set range. For example, the thickness of the metal layer (120a) may be 20 μm to 75 μm, 22 μm to 65 μm, or 25 μm to 60 μm. When the thickness of the metal layer (120a) is less than 20 μm, the resistance of the metal layer (120a) may increase, and thus the resistance of the first conductive pattern portion (120) may increase, resulting in deterioration of signal characteristics. When the thickness of the metal layer (120a) exceeds 75 μm, the thickness of the smart IC substrate may increase, and the thickness of the smart IC card may increase. Furthermore, when the thickness of the metal layer (120a) exceeds 75 μm, the time for forming the first conductive pattern portion (120) may increase, resulting in deterioration of process efficiency and deterioration of product yield.

[0074] The first plating layer (120b) may be disposed on the metal layer (120a). Here, the fact that the first plating layer (120b) is disposed on the metal layer (120a) may mean that the first plating layer (120b) is disposed on a surface that is not in contact with the substrate (110) and the first adhesive layer (140) among the upper surface, lower surface, and side surface of the metal layer (120a). The first plating layer (120b) may be provided to surround the upper surface and side surface of the metal layer of each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, and 128). In addition, at least a portion of the lower surface of the metal layer of each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in a vertical direction. Accordingly, the first plating layer (120b) may be disposed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the first plating layer (120b) may be disposed on the lower surface of the metal layer (120a) that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in a vertical direction.

[0075] A dummy pattern portion (DP) may be further provided on one side (110S1) of the substrate (110). The dummy pattern portion (DP) may include the same material as the first conductive pattern portion (120), and preferably, may have the same layer structure as the first conductive pattern portion (120). The dummy pattern portion (DP) may be electrically spaced from the first conductive pattern portion (120), thereby improving the rigidity of the smart IC substrate (100). In addition, the dummy pattern portion (DP) may be provided at a corner region of the one side (110S1) of the substrate (110) to improve process characteristics in the assembly process of the smart IC substrate (100). For example, the dummy pattern portion (DP) may include first to fourth dummy patterns (DP1, DP2, DP3, DP4) respectively provided at a corner region of the one side (110S1) of the substrate (110).

[0076] The second plating layer (120c) may be disposed on the first plating layer (120b). Here, the fact that the second plating layer (120c) is disposed on the first plating layer (120b) may mean that the second plating layer (120c) is disposed on the upper surface, side surface, and lower surface of the first plating layer (120b) that are exposed. For example, the second plating layer (120c) may be disposed on the upper surface of the first plating layer (120b) that is disposed on the upper surface of the metal layer (120a). For example, the second plating layer (120c) may be disposed on the side surface of the first plating layer (120b) that is disposed on the side surface of the metal layer (120a). For example, the second plating layer (120c) may be disposed on the lower surface of the first plating layer (120b) which is disposed on the lower surface of the metal layer (120a) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0077] The first plating layer (120b) and the second plating layer (120c) are surface treatment layers that protect the surfaces of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) of the first conductive pattern portion (120), while imparting a certain level of wear resistance, hardness, wire bondability, gloss, etc. to the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128). For this purpose, the first plating layer (120b) may be formed of nickel, and the second plating layer (120c) may be formed of gold (Au) or palladium (Pd), but is not limited thereto.

[0078] The second conductive pattern portion (130, 135) is arranged on the other surface (110S2) of the substrate (110). For example, the second conductive pattern portion (130, 135) may be arranged spaced apart from the first conductive pattern portion (120) with the substrate (110) therebetween. The second conductive pattern portion (130, 135) may be an antenna pad for an antenna function. For example, the second conductive pattern portion (130, 135) may be an antenna pad that electrically connects a chip mounted on a smart IC substrate (100) and an antenna pattern.

[0079] At this time, the second conductive pattern portion (130, 135) may be formed in a different manner from the first conductive pattern portion (120). For example, the first conductive pattern portion (120) may be formed by etching a copper foil layer attached via the first adhesive layer (140) through an exposure and development process. For example, the first conductive pattern portion (120) may be formed through a photolithography process.

[0080] In contrast, the second conductive pattern portion (130, 135) may be attached to the other surface (110S2) of the substrate (110) in a pick and place manner. For example, the second conductive pattern portion (130, 135) may be formed on a separate structure and then attached to the other surface (110S2) of the substrate (110).

[0081] To this end, a second adhesive layer (150) may be provided between the other surface (110S2) of the substrate (110) and the second conductive pattern portion (130, 135). The second adhesive layer (150) may provide adhesive strength for attaching the pre-manufactured second conductive pattern portion (130, 135) to the other surface (110S2) of the substrate (110).

[0082] In this way, the embodiment can form the first conductive pattern portion (120) and the second conductive pattern portion (130, 135) on one side (110S1) and the other side (110S2) of the substrate (110) in different ways, respectively. Therefore, the embodiment can solve the problem that the manufacturing process of the double-sided wiring structure is complicated due to the product structure characteristics of the smart IC substrate (100), and the manufacturing cost increases as the product yield decreases. That is, the embodiment can simplify the manufacturing process of the smart IC substrate (100) by forming the antenna pattern by attaching the second conductive pattern portion (130, 135) manufactured in advance to the substrate (110). Furthermore, the embodiment can easily adjust the attachment position of the second conductive pattern portion (130, 135) according to various product designs, can be applied to products of various designs, and can improve the degree of design freedom accordingly. Furthermore, the embodiment can reduce manufacturing costs by simplifying the process, and further improve product yield.

[0083] By virtue of the characteristics described above, the second adhesive layer (150) may have the structure and / or properties of the first adhesive layer (140).

[0084] The second adhesive layer (150) may be selectively provided on the other side (110S2) of the substrate (110). For example, the first adhesive layer (140) may be provided to entirely cover one side (110S1) of the substrate (110). In contrast, the second adhesive layer (150) may be selectively provided only in the region where the second conductive pattern portions (130, 135) are to be arranged on the other side (110S2) of the substrate (110). Through this, the embodiment can reduce the plane area of ​​the second adhesive layer (150) and the amount of the second adhesive layer (150), thereby further reducing the manufacturing cost. Through this, the other side (110S2) of the substrate (110) may include a portion covered by the second adhesive layer (150) and a portion not covered by the second adhesive layer (150). In addition, the portion not covered by the second adhesive layer (150) can provide space for a separate adhesive material to be placed during a later process of assembling the smart IC card. Therefore, in the embodiment, it is possible to increase the thickness of the adhesive material described above in a smart IC substrate (100) having the same thickness as the comparative example, thereby improving process characteristics in the assembly process and enabling the smart IC substrate (100) to be more stably bonded.

[0085] In addition, the second adhesive layer (150) may have a predetermined thickness (T2). For example, the second adhesive layer (150) may be greater than the thickness (T1) of the first adhesive layer (140). For example, the thickness (T2) of the second adhesive layer (150) may satisfy a range of 105% to 220%, or 110% to 210%, or 115% to 200% of the thickness (T1) of the first adhesive layer (140). That is, the embodiment allows the thickness (T2) of the second adhesive layer (150) to be greater than the thickness (T1) of the first adhesive layer (140), thereby enabling the second conductive pattern portion (130, 135) to be more stably attached to the other surface (110S2) of the substrate (110), thereby improving product reliability. Furthermore, the embodiment can reduce the height difference between the terminal of the chip and the second conductive pattern portion (130, 135) by the difference in the thicknesses (T1, T2) described above by making the thickness (T2) of the second adhesive layer (150) greater than the thickness (T1) of the first adhesive layer (140). Therefore, the embodiment can improve the process characteristics in the process of wire-bonding the terminal of the chip and the second conductive pattern portion (130, 135), and can further improve the wire bonding reliability accordingly. At this time, if the thickness (T2) of the second adhesive layer (150) is less than 105% of the thickness (T1) of the first adhesive layer (140), the product reliability improvement effect and the process characteristic improvement effect as described above may be insufficient. Additionally, if the thickness (T2) of the second adhesive layer (150) exceeds 200% of the thickness (T1) of the first adhesive layer (140), the thickness of the smart IC substrate (100) may increase.

[0086] The second adhesive layer (150) can be formed of various adhesive materials by being selectively disposed only in the area where the second conductive pattern portion (130, 135) is disposed. For example, the second adhesive layer (150) can be provided as a paste having adhesive properties. For example, the second adhesive layer (150) can be provided as a conductive paste or a non-conductive paste.

[0087] The second conductive pattern portion (130, 135) can be attached to the other surface (110S2) of the substrate (110) by adhesive force provided through the second adhesive layer (150). The second conductive pattern portion (130, 135) can have a predetermined width (W2) and thickness (W3).

[0088] At this time, the embodiment can form the second conductive pattern portion (130, 135) by attaching the pre-manufactured conductive pattern as described above, and thus, formation is possible without restrictions on the width (W2) of the second conductive pattern portion (130, 135). To this end, the embodiment makes the width (W2) of the second conductive pattern portion (130, 135) larger than the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the width (W2) of the second conductive pattern portion (130, 135) can be larger than the width of the lower surface of the first conductive pattern portion (120) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the width (W2) of the second conductive pattern portion (130, 135) may be either the width in the longitudinal direction and / or the width in the width direction. The width (W2) of the second conductive pattern portion (130, 135) may satisfy a range of 105% to 220%, or a range of 110% to 210%, or a range of 120% to 200% of the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0089] In the embodiment, the width (W2) of the second conductive pattern portion (130, 135) is made larger than the width (W2) of the first conductive pattern portion (120), thereby increasing the contact area between the second conductive pattern portion (130, 135) and the second adhesive layer (150), increasing their bonding strength, and thereby enabling the second conductive pattern portion (130, 135) to be more stably attached to the other surface (110S2) of the substrate (110). Through this, the embodiment can further improve product reliability. In addition, in the embodiment, the width (W2) of the second conductive pattern portion (130, 135) is made larger than the width (W2) of the first conductive pattern portion (120), thereby increasing the allowable current of the second conductive pattern portion (130, 135), thereby improving antenna characteristics.

[0090] At this time, if the width (W2) of the second conductive pattern portion (130, 135) is less than 105% of the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), the product reliability improvement effect and / or antenna characteristic improvement effect as described above may be insufficient. In addition, if the width (W2) of the second conductive pattern portion (130, 135) exceeds 220% of the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), the thickness of the smart IC substrate (100) may increase.

[0091] In addition, the thickness (T3) of the second conductive pattern portion (130, 135) may be different from the thickness of the first conductive pattern portion (120). Preferably, the thickness (T3) of the second conductive pattern portion (130, 135) may satisfy a range of 105% to 220% of the thickness of the first conductive pattern portion (120). In this case, the thickness of the first conductive pattern portion (120) may mean the thickness of the metal layer (120a), or may mean the sum of the thicknesses of the metal layer (120a), the first conductive layer (120b), and the second conductive layer (120c) in the vertical direction. In the embodiment, the thickness (T3) of the second conductive pattern portion (130, 135) is made larger than the thickness of the first conductive pattern portion (120), thereby improving the allowable current of the second conductive pattern portion (130, 135), and thus further improving the antenna characteristics. In addition, in the embodiment, the thickness (T3) of the second conductive pattern portion (130, 135) is made larger than the thickness of the first conductive pattern portion (120), thereby reducing the step between the second conductive pattern portion (130, 135) and the terminal of the chip, thereby improving the wire bonding process characteristics. Therefore, the embodiment can improve the product reliability of the smart IC substrate (100).

[0092] At this time, the second conductive pattern portion (130, 135) may be provided as an alloy. For example, the second conductive pattern portion (130, 135) may be provided as a Cu / Sn / Ag alloy, a Fe / Ni / Ag alloy, or a Cu / Sn / Ag / Al / Ni alloy.

[0093] The second conductive pattern portion (130, 135) may include a plurality of pads that are electrically spaced apart from each other. For example, the second conductive pattern portion (130, 135) may include a first antenna pad (130) and a second antenna pad (135) that is electrically spaced apart from the first antenna pad (130). For example, the first antenna pad (130) may be a pad to which positive polarity power is applied, and the second antenna pad (135) may be a pad to which negative polarity power is applied.

[0094] Each of the first antenna pad (130) and the second antenna pad (135) can be divided into a plurality of parts. At this time, the first antenna pad (130) and the second antenna pad (135) can be referred to as lower pads placed on the other surface (110S2) of the substrate (110).

[0095] The first antenna pad (130) may include a first portion (131) that is positioned most adjacent to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) without overlapping with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in a vertical direction. The first portion (131) of the first antenna pad (130) may be a wire bonding area for electrically connecting with a terminal of the chip.

[0096] The first antenna pad (130) may include a second portion (132) of the first antenna pad (130) that is located further from the through-holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) than the first portion (131) of the first antenna pad (130). The second portion (132) of the first antenna pad (130) may be an area closest to the edge of the other surface (110S2) of the substrate (110) in the first antenna pad (130). The second portion (132) of the first antenna pad (130) may be a terminal area for connection with an antenna pattern (not shown).

[0097] The first antenna pad (130) may include a third portion (133) connecting the first portion (131) and the second portion (132). The third portion (133) of the first antenna pad (130) may electrically connect the first portion (131) and the second portion (132) of the first antenna pad (130) while spacing them apart from each other by a predetermined distance. For example, the third portion (133) of the first antenna pad (130) may facilitate an electrical connection process with a chip in the first portion (131) of the first antenna pad (130) and a connection process with an antenna pattern in the second portion (132) of the first antenna pad (130) at predetermined distances, respectively.

[0098] The second antenna pad (135) may include a first portion (136) of the second antenna pad (135) that is positioned most adjacent to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) without overlapping with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in a vertical direction. The first portion (136) of the second antenna pad (135) may be a wire bonding area for electrically connecting to a terminal of the chip.

[0099] The second antenna pad (135) may include a second portion (137) of the second antenna pad (135) that is located further from the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) than the first portion (136) of the second antenna pad (135). The second portion (137) of the second antenna pad (135) may be an area closest to the edge of the other surface (110S2) of the substrate (110) in the second antenna pad (135). The second portion (137) of the second antenna pad (135) may be a terminal area for connection with an antenna pattern (not shown).

[0100] The second antenna pad (136) may include a third portion (138) of the second antenna pad (135) that connects the first portion (136) of the second antenna pad (135) and the second portion (137) of the second antenna pad (135). The third portion (138) of the second antenna pad (135) may electrically connect the first portion (136) of the second antenna pad (135) and the second portion (137) of the second antenna pad (135) while spacing them apart from each other by a predetermined distance. For example, the third portion (138) of the second antenna pad (135) may facilitate an electrical connection process with a chip in the first portion (136) of the second antenna pad (135) and a connection process with an antenna pattern in the second portion (137) of the second antenna pad (135) at a predetermined distance from each other.

[0101]

[0102] Hereinafter, a smart IC substrate according to another embodiment will be described. In the following embodiments, components that are substantially the same as the configuration of the smart IC substrate illustrated in FIGS. 1 to 4 are given the same reference numerals, and a detailed description thereof will be omitted.

[0103] FIG. 5 is a plan view of the other surface of a smart IC substrate according to the second embodiment, and FIG. 6 is a plan view of the other surface of a smart IC substrate according to the third embodiment.

[0104] Referring to FIG. 5, the smart IC substrate (100A) of the second embodiment may have a different structure of the conductive pattern portion arranged on the other surface (110S2) of the substrate (110) compared to the smart IC substrate (100) of the first embodiment.

[0105] The second conductive pattern portion (130A, 135A) of the second embodiment includes a first antenna pad (130A) and a second antenna pad (135A).

[0106] Each of the first antenna pad (130A) and the second antenna pad (135A) may include a first portion (131, 136) defined as an area where the terminal of the chip is wire-bonded, a second portion (132, 137) defined as an antenna pattern bonding area coupled to the antenna pattern, and a third portion (133, 138) defined as a connection area connecting the first portion (131, 136) and the second portion (132, 137).

[0107] At this time, each of the first antenna pad (130A) and the second antenna pad (135A) may further include a fourth portion (134, 139) extending in the circumferential direction of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the third portion (133, 138).

[0108] The fourth portion (134, 139) of each of the first antenna pad (130A) and the second antenna pad (135A) may be connected to the third portion (133, 138) of the first antenna pad (130A) and the second antenna pad (135A) and may be provided to surround the outer side of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the fourth portion (134, 139) of each of the first antenna pad (130A) and the second antenna pad (135A) may be positioned between the circumference of the other surface (110S2) of the substrate (110) and a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) and may extend along the circumference direction of the other surface (110S2) of the substrate (110).

[0109] For example, the fourth portion (134) of the first antenna pad (130A) may extend from the third portion (133) of the first antenna pad (130A) along the circumferential direction of the other surface (110S2) of the substrate (110). At this time, the fourth portion (134) of the first antenna pad (130A) may be provided in an area adjacent to the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), between some of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) and the circumference of the other surface (110S2) of the substrate (110). Specifically, the fourth portion (134) of the first antenna pad (130A) may be provided to surround the outer side of the first region in which the first through hole (TH1), the second through hole (TH2), and the third through hole (TH3) are arranged. Here, the first region may include the region in which the first through hole (TH1) is arranged, the region in which the second through hole (TH2) is arranged, the region in which the third through hole (TH3) is arranged, the region between the first through hole (TH1) and the second through hole (TH2), and the region between the second through hole (TH2) and the third through hole (TH3).

[0110] The fourth portion (134) of the first antenna pad (130A) can prevent the molding member from flowing out of the first through hole (TH1), the second through hole (TH2), and the third through hole (TH3) described above during the molding process of the chip that is performed later. For example, the fourth portion (134) of the first antenna pad (130A) can have a dam function that prevents the molding member of the chip from flowing out of the designated area while ensuring that it is placed only in the designated area. Through this, the embodiment can ensure that the chip and the connecting member (to be described later) connecting the chip and the pads are stably molded through the molding member, thereby improving the operating characteristics of the chip. Therefore, the embodiment can prevent external moisture or foreign substances from penetrating into the molding area of ​​the chip, thereby further improving the operating reliability.

[0111] In response to this, the fourth portion (139) of the second antenna pad (135A) may extend from the third portion (138) of the second antenna pad (135A) along the circumferential direction of the other surface (110S2) of the substrate (110). At this time, the fourth portion (139) of the second antenna pad (135A) may be provided in an area adjacent to the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), between some of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) and the circumference of the other surface (110S2) of the substrate (110). Specifically, the fourth portion (139) of the second antenna pad (135A) may be provided to surround the outer side of the second region in which the sixth through hole (TH6), the seventh through hole (TH7), and the eighth through hole (TH8) are arranged. Here, the second region may include the region in which the sixth through hole (TH6) is arranged, the region in which the seventh through hole (TH7) is arranged, the region in which the eighth through hole (TH8) is arranged, the region between the sixth through hole (TH6) and the seventh through hole (TH7), and the region between the seventh through hole (TH7) and the eighth through hole (TH8).

[0112] The fourth portion (139) of the second antenna pad (135A) can prevent the molding member from flowing out of the sixth through hole (TH6), the seventh through hole (TH7), and the eighth through hole (TH8) described above during the molding process of the chip that is performed later. For example, the fourth portion (139) of the second antenna pad (135A) can function as a dam that prevents the molding member of the chip from flowing out of the designated area while ensuring that it is placed only in the designated area. Through this, the embodiment can ensure that the chip and the connecting member (to be described later) connecting the chip and the pads are stably molded through the molding member, thereby improving the operating characteristics of the chip. Therefore, the embodiment can prevent external moisture or foreign substances from penetrating into the molding area of ​​the chip, thereby further improving the operating reliability.

[0113] At this time, the fourth part (134) of the first antenna pad (130A) and the fourth part (139) of the second antenna pad (135A) may be spaced apart from each other. That is, the fourth part (134) of the first antenna pad (130A) and the fourth part (139) of the second antenna pad (135A) are connected to terminals of different chips, and thus may be spaced apart from each other so as to prevent an electrical short circuit from occurring.

[0114] Meanwhile, although not shown in the drawing, at least one of the first antenna pad (130A) and the second antenna pad (135A) may further include a fifth portion (not shown) surrounding the outer side of the third region in which the first portion (131) of the first antenna pad (130A), the first portion (136) of the second antenna pad (135A), the fourth through hole (TH4), and the fifth through hole (TH5) are arranged. Through this, the process characteristics of the molding process can be further improved, and further, the molding reliability can be further improved.

[0115]

[0116] Referring to FIG. 6, the smart IC substrate (100C) of the third embodiment may further include a dummy portion that functions as the fourth portion (134) of the first antenna pad (130A) and the fourth portion (139) of the second antenna pad (135A) of FIG. 5. For example, the second conductive pattern portion (130, 135) of the smart IC substrate (100C) of the third embodiment may have the same structure as the first embodiment of FIG. 1, and may further include a dummy portion.

[0117] The dummy portion may be electrically connected to the first antenna pad (130) and the second antenna pad (135) of the second conductive pattern portion (130, 135), and may be provided in the outer region of a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). The dummy portion may include one dummy pattern that is connected to each other, or may include a plurality of dummy patterns that are spaced apart from each other.

[0118] For example, the dummy portion may include a first dummy pattern (161), a second dummy pattern (162), a third dummy pattern (163), a fourth dummy pattern (164), and a fifth dummy pattern (165). The first dummy pattern (161), the second dummy pattern (162), the third dummy pattern (163), the fourth dummy pattern (164), and the fifth dummy pattern (165) may be spaced apart from each other and thereby function as a dam to prevent the molding member from overflowing outside of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). In addition, the area between each of the first dummy pattern (161), the second dummy pattern (162), the third dummy pattern (163), the fourth dummy pattern (164), and the fifth dummy pattern (165) can be spaced apart, which can serve to allow gas generated in the process of curing the molding member to be easily discharged to the outside.

[0119] However, the embodiment is not limited thereto, and at least two or more of the first dummy pattern (161), the second dummy pattern (162), the third dummy pattern (163), and the fourth dummy pattern (164) may be provided as one pattern that is connected to each other.

[0120]

[0121] Fig. 7 is a plan view illustrating a smart IC module according to an embodiment, and Fig. 8 is a cross-sectional view illustrating a smart IC module according to an embodiment. Preferably, Fig. 7 may be a plan view illustrating the other side of the smart IC module in a state where a molding member (1300) is not arranged.

[0122] Referring to FIGS. 7 and 8, the smart IC module (1000) may include a chip (1100) placed in a chip mounting area. Here, the chip mounting area may be an inner area of ​​an area surrounded by a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), a first antenna pad (130), and a second antenna pad (135) on the other surface (110S2) of the substrate (110).

[0123] At this time, an adhesive member (not shown) may be placed in the inner region described above, and the chip (1100) may be attached on the adhesive member described above.

[0124] The chip (1100) may include a plurality of terminals (not shown). For example, the chip (1100) may include first to tenth terminals.

[0125] In addition, it may include a connecting member (1200) that connects the terminals of the chip (1100) and the pads of the smart IC substrate (100). The connecting member (1200) may be a wire, but is not limited thereto. The connecting member (1200) may include first to tenth connecting members. For example, the connecting member (1200) may include first to eighth connecting members that connect the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) exposed through a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to the first to eighth terminals of the chip (1100), respectively. Additionally, the connecting member (1200) may include a ninth connecting member connecting the first antenna pad (130) and the ninth terminal of the chip (1100). Additionally, the connecting member (1200) may include a tenth connecting member connecting the second antenna pad (135) and the tenth terminal.

[0126] At this time, the smart IC module (1000) may further include a molding member (1200). The molding member (1200) may mold the chip (1100). In addition, the molding member (1200) may mold the connection member (1200). Accordingly, the molding member (1200) may be provided to cover the chip (1100) and the connection member (1200) while filling the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0127] As described above, the smart IC substrate may include a fourth portion or dummy portion that functions as a dam portion to improve the molding process characteristics of the molding member (1200), thereby allowing the molding member (1200) to be placed only in a designated area to stably mold the chip (1100) and the connecting member (1200).

[0128]

[0129] Fig. 9 is a perspective view showing a smart IC card according to an embodiment, and Fig. 10 is a cross-sectional view schematically showing the smart IC card of Fig. 9.

[0130] Referring to FIGS. 9 and 10, a smart IC card (3000) according to an embodiment may include a main body (3100), a first protective layer (3210), and a second protective layer (3220).

[0131] The main body (3100) includes a receiving portion (3110). At this time, a smart IC module (2000) manufactured according to any one of the embodiments of FIGS. 1 to 8 may be manufactured, and the manufactured smart IC module (2000) may be placed inside the receiving portion (3110).

[0132] The receiving portion (3110) may have a step. For example, the inner wall of the receiving portion (3110) may have a step. Preferably, the receiving portion (3110) may have a width in an area corresponding to the upper portion of the smart IC card (3000) greater than a width in an area corresponding to the lower portion of the smart IC card (3000). Accordingly, the receiving portion (3110) may include a first portion having a first width and a second portion having a second width greater than the first width. In addition, the second portion of the receiving portion (3110) may receive a chip (1100) and a molding member (1200) provided in the smart IC module, and the remaining components of the smart IC module excluding at least a portion of the chip (1100) and the molding member (1200) may be received in the first portion of the receiving portion (3110). Accordingly, the embodiment can further dramatically reduce the thickness of the smart IC card and enable the chip (1100) to be inserted more stably into the smart IC card.

[0133] At this time, an antenna pattern (AP) may be arranged on the main body (3100). In detail, the antenna pattern (AP) may be arranged in a coil shape at the edge of the main body (3100).

[0134] At this time, the second part (132, 137) of the antenna pads provided in the smart IC module (2000) can be connected to the antenna pattern (AP) arranged on the main body (3100) described above. An IC card including a smart IC module according to this operates as a contactless card, a combination card, or a hybrid card.

[0135] The smart IC module (2000) is inserted into the receiving portion (3110). The smart IC module (2000) and the main body (3100) are bonded by an adhesive layer (3120). As a result, the smart IC module (2000) is inserted into and fixed in the receiving portion (3110).

[0136] The first protective layer (3210) is disposed on the upper portion of the main body (3100). The first protective layer (3210) may include a transparent material. The first protective layer (3210) may include a transparent resin material. The first protective layer (3210) may be disposed as at least one layer. That is, the first protective layer (3210) may include a plurality of layers.

[0137] The second protective layer (3220) is disposed on the lower portion of the body (3100). A magnetic stripe may be disposed on the second protective layer (3220). The second protective layer (3220) may include a transparent material. The second protective layer (3220) may include a transparent resin material. The second protective layer (3220) may be disposed as at least one layer. That is, the second protective layer (3220) may include a plurality of layers.

[0138]

[0139] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0140] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A substrate including the upper surface and the other surface opposite to the upper surface; A first adhesive layer disposed on one side of the above-described substrate; A second adhesive layer disposed on the other side of the above-mentioned substrate; A first conductive pattern portion attached to the first adhesive layer on one side of the above-described substrate; and A second conductive pattern portion is included attached to the second adhesive layer on the surface of the above-mentioned substrate, The thickness of the first adhesive layer and the thickness of the second adhesive layer are different from each other, A smart IC substrate, wherein the thickness of the first conductive pattern portion and the thickness of the second conductive pattern portion are different from each other.

2. In paragraph 1, It includes a plurality of through holes spaced apart from each other and penetrating through the above-mentioned substrate and the first adhesive layer, The first conductive pattern portion includes a plurality of upper pads each overlapping with the plurality of through holes along the vertical direction, A smart IC substrate, wherein the second conductive pattern portion includes a plurality of lower pads that do not overlap the plurality of through holes along the vertical direction.

3. In paragraph 2, A smart IC substrate, wherein the thickness of the second adhesive layer is greater than the thickness of the first adhesive layer.

4. In paragraph 2, A smart IC substrate, wherein the thickness of the second conductive pattern portion is greater than the thickness of the first conductive pattern portion.

5. In paragraph 2, A smart IC substrate, wherein the width of the second conductive pattern portion is greater than the width of at least one of the plurality of through holes.

6. In paragraph 2, A smart IC substrate, wherein each of the plurality of lower pads comprises a first portion arranged adjacent to one of the plurality of through holes, a second portion arranged adjacent to the periphery of the other surface of the substrate than the first portion, and a third portion connecting the second portion and the second portion.

7. In paragraph 6, The first portion of the above lower pad is a bonding area connected to the terminal of the chip, The second part of the above lower pad is a bonding area that is bonded to the antenna pattern, A smart IC substrate, wherein the third portion of the lower pad is a connection area connecting the bonding area and the joining area.

8. In paragraph 6, A smart IC substrate, wherein each of the plurality of lower pads further includes a fourth portion extending from the third portion to the outside of the plurality of through holes and provided along the circumferential direction of the area in which the plurality of through holes are arranged.

9. In paragraph 6, The second conductive pattern portion is: A smart IC substrate further comprising a dummy portion provided along the circumferential direction of an area in which the plurality of through holes are arranged on the outside of the plurality of through holes, and spaced apart from the lower pad.

10. In paragraph 9, A smart IC substrate, wherein the dummy portion includes a plurality of dummy patterns spaced apart from each other along the circumferential direction.

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