PWM signal generation circuit, pixel circuit, display substrate, display device and electronic device

Abstract

A PWM signal generation circuit, comprising: a first signal transmission circuit; and a second signal transmission circuit, wherein a first output end of the first signal transmission circuit is connected to a second output end of the second signal transmission circuit and serves as an output end of the PWM signal generation circuit; a first high level for generating a first output signal of the first signal transmission circuit is different from a second high level for generating a second output signal of the second signal transmission circuit; and an output signal of the PWM signal generation circuit has a step between the first high level and the second high level. Also provided are a pixel circuit, a display substrate, a display device and an electronic device.

Description

PWM signal generation circuit, pixel circuit, display substrate, display device and electronic device Technical Field

[0001] This disclosure relates to the field of circuit technology, and more specifically, to a pulse width modulation (PWM) signal generation circuit, a pixel circuit, a display substrate including the pixel circuit, a display device including the display substrate, and an electronic device including the display device. Background Technology

[0002] When using pulse width modulation (PWM) to drive LED displays, achieving an 8-bit Gamma 2.2 brightness scheme typically requires at least 10 to 12 subframes. For applications with a large number of display lines, the write time for each line of data signal is less than 1μs, resulting in a severely insufficient data write time.

[0003] Summary of the Invention

[0004] This disclosure aims to provide a pixel circuit that achieves an 8-bit Gamma 2.2 brightness scheme using fewer subframes, thereby ensuring that the refresh time of each subframe is sufficient for writing data signals for each row. This disclosure also provides a PWM signal generation circuit to generate a Sweep signal applicable to the pixel circuit according to this disclosure. Furthermore, this disclosure provides a display substrate including the pixel circuit according to this disclosure, a display device including the display substrate according to this disclosure, and an electronic device including the display device according to this disclosure.

[0005] This disclosure provides a PWM signal generation circuit, including: a first signal transmission circuit; and a second signal transmission circuit, wherein a first output terminal of the first signal transmission circuit is connected to a second output terminal of the second signal transmission circuit and serves as the output terminal of the PWM signal generation circuit, wherein a first high level for generating a first output signal of the first signal transmission circuit is different from a second high level for generating a second output signal of the second signal transmission circuit, and the output signal of the PWM signal generation circuit has a step between the first high level and the second high level.

[0006] According to an embodiment of this disclosure, the first signal transmission circuit and the second signal transmission circuit are connected to a first clock signal and a second clock signal. The first clock signal and the second clock signal are periodic signals with the same waveform and a duty cycle of 20%-40%.

[0007] According to an embodiment of this disclosure, the first signal transmission circuit includes a first input module, a first forward voltage generation module, a first reverse voltage generation module, a first signal generation module, and a first output enable module. The first input module, the first forward voltage generation module, the first reverse voltage generation module, and the first signal generation module are connected to a first node of the first signal transmission circuit. The first forward voltage generation module and the first reverse voltage generation module are connected to a first control node of the first signal transmission circuit. The first reverse voltage generation module and the first signal generation module are connected to a second node of the first signal transmission circuit. The first signal generation module and the first output enable module are connected to a first output node of the first signal transmission circuit. The second signal transmission circuit includes a second input module, a second forward voltage generation module, a second reverse voltage generation module, a second signal generation module, and a second output enable module. The second input module, the second forward voltage generation module, the second reverse voltage generation module, and the second signal generation module are connected to a third node of the second signal transmission circuit. The second forward voltage generation module and the second reverse voltage generation module are connected to a second control node of the second signal transmission circuit. The second reverse voltage generation module and the second signal generation module are connected to a fourth node of the second signal transmission circuit. The second signal generation module and the second output enable module are connected to the second output node of the second signal transmission circuit.

[0008] According to an embodiment of this disclosure, the first input module includes a first input transistor, and the second input module includes a second input transistor. A first terminal of the first input transistor serves as a first input terminal of the first signal transmission circuit, a first input signal is applied to the first terminal of the first input transistor, a second terminal of the first input transistor is connected to the first node, and a second clock signal is applied to the gate of the first input transistor. A first terminal of the second input transistor serves as a second input terminal of the second signal transmission circuit, a second input signal is applied to the first terminal of the second input transistor, the second terminal of the second input transistor is connected to the third node, and the first clock signal is applied to the gate of the second input transistor.

[0009] According to embodiments of this disclosure, the first forward voltage generation module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the second forward voltage generation module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. A high-level signal is applied to a first terminal of the first transistor, the gate of the first transistor is connected to the first control node, and a second terminal of the first transistor is connected to a first terminal of the second transistor. A second terminal of the second transistor is connected to the first node, and a first clock signal is applied to the gate of the second transistor. A second clock signal is applied to a first terminal of the third transistor and a gate of the fourth transistor, the gate of the third transistor is connected to the first node, the second terminals of the third transistor and the fourth transistor are connected to the first control node, and a first terminal of the fourth transistor is connected to a low-level signal. A high-level signal is applied to a first terminal of the fifth transistor, the gate of the fifth transistor is connected to the second control node, and a second terminal of the fifth transistor is connected to a first terminal of the sixth transistor. A second terminal of the sixth transistor is connected to the third node, and the second clock signal is applied to the gate of the sixth transistor. The first clock signal is applied to the first terminal of the seventh transistor and the gate of the eighth transistor, the gate of the seventh transistor is connected to the third node, the second terminals of the seventh transistor and the eighth transistor are connected to the second control node, and the first terminal of the eighth transistor is connected to a low level.

[0010] According to an embodiment of this disclosure, the first reverse voltage generation module includes a ninth transistor, a tenth transistor, and an eleventh transistor, and the second reverse voltage generation module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. A high-level signal is applied to a first terminal of the ninth transistor, the gate of which is connected to the first node, and a second terminal of which is connected to the second node. The first terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and is connected to the first control node via a first capacitor. A first clock signal is applied to the gate of the tenth transistor and the first terminal of the eleventh transistor, the second terminal of which is connected to the second node, and the gate of the eleventh transistor is connected to the first control node. A high-level signal is applied to a first terminal of the twelfth transistor, the gate of which is connected to the third node, and a second terminal of which is connected to the fourth node. The first terminal of the thirteenth transistor is connected to the second terminal of the fourteenth transistor and is connected to the second control node via a second capacitor. A second clock signal is applied to the gate of the thirteenth transistor and the first terminal of the fourteenth transistor, the second terminal of which is connected to the fourth node, and the gate of the fourteenth transistor is connected to the second control node.

[0011] According to embodiments of this disclosure, the first signal generation module includes a fifteenth transistor and a sixteenth transistor, and the second signal generation module includes a seventeenth transistor and an eighteenth transistor. A first high-level voltage is applied to a first terminal of the fifteenth transistor, the gate of the fifteenth transistor is connected to the second node and is connected to the first terminal of the fifteenth transistor via a third capacitor, and the second terminal of the fifteenth transistor is connected to the first output node. The first terminal of the sixteenth transistor is connected to a low-level voltage, the gate of the sixteenth transistor is connected to the first node, and the second terminal of the sixteenth transistor is connected to the first output node. A second high-level voltage is applied to a first terminal of the seventeenth transistor, the gate of the seventeenth transistor is connected to the fourth node and is connected to the first terminal of the seventeenth transistor via a fourth capacitor, and the second terminal of the seventeenth transistor is connected to the second output node. The first terminal of the eighteenth transistor is connected to a low-level voltage, the gate of the eighteenth transistor is connected to the third node, and the second terminal of the eighteenth transistor is connected to the second output node.

[0012] According to an embodiment of this disclosure, the first output enable module includes a first output transistor, and the second output enable module includes a second output transistor. The first output transistor is connected between the first output node and the first output terminal, and the second output transistor is connected between the second output node and the second output terminal. The first output signal is output to the first output terminal via the first output transistor, and the second output signal is output to the second output terminal via the second output transistor. The first output signal is also output to the gate of the second output transistor as an output enable signal for the second signal transmission circuit, and the second output signal is also output to the gate of the first output transistor as an output enable signal for the first signal transmission circuit.

[0013] According to an embodiment of this disclosure, the first signal generation module further includes a fifth capacitor and a nineteenth transistor, and the second signal generation module further includes a sixth capacitor and a twentieth transistor. A first clock signal is applied to a first terminal of the fifth capacitor, and a second terminal of the fifth capacitor is connected to the gate of the sixteenth transistor. A second clock signal is applied to a second terminal of the sixth capacitor, and a second terminal of the sixth capacitor is connected to the gate of the eighteenth transistor. The gate of the sixteenth transistor is connected to the first node via the nineteenth transistor, and the gate of the eighteenth transistor is connected to the third node via the twentieth transistor.

[0014] According to an embodiment of this disclosure, the second high level is twice the first high level.

[0015] According to an embodiment of this disclosure, the output signal of the PWM signal generation circuit is at a first duration of the first high level and at a second duration of the second high level for different durations.

[0016] This disclosure also provides a pixel circuit, including: a driving module; a light-emitting control module; and a light-emitting element. The driving module is connected to the light-emitting control module, and the light-emitting control module and the light-emitting element are connected in series between a power supply voltage and a ground voltage. The light-emitting control module includes a first light-emitting control module and a second light-emitting control module connected to each other. The first light-emitting control module is connected to a first data signal and a first Sweep signal, and the second light-emitting control module is connected to a second data signal and a second Sweep signal. Both the first and second light-emitting control modules are connected to a first scan signal. The first Sweep signal and the second Sweep signal are different, and are generated by a PWM signal generation circuit according to embodiments of this disclosure.

[0017] According to an embodiment of this disclosure, the first light-emitting control module includes a first control transistor, a second control transistor, and a first control capacitor, and the second light-emitting control module includes a third control transistor, a fourth control transistor, and a second control capacitor. A first Sweep signal is applied to a first terminal of the first control capacitor, and a second terminal of the first control capacitor is connected to the gate of the first control transistor. A first data signal is applied to a first terminal of the second control transistor, a first scan signal is applied to the gate of the second control transistor, and a second terminal of the second control transistor is connected to the gate of the first control transistor. A second Sweep signal is applied to a first terminal of the second control capacitor, and a second terminal of the second control capacitor is connected to the gate of the third control transistor. A second data signal is applied to a first terminal of the fourth control transistor, the first scan signal is applied to the gate of the fourth control transistor, and a second terminal of the fourth control transistor is connected to the gate of the third control transistor. A first terminal of the first control transistor is connected to a first terminal of the third control transistor, and a second terminal of the first control transistor is connected to a second terminal of the third control transistor.

[0018] According to an embodiment of this disclosure, the driving module is connected to a second scan signal, and the driving module includes a first driving transistor, a second driving transistor, a third driving transistor, and a first driving capacitor. A driving current is applied to a first terminal of the first driving transistor and a first terminal of the second driving transistor. The second scan signal is applied to the gate of the first driving transistor and the gate of the second driving transistor. A second terminal of the first driving transistor is connected to a first terminal of the third driving transistor, and a second terminal of the second driving transistor is connected to the gate of the third driving transistor. A first terminal of the first driving capacitor is connected to the gate of the third driving transistor, and a second terminal of the first driving capacitor is connected to a second terminal of the third driving transistor.

[0019] According to an embodiment of this disclosure, the pixel circuit further includes a switching module. The switching module, the light-emitting control module, and the light-emitting element are connected in series between the power supply voltage and the ground voltage, and the driving module is connected to the light-emitting control module via the switching module.

[0020] According to an embodiment of this disclosure, the switching module includes a switching transistor, and the gate of the third driving transistor is connected to the gate of the switching transistor.

[0021] According to an embodiment of this disclosure, the driving module is connected to a first scan signal, a second scan signal, and a third scan signal, and the driving module includes a fourth driving transistor, a fifth driving transistor, a sixth driving transistor, a seventh driving transistor, an eighth driving transistor, a ninth driving transistor, and a second driving capacitor. The fourth driving transistor is connected between a first node of the driving module and the ground voltage, and the second scan signal is applied to the gate of the fourth driving transistor. The fifth driving transistor is connected between the first node of the driving module and the ground voltage, and the third scan signal is applied to the gate of the fifth driving transistor. The sixth driving transistor is connected between a second node of the driving module and the ground voltage, and the third scan signal is applied to the gate of the sixth driving transistor. The seventh driving transistor is connected between the first node of the driving module and a reference voltage, and the first scan signal is applied to the gate of the seventh driving transistor. The power supply voltage is applied to a first terminal of the eighth driving transistor, the gate of the eighth driving transistor is connected to the second node of the driving module, and the second terminal of the eighth driving transistor is connected to the second terminal of the ninth driving transistor. The first terminal of the ninth driving transistor is connected to the second node of the driving module, and the second scan signal is applied to the gate of the ninth driving transistor. The second driving capacitor is connected between the first node and the second node of the driving module.

[0022] This disclosure also provides a display substrate, including pixel circuits according to various embodiments of this disclosure.

[0023] This disclosure also provides a display device, including a display substrate according to embodiments of this disclosure.

[0024] This disclosure also provides an electronic device, including a display device according to embodiments of this disclosure.

[0025] According to the pixel circuit of this disclosure, an 8-bit Gamma 2.2 brightness scheme can be implemented using fewer subframes, thus ensuring that the refresh time of each subframe is sufficient for writing data signals for each row, even for applications with a large number of screen rows. According to the PWM signal generation circuit of this disclosure, a Sweep signal applicable to the pixel circuit of this disclosure can be generated, which is beneficial for implementing the pixel circuit according to the embodiments of this disclosure. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate embodiments of the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of detailed exemplary embodiments with reference to the accompanying drawings. The embodiments described herein are shown in the figures by way of example, not limitation. In the figures, similar reference numerals indicate similar elements. Moreover, for illustrative purposes, the figures are not drawn to scale.

[0027] Figure 1 illustrates a PWM signal generation circuit according to an embodiment of the present disclosure;

[0028] Figure 2 shows a timing diagram of a PWM signal generation circuit according to an embodiment of the present disclosure;

[0029] Figure 3 illustrates a pixel circuit according to an embodiment of the present disclosure;

[0030] Figure 4 illustrates another pixel circuit according to an embodiment of the present disclosure;

[0031] Figure 5 shows a timing diagram of the light emission control module in the pixel circuit according to an embodiment of the present disclosure;

[0032] Figure 6 illustrates an example of a transition of the Sweep signal used in a pixel circuit according to an embodiment of the present disclosure;

[0033] Figure 7 shows a timing diagram of a combination of three subframes in a pixel circuit according to an embodiment of the present disclosure;

[0034] Figures 8A to 8C show timing diagrams of a driving module in a pixel circuit according to an embodiment of the present disclosure;

[0035] Figure 9 shows a schematic block diagram of a display substrate according to an embodiment of the present disclosure;

[0036] Figure 10 shows a schematic block diagram of a display device according to an embodiment of the present disclosure; and

[0037] Figure 11 shows a schematic block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0038] To enable those skilled in the art to better understand the technical solutions of this disclosure, the PWM signal generation circuit, pixel circuit, display substrate, display device, and electronic device provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0039] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0040] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0041] As used herein, the term “and / or” includes any and all combinations of at least one related enumerated entry.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the said feature, integral, step, operation, element, and / or component is specified, but the presence or addition of at least one other feature, integral, step, operation, element, component, and / or group thereof is not excluded.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0044] Figure 1 illustrates a PWM signal generation circuit according to an embodiment of the present disclosure.

[0045] As shown in Figure 1, the PWM signal generation circuit according to an embodiment of this disclosure includes a first signal transmission circuit and a second signal transmission circuit. The first signal transmission circuit includes a first input module, a first forward voltage generation module, a first reverse voltage generation module, a first signal generation module, and a first output enable module; the second signal transmission circuit includes a second input module, a second forward voltage generation module, a second reverse voltage generation module, a second signal generation module, and a second output enable module.

[0046] The first output terminal of the first signal transmission circuit is connected to the second output terminal of the second signal transmission circuit, and serves as the output terminal of the PWM signal generation circuit.

[0047] As shown in Figure 1, the first high level VGH1 used to generate the first output signal EA(n) of the first signal transmission circuit is different from the second high level VGH2 used to generate the second output signal EB(n) of the second signal transmission circuit. Therefore, the output signal Sweep(n) of the PWM signal generation circuit has a step between the first high level VGH1 and the second high level VGH2 (see the Sweep(n) signal shown in Figure 2). How the output signal Sweep(n) is generated will be explained in detail later with reference to Figure 2.

[0048] As shown in Figure 1, the first input module, the first forward voltage generation module, the first reverse voltage generation module, and the first signal generation module are connected to the first node N1 of the first signal transmission circuit; the first forward voltage generation module and the first reverse voltage generation module are connected to the first control node CN1 of the first signal transmission circuit; the first reverse voltage generation module and the first signal generation module are connected to the second node N2 of the first signal transmission circuit; and the first signal generation module and the first output enable module are connected to the first output node ON1 of the first signal transmission circuit. The second input module, the second forward voltage generation module, the second reverse voltage generation module, and the second signal generation module are connected to the third node N3 of the second signal transmission circuit; the second forward voltage generation module and the second reverse voltage generation module are connected to the second control node CN2 of the second signal transmission circuit; the second reverse voltage generation module and the second signal generation module are connected to the fourth node N4 of the second signal transmission circuit; and the second signal generation module and the second output enable module are connected to the second output node ON2 of the second signal transmission circuit.

[0049] The first signal transmission circuit and the second signal transmission circuit are respectively connected to the first clock signal ECK1 and the second clock signal ECK2. The first clock signal ECK1 and the second clock signal ECK2 are periodic signals with the same waveform and a duty cycle of 20%-40% (see Figure 2). It should be understood that the "same waveform" mentioned herein includes reasonable errors within an acceptable range; that is, it refers to substantially the same waveform that can achieve the required function, but not necessarily to be exactly the same waveform.

[0050] As shown in Figure 1, the first input module includes a first input transistor IN_T1, and the second input module includes a second input transistor IN_T2.

[0051] The first terminal of the first input transistor IN_T1 serves as the first input terminal of the first signal transmission circuit, and the first input signal EA(n-1) is applied to the first terminal of the first input transistor IN_T1. The second terminal of the first input transistor IN_T1 is connected to the first node N1, and the second clock signal ECK2 is applied to the gate of the first input transistor IN_T1. The first terminal of the second input transistor IN_T2 serves as the second input terminal of the second signal transmission circuit, and the second input signal EB(n-1) is applied to the first terminal of the second input transistor IN_T2. The second terminal of the second input transistor IN_T2 is connected to the third node N3, and the first clock signal ECK1 is applied to the gate of the second input transistor IN_T2.

[0052] As shown in Figure 1, the first positive voltage generation module includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, and the second positive voltage generation module includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0053] A high-level voltage VGH is applied to the first terminal of the first transistor T1, whose gate is connected to the first control node CN1, and whose second terminal is connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 is connected to the first node N1, and a first clock signal ECK1 is applied to its gate. A second clock signal ECK2 is applied to the first terminal of the third transistor T3 and the gate of the fourth transistor T4, whose gate is connected to the first node N1, and whose second terminals are connected to the first control node CN1. The first terminal of the fourth transistor T4 is connected to a low-level voltage VGL.

[0054] A high-level voltage VGH is applied to the first terminal of the fifth transistor T5, whose gate is connected to the second control node CN2, and whose second terminal is connected to the first terminal of the sixth transistor T6. The second terminal of the sixth transistor T2 is connected to the third node N3, and a second clock signal ECK2 is applied to the gate of the sixth transistor T6. A first clock signal ECK1 is applied to the first terminal of the seventh transistor T7 and the gate of the eighth transistor T8, whose gate is connected to the third node N3, and whose second terminals are connected to the second control node CN2. The first terminal of the eighth transistor T8 is connected to a low-level voltage VGL.

[0055] As shown in Figure 1, the first reverse voltage generation module includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, and the second reverse voltage generation module includes a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0056] A high-level voltage VGH is applied to the first terminal of the ninth transistor T9, whose gate is connected to the first node N1, and whose second terminal is connected to the second node N2. The first terminal of the tenth transistor T10 is connected to the second terminal of the eleventh transistor T11, and is connected to the first control node CN1 via the first capacitor C1. A first clock signal ECK1 is applied to the gate of the tenth transistor T10 and the first terminal of the eleventh transistor T11, whose second terminal is connected to the second node N2, and whose gate is connected to the first control node CN1.

[0057] A high-level voltage VGH is applied to the first terminal of the twelfth transistor T12. The gate of the twelfth transistor T12 is connected to the third node N3, and the second terminal of the twelfth transistor T12 is connected to the fourth node N4. The first terminal of the thirteenth transistor T13 is connected to the second terminal of the fourteenth transistor T14, and is connected to the second control node CN2 via the second capacitor C2. A second clock signal ECK2 is applied to the gate of the thirteenth transistor T13 and the first terminal of the fourteenth transistor T14. The second terminal of the thirteenth transistor T13 is connected to the fourth node N4, and the gate of the fourteenth transistor T14 is connected to the second control node CN2.

[0058] As shown in Figure 1, the first signal generation module includes a fifteenth transistor T15 and a sixteenth transistor T16, and the second signal generation module includes a seventeenth transistor T17 and an eighteenth transistor T18.

[0059] A first high-level voltage VGH1 is applied to the first terminal of the fifteenth transistor T15. The gate of the fifteenth transistor T15 is connected to the second node N2 and is also connected to the first terminal of the fifteenth transistor T15 via the third capacitor C3. The second terminal of the fifteenth transistor T15 is connected to the first output node ON1. The first terminal of the sixteenth transistor T16 is connected to the low-level voltage VGL. The gate of the sixteenth transistor T16 is connected to the first node N1, and the second terminal of the sixteenth transistor T16 is connected to the first output node ON1.

[0060] A second high-level voltage VGH2 is applied to the first terminal of the seventeenth transistor T17. The gate of the seventeenth transistor T17 is connected to the fourth node N4 and is also connected to the first terminal of the seventeenth transistor T17 via the fourth capacitor C4. The second terminal of the seventeenth transistor T17 is connected to the second output node ON2. The first terminal of the eighteenth transistor T18 is connected to the low-level voltage VGL. The gate of the eighteenth transistor T18 is connected to the third node N3, and the second terminal of the eighteenth transistor T18 is connected to the second output node ON2.

[0061] As shown in Figure 1, the first signal generation module further includes a fifth capacitor C5 and a nineteenth transistor T19, and the second signal generation module further includes a sixth capacitor C6 and a twentieth transistor T20.

[0062] A first clock signal, ECK1, is applied to the first terminal of the fifth capacitor C5, and the second terminal of the fifth capacitor C5 is connected to the gate of the sixteenth transistor T16. A second clock signal, ECK2, is applied to the second terminal of the sixth capacitor C6, and the second terminal of the sixth capacitor C6 is connected to the gate of the eighteenth transistor T18. The gate of the sixteenth transistor T16 is connected to the first node N1 via the nineteenth transistor T19, and the gate of the eighteenth transistor T18 is connected to the third node N3 via the twentieth transistor T20.

[0063] As shown in Figure 1, the first output enable module includes a first output transistor OUT_T1, and the second output enable module includes a second output transistor OUT_T2. The first output transistor OUT_T1 is connected between the first output node ON1 and the first output terminal of the first signal transmission circuit, and the second output transistor OUT_T2 is connected between the second output node OUT_T2 and the second output terminal of the second signal transmission circuit.

[0064] The first output signal EA(n) is output to the first output terminal of the first signal transmission circuit via the first output transistor OUT_T1, and the second output signal EB(n) is output to the second output terminal of the second signal transmission circuit via the second output transistor OUT_T2. The first output signal EA(n) is also output to the gate of the second output transistor OUT_T2 as an output enable signal for the second signal transmission circuit, and the second output signal EB(n) is also output to the gate of the first output transistor OUT_T1 as an output enable signal for the first signal transmission circuit.

[0065] It should be recognized that the high level VGH shown in Figure 1 can be the same level or different levels from the first high level VGH1 or the second high level VGH2.

[0066] The high-level VGH shown in Figure 1 is used to set the first node N1, the second node N2, the third node N3 and the fourth node N4, thereby turning off each transistor connected to the first node N1, the second node N2, the third node N3 and the fourth node N4 respectively. Therefore, the high-level VGH can be implemented as the cutoff voltage of each transistor.

[0067] On the other hand, the first high level VGH1 and the second high level VGH2 shown in Figure 1 are used to generate the high levels at which the first output signal EA(n) and the second output signal EB(n) are located, respectively, thereby generating the output signal Sweep(n) with a step between the first high level VGH1 and the second high level VGH2. Therefore, the first high level VGH1 and the second high level VGH2 are different from each other. For example, the second high level VGH2 can be twice the first high level VGH1.

[0068] The PWM signal generation circuit shown in Figure 1 is used to drive a display substrate with multiple rows of pixel circuits. In each row of pixel circuits, the first row to be driven is called the "startup row" or "startup stage." For the startup row (or startup stage), a startup input signal is input. Within the same stage, the output signal and the input signal have the same waveform and a fixed phase difference. Between subsequent stages, the output signal of the previous stage (e.g., the first output signal and the second output signal) serves as the input signal of the next stage (e.g., the first input signal and the second input signal), thus ensuring that the initial startup input signal is transmitted between stages with a fixed phase difference.

[0069] The following will describe in detail, with reference to FIG2, how to obtain an output signal Sweep(n) with a first duration at a first high level and a second duration at a second high level through the PWM signal generation circuit of the present disclosure embodiment.

[0070] Figure 2 shows a timing diagram of a PWM signal generation circuit according to an embodiment of the present disclosure.

[0071] Referring to Figures 1 and 2, during time period P1, both the first clock signal ECK1 and the second clock signal ECK2 are at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0072] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0073] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0074] Both the first output transistor OUT_T1 and the second output transistor OUT_T2 are turned on, and the output signal Sweep(n) is at a low level.

[0075] During time period P2, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0076] In the first signal transmission circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the high level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at a high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned off; the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at a low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at a high level, and the fifteenth transistor T15 is turned off; the first output node ON1 is maintained at a low level, and the first output signal EA(n) is at a low level.

[0077] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is on, the eighth transistor T8 is off, and the thirteenth transistor T13 is on; the third node N3 is maintained at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0078] Both the first output transistor OUT_T1 and the second output transistor OUT_T2 are turned on, and the output signal Sweep(n) is at a low level.

[0079] During time period P3, both the first clock signal ECK1 and the second clock signal ECK2 are at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0080] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are on; the second node N2 is maintained at a high level, and the fifteenth transistor T15 is off; the first output node ON1 is maintained at a low level, and the first output signal EA(n) is at a low level.

[0081] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0082] Both the first output transistor OUT_T1 and the second output transistor OUT_T2 are turned on, and the output signal Sweep(n) is at a low level.

[0083] During time period P4, the first clock signal ECK1 is at a low level, the second clock signal ECK2 is at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0084] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is on, the fourth transistor T4 is off, and the tenth transistor T10 is on; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are on; a high level is applied to the first node N1 through the first transistor T1 and the second transistor T2, and the first node N1 is at a high level, while the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the low level of the first clock signal ECK1 is applied to the second node N2 through the eleventh transistor T11 and the tenth transistor T10, and the second node N2 is at a low level, while the fifteenth transistor T15 is on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, and the first output node ON1 is at the first high level VGH1, while the first output signal EA(n) is at the first high level VGH1.

[0085] In the second signal transmission circuit: the second input transistor IN_T2 is turned on, the sixth transistor T6 is turned off, the eighth transistor T8 is turned on, and the thirteenth transistor T13 is turned off; the low level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the low level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, and the low level is applied to the control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are turned on; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is turned off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0086] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0087] During time period P5, both the first clock signal ECK1 and the second clock signal ECK2 are at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0088] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0089] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0090] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0091] During time period P6, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0092] In the first signal transmission circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the high level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at a high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned off; the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at a low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is turned on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0093] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is on, the eighth transistor T8 is off, and the thirteenth transistor T13 is on; the third node N3 is maintained at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0094] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0095] During time period P7, both the first clock signal ECK1 and the second clock signal ECK2 are at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0096] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0097] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0098] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0099] During time period P8, the first clock signal ECK1 is at a low level, the second clock signal ECK2 is at a high level, the first input signal EA(n-1) is at a low level, and the second input signal EB(n-1) is at a high level.

[0100] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is on, the fourth transistor T4 is off, and the tenth transistor T10 is on; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are on; a high level is applied to the first node N1 through the first transistor T1 and the second transistor T2, and the first node N1 is at a high level, while the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the low level of the first clock signal ECK1 is applied to the second node N2 through the eleventh transistor T11 and the tenth transistor T10, and the second node N2 is at a low level, while the fifteenth transistor T15 is on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, and the first output node ON1 is at the first high level VGH1, while the first output signal EA(n) is at the first high level VGH1.

[0101] In the second signal transmission circuit: the second input transistor IN_T2 is turned on, the sixth transistor T6 is turned off, the eighth transistor T8 is turned on, and the thirteenth transistor T13 is turned off; the high level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned off; the low level is applied to the control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are turned on; the fourth node N4 is maintained at a high level, and the seventeenth transistor T17 is turned off; the second output node ON2 is maintained at a low level, and the second output signal EB(n) is at a low level.

[0102] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0103] During time period P9, the first clock signal ECK1 and the second clock signal ECK2 are both at a high level, the first input signal EA(n-1) is at a low level, and the second input signal EB(n-1) is at a high level.

[0104] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0105] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the second control node CN2 is maintained at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are on; the fourth node N4 is maintained at a high level, and the seventeenth transistor T17 is off; the second output node ON2 is maintained at a low level, and the second output signal EB(n) is at a low level.

[0106] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0107] During time period P10, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, the first input signal EA(n-1) is at a low level, and the second input signal EB(n-1) is at a high level.

[0108] In the first signal transmission circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the low level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the low level of the second clock signal ECK2 is applied to the first control node CN1 through the T3 transistor, the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at a low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is turned off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0109] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is on, the eighth transistor T8 is off, and the thirteenth transistor T13 is on; the second control node CN2 is maintained at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are on; a high level is applied to the third node N3 through the fifth transistor T5 and the sixth transistor T6, the third node N3 is at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the low level of the second clock signal ECK2 is applied to the fourth node N4 through the fourteenth transistor T14 and the thirteenth transistor T13, the fourth node N4 is at a low level, and the seventeenth transistor T17 is on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0110] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0111] During time period P11, both the first clock signal ECK1 and the second clock signal ECK2 are at a high level, the first input signal EA(n-1) is at a low level, and the second input signal EB(n-1) is at a high level.

[0112] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0113] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the second control node CN2 is maintained at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are on; the fourth node N4 is maintained at a low level, and the seventeenth transistor T17 is on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0114] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0115] During time period P12, the first clock signal ECK1 is at a low level, the second clock signal ECK2 is at a high level, the first input signal EA(n-1) is at a low level, and the second input signal EB(n-1) is at a high level.

[0116] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is on, the fourth transistor T4 is off, and the tenth transistor T10 is on; the first node N1 is maintained at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0117] In the second signal transmission circuit: the second input transistor IN_T2 is turned on, the sixth transistor T6 is turned off, the eighth transistor T8 is turned on, and the thirteenth transistor T13 is turned off; the high level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned off; the low level is applied to the second control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are turned on; the fourth node N4 is maintained at a low level, and the seventeenth transistor T17 is turned on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0118] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0119] During time periods P13, P15, and P17, the state of the circuit is the same as during time period P11; during time periods P14 and P16, the state of the circuit is the same as during time period P12, which will not be repeated here.

[0120] During time period P18, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, and the first input signal EA(n-1) and the second input signal EB(n-1) are both at a low level.

[0121] In the first signal transmission circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the low level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the low level of the second clock signal ECK2 is applied to the first control node CN1 through the T3 transistor, the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at a low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is turned off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0122] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is on, the eighth transistor T8 is off, and the thirteenth transistor T13 is on; the second control node CN2 is maintained at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are on; a high level is applied to the third node N3 through the fifth transistor T5 and the sixth transistor T6, the third node N3 is at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the low level of the second clock signal ECK2 is applied to the fourth node N4 through the fourteenth transistor T14 and the thirteenth transistor T13, the fourth node N4 is at a low level, and the seventeenth transistor T17 is on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0123] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0124] During time period P19, both the first clock signal ECK1 and the second clock signal ECK2 are at a high level, while both the first input signal EA(n-1) and the second input signal EB(n-1) are at a low level.

[0125] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0126] In the second signal transmission circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the second control node CN2 is maintained at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are on; the fourth node N4 is maintained at a low level, and the seventeenth transistor T17 is on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0127] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0128] During time period P20, the first clock signal ECK1 is at a low level, the second clock signal ECK2 is at a high level, and the first input signal EA(n-1) and the second input signal EB(n-1) are both at a low level.

[0129] In the first signal transmission circuit: the first input transistor IN_T1 is off, the second transistor T2 is on, the fourth transistor T4 is off, and the tenth transistor T10 is on; the first node N1 is maintained at a low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0130] In the second signal transmission circuit: the second input transistor IN_T2 is turned on, the sixth transistor T6 is turned off, the eighth transistor T8 is turned on, and the thirteenth transistor T13 is turned off; the low level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the low level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, and the low level is applied to the control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are turned on; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is turned off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0131] Both the first output transistor OUT_T1 and the second output transistor OUT_T2 are turned on, and the output signal Sweep(n) is at a low level.

[0132] It should be recognized that time period P1 is a time period unique to the startup level and is not included when passing data between subsequent levels.

[0133] Furthermore, Figure 2 shows that the high-level period of the first input signal EA(n-1) includes the time period P1. However, it should be understood that since the time period P1 is unique to the startup stage, the high-level period of the first input signal EA(n-1) will not include the time period P1 when passing between subsequent stages. For example, when the first output signal EA(n) is used as the input signal for the next stage (i.e., stage n+1), its high-level period will no longer include the time period corresponding to time period P1. In other words, for the startup stage (i.e., n=1), EA(n-1) (i.e., EA(0)) shown in Figure 2 needs to be provided as the first input signal of the startup stage.

[0134] It should also be recognized that the first input signal EA(0) and the second input signal EB(0) (i.e., the start input signal) provided in the startup stage are transmitted between subsequent stages (excluding the time period P1 of the first input signal EA(0)). In each stage, the phase difference between the first input signal EA(n-1) and the first output signal EA(n) is the same as the phase difference between the first clock signal ECK1 and the second clock signal ECK2 (ignoring the time period P1 included in the first input signal EA(0) of the startup stage), and the phase difference between the second input signal EB(n-1) and the second output signal EB(n) is the same as the phase difference between the first clock signal ECK1 and the second clock signal ECK2. Since the first clock signal ECK1 and the second clock signal ECK2 are periodic signals with the same waveform and a duty cycle of 20%-40%, the initial start input signal is transmitted between stages with a fixed phase difference.

[0135] It should also be recognized that the first duration of the output signal Sweep(n) at the first high level VGH1 is the same as the duration of the first output signal EA(n) at the first high level VGH1, and the second duration of the output signal Sweep(n) at the second high level VGH2 is the same as the duration of the second output signal EB(n) at the second high level VGH2. In order for the first duration of the output signal Sweep(n) at the first high level VGH1 and the second duration at the second high level VGH2 to be different, the duration of the first output signal EA(n) at the first high level VGH1 and the duration of the second output signal EB(n) at the second high level VGH2 should be different. Since the first input signal EA(n-1) and the first output signal EA(n) have the same waveform and a fixed phase difference, and the second input signal EB(n-1) and the second output signal EB(n) have the same waveform and a fixed phase difference, the duration of the first input signal EA(n-1) at the first high level VGH1 and the duration of the second input signal EB(n-1) at the second high level VGH2 should be different. Therefore, it can be deduced that the start input signals EA(0) and EB(0) should each have different high-level time periods.

[0136] For example, referring to Figures 1 and 2, the low-level portions of the first clock signal ECK1 and the second clock signal ECK2 can turn on the connected transistors (e.g., the second transistor T2 and the fourth transistor T4). Therefore, the low-level portions of the first clock signal ECK1 and the second clock signal ECK2 shown in Figure 2 (e.g., time periods P2 and P4) are referred to as the "enable portions". The high-level time period of the first input signal EA(n-1) covers three enable portions of the first clock signal ECK1 and the second clock signal ECK2 (time periods P2, P4, and P6), and the high-level time period of the second input signal EB(n-1) covers five enable portions of the first clock signal ECK1 and the second clock signal ECK2 (time periods P8, P10, P12, P14, and P16).

[0137] By adjusting the high-level time periods of the start-up input signals EA(0) and EB(0), respectively covering different amounts of the enable portions of the first clock signal ECK1 and the second clock signal ECK2, the first duration of the output signal Sweep(n) at the first high level VGH1 and the second duration at the second high level VGH2 can be made different. Furthermore, multiple output signals Sweep can be implemented, each with a different first duration (at the first high level VGH1) and a different second duration (at the second high level VGH2).

[0138] According to the PWM signal generation circuit of this disclosure, a Sweep signal that can be applied to the pixel circuit according to this disclosure can be generated. By combining different Sweep signals, it is advantageous to realize the pixel circuit according to the embodiments of this disclosure.

[0139] The inventors of this application noted that when using PWM driving to drive LED displays, at least 10 to 12 subframes are required to achieve an 8-bit Gamma 2.2 brightness scheme. Assuming 12 subframes, the refresh time for each subframe is (1 / 60Hz) / 12 = 1.4ms. For applications with a small number of display screen lines (e.g., wearable devices like smartwatches), where the screen typically has 480 to 600 lines, the write time for each line of data signal is 1.4ms / 600 = 2.3μs, which basically meets the data write time requirements. However, for applications with a large number of display screen lines (e.g., mobile phones or televisions), where the screen typically has around 2000 to 4000 lines, the write time for each line of data signal is less than 1μs, resulting in a severely insufficient data write time.

[0140] To address this issue, this disclosure proposes a pixel circuit that can implement an 8-bit Gamma 2.2 brightness scheme using fewer subframes (e.g., 3 subframes), thereby ensuring that the refresh time of each subframe is sufficient for writing data signals for each row, even for applications with a large number of screen rows.

[0141] Specifically, in the technical solution of this disclosure, the gate driver on array (GOA) may include 2N rows (N is the number of rows on the display screen), with two rows of driving circuits corresponding to one row of pixel circuits. That is, two different Sweep signals are generated using the PWM signal generation circuits of two embodiments of this disclosure, and then these two different Sweep signals are applied to one row of pixel circuits, enabling each subframe to achieve nine different emission durations. The nine emission durations of each of the three subframes are different from each other, thus enabling the writing of 9×9×9=729 gray levels through three subframes to achieve an 8-bit Gamma 2.2 brightness scheme. The pixel circuit according to this disclosure will now be described in detail with reference to Figures 3 and 4.

[0142] Figure 3 illustrates a pixel circuit according to an embodiment of the present disclosure, and Figure 4 illustrates another pixel circuit according to an embodiment of the present disclosure.

[0143] Referring to Figures 3 and 4, the pixel circuit according to an embodiment of this disclosure includes: a driving module; a light emission control module; and a light emission element. The driving module is connected to the light emission control module, and the light emission control module and the light emission element are connected in series between the power supply voltage ELVDD and the ground voltage VSS.

[0144] The light-emitting control module includes a first light-emitting control module and a second light-emitting control module connected to each other. The first light-emitting control module is connected to a first data signal and a first Sweep signal Sweep1(n), and the second light-emitting control module is connected to a second data signal and a second Sweep signal Sweep2(n). Both the first and second light-emitting control modules are connected to a first scan signal Scan(n). The first Sweep signal Sweep1(n) and the second Sweep signal Sweep2(n) are different, and the first Sweep signal Sweep1(n) and the second Sweep signal Sweep2(n) are generated respectively by the PWM signal generation circuits of various embodiments of this disclosure.

[0145] As shown in Figures 3 and 4, the first light-emitting control module includes a first control transistor CT1, a second control transistor CT2, and a first control capacitor CC1, and the second light-emitting control module includes a third control transistor CT3, a fourth control transistor CT4, and a second control capacitor CC2.

[0146] A first Sweep signal, Sweep1(n), is applied to the first terminal of the first control capacitor CC1, and the second terminal of the first control capacitor CC1 is connected to the gate of the first control transistor CT1. A first data signal, Data1, is applied to the first terminal of the second control transistor CT2, a first scan signal, Scan(n), is applied to the gate of the second control transistor CT2, and the second terminal of the second control transistor CT2 is connected to the gate of the first control transistor CT1.

[0147] A second Sweep signal, Sweep2(n), is applied to the first terminal of the second control capacitor CC2, and the second terminal of the second control capacitor CC2 is connected to the gate of the third control transistor CT3. A second data signal, Data2, is applied to the first terminal of the fourth control transistor CT4, a first scan signal, Scan(n), is applied to the gate of the fourth control transistor CT4, and the second terminal of the fourth control transistor CT4 is connected to the gate of the third control transistor CT3.

[0148] The first terminal of the first control transistor CT1 is connected to the first terminal of the third control transistor CT3, and the second terminal of the first control transistor CT1 is connected to the second terminal of the third control transistor CT3.

[0149] The operation timing of the light emission control module in the pixel circuit according to an embodiment of the present disclosure will now be described with reference to FIG5.

[0150] Figure 5 shows a timing diagram of the light emission control module in a pixel circuit according to an embodiment of the present disclosure.

[0151] Referring to Figures 3 to 5, during time period CP1, the positions of points A and B are the data values ​​of the previous frame, and the first control transistor CT1 and the third control transistor CT3 are turned off.

[0152] During time period CP2, the first scan signal Scan(n) is high, the second control transistor CT2 and the fourth control transistor CT4 are turned on, and the values ​​corresponding to the first data signal Data1 and the second data signal Data2 are written at points A and B respectively. That is, the potential at point A is data1 and the potential at point B is data2.

[0153] In this embodiment, the Sweep signal (i.e., the first Sweep signal Sweep1(n) and the second Sweep signal Sweep2(n)) is a signal generated by the PWM signal generation circuit according to the embodiments of this disclosure. Such a Sweep signal has a step between the first high level VGH1 and the second high level VGH2. That is, the Sweep signal used in this embodiment has two transitions: the first transition is from the low level VGL to the first high level VGH1, and the second transition is from the first high level VGH1 to the second high level VGH2.

[0154] During time period CP3, the first Sweep signal Sweep1(n) transitions from low level VGL to first high level VGH1; during time period CP4, the first Sweep signal Sweep1(n) transitions from first high level VGH1 to second high level VGH2; during time period CP5, the second Sweep signal Sweep2(n) transitions from low level VGL to first high level VGH1; during time period CP6, the second Sweep signal Sweep2(n) transitions from first high level VGH1 to second high level VGH2.

[0155] Referring to Figure 6, assume the amplitude of each transition is ΔV, i.e., the first high level VGH1 = ΔV, and the second high level VGH2 = 2ΔV. Accordingly, during time period CP3, the potential at point A is data1 + ΔV; during time period CP4, the potential at point A is data1 + 2ΔV; during time period CP5, the potential at point B is data2 + ΔV; and during time period CP6, the potential at point B is data2 + 2ΔV.

[0156] Therefore, the following three situations may occur:

[0157] Case 1: The written value data1 is negative, i.e., -V, and -V+ΔV is greater than the turn-on voltage of the first control transistor CT1. Therefore, the light-emitting element emits light in both time periods shown in E0 and E1.

[0158] Case 2: -V+ΔV is less than the turn-on voltage of the first control transistor CT1, and -V+2ΔV is greater than the turn-on voltage of the first control transistor CT1. Therefore, the light-emitting element does not emit light during the time period indicated by E0, and emits light during the time period indicated by E1.

[0159] Case 3: -V+ΔV and -V+2ΔV are both less than the turn-on voltage of the first control transistor CT1. Therefore, the light-emitting element does not emit light in the two time periods shown in E0 and E1.

[0160] Similar to the value data1, the writing of the value data2 will also involve the above three scenarios. Based on the combination of these scenarios, the following nine different light emission durations can be formed:

[0161] No light; E1; E3; E0+E1; E2+E3; E1+E3; E1+E2+E3; E0+E1+E3; E0+E1+E2+E3.

[0162] It should be recognized that the first duration E0 of the first Sweep signal Sweep1(n) at the first high level VGH1 and the second duration E1 at the second high level VGH2 are different, and the first duration E2 of the second Sweep signal Sweep2(n) at the first high level VGH1 and the second duration E3 at the second high level VGH2 are different. Therefore, the above nine different light emission durations can be obtained.

[0163] Figure 7 shows the timing diagram of the combination of the three subframes.

[0164] As shown in Figure 7, each subframe corresponds to four emission durations: the first subframe corresponds to E0, E1, E2, and E3; the second subframe corresponds to E4, E5, E6, and E7; and the third subframe corresponds to E8, E9, E10, and E11. E0 to E11 are different from each other.

[0165] Based on the above analysis, each subframe contains 9 different light emission durations. By combining three subframes, 729 gray levels can be written, thus realizing an 8-bit Gamma2.2 brightness scheme.

[0166] Referring back to Figure 3, according to an embodiment of this disclosure, the driving module of the pixel circuit is connected to a second scan signal Scan(n-1), and the driving module includes a first driving transistor DT1, a second driving transistor DT2, a third driving transistor DT3, and a first driving capacitor DC1.

[0167] Drive current I Pixel A second scan signal Scan(n-1) is applied to the first terminal of the first driving transistor DT1 and the first terminal of the second driving transistor DT2. The second terminal of the first driving transistor DT1 is connected to the first terminal of the third driving transistor DT3, and the second terminal of the second driving transistor DT2 is connected to the gate of the third driving transistor DT3. The first terminal of the first driving capacitor DC1 is connected to the gate of the third driving transistor DT3, and the second terminal of the first driving capacitor DC1 is connected to the second terminal of the third driving transistor DT3.

[0168] As shown in Figure 3, the pixel circuit according to the disclosed embodiment may further include a switching module. The switching module, the light emission control module, and the light emission element are connected in series between the power supply voltage ELVDD and the ground voltage Vss, and the driving module is connected to the light emission control module and the light emission element via the switching module.

[0169] As shown in Figure 3, the switching module includes a switching transistor ST, and the gate of the third driving transistor DT3 is connected to the gate of the switching transistor ST.

[0170] Referring to the timing diagram in Figure 5, during time period CP1, the second scan signal Scan(n-1) is high, the first driving transistor DT1 and the second driving transistor DT2 are turned on, and the driving current I... Pixel Point C is charged through the second driving transistor DT2. When the voltage across the first driving capacitor DC1 reaches a certain value, the driving current I... Pixel The current flows from the first driving transistor DT1 to the third driving transistor DT3. Since the gate voltages of the third driving transistor DT3 and the switching transistor ST are equal, according to the current mirror principle, the current I flowing through the light-emitting element... LED The following calculation formula is satisfied:

[0171] in, μ is the field-effect mobility, C OX Let W be the capacitance per unit area of ​​the insulating layer, and L be the channel width and length of the MOSFET, respectively. Since the third driving transistor DT3 and the switching transistor ST can be manufactured using the same process, therefore... It is a constant.

[0172] During the pixel emission driving stage, the switching transistor ST operates in the saturation region, and the threshold voltage V does not need to be considered. th Therefore, the light-emitting driving current of all pixels is consistent, and there is no color shift.

[0173] Referring back to Figure 4, according to an embodiment of this disclosure, the driving module of the pixel circuit can employ constant current control. The current of the LED can control the brightness of the entire screen's LED illumination duration, unaffected by voltage drop (IR drop).

[0174] As shown in Figure 4, the driving module is connected to a first scan signal Scan(n), a second scan signal Scan(n-1) and a third scan signal Scan(n-2), and the driving module includes a fourth driving transistor DT4, a fifth driving transistor DT5, a sixth driving transistor DT6, a seventh driving transistor DT7, an eighth driving transistor DT8, a ninth driving transistor DT9 and a second driving capacitor DC2.

[0175] The fourth driving transistor DT4 is connected between the first node Node1 of the driving module and the ground voltage Vss, and the second scan signal Scan(n-1) is applied to the gate of the fourth driving transistor DT4.

[0176] The fifth driving transistor DT5 is connected between the first node Node1 of the driving module and the ground voltage Vss, and the third scan signal Scan(n-2) is applied to the gate of the fifth driving transistor DT5.

[0177] The sixth driving transistor DT6 is connected between the second node Node2 of the driving module and the ground voltage Vss, and the third scan signal Scan(n-2) is applied to the gate of the sixth driving transistor DT6.

[0178] The seventh driving transistor DT7 is connected between the first node Node1 of the driving module and the reference voltage Vref, and the first scan signal Scan(n) is applied to the gate of the seventh driving transistor DT7.

[0179] The power supply voltage ELVDD is applied to the first terminal of the eighth driving transistor DT8. The gate of the eighth driving transistor DT8 is connected to the second node Node2 of the driving module, and the second terminal of the eighth driving transistor DT8 is connected to the second terminal of the ninth driving transistor DT9.

[0180] The first terminal of the ninth driving transistor DT9 is connected to the second node Node2 of the driving module, and the second scan signal Scan(n-1) is applied to the gate of the ninth driving transistor DT9.

[0181] The second driving capacitor DC2 is connected between the first node Node1 and the second node Node2 of the driving module.

[0182] In the circuit diagram shown in Figure 4, the fourth driving transistor DT4 to the ninth driving transistor DT9 constitute the constant current control unit. Since the current is constant when the LED is emitting light, there is no color shift problem. Adding this structure can reduce the threshold voltage V of the inter-pixel switching transistors. th Different LEDs produce different currents. Furthermore, as the driving current of an LED increases, its photoelectric efficiency also increases.

[0183] The operation timing of the drive module (i.e., constant current control unit) in this embodiment will be described below with reference to Figures 8A to 8C.

[0184] Figures 8A to 8C show timing diagrams of a driving module in a pixel circuit according to an embodiment of the present disclosure.

[0185] As shown in Figure 8A, during time period DP1, the third scan signal Scan(n-2) is high, and the fifth driving transistor DT5 and the sixth driving transistor DT6 are turned on. The first scan signal Scan(n) and the second scan signal Scan(n-1) are low, and the fourth driving transistor DT4, the seventh driving transistor DT7, and the ninth driving transistor DT9 are turned off. The ground voltage Vss is applied to the first node Node1 and the second node Node2 via the fifth driving transistor DT5 and the sixth driving transistor DT6 to reset the first node Node1 and the second node Node2.

[0186] As shown in Figure 8B, during time period DP2, the second scan signal Scan(n-1) is high, and the fourth driving transistor DT4 and the ninth driving transistor DT9 are turned on. The first scan signal Scan(n) and the third scan signal Scan(n-2) are low, and the fifth driving transistor DT5, the sixth driving transistor DT6, and the seventh driving transistor DT7 are turned off. The power supply voltage ELVDD is applied to the second node Node2 via the eighth driving transistor DT8 and the ninth driving transistor DT9 to charge the second node Node2. When the potential of the second node Node2 is charged to ELVDD+V... th At that time, the eighth driving transistor DT8 is turned off, V th This is the threshold voltage of the eighth driving transistor DT8.

[0187] As shown in Figure 8C, during time period DP3, the first scan signal Scan(n) is high, and the seventh driving transistor DT7 is turned on. The second scan signal Scan(n-1) and the third scan signal Scan(n-2) are low, and the fourth driving transistor DT4, the fifth driving transistor DT5, the sixth driving transistor DT6, and the ninth driving transistor DT9 are turned off. The potential of the first node Node1 changes from ground voltage Vss to reference voltage Vref. The potential of the second node Node2 changes from voltage ELVDD+V th The transition to voltage ELVDD+V th +Vref-Vss.

[0188] Table 1 lists the potentials of the first node Node1 and the second node Node2 during time period DP1 to time period DP3.

[0189] Table 1

[0190] The current flowing through the eighth driving transistor DT8 is the source-drain current I. ds The calculation is performed using the following formula: I ds =k*(V gs -V th ) 2 =k*(ELVDD+V) th +Vref-Vss-ELVDD-V th ) 2 = k*(Vref-Vss) 2

[0191] Among them, V gs V is the gate-source voltage of the eighth driving transistor DT8. th is the threshold voltage of the eighth driving transistor DT8, and k is a constant related to the W / L capacitance mobility of the eighth driving transistor DT8 (W and L are the channel width and length of the MOS transistor, respectively).

[0192] As can be seen from the above formula, the current through the eighth driving transistor DT8 is the source-drain current I. ds It is only related to the reference voltage Vref and the ground voltage Vss, thus achieving constant current control.

[0193] According to the pixel circuit of the present disclosure, an 8-bit Gamma 2.2 brightness scheme can be achieved using fewer subframes. Therefore, even for applications with a large number of screen rows, the refresh time of each subframe is sufficient for writing data signals for each row. According to the pixel circuit driving module shown in Figure 3, during the pixel emission driving stage, the switching transistor ST operates in the saturation region, and the threshold voltage V does not need to be considered. thTherefore, the light-emitting driving current of all pixels is consistent, and there is no color shift. According to the pixel circuit driving module shown in Figure 4, since the current is constant when the LED emits light, there is no color shift problem. Adding this structure can reduce the threshold voltage V of the switching transistors between pixels. th Different LEDs produce different currents. Furthermore, as the driving current of an LED increases, its photoelectric efficiency also increases.

[0194] The PWM signal generation circuit according to this disclosure can generate a Sweep signal that can be applied to the pixel circuit according to this disclosure, which is beneficial for realizing the pixel circuit according to the embodiments of this disclosure.

[0195] Figure 9 shows a schematic block diagram of a display substrate according to an embodiment of the present disclosure.

[0196] The display substrate according to embodiments of the present disclosure may include pixel circuits according to various embodiments of the present disclosure.

[0197] Figure 10 shows a schematic block diagram of a display device according to an embodiment of the present disclosure.

[0198] The display device according to embodiments of the present disclosure may include a display substrate according to embodiments of the present disclosure.

[0199] Figure 11 shows a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0200] An electronic device according to an embodiment of the present disclosure may include a display device according to an embodiment of the present disclosure.

[0201] The display substrate, display device, and electronic device according to embodiments of the present disclosure all include pixel circuits according to embodiments of the present disclosure, thereby enabling the implementation of an 8-bit Gamma 2.2 brightness scheme using fewer subframes. Even for applications with a large number of screen rows, the refresh time of each subframe is sufficient for writing data signals for each row.

[0202] It should be understood that although specific types of transistors, such as low-level-on transistors and high-level-on transistors, are shown in the various figures, those skilled in the art will appreciate that the shown transistors can be replaced with other types of transistors as needed, and various corresponding control signals can be applied according to the adjusted circuit. This disclosure is intended to protect all such modified technical solutions.

[0203] In this disclosure, the terms first, second, third, etc., may be used to describe various elements, and these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0204] In this disclosure, references to a layer, region, or substrate “on” or “extending” to another element mean that it can be directly on or extend directly to another element, or that there may be intermediate elements. Furthermore, when an element is referred to as “connected” or “coupled” to another element, it can be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intermediate elements.

[0205] In this disclosure, references to "an embodiment," "some embodiments," "one or more embodiments," or "embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" throughout this disclosure does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0206] Although this disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A pulse width modulation (PWM) signal generation circuit, comprising: First signal transmission circuit; as well as Second signal transmission circuit, The first output terminal of the first signal transmission circuit is connected to the second output terminal of the second signal transmission circuit, and serves as the output terminal of the PWM signal generation circuit. The first high level used to generate the first output signal of the first signal transmission circuit is different from the second high level used to generate the second output signal of the second signal transmission circuit, and the output signal of the PWM signal generation circuit has a step between the first high level and the second high level.

2. The PWM signal generation circuit according to claim 1, wherein, The first signal transmission circuit and the second signal transmission circuit are connected to a first clock signal and a second clock signal. The first clock signal and the second clock signal are periodic signals with the same waveform and a duty cycle of 20%-40%.

3. The PWM signal generation circuit according to claim 2, wherein, The first signal transmission circuit includes a first input module, a first forward voltage generation module, a first reverse voltage generation module, a first signal generation module, and a first output enable module. The first input module, the first forward voltage generation module, the first reverse voltage generation module, and the first signal generation module are connected to the first node of the first signal transmission circuit. The first forward voltage generation module and the first reverse voltage generation module are connected to the first control node of the first signal transmission circuit. The first reverse voltage generation module and the first signal generation module are connected to the second node of the first signal transmission circuit. The first signal generation module and the first output enable module are connected to the first output node of the first signal transmission circuit. The second signal transmission circuit includes a second input module, a second forward voltage generation module, a second reverse voltage generation module, a second signal generation module, and a second output enable module. The second input module, the second forward voltage generation module, the second reverse voltage generation module, and the second signal generation module are connected to the third of the second signal transmission circuit. node, The second forward voltage generation module and the second reverse voltage generation module are connected to the second control node of the second signal transmission circuit. The second reverse voltage generation module and the second signal generation module are connected to the fourth node of the second signal transmission circuit. The second signal generation module and the second output enable module are connected to the second output node of the second signal transmission circuit.

4. The PWM signal generation circuit according to claim 3, wherein, The first input module includes a first input transistor, and the second input module includes a second input transistor. The first terminal of the first input transistor serves as the first input terminal of the first signal transmission circuit. A first input signal is applied to the first terminal of the first input transistor. The second terminal of the first input transistor is connected to the first node, and a second clock signal is applied to the gate of the first input transistor. The first terminal of the second input transistor serves as the second input terminal of the second signal transmission circuit. A second input signal is applied to the first terminal of the second input transistor. The second terminal of the second input transistor is connected to the third node, and the first clock signal is applied to the gate of the second input transistor.

5. The PWM signal generation circuit according to claim 4, wherein, The first forward voltage generation module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the second forward voltage generation module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. A high-level signal is applied to the first terminal of the first transistor, the gate of the first transistor is connected to the first control node, and the second terminal of the first transistor is connected to the first terminal of the second transistor. The second terminal of the second transistor is connected to the first node, and the first clock signal is applied to the gate of the second transistor. The second clock signal is applied to the first terminal of the third transistor and the gate of the fourth transistor. The gate of the third transistor is connected to the first node, the second terminals of the third transistor and the fourth transistor are connected to the first control node, and the first terminal of the fourth transistor is connected to a low level. A high level is applied to the first terminal of the fifth transistor, and the gate of the fifth transistor is connected to... The fifth transistor is connected to the second control node, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor. The second terminal of the sixth transistor is connected to the third node, and the second clock signal is applied to the gate of the sixth transistor. The first clock signal is applied to the first terminal of the seventh transistor and the gate of the eighth transistor, the gate of the seventh transistor is connected to the third node, the second terminals of the seventh transistor and the eighth transistor are connected to the second control node, and the first terminal of the eighth transistor is connected to a low level.

6. The PWM signal generation circuit according to claim 5, wherein, The first reverse voltage generation module includes a ninth transistor, a tenth transistor, and an eleventh transistor, and the second reverse voltage generation module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. A high-level signal is applied to the first terminal of the ninth transistor, the gate of the ninth transistor is connected to the first node, and the second terminal of the ninth transistor is connected to the second node. The first terminal of the tenth transistor is connected to the second terminal of the eleventh transistor, and is also connected to the first control node via a first capacitor. The first clock signal is applied to the gate of the tenth transistor and the first terminal of the eleventh transistor, the second terminal of the tenth transistor is connected to the second node, and the gate of the eleventh transistor is connected to the first control node. A high-level signal is applied to the first terminal of the twelfth transistor, the gate of the twelfth transistor is connected to the third node, and the second terminal of the twelfth transistor is connected to the fourth node. The first terminal of the thirteenth transistor is connected to the second terminal of the fourteenth transistor, and is also connected to the second control node via a second capacitor. The second clock signal is applied to the gate of the thirteenth transistor and the first terminal of the fourteenth transistor, the second terminal of the thirteenth transistor is connected to the fourth node, and the gate of the fourteenth transistor is connected to the second control node.

7. The PWM signal generation circuit according to claim 6, wherein, The first signal generation module includes a fifteenth transistor and a sixteenth transistor, and the second signal generation module includes a seventeenth transistor and an eighteenth transistor. The first high level is applied to the first terminal of the fifteenth transistor, the gate of the fifteenth transistor is connected to the second node, and is connected to the tenth node via the third capacitor. The first terminal of the five transistors and the second terminal of the fifteenth transistor are connected to the first output node. The first terminal of the sixteenth transistor is connected to a low level, the gate of the sixteenth transistor is connected to the first node, and the second terminal of the sixteenth transistor is connected to the first output node. The second high level is applied to the first terminal of the seventeenth transistor, the gate of the seventeenth transistor is connected to the fourth node and connected to the first terminal of the seventeenth transistor via the fourth capacitor, and the second terminal of the seventeenth transistor is connected to the second output node. The first terminal of the eighteenth transistor is connected to a low level, the gate of the eighteenth transistor is connected to the third node, and the second terminal of the eighteenth transistor is connected to the second output node.

8. The PWM signal generation circuit according to claim 7, wherein, The first output enable module includes a first output transistor, and the second output enable module includes a second output transistor. The first output transistor is connected between the first output node and the first output terminal, and the second output transistor is connected between the second output node and the second output terminal. The first output signal is output to the first output terminal via the first output transistor, and the second output signal is output to the second output terminal via the second output transistor. The first output signal is also output to the gate of the second output transistor as an output enable signal for the second signal transmission circuit, and The second output signal is also output to the gate of the first output transistor as an output enable signal of the first signal transmission circuit.

9. The PWM signal generation circuit according to claim 7, wherein, The first signal generation module further includes a fifth capacitor and a nineteenth transistor, and the second signal generation module further includes a sixth capacitor and a twentieth transistor. The first clock signal is applied to the first terminal of the fifth capacitor, and the second terminal of the fifth capacitor is connected to the gate of the sixteenth transistor. The second clock signal is applied to the second terminal of the sixth capacitor, and the second terminal of the sixth capacitor is connected to the gate of the eighteenth transistor. The gate of the sixteenth transistor is connected to the first node via the nineteenth transistor, and the gate of the eighteenth transistor is connected to the first node via the twentieth transistor. Three nodes.

10. The PWM signal generation circuit according to claim 1, wherein, The second high level is twice the first high level.

11. The PWM signal generation circuit according to claim 1, wherein, The output signal of the PWM signal generation circuit has a different duration when it is at the first high level and a different duration when it is at the second high level.

12. A pixel circuit, comprising: Driver module; Light emission control module; as well as Light-emitting elements The driving module is connected to the light-emitting control module, and the light-emitting control module and the light-emitting element are connected in series between the power supply voltage and the ground voltage. The light-emitting control module includes a first light-emitting control module and a second light-emitting control module that are connected to each other. The first light-emitting control module is connected to a first data signal and a first Sweep signal, the second light-emitting control module is connected to a second data signal and a second Sweep signal, and both the first and second light-emitting control modules are connected to a first scan signal. The first Sweep signal and the second Sweep signal are different, and the first Sweep signal and the second Sweep signal are generated by the PWM signal generation circuit according to any one of claims 1 to 11.

13. The pixel circuit according to claim 12, wherein, The first light-emitting control module includes a first control transistor, a second control transistor, and a first control capacitor, and the second light-emitting control module includes a third control transistor, a fourth control transistor, and a second control capacitor. The first Sweep signal is applied to a first terminal of the first control capacitor, and the second terminal of the first control capacitor is connected to the gate of the first control transistor. The first data signal is applied to the first terminal of the second control transistor, the first scan signal is applied to the gate of the second control transistor, and the second terminal of the second control transistor is connected to the gate of the first control transistor. The second Sweep signal is applied to the first terminal of the second control capacitor, and the second terminal of the second control capacitor is connected to the gate of the third control transistor. The second data signal is applied to the first terminal of the fourth control transistor, the first... A scan signal is applied to the gate of the fourth control transistor, and the second terminal of the fourth control transistor is connected to the gate of the third control transistor. The first terminal of the first control transistor is connected to the first terminal of the third control transistor, and the second terminal of the first control transistor is connected to the second terminal of the third control transistor.

14. The pixel circuit according to claim 13, wherein, The driving module is connected to a second scan signal, and the driving module includes a first driving transistor, a second driving transistor, a third driving transistor, and a first driving capacitor. A driving current is applied to the first terminals of the first driving transistor and the second driving transistor; a second scan signal is applied to the gates of the first driving transistor and the second driving transistor; the second terminal of the first driving transistor is connected to the first terminal of the third driving transistor, and the second terminal of the second driving transistor is connected to the gate of the third driving transistor. The first end of the first driving capacitor is connected to the gate of the third driving transistor, and the second end of the first driving capacitor is connected to the second end of the third driving transistor.

15. The pixel circuit according to claim 14, further comprising a switching module, The switching module, the light-emitting control module, and the light-emitting element are connected in series between the power supply voltage and the ground voltage, and The driving module is connected to the light-emitting control module via the switching module.

16. The pixel circuit according to claim 15, wherein, The switching module includes a switching transistor, and the gate of the third driving transistor is connected to the gate of the switching transistor.

17. The pixel circuit according to claim 13, wherein, The driving module is connected to the first scan signal, the second scan signal, and the third scan signal, and the driving module includes a fourth driving transistor, a fifth driving transistor, a sixth driving transistor, a seventh driving transistor, an eighth driving transistor, a ninth driving transistor, and a second driving capacitor. The fourth driving transistor is connected between the first node of the driving module and the ground voltage, and the second scan signal is applied to the gate of the fourth driving transistor. The fifth driving transistor is connected between the first node of the driving module and the ground voltage, and the third scan signal is applied to the gate of the fifth driving transistor. The sixth driving transistor is connected between the second node of the driving module and the ground voltage, and the third scan signal is applied to the gate of the sixth driving transistor. The seventh driving transistor is connected between the first node of the driving module and the reference voltage, and the first scan signal is applied to the gate of the seventh driving transistor. The power supply voltage is applied to the first terminal of the eighth driving transistor, the gate of the eighth driving transistor is connected to the second node of the driving module, and the second terminal of the eighth driving transistor is connected to the second terminal of the ninth driving transistor. The first terminal of the ninth driving transistor is connected to the second node of the driving module, and the second scan signal is applied to the gate of the ninth driving transistor. The second driving capacitor is connected between the first node and the second node of the driving module.

18. A display substrate comprising a pixel circuit according to any one of claims 12 to 17.

19. A display device comprising a display substrate according to claim 18.

20. An electronic device comprising the display device according to claim 19.

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