Array substrate, display panel and display device
By placing the signal lines in the array substrate of VR headset products and using a reflective film layer and an oxide dual-gate structure, the problems of high cost and low aperture ratio are solved, the display effect and efficiency are improved, and the manufacturing process is simplified.
Patent Information
- Application Number
- PCT/CN2024/090643
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2026-01-29
AI Technical Summary
Among existing VR headset products, Micro OLED display devices are expensive and difficult to manufacture, while LCD products suffer from low pixel aperture ratio, low contrast and high power consumption when increasing resolution, and there are problems such as light leakage and capacitive coupling caused by metal traces covering vias.
Design an array substrate structure in which signal lines are located below the active layer, and vias are covered by a film layer that reflects light of a specific wavelength while allowing light of other wavelengths to pass through, reducing the use of metal light-shielding layers. In the peripheral area, an oxide dual-gate structure and simplified masking process are adopted to reduce capacitive coupling and power consumption.
It improves the light efficiency and aperture ratio of the display panel, reduces power consumption, improves contrast and pixel charging rate, and simplifies the manufacturing process.
Smart Images
Figure CN2024090643_29012026_PF_FP_ABST
Abstract
Description
Array substrate, display panel and display device TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND
[0002] With the rise of the concept of metaverse, Virtual Reality (VR) head-mounted products as port devices have attracted much attention. At present, the display products with good effects in the market are usually micro organic light-emitting display devices (Micro OLED) products with 3000+PPI. However, the Micro OLED products have high cost and great process difficulty, and are difficult to popularize.
[0003] SUMMARY
[0004] The present application provides an array substrate, a display panel and a display device. The array substrate has a pixel region and a peripheral region located at the periphery of the pixel region. The array substrate comprises:
[0005] a substrate;
[0006] a first active layer located on one side of the substrate and having a plurality of first active patterns located in the pixel region;
[0007] a first metal layer located on the side of the first active layer facing the substrate and comprising a plurality of first signal lines;
[0008] a first insulating layer located between the first active layer and the first metal layer; the first insulating layer has a first via hole; the first signal lines are electrically connected to the first active patterns through the first via hole;
[0009] wherein the first insulating layer comprises at least a first film layer; the first film layer has a first pattern; the orthographic projection of the first pattern on the substrate at least partially overlaps the orthographic projection of the first active pattern on the substrate, and the first pattern reflects light of a first waveband.
[0010] In a possible implementation, the array substrate further comprises a first conductive layer located on the side of the first active layer away from the substrate, and a second insulating layer located between the first conductive layer and the first active layer; the first conductive layer comprises a plurality of first electrodes; the second insulating layer has a second via hole; the first electrodes are electrically connected to the first active patterns through the second via hole;
[0011] The first electrodes comprise a plurality of first sub-electrodes; the first sub-electrodes are located in a region from which a first waveband of light is emitted; the first film layer has a plurality of hollow portions; the hollow portions in the orthographic projection of the substrate at least partially overlap the first sub-electrodes in the orthographic projection of the substrate.
[0012] In a possible implementation, the first electrodes comprise a plurality of second sub-electrodes and a third sub-electrode; the second sub-electrodes are located in a region from which a second waveband of light is emitted, and the third sub-electrode is located in a region from which a third waveband of light is emitted.
[0013] The first pattern in the orthographic projection of the substrate covers the second sub-electrodes and the third sub-electrode in the orthographic projection of the substrate.
[0014] In a possible implementation, the hollow portions in the orthographic projection of the substrate do not overlap the first pattern in the orthographic projection of the substrate.
[0015] In a possible implementation, the first pattern comprises a plurality of sub-film layers arranged in a stack.
[0016] In a possible implementation, the material of the sub-film layers comprises one or a combination of the following:
[0017] Silicon dioxide;
[0018] Niobium pentoxide;
[0019] Titanium dioxide.
[0020] In a possible implementation, the first pattern transmits the first waveband of light and the second waveband of light, and reflects the third waveband of light; the wavelength range of the first waveband of light is greater than the wavelength range of the second waveband of light, and the wavelength range of the second waveband of light is greater than the wavelength range of the third waveband of light.
[0021] In a possible implementation, the array substrate further comprises a second metal layer located on a side of the first active layer facing away from the substrate; the second metal layer comprises a plurality of second signal lines.
[0022] The first active pattern comprises a first portion and a second portion; the first portion in the orthographic projection of the substrate overlaps the first signal lines in the orthographic projection of the substrate; and the second portion in the orthographic projection of the substrate overlaps the second signal lines in the orthographic projection of the substrate.
[0023] The first pattern in the orthographic projection of the substrate covers the second portion in the orthographic projection of the substrate.
[0024] In a possible implementation, a width of the first signal line in a direction parallel to an extending direction of the second signal line is greater than a width of the first via; the first via exposes a portion of the first signal line away from a side surface of the substrate.
[0025] In a possible implementation, the first active pattern covers at least a side wall of the first via toward a side of the second part, a peripheral portion of the first signal line toward the side of the second part, and a portion of the first signal line away from a side surface of the substrate.
[0026] In a possible implementation, a width of the first signal line in a direction parallel to an extending direction of the second signal line is less than a width of the first via; the first via exposes the first signal line and a portion of an area around the first signal line.
[0027] In a possible implementation, the first active pattern covers at least a side wall of the first via toward a side of the second part, a peripheral portion of the first signal line toward the side of the second part, and a portion of the first signal line away from a side surface of the substrate.
[0028] In a possible implementation, the second metal layer further includes: a first transfer electrode; a projection of the first transfer electrode on the substrate at least partially overlaps with a projection of the first via on the substrate.
[0029] The first transfer electrode is in contact with a side surface of the first active pattern and a surface of the first signal line away from the substrate, and the first signal line is electrically connected to the first active pattern through the first transfer electrode.
[0030] In a possible implementation, the first active layer further includes: a plurality of second active patterns in the peripheral area; and the array substrate further includes: a driving gate in the peripheral area and located on a side of the second active pattern away from the substrate.
[0031] The first metal layer further includes: a plurality of light shielding patterns in the peripheral area, the light shielding patterns are electrically connected to the driving gate; and a projection of the light shielding patterns on the substrate at least partially overlaps with a projection of the second active pattern on the substrate.
[0032] In a possible implementation, the first active layer further includes: a plurality of second active patterns in the peripheral area; and the first insulating layer further includes: a plurality of third vias.
[0033] The first metal layer further includes: a plurality of third signal lines; and the third signal lines are electrically connected to the second active patterns through the third vias.
[0034] In a possible implementation, the array substrate further includes a driving gate located at the peripheral area and away from the substrate side of the second active pattern; the second metal layer further includes the driving gate and a second transfer electrode; a projection of the second transfer electrode on the substrate at least partially overlaps with a projection of the third via on the substrate.
[0035] The second transfer electrode partially contacts a sidewall of the second active pattern and partially contacts a surface of the third signal line away from the substrate side of the third signal line, and the third signal line is electrically connected to the second active pattern through the second transfer electrode.
[0036] In a possible implementation, the array substrate further includes a color filter layer located at the first active layer side away from the substrate, and the color filter layer includes a plurality of color resistances.
[0037] The display panel provided by the embodiments of the present disclosure is also provided.
[0038] The display device provided by the embodiments of the present disclosure is also provided. BRIEF DESCRIPTION OF DRAWINGS
[0039] FIG. 1A is a schematic cross-sectional view of an array substrate at a blue sub-pixel;
[0040] FIG. 1B is a schematic cross-sectional view of an array substrate at a red or green sub-pixel;
[0041] FIG. 1C is a schematic top view of a part of the peripheral area of FIG. 1A;
[0042] FIG. 2A is a schematic view of a stack of a sub-pixel electrode and a first film layer;
[0043] FIG. 2B is a schematic view of a single film layer of the sub-pixel electrode layer in FIG. 2A;
[0044] FIG. 2C is a schematic view of a single film layer of the first film layer in FIG. 2A;
[0045] FIG. 3A is a schematic view of a relationship between a first signal line and a first via according to an embodiment of the present disclosure;
[0046] FIG. 3B is a schematic view of a relationship between a first signal line and a first via according to another embodiment of the present disclosure;
[0047] FIG. 3C is a schematic view of a relationship between a first signal line and a first via according to a third embodiment of the present disclosure;
[0048] FIG. 3D is a schematic view of a relationship between a first signal line and a first via according to a fourth embodiment of the present disclosure;
[0049] FIG. 4A is a schematic view of a relationship between a first signal line and a first via according to an embodiment of the present disclosure;
[0050] FIG. 4B is a schematic view of a relationship between a first signal line and a first via according to an embodiment of the present disclosure;
[0051] FIG. 4C is a schematic view of a relationship between a first signal line and a first via according to an embodiment of the present disclosure;
[0052] FIG. 4D is a schematic view of a relationship between a first signal line and a first via according to an embodiment of the present disclosure;
[0053] FIG. 5 is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0054] FIG. 6A is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0055] FIG. 6B is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0056] FIG. 7A is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0057] FIG. 7B is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0058] FIG. 7C is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0059] FIG. 7D is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure;
[0060] FIG. 8 is a schematic view of a cross section of an array substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0061] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. Embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a composition of matter, and / or a recording medium containing instructions. Some of the embodiments according to the present disclosure can be implemented as computer-readable commands stored on a computer-readable storage medium, which can be read and executed by one or more processors that can be included in a computer or other processing system. As used herein, the term "computer-readable storage medium" means a device that can store data, which can be read by a computer or other processing system. Examples of a computer-readable storage medium include a read-only memory (ROM), a random-access memory (RAM), a flash memory, and an optical memory. The computer-readable storage medium can also be distributed over network-coupled (and / or wireless) computer systems so that the computer-readable commands can be stored and executed in a distributed fashion. In some embodiments, the computer-readable storage medium can comprise a non-transitory computer-readable storage medium. Here, the term "non-transitory" simply means that the computer-readable medium does not include a signal. In some embodiments, one or more computer-readable storage media can be used.
[0062] In the drawings, the size, the layer thickness, or the region of one or more constituent elements can sometimes be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, the shape, and the relative arrangement of the components illustrated in the drawings. The drawings are intended to conceptually illustrate the idea of the present disclosure, and the size, the shape, and the arrangement of the components in the drawings are not intended to limit the scope of the present disclosure. In addition, the drawings are provided to conceptually illustrate an ideal example, and one embodiment of the present disclosure is not limited to the shapes or values illustrated in the drawings.
[0063] In the present specification, ordinal terms, such as "first", "second", and "third", are used to avoid confusion among components, and are not used to limit the number in the specification. In the present disclosure, "a plurality of" can include two or more numbers.
[0064] In the present specification, words for indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings for the convenience of the description of the present specification and the simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which the components are described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.
[0065] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the situation.
[0066] In the present specification, "electrically connected" includes the case where the components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
[0067] In the present specification, a transistor refers to an element including at least a gate electrode (gate), a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.
[0068] In addition, the gate of the transistor can be referred to as the control electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the operation of the circuit, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present specification, the "source electrode" and the "drain electrode" can be exchanged with each other.
[0069] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.
[0070] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.
[0071] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."
[0072] In this specification, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this specification, "roughly the same" can mean that the values differ by no more than 10%.
[0073] The demand for ultra-high resolution in VR headsets is growing stronger, and LCD displays, due to their price advantage, hold a leading market share. However, higher resolutions require a higher proportion of metal traces, resulting in lower pixel aperture ratios. In existing Low Temperature Polycrystalline Oxide (LTPO) VR products, to ensure the characteristics of oxide devices in the pixel area, the single-sided shading of the light-shielding metal layer exceeds 2μm, severely reducing the aperture ratio. Moreover, in existing VR products, the data line layer is located above the active layer. When the data lines cover vias, light leakage occurs due to the metal depolarization effect, leading to low contrast. In addition, there is the problem of low pixel charging rate and high power consumption caused by capacitive coupling between the data line layer and the gate layer.
[0074] This disclosure provides an array substrate, as shown in Figures 1A-1B and 2A-2C. Figure 1A is a cross-sectional view of the array substrate at the blue sub-pixel; Figure 1B is a cross-sectional view of the array substrate at the red or green sub-pixel; Figure 2A is a stacked view of the sub-pixel electrode and the first film layer; Figure 2B is a single film layer view of the sub-pixel electrode layer in Figure 2A; and Figure 2C is a single film layer view of the first film layer in Figure 2A. The substrate has a pixel region AA and a peripheral region BB located around the pixel region AA, comprising:
[0075] Substrate 1;
[0076] The first active layer is located on one side of the substrate 1 and has multiple first active patterns 2 located in the pixel area AA;
[0077] The first metal layer, located on the side of the first active layer facing the substrate 1, includes: a plurality of first signal lines 3; optionally, the first signal lines 3 can be data lines;
[0078] A first insulating layer 4 is located between a first active layer and a first metal layer; the first insulating layer 4 has a first via K1; the first signal line 3 is electrically connected to the first active pattern 2 through the first via K1;
[0079] The first insulating layer 4 includes at least: a first film layer 41; the first film layer 41 has a first pattern 410; the orthographic projection of the first pattern 410 onto the substrate 1 overlaps at least partially with the orthographic projection of the first active pattern 2 onto the substrate 1, and the first pattern 410 reflects light of a first wavelength band. Optionally, the first wavelength band can be the wavelength band corresponding to blue light.
[0080] In this embodiment, the first signal line 3 is located on the side of the first active layer facing the substrate 1. Placing the first signal line 3 downwards can improve the problem of low contrast caused by light leakage at the first via K1 due to the metal depolarization effect when the first signal line 3 is located on the side of the first active layer away from the substrate 1. Furthermore, a first film layer 41 is provided between the first signal line 3 and the substrate 1. The first film layer 41 can reflect the first wavelength light, which can avoid the influence of the first wavelength light on the first active pattern 2. Other wavelengths of light can be transmitted, and the problem of low aperture ratio of the display panel caused by the light-blocking structure of the first active pattern 2 in conventional technology can be avoided. The reflected blue light can be reused to improve the light efficiency of the display panel. At the same time, the setting of the first film layer 41 can also increase the spacing between the first signal line 3 and other metal layers (such as gate layers), thereby reducing the capacitive coupling between the first signal line 3 and other signal line layers (such as gate layers), thereby improving the problem of low pixel charging rate and high power consumption caused by the coupling between the first signal line 3 and other signal lines in conventional technology.
[0081] In one possible implementation, the first pattern can transmit both second and third band light and reflect the first band light; wherein the wavelength range of the first band light is smaller than that of the second band light, and the wavelength range of the second band light is smaller than that of the third band light. Optionally, the second band light can be the band corresponding to green light, and the third band light can be the band corresponding to red light. That is, the first pattern 410 of the first film layer 4 can be a dielectric film that transmits red and green light and reflects blue light.
[0082] In one possible implementation, as shown in Figures 1A and 2A-2C, the array substrate further includes: a first conductive layer located on the side of the first active layer facing away from the substrate 1, and a second insulating layer 5 located between the first conductive layer and the first active layer; the first conductive layer includes: a plurality of first electrodes 6; the second insulating layer 5 has a second via K2; the first electrodes 6 are electrically connected to the first active pattern 2 through the second via K2; the plurality of first electrodes 6 include: a plurality of first sub-electrodes 61; the region where the first sub-electrodes 61 are located emits light of a first wavelength band; optionally, the first sub-electrodes 61 may be the pixel electrode of the blue sub-pixel B; the first film layer 41 has a plurality of cutouts L; the orthographic projection of the cutouts L onto the substrate 1 coincides at least partially with the orthographic projection of the first sub-electrodes 61 onto the substrate 1.
[0083] In one possible implementation, as shown in FIG1A and FIG2A-2C, the first electrode 6 may further include a second sub-electrode 62 and a third sub-electrode 63; optionally, the second sub-electrode 62 may be a pixel electrode of the green sub-pixel G; the third sub-electrode 63 may be a pixel electrode of the red sub-pixel R; the area where the second sub-electrode 62 is located emits second-band light, and the area where the third sub-electrode 63 is located emits third-band light; the orthographic projection of the first pattern 410 on the substrate 0 covers the orthographic projections of the second sub-electrode 62 and the third sub-electrode 63 on the substrate 1.
[0084] In one possible implementation, as shown in Figures 2A-2C, the first pattern 410 can be any pattern in the first film layer 41 except for the cutout portion L1.
[0085] In one possible implementation, the sub-pixel electrode arrangement can be a conventional 1:3 ratio sub-pixel design (that is, taking a square pixel as an example, in the three sub-pixels, the width of each sub-pixel electrode in the row direction can be one-third of the side length of the square, and the width of each sub-pixel electrode in the column direction can be equal to the side length of the square), or other ratios, such as 1:2 or 3:4; the pattern of the sub-pixel electrodes can be quadrilaterals, hexagons, or other polygons, circles, etc.; the specific arrangement can be a through-type or a pixel staggered design (as shown in Figure 2A).
[0086] In one possible implementation, as shown in FIG1A and FIG2A-2C, the orthographic projection of the cutout portion L on the substrate 1 does not overlap with the orthographic projection of the first pattern 410 on the substrate 1.
[0087] In one possible implementation, the first pattern 410 includes a plurality of sub-film layers stacked together. That is, the first pattern 410 can be a stacked structure formed by a plurality of sub-film layers. Each sub-film layer of the first pattern 410 can be an inorganic film layer, an organic film layer, or a combination of inorganic and organic film layers.
[0088] In one possible implementation, the material of the subfilm layer includes one or a combination of the following:
[0089] Silicon dioxide;
[0090] Niobium pentoxide;
[0091] Titanium dioxide.
[0092] In one possible implementation, the number of sub-film layers in the first pattern 410 can be 2 to 20, and the thickness of the first cluster 410 in the direction perpendicular to the substrate 1 can be 0.1 μm to 2 μm.
[0093] In one possible implementation, as shown in FIG1A, the slope angle α1 of the first pattern 410 can be in the range of 45° to 90°.
[0094] In one possible implementation, referring to Figures 1A and 2A-2C, the array substrate further includes: a second metal layer located on the side of the first active layer facing away from the substrate 1; the second metal layer includes multiple second signal lines 7; the first active pattern 2 includes: a first portion 21 and a second portion 22; the orthographic projection of the first portion 21 onto the substrate 1 overlaps with the orthographic projection of the first signal line 3 onto the substrate 1; the orthographic projection of the second portion 22 onto the substrate 1 overlaps with the orthographic projection of the second signal line 7 onto the substrate; the orthographic projection of the first pattern 410 onto the substrate 1 covers the orthographic projection of the second portion 22 onto the substrate 1. Optionally, the second signal line 7 can be a gate line, and the area in the first active pattern 2 corresponding to the second signal line 7 can be used as a channel region. The orthographic projection of the first pattern 410 onto the substrate 1 covers the orthographic projection of the second portion 22 onto the substrate 1, thereby preventing external light from irradiating the channel region and thus avoiding the impact on transistor performance.
[0095] In conventional processes, the linewidth of the first signal line 3 ranges from 1μm to 3μm, and the size of the first via K1 ranges from 1μm to 4μm. In the specific fabrication process, various overlapping relationships can be formed, which will be described in detail below. For example, in one possible implementation, as shown in Figures 3A-3D, in the direction parallel to the extension of the second signal line 7, the width a1 of the first signal line 3 is greater than the width b1 of the first via K1; the first via K1 exposes the portion of the first signal line 3 on the side facing away from the substrate 1.
[0096] In one possible implementation, as shown in Figures 3A-3D, the first active pattern 2 at least covers the sidewall of the first via K1 facing the second part 22, and the portion of the first signal line 3 facing away from the substrate 1.
[0097] In one possible implementation, as shown in FIG3A, the first active pattern 2 covers the sidewall of the first via K1 facing the second part 22, and the portion of the first signal line 3 facing away from the substrate 1; in one possible implementation, as shown in FIG3B, the first active pattern 2 covers the sidewall of the first via K1 facing the second part 22, and the entire surface of the first signal line 3 facing away from the substrate 1; in one possible implementation, as shown in FIG3C, the first active pattern 2 covers the entire sidewall of the first via K1, and the entire surface of the first signal line 3 facing away from the substrate 1; in one possible implementation, as shown in FIG3D, the first active pattern 2 covers the entire sidewall of the first via K1, the entire surface of the first signal line 3 facing away from the substrate 1, and the portion of the first insulating layer 4 facing away from the substrate 1.
[0098] In one possible implementation, as shown in Figures 4A-4D, in the direction parallel to the extension of the second signal line 7, the width a1 of the first signal line 3 is smaller than the width b1 of the first via K1, and the first via K1 exposes the first signal line 3 and a portion of the area surrounding the first signal line 3.
[0099] In one possible implementation, as shown in Figures 4A-4D, the first active pattern 2 at least covers the sidewall of the first via K1 facing the second part 22, the peripheral portion of the first signal line 3 facing the second part 22, and the portion of the first signal line 3 facing away from the substrate 1.
[0100] In one possible implementation, referring to FIG4A, the first active pattern 2 covers the sidewall of the first via K1 facing the second part 22, the peripheral portion of the first signal line 3 facing the second part 22, and the portion of the first signal line 3 facing away from the substrate 1; in one possible implementation, referring to FIG4B, the first active pattern 2 covers the sidewall of the first via K1 facing the second part 22, the peripheral portion of the first signal line 3 facing the second part 22 (i.e., the gap on the right side of the first signal line 3), the entire surface of the first signal line 3 facing away from the substrate 1, and the peripheral portion of the first signal line 3 away from the second part 22 (i.e., the gap on the left side of the first signal line 3); in one possible implementation, referring to FIG4C, the first active pattern 2 covers the sidewall of the first via K1 facing the second part 22, the peripheral portion of the first signal line 3 facing the second part 22 (i.e., the gap on the left side of the first signal line 3); in one possible implementation, referring to FIG4C, the first active pattern 2 covers the sidewall of the first via K1 facing the second part 22, the peripheral portion of the first signal line 3 facing the second part 22 (i.e., the gap on the left side of the first signal line 3). The first active pattern 2 covers the entire sidewall of the first via K1, the peripheral portion of the first signal line 3 facing the second part 22 (i.e., the gap to the right of the first signal line 3), the entire surface of the first signal line 3 facing away from the substrate 1, and the peripheral portion of the first signal line 3 away from the second part 22 (i.e., the gap to the left of the first signal line 3); in one possible embodiment, as shown in FIG4D, the first active pattern 2 covers the entire sidewall of the first via K1, the peripheral portion of the first signal line 3 facing the second part 22 (i.e., the gap to the right of the first signal line 3), the entire surface of the first signal line 3 facing away from the substrate 1, the peripheral portion of the first signal line 3 away from the second part 22 (i.e., the gap to the left of the first signal line 3), and the portion of the first insulating layer 4 facing away from the substrate 1.
[0101] In one possible implementation, referring to FIG5, the second metal layer further includes: a first transition electrode 81; the orthographic projection of the first transition electrode 81 onto the substrate 1 overlaps at least partially with the orthographic projection of the first via K1 onto the substrate 1; the first transition electrode 81 partially contacts the side surface of the first active pattern 2 and partially contacts the surface of the first signal line 3 facing away from the substrate 1, and the first signal line 3 is electrically connected to the first active pattern 2 through the first transition electrode 81. Since the conductor depth of the first active pattern 2 may not reach the expected level during the conductor formation process, in this embodiment of the present disclosure, by providing the first transition electrode 81, which partially contacts the side surface of the first active pattern 2 and partially contacts the surface of the first signal line 3 facing away from the substrate 1, the conduction effect between the first signal line 3 and the first active pattern 2 can be improved.
[0102] In one possible implementation, referring to Figures 1A-1C, 5, and 7C-7D, the first active layer further includes: a plurality of second active patterns Q1 located in the peripheral region; the array substrate further includes: a driving gate Q2 located in the peripheral region BB on the side of the second active patterns facing away from the substrate; the first metal layer further includes: a plurality of light-shielding patterns LS located in the peripheral region BB, the light-shielding patterns LS and the driving gate Q2 being electrically connected through a fourth via K4; the orthographic projection of the light-shielding patterns LS onto the substrate 1 overlaps at least partially with the orthographic projection of the second active patterns Q1 onto the substrate 1. Optionally, the light-shielding pattern LS can serve as the bottom gate, and the driving gate Q2 can serve as the top gate. The size of the light-shielding pattern LS can be larger than the size of the driving gate Q2, that is, the bottom gate size of the peripheral region transistor is larger than the top gate size (the single-sided wrapping size can be 0.5μm to 2μm), which can effectively improve the on-state current and device stability of the peripheral region transistor.
[0103] In one possible implementation, referring to Figures 6A and 6B, the first active layer further includes: a plurality of second active patterns Q1 located in the peripheral region BB; the first insulating layer further includes: a plurality of third vias K3; the first metal layer further includes: a plurality of third signal lines Q3; the third signal lines Q3 are electrically connected to the second active patterns Q1 through the third vias K3. In this embodiment, the third signal lines Q3 in the peripheral region BB are also placed at the bottom, which can eliminate the need for etching the vias of the gate insulating layer 91. Compared with the array substrate structure shown in Figure 1A, this can save one mask process and simplify the fabrication process of the array substrate.
[0104] In one possible implementation, referring to Figures 7A-7D, the array substrate further includes: a driving gate Q2 located in the peripheral region BB on the side of the second active pattern Q1 away from the substrate 1; the second metal layer further includes: the driving gate Q2 and a second transition electrode 82; the orthographic projection of the second transition electrode 82 on the substrate 1 overlaps at least partially with the orthographic projection of the third via K3 on the substrate 1; the second transition electrode 82 partially contacts the sidewall of the second active pattern Q1 and partially contacts the surface of the third signal line Q3 away from the substrate 1, and the third signal line Q3 is electrically connected to the second active pattern Q1 through the second transition electrode 82.
[0105] The materials of the first active pattern 2 and the second active pattern Q1 can both include metal oxide semiconductor materials. The metal oxide semiconductor materials can include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element doped metal oxide (RE-OS). The rare earth element doped metal oxide can include lanthanide doped metal oxide (Ln-OS). The crystal state of the first active layer material can be amorphous, partially crystalline, or polycrystalline. In the embodiments of this disclosure, the first active pattern 2 of the transistor in the pixel area AA can be metal oxide semiconductor. Metal oxide semiconductor thin film transistors have advantages such as low leakage current.
[0106] In this embodiment of the disclosure, when the active layers of the transistors in the pixel area and the peripheral area can both be oxide active layers, the transistors in the peripheral area and the transistors in the pixel area can both adopt an oxide double-gate structure, and the bottom gate size of the transistor in the peripheral area is larger than the top gate size (the single-side wrapping size can be 0.5μm to 2μm), which can effectively improve the on-state current of the transistor in the peripheral area and the device stability.
[0107] In one possible implementation, the first active pattern 2 can be conductor-treated, optionally by doping with B or P ions, or by treating with Ar or He ions.
[0108] In one possible implementation, the material of at least one of the first metal layer (including the first signal line 3) and the second metal layer (including the second signal line 7) may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. Optionally, the thickness of the first signal line 3 may be [missing information].
[0109] In one possible implementation, referring to FIG8, the array substrate further includes a color filter layer 90 located on the side of the first active layer facing away from the substrate 1, and the color filter layer 90 includes a plurality of color filters. In this embodiment of the present disclosure, the array substrate further includes a color filter layer 90 located on the side of the first active layer facing away from the substrate 1, which can further reduce the color filter thickness and improve the color gamut.
[0110] In one possible implementation, the thickness of the color filter layer 90 can range from 0.5 μm to 2 μm.
[0111] Optionally, the multiple color resists may include a first color resist 91 that transmits blue light, a second color resist (not shown in the figure) that transmits green light, and a third color resist (not shown in the figure) that transmits red light.
[0112] In one possible implementation, as shown in FIG1A, the first insulating layer 4 may further include a buffer layer 42; a gate insulating layer 91 may be disposed between the layer containing the first active pattern 2 and the layer containing the second signal line 7; an interlayer dielectric layer 92 may be disposed between the second signal line 7 and the first electrode 6, and a planarization layer 93 located on the side of the interlayer dielectric layer 92 facing away from the substrate 1; a passivation layer 94 may be disposed on the side of the first electrode 6 facing away from the substrate 1; a second light-shielding pattern 95 may be disposed on the side of the passivation layer 94 facing away from the substrate 1, and a common electrode layer 96 located on the side of the second light-shielding pattern 95 facing away from the substrate 1. The second light-shielding pattern 95, projected onto the substrate 1, can cover the projection of the first signal line 3 onto the substrate 1. Specifically, the material of the second light-shielding pattern 95 can be metal, and the material of the common electrode layer 96 can be metal oxide (e.g., indium tin oxide). The second light-shielding pattern 95 is in direct contact with the common electrode layer 96, and the conductivity of the second light-shielding pattern 95 can be better than that of the common electrode layer 96, thereby reducing the resistance of the common electrode layer 96.
[0113] In one possible implementation, as shown in FIG1A, the first electrode 6 may include a first electrode portion 61 and a second electrode portion 62 located on the side of the first electrode portion 61 facing away from the substrate 1. After the first electrode portion 61 is formed, the second insulating layer 5 may be filled at the location of the second via K2, and the second electrode portion 62 may be formed after the second via K2 is filled. Optionally, the first electrode 6 may be a transparent electrode.
[0114] In one possible implementation, for the first film layer 41, different designs can be made in the corresponding regions for different color sub-pixels to improve the light efficiency of the dielectric film for each color.
[0115] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, including an array substrate as provided in embodiments of this disclosure.
[0116] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.
[0117] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0118] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.
Claims
1. An array substrate having a pixel region and a peripheral region located at a periphery of the pixel region, wherein, The array substrate comprises: a substrate; a first active layer located on one side of the substrate and having a plurality of first active patterns located in the pixel region; a first metal layer located on the side of the first active layer facing the substrate and comprising a plurality of first signal lines; a first insulating layer located between the first active layer and the first metal layer; the first insulating layer has a first via; the first signal lines are electrically connected to the first active patterns through the first via; wherein the first insulating layer comprises at least a first film layer; the first film layer has a first pattern; the first pattern in the orthographic projection of the substrate at least partially overlaps with the first active pattern in the orthographic projection of the substrate, and the first pattern reflects first waveband light.
2. The array substrate of claim 1, wherein, The array substrate further comprises a first conductive layer located on the side of the first active layer away from the substrate, and a second insulating layer located between the first conductive layer and the first active layer; the first conductive layer comprises a plurality of first electrodes; the second insulating layer has a second via; the first electrodes are electrically connected to the first active patterns through the second via; the plurality of first electrodes comprise a plurality of first sub-electrodes; the area where the first sub-electrodes are located emits first waveband light; the first film layer has a plurality of hollow parts; the hollow parts in the orthographic projection of the substrate at least partially coincide with the first sub-electrodes in the orthographic projection of the substrate.
3. The array substrate of claim 2, wherein, the plurality of first electrodes comprise a plurality of second sub-electrodes and a third sub-electrode; the area where the second sub-electrodes are located emits second waveband light, and the area where the third sub-electrode is located emits third waveband light; the first pattern in the orthographic projection of the substrate covers the second sub-electrodes and the third sub-electrode in the orthographic projection of the substrate. the hollow parts in the orthographic projection of the substrate do not overlap with the first pattern in the orthographic projection of the substrate.
4. The array substrate of claim 2 or 3, wherein, the first pattern comprises a plurality of sub-film layers arranged in a stack.
5. The array substrate of any one of claims 1-4, wherein, the material of the sub-film layers comprises one or a combination of the following:
6. The array substrate of claim 5, wherein, silicon dioxide; niobium pentoxide; titanium dioxide. the first pattern transmits first waveband light and second waveband light and reflects third waveband light; wherein the wavelength range of the first waveband light is greater than the wavelength range of the second waveband light, and the wavelength range of the second waveband light is greater than the wavelength range of the third waveband light.
7. The array substrate of any one of claims 1-6, wherein, The array substrate further comprises a second metal layer located on the side of the first active layer away from the substrate; the second metal layer comprises a plurality of second signal lines; 8. The array substrate of any one of claims 1-7, wherein, the first active pattern comprises a first part and a second part; the first part in the orthographic projection of the substrate overlaps with the first signal lines in the orthographic projection of the substrate; the second part in the orthographic projection of the substrate overlaps with the second signal lines in the orthographic projection of the substrate; the first pattern in the orthographic projection of the substrate covers the second part in the orthographic projection of the substrate. in the direction parallel to the extension direction of the second signal lines, the width of the first signal lines is greater than the width of the first via; 9. The array substrate of claim 8, wherein, the first via exposes part of the surface of the first signal lines away from the substrate. 10. The array substrate of claim 9, wherein, The first active pattern covers at least a sidewall of the first via towards a side of the second portion, and a portion of the first signal line on a side surface away from the substrate.
11. The array substrate of claim 8, wherein, In a direction parallel to an extending direction of the second signal line, a width of the first signal line is less than a width of the first via, the first via exposes the first signal line, and exposes a partial area of a periphery of the first signal line.
12. The array substrate of claim 11, wherein, The first active pattern covers at least a sidewall of the first via towards a side of the second portion, a periphery portion of the first signal line towards the side of the second portion, and a portion of the first signal line on a side surface away from the substrate.
13. The array substrate of claim 8, wherein, The second metal layer further comprises: a first transfer electrode; a projection of the first transfer electrode on the substrate at least partially overlaps with a projection of the first via on the substrate; The first transfer electrode is in contact with a side surface of the first active pattern, and in contact with a surface of the first signal line away from the substrate, the first signal line is electrically connected with the first active pattern through the first transfer electrode.
14. The array substrate of any of claims 1-13, wherein, The first active layer further comprises: a plurality of second active patterns in the peripheral area; the array substrate further comprises: a driving gate in the peripheral area on a side of the second active pattern away from the substrate; The first metal layer further comprises: a plurality of light shielding patterns in the peripheral area, the light shielding patterns are electrically connected with the driving gate; a projection of the light shielding pattern on the substrate at least partially overlaps with a projection of the second active pattern on the substrate.
15. The array substrate of any one of claims 8-13, wherein, The first active layer further comprises: a plurality of second active patterns in the peripheral area; the first insulating layer further comprises: a plurality of third vias; The first metal layer further comprises: a plurality of third signal lines; the third signal lines are electrically connected with the second active patterns through the third vias.
16. The array substrate of claim 14, wherein, The array substrate further comprises: a driving gate in the peripheral area on a side of the second active pattern away from the substrate; the second metal layer further comprises: the driving gate and a second transfer electrode; a projection of the second transfer electrode on the substrate at least partially overlaps with a projection of the third via on the substrate; The second transfer electrode is in contact with a sidewall of the second active pattern, and in contact with a surface of the third signal line away from the substrate, the third signal line is electrically connected with the second active pattern through the second transfer electrode.
17. The array substrate of any one of claims 1-16, wherein, The array substrate further comprises a color filter layer on a side of the first active layer away from the substrate, the color filter layer comprises a plurality of color resist.
18. A display panel, wherein, An array substrate as claimed in any one of claims 1-17.
19. A display device, wherein, A display panel as claimed in claim 18.