Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of transistors distributed in different layers, and vertically-extending word lines (40); the transistors comprise semiconductor pillars (10) extending in a first direction; and each semiconductor pillar (10) comprises a first region (101), a channel region (103), and a second region (102). The semiconductor device further comprises channels for isolating the transistors in different rows; a first isolation layer and a second isolation layer are arranged in each channel; the first isolation layer is distributed on the side wall of the side of the corresponding word line (40) distant from the corresponding channel region (103); the first isolation layer partitions the corresponding channel into a first hole (K1) and a second hole (K2); and a transverse hole is present among each first isolation layer, the corresponding word line (40), and a substrate (1); each first hole (K1) and each second hole (K2) are communicated through the corresponding transverse hole; and each second isolation layer continuously extends in the corresponding first hole, the corresponding second hole, and the corresponding transverse hole.

Description

A semiconductor device, a manufacturing method thereof, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410538489.1, filed on April 30, 2024, and entitled "A semiconductor device, a manufacturing method thereof, and an electronic device", the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the technical field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising: a plurality of transistors distributed in different layers and arranged on a substrate, a word line extending in a direction perpendicular to the substrate;

[0008] The plurality of transistors in the same layer are arrayed in a first direction and a second direction; the transistors comprise a semiconductor pillar extending in the first direction, the semiconductor pillar comprises a first region, a channel region and a second region arranged in sequence in the first direction, and the word line continuously extends on the sidewall of the channel region of the plurality of transistors at the same position in different layers;

[0009] The semiconductor device further comprises trenches of the transistors extending along the first direction and spaced different rows along the second direction, the trenches are provided with a first isolation layer and a second isolation layer, the first isolation layer is distributed on sidewalls of the word lines away from the channel regions; the first isolation layer separates the trenches into a first hole and a second hole corresponding to the first region and the second region respectively; there is a lateral hole between the first isolation layer, the word lines and the substrate for spacing the first isolation layer, the word lines and the substrate; the first hole and the second hole are communicated through the lateral hole, and the second isolation layer continuously extends in the first hole, the second hole and the lateral hole.

[0010] In some embodiments, the second isolation layer comprises: a first insulating layer covering inner walls of the first hole, the second hole and the lateral hole, and a second insulating layer filling the first hole, the second hole and the lateral hole.

[0011] In some embodiments, the second isolation layer comprises: a first insulating layer covering inner walls of the first hole, the second hole and the lateral hole, and a second insulating layer partially filling the first hole, the second hole and the lateral hole, and the second insulating layer at least in the lateral hole is provided with a cavity.

[0012] In some embodiments, the second isolation layer fills the first hole, the second hole and the lateral hole; or the second isolation layer partially fills the first hole, the second hole and the lateral hole, and the second isolation layer at least in the lateral hole is provided with a cavity.

[0013] In some embodiments, the semiconductor device further comprises a gate insulating layer provided between the sidewalls of the channel regions and the word lines, the sidewalls of the channel regions of the plurality of transistors at different layers and at the same position continuously extend, and the lateral hole further separates the gate insulating layer and the substrate.

[0014] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0015] providing a substrate, and forming a stack structure comprising alternately stacked first insulating layers and semiconductor layers on the substrate;

[0016] forming a plurality of first trenches extending along a first direction through the stack structure, and forming semiconductor pillars between the first trenches adjacent along a second direction; the semiconductor pillars comprise a first region, a channel region and a second region distributed in sequence along the first direction;

[0017] forming a second insulating layer covering inner walls of the first trenches and a sacrificial layer filling the first trenches;

[0018] etching the second insulating layer and part of the sacrificial layer to form a second trench, the second trench exposing sidewalls of a plurality of the channel regions at the same positions of different layers and not exposing sidewalls of the first regions and the second regions, and the etching depth of the second insulating layer and the sacrificial layer being less than the thickness of the sacrificial layer to reserve a preset thickness of the sacrificial layer;

[0019] forming, in sequence, a gate insulating layer and a word line covering the bottom wall and the sidewalls of the second trench, and a first isolation layer filling the second trench;

[0020] etching to remove the remaining sacrificial layer to form a first hole corresponding to the first regions, a second hole corresponding to the second regions, and a lateral hole connecting the first hole and the second hole;

[0021] wet etching to remove the gate insulating layer exposed to the bottom wall of the lateral hole, the sidewalls of the first hole, and the sidewalls of the second hole; and wet etching to remove the word line towards the bottom wall of the lateral hole, the sidewalls of the first hole, and the sidewalls of the second hole;

[0022] forming a second isolation layer continuously extending in the first hole, the second hole, and the lateral hole.

[0023] In some embodiments, the forming of the second isolation layer continuously extending in the first hole, the second hole, and the lateral hole includes forming a third insulating layer covering inner walls of the first hole, the second hole, and the lateral hole.

[0024] forming a fourth insulating layer filling the first hole, the second hole, and the lateral hole; or forming a fourth insulating layer partially filling the first hole, the second hole, and the lateral hole, and a cavity being arranged in the fourth insulating layer in the lateral hole.

[0025] In some embodiments, the forming of the second isolation layer continuously extending in the first hole, the second hole, and the lateral hole includes:

[0026] forming a third insulating layer filling the first hole, the second hole, and the lateral hole; or forming a third insulating layer filling the first hole, the second hole, and the lateral hole, and a cavity being arranged in the third insulating layer in the lateral hole.

[0027] In some embodiments, the preset thickness is 20 nanometers to 500 nanometers.

[0028] In some embodiments, before the forming of the plurality of first trenches extending along the first direction through the stack structure, further comprising: forming a hard mask layer covering the first insulating layers and the semiconductor layers of the alternating stack;

[0029] When etching the second insulating layer and the sacrificial layer to form the second trench, the hard mask layer covering the channel region is also etched, and the channel region is not exposed;

[0030] The sequentially forming the gate insulating layer and the word line covering the bottom wall and the sidewall of the second trench, and the first isolation layer filling the second trench comprises:

[0031] Sequentially depositing a gate insulating film and a conductive film;

[0032] Forming the first isolation layer filling the second trench;

[0033] The gate insulating film and the conductive film outside the second trench are removed by grinding, to form the gate insulating layer and the word line covering the bottom wall and the sidewall of the second trench.

[0034] In some embodiments, the wet etching to remove the bottom wall of the word line towards the lateral hole, the sidewall of the word line towards the first hole, and the sidewall of the word line towards the second hole further comprises: wet etching to remove the second insulating layer exposed in the first hole, the second hole, and the lateral hole.

[0035] The electronic device comprises the semiconductor device of any one of the above embodiments, or is formed by the manufacturing method of the semiconductor device of any one of the above embodiments.

[0036] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly described herein.

[0037] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0038] SUMMARY

[0039] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is included to explain the present application, and are not intended to limit the present application.

[0040] FIG. 1A is a sectional view of a semiconductor layer of a semiconductor device according to an embodiment of the present disclosure along a direction parallel to the substrate, FIG. 1B is a sectional view along aa' direction in FIG. 1A, FIG. 1C is a sectional view along bb' direction in FIG. 1A, FIG. 1D is a sectional view along cc' direction in FIG. 1A, and FIG. 1E is a sectional view along dd' direction in FIG. 1A;

[0041] FIG. 2A is a cross-sectional view along the aa' direction after forming the plurality of semiconductor pillars according to some embodiments, FIG. 2B is a cross-sectional view along the bb' direction, FIG. 2C is a cross-sectional view along the cc' direction, and FIG. 2D is a cross-sectional view along the dd' direction;

[0042] FIG. 3A is a cross-sectional view along the aa' direction after forming the second trenches according to some embodiments, FIG. 3B is a cross-sectional view along the bb' direction, FIG. 3C is a cross-sectional view along the cc' direction, and FIG. 3D is a cross-sectional view along the dd' direction;

[0043] FIG. 4A is a cross-sectional view along the aa' direction after exposing the sidewalls of the semiconductor pillars according to some embodiments, FIG. 4B is a cross-sectional view along the bb' direction, FIG. 4C is a cross-sectional view along the cc' direction, and FIG. 4D is a cross-sectional view along the dd' direction;

[0044] FIG. 5A is a cross-sectional view along the aa' direction after forming the gate insulating layer and the word lines according to some embodiments, FIG. 5B is a cross-sectional view along the bb' direction, FIG. 5C is a cross-sectional view along the cc' direction, and FIG. 5D is a cross-sectional view along the dd' direction;

[0045] FIG. 6A is a cross-sectional view along the aa' direction after forming the third insulating layer and the fourth insulating layer according to some embodiments, FIG. 6B is a cross-sectional view along the bb' direction, FIG. 6C is a cross-sectional view along the cc' direction, and FIG. 6D is a cross-sectional view along the dd' direction;

[0046] FIG. 7A is a cross-sectional view along the aa' direction after etching to remove the word lines outside the second trenches according to some embodiments, FIG. 7B is a cross-sectional view along the bb' direction, FIG. 7C is a cross-sectional view along the cc' direction, and FIG. 7D is a cross-sectional view along the dd' direction;

[0047] FIG. 8A is a cross-sectional view along the aa' direction after etching to remove the sacrificial layer according to some embodiments, FIG. 8B is a cross-sectional view along the bb' direction, FIG. 8C is a cross-sectional view along the cc' direction, and FIG. 8D is a cross-sectional view along the dd' direction;

[0048] FIG. 9A is a cross-sectional view along the aa' direction after disconnecting the word lines of different rows according to some embodiments, FIG. 9B is a cross-sectional view along the bb' direction, FIG. 9C is a cross-sectional view along the cc' direction, and FIG. 9D is a cross-sectional view along the dd' direction;

[0049] FIG. 10A is a cross-sectional view along the aa' direction after forming the fifth insulating layer and the sixth insulating layer according to some embodiments, FIG. 10B is a cross-sectional view along the bb' direction, FIG. 10C is a cross-sectional view along the cc' direction, and FIG. 10D is a cross-sectional view along the dd' direction;

[0050] FIG. 11A is a cross-sectional view of the cavity along the direction of bb', FIG. 11B is a cross-sectional view along the direction of cc', and FIG. 11C is a cross-sectional view along the direction of dd', according to some embodiments.

[0051] DETAILED DESCRIPTION

[0052] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0053] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0054] The embodiments of the present disclosure are not necessarily limited to the sizes of the components shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0055] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of the components, and do not represent any order, number, or importance.

[0056] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0057] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection, a direct connection, or an indirect connection through an intermediate, or a communication between two elements inside. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0058] In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to a region through which current mainly flows.

[0059] In this disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0060] In this disclosure, "connection" includes a case where components are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the components to be connected. Examples of the element having a certain electrical action include not only electrodes and wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having various functions, and the like.

[0061] In this disclosure, "parallel" means approximately parallel or almost parallel, such as a state where the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus also includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means approximately perpendicular, such as a state where the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus also includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0062] "A and B are of an integral structure" in an embodiment of the present disclosure can mean that there is no clear boundary interface such as a clear boundary interface of a fault or a gap in a microscopic structure. Generally, a film layer formed by patterning on one film layer is of an integral structure. For example, A and B are formed as one film layer using the same material and are formed by the same patterning process to have a connection relationship.

[0063] In an embodiment of the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A and the boundary of the orthogonal projection of B overlap.

[0064] FIG. 1A is a sectional view of a semiconductor layer of a semiconductor device along a direction parallel to a substrate 1 according to an embodiment of the present disclosure, FIG. 1B is a sectional view along aa' direction in FIG. 1A, FIG. 1C is a sectional view along bb' direction in FIG. 1A, FIG. 1D is a sectional view along cc' direction in FIG. 1A, and FIG. 1E is a sectional view along dd' direction in FIG. 1A. As shown in FIGS. 1A-1E, the semiconductor device according to an embodiment of the present disclosure can include a plurality of transistors arranged in different layers on the substrate 1, and a word line 40 extending along a direction perpendicular to the substrate 1. The plurality of transistors in the same layer are arranged in a first direction X and a second direction Y. The transistors can include a semiconductor pillar 10 extending along the first direction X, the semiconductor pillar 10 including a first region 101, a channel region 103, and a second region 102 arranged in sequence along the first direction X. One of the first region 101 and the second region 102 is a source region, and the other is a drain region. The word line 40 can continuously extend on sidewalls of the channel regions 103 of the plurality of transistors in the same position in different layers. The first direction X is referred to as a row direction, and the second direction Y is referred to as a column direction. The word line 40 covering the sidewalls of the channel regions 103 of the transistors in different rows is discontinuous. The first direction X and the second direction Y are parallel to the substrate 1 and intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0065] A trench extending along the first direction X is present between the transistors of adjacent rows, and the trench separates the multi-layer transistors of adjacent rows. The trench can be provided with a first isolation layer and a second isolation layer. The first isolation layer is arranged on sidewalls of the word line 40 away from the channel region 103. The trench is separated by the first isolation layer into a first hole K1 and a second hole K2 corresponding to the first region 101 and the second region 102, respectively. The first hole K1 corresponds to the first region 101 of the plurality of transistors in different layers, and the second hole K2 corresponds to the second region 102 of the different plurality of transistors. The first hole K1 and the second hole K2 are in communication through a lateral hole K3 provided between the first isolation layer, the word line 40, and the substrate 1. The second isolation layer continuously extends between the first hole K1, the second hole K2, and the lateral hole K3.

[0066] The word line 40 covering the sidewalls of the channel regions 103 of the transistors in adjacent rows is discontinuous at the lateral hole K3. That is, the word line 40 is not arranged in the lateral hole K3, so that the adjacent word lines 40 are discontinuous.

[0067] The scheme provided by the present embodiment has a lateral hole between the word line and the substrate, which increases the distance between the word line and the substrate, reduces the leakage between the word line and the substrate, and by providing the first hole, the second hole, and the lateral hole in communication with each other, the word line between the transistors in different rows can be removed by one-time etching, which is easy to manufacture and reduces the process difficulty.

[0068] The gate electrode 26 of the transistor is part of the word line 40, i.e., the gate electrodes 26 of the transistors in the same position in different layers are connected to form the word line 40 in an integrated structure.

[0069] In some embodiments, the second isolation layer can fill the first hole K1, the second hole K2, and the lateral hole K3.

[0070] In some embodiments, the first isolation layer can include one or more insulating film layers, and the second isolation layer can include one or more insulating film layers.

[0071] In some embodiments, the first isolation layer can include a third insulating layer 13 and a fourth insulating layer 14. The third insulating layer 13 covers the side of the word line 40 away from the semiconductor pillar 10, and the fourth insulating layer 14 covers the third insulating layer 13 and fills the region between the channel regions 103 of adjacent transistors in the trench.

[0072] In some embodiments, the second isolation layer can include a fifth insulating layer 15 and a sixth insulating layer 16. The fifth insulating layer 15 covers the inner walls of the first hole K1, the second hole K2, and the lateral hole K3, and the sixth insulating layer 16 fills the first hole K1, the second hole K2, and the lateral hole K3. However, embodiments of the present disclosure are not limited thereto. The second isolation layer can include only one insulating film layer, or more insulating film layers. By providing insulating film layers of different structures, the leakage between the word line 40 and the substrate 1 can be improved.

[0073] In some embodiments, the second isolation layer can partially fill the first hole K1, the second hole K2, and the lateral hole K3. In this case, the second isolation layer can include a cavity, which is located at least in the lateral hole K3. The cavity can extend to the region of the first hole K1 close to the substrate 1, and the region of the second hole K2 close to the substrate 1.

[0074] When the second isolation layer includes multiple insulating film layers, such as the fifth insulating layer 15 and the sixth insulating layer 16, referring to FIGS. 11A, 11B, and 11C, a cavity 70 is provided in the sixth insulating layer 16 located at least in the lateral hole K3. The cavity 70 can extend into the first hole K1 and the second hole K2.

[0075] In some embodiments, the semiconductor device can further include: a gate insulating layer 24 disposed between the sidewall of the channel region 103 and the word line 40, the sidewall of the channel region 103 of the plurality of transistors at the same position of different layers continuously extends, the lateral hole K3 also separates the gate insulating layer 24 and the substrate 1. The end of the gate insulating layer 24, the end of the word line 40 is exposed in the lateral hole K3, and the gate insulating layer 24 and the word line 40 are isolated from the substrate 1 by the film layer filled in the lateral hole K3, so as to reduce the leakage between the word line 40 and the substrate 1.

[0076] In some embodiments, the gate insulating layers 24 of the transistors at the same position of different layers can be connected to form an integrated structure, so that the gate insulating layers 24 of the plurality of transistors can be manufactured by one process, and the process is simplified.

[0077] In some embodiments, the semiconductor device can further include a hard mask layer disposed on the side of the semiconductor pillar 10 away from the substrate 1 at the top layer, the hard mask layer forms a groove at the position of the channel region 103 away from the substrate 1, and the gate insulating layer 24 and the word line 40 are also distributed in the groove, that is, the word line 40 can be distributed on the opposite two sidewalls of the channel region 103 and in the groove on the side of the channel region 103 away from the substrate 1, so that the word lines 40 covering the opposite two sidewalls of the channel region 103 are connected. The first isolation layer also fills the groove. The hard mask layer can include a first hard mask layer 9 and a second hard mask layer 8 stacked in turn in the direction perpendicular to the substrate 1. The second hard mask layer 8 is disposed on the side of the first hard mask layer 9 away from the substrate 1.

[0078] The bit line is not shown in the above structure, and the semiconductor layer connected to the first region 101 or the second region 102 can be removed and replaced with a conductive line to realize the manufacture of the bit line.

[0079] The embodiments of the present disclosure further provide a manufacturing method of a semiconductor device, which can include:

[0080] S101, providing a substrate 1, and forming a stack structure including a first insulating layer 11 and a semiconductor layer 10' stacked alternately on the substrate 1; that is, the stack structure includes a plurality of first insulating layers 11 and a plurality of semiconductor layers 10', and the first insulating layer 11 and the semiconductor layer 10' are distributed alternately.

[0081] S102, a plurality of first trenches T1 extending along a first direction X are formed through the stack structure, and a semiconductor pillar 10 is formed between the first trenches T1 adjacent along a second direction Y; the semiconductor pillar 10 includes a first region 101, a channel region 103, and a second region 102 distributed along the first direction X in sequence; the first region 101, the channel region 103, and the second region 102 of the semiconductor pillar 10 can be doped to form a source region, a channel region, and a drain region of a transistor. When the first trench T1 is formed, the substrate 1 can be etched to a certain depth.

[0082] S103, a second insulating layer 12 covering inner walls of the first trench T1 and a sacrificial layer 7 filling the first trench T1 are formed.

[0083] S104, a second trench T2 is formed by etching the second insulating layer 12 and part of the sacrificial layer 7, the second trench T2 exposes sidewalls of a plurality of channel regions 103 at the same position of different layers, and does not expose sidewalls of the first region 101 and the second region 102, and the etching depth of the second insulating layer 12 and the sacrificial layer 7 is less than the thickness of the sacrificial layer 7 to retain a predetermined thickness of the sacrificial layer 7; that is, the second trench T2 exposes the channel regions 103 of a plurality of semiconductor layer pillars 10 of the stack structure.

[0084] S105, a gate insulating layer 24 and a word line 40 covering the bottom wall and the sidewall of the second trench T2 are sequentially formed.

[0085] S106, the remaining sacrificial layer 7 is etched and removed to form a first hole K1 corresponding to the first region 101, a second hole K2 corresponding to the second region 102, and a lateral hole K3 connecting the first hole K1 and the second hole K2; at this time, the gate insulating layer 24 is exposed in the first hole K1, the second hole K2, and the lateral hole K3;

[0086] S107, the gate insulating layer 24 exposed to the bottom wall of the lateral hole K3, the sidewall exposed to the first hole K1, and the sidewall exposed to the second hole K2 are removed by wet etching; and the word line 40 towards the bottom wall of the lateral hole K3, the sidewall towards the first hole K1, and the sidewall towards the second hole K2 are removed by wet etching.

[0087] The scheme provided by the embodiment can simultaneously remove the sidewall and the bottom word line by forming the first hole, the second hole, and the lateral hole, reduce the process steps, reduce the process difficulty, have a large process window, and can realize the removal of the sidewall and the bottom word line in a self-alignment manner. In addition, the distance between the word line and the substrate is increased, the leakage between the word line and the substrate can be reduced, and the size of the lateral hole can be changed as needed, so that the distance between the word line and the substrate can be adjusted.

[0088] In some embodiments, the method can further include forming a fifth insulating layer 15 covering the inner walls of the first hole K1, the second hole K2, and the lateral hole K3.

[0089] forming a sixth insulating layer 16 filling the first hole K1, the second hole K2, and the lateral hole K3, or forming a sixth insulating layer 16 filling the first hole K1, the second hole K2, and the lateral hole K3, and at least the sixth insulating layer 16 in the lateral hole K3 is provided with a cavity 70. That is, when forming the sixth insulating layer 16, it can not be completely filled, and a part of the area is left as a cavity to improve the leakage between the substrate 1 and the word line 40, but in the first hole K1 and the second hole K2, the area on the side away from the substrate 1 is completely filled. The cavity 70 can be achieved by controlling the depth of the lateral hole K3.

[0090] In some embodiments, the method can further include forming a sixth insulating layer 16 filling the first hole K1, the second hole K2, and the lateral hole K3, or forming a sixth insulating layer 16 filling the first hole K1, the second hole K2, and the lateral hole K3, and at least the sixth insulating layer 16 in the lateral hole K3 is provided with a cavity 70. In this embodiment, only one or part of the insulating film layer can be filled in the first hole K1, the second hole K2, and the lateral hole K3.

[0091] In some embodiments, the preset thickness can be 20 nanometers to 500 nanometers. At this thickness, the thickness of the word line 40 and the substrate 1 can be reduced, and the size of the device is not greatly affected.

[0092] In some embodiments, before forming the plurality of first trenches T1 extending along the first direction X through the stack structure, the method further includes forming a hard mask layer covering the alternately stacked first insulating layer 11 and semiconductor layer 10'; the hard mask layer can include one or more sequentially stacked film layers.

[0093] When etching the second insulating layer 12 and the sacrificial layer 7 to form the second trench T2, the hard mask layer covering the channel region 103 is also etched, and the channel region 103 is not exposed, that is, the hard mask layer is not completely etched, and a certain thickness of the hard mask layer is retained on the side of the channel region 103 away from the substrate 1; in addition, the hard mask layer covering the first region 101 and the second region 102 is not etched;

[0094] The sequentially forming the gate insulating layer 24 and the word line 40 covering the bottom wall and the sidewall of the second trench T2 includes:

[0095] sequentially depositing a gate insulating film and a conductive film;

[0096] forming a first isolation layer filling the second trench T2;

[0097] The gate insulating layer 24 and the word line 40 covering the bottom wall and the side wall of the second trench T2 are formed by removing the gate insulating film and the conductive film outside the second trench T2 by polishing.

[0098] In some embodiments, before the wet etching removes the bottom wall of the word line 40 towards the lateral hole K3, the side wall of the word line 40 towards the first hole K1 and the side wall of the word line 40 towards the second hole K2, the wet etching can further remove the second insulating layer 12 exposed in the first hole K1, the second hole K2 and the lateral hole K3. At this time, the first region 101 and the second region 102 of the semiconductor pillar 10 are exposed, and the first region 101 and the second region 102 can be doped according to the doping requirements of the source region and the drain region.

[0099] The technical scheme of the embodiment is further illustrated by the manufacturing process of the semiconductor device in the embodiment. The "patterning process" in the embodiment includes deposition of a film, coating of photoresist, mask exposure, development, etching, stripping of photoresist and the like, which are mature manufacturing processes in the related art. The "photolithography process" in the embodiment includes coating of a film, mask exposure and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the embodiment, it should be understood that "film" refers to a thin film of a certain material on a substrate manufactured by deposition or coating process. If the "film" does not need patterning process or photolithography process during the entire manufacturing process, the "film" can also be referred to as "layer". If the "film" still needs patterning process or photolithography process during the entire manufacturing process, it is referred to as "film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".

[0100] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0101] 1) forming a plurality of semiconductor pillars 10;

[0102] depositing a first insulating film and a semiconductor film on the substrate 1 in sequence to form a stack structure including alternately stacked first insulating layers 11 and semiconductor layers 10';

[0103] depositing a first hard mask film and a second hard mask film in sequence to form a first hard mask layer 9 and a second hard mask layer 8 covering the stack structure;

[0104] The second hard mask layer 8, the first hard mask layer 9, the first insulating layer 11 and the semiconductor layer 10' in the alternative stack, and the substrate 1 are etched in a direction perpendicular to the substrate 1 to form a plurality of first trenches T1; the bottom of the plurality of first trenches T1 exposes the substrate 1; the first trenches T1 extend along the first direction X, and the plurality of first trenches T1 are spaced apart along the second direction Y; adjacent first trenches T1 define a semiconductor pillar 10 extending along the first direction X.

[0105] A second insulating film and a sacrificial layer film are sequentially deposited to form a second insulating layer 12 covering the bottom wall and the sidewall of the first trench T1 and a sacrificial layer 7 filling the first trench T1, as shown in FIGS. 2A, 2B, 2C and 2D, wherein FIG. 2A is a cross-sectional view along the aa' direction after forming the plurality of semiconductor pillars 10, FIG. 2B is a cross-sectional view along the bb' direction after forming the plurality of semiconductor pillars 10, FIG. 2C is a cross-sectional view along the cc' direction after forming the plurality of semiconductor pillars 10, and FIG. 2D is a cross-sectional view along the dd' direction after forming the plurality of semiconductor pillars 10.

[0106] In some embodiments, the first semiconductor film can be silicon or polycrystalline silicon or the like material with a band gap less than 1.65 eV, or can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0107] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, and the like; and can also include other small amounts of doped elements.

[0108] In some embodiments, the material of the metal-oxide semiconductor layer or channel can include one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor meets the requirements, which can be adjusted according to actual conditions.

[0109] The band gap of these materials is wide, and the leakage current is low. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0110] The material of the metal-oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0111] In some embodiments, the first insulating thin film can be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2), and the like.

[0112] In some embodiments, the first hard mask thin film can be a low-K dielectric layer, such as SiO2, and the like.

[0113] In some embodiments, the second hard mask thin film can be a film layer that has an etching selectivity with the first insulating thin film, such as silicon nitride (SiN), and the like.

[0114] In some embodiments, the second insulating thin film can be a film layer that has an etching selectivity with the first insulating thin film.

[0115] In some embodiments, the sacrificial layer thin film can be polysilicon.

[0116] 2) forming a second trench T2;

[0117] The second hard mask layer 8, the sacrificial layer 7 and the second insulating layer 12 are etched along a direction perpendicular to the substrate 1 to form a second trench T2 extending along the second direction Y. The second trench T2 defines a channel region (i.e., a channel region 103) of the semiconductor pillar 10 and a region between channel regions adjacent along the second direction Y. The channel region is located in a middle portion of the semiconductor pillar 10, and two ends of the channel region are a first region 101 and a second region 102. One of the first region 101 and the second region 102 is a source region, and the other is a drain region. The second hard mask layer 8 is etched to a first preset depth (without etching through the second hard mask layer 8) in a region corresponding to the channel region, and the second insulating layer 12 is etched to the first preset depth. The sacrificial layer 7 is etched to a second preset depth, and is etched to a bottommost semiconductor pillar 10 and a preset thickness of the sacrificial layer 7 is reserved. The preset thickness can be 20 nanometers (nm) to 500 nm. As shown in FIGS. 3A, 3B, 3C and 3D, FIG. 3A is a cross-sectional view along an aa' direction after the second trench T2 is formed according to some embodiments, FIG. 3B is a cross-sectional view along a bb' direction after the second trench T2 is formed according to some embodiments, FIG. 3C is a cross-sectional view along a cc' direction after the second trench T2 is formed according to some embodiments, and FIG. 3D is a cross-sectional view along a dd' direction after the second trench T2 is formed according to some embodiments.

[0118] In some embodiments, the second hard mask layer 8, the sacrificial layer 7 and the second insulating layer 12 can be etched by dry etching, and then the sacrificial layer 7 remaining on the second insulating layer 12 in the channel region can be removed by wet etching.

[0119] In this embodiment, by controlling the etching depth of the sacrificial layer 7, the distance between the word line 40 and the substrate 1 can be controlled, that is, the distance between the word line 40 and the substrate 1 is adjustable.

[0120] 3) The second insulating layer 12 exposed in the second trench T2 is etched and removed to expose the sidewall of the channel region of the semiconductor pillar 10. As shown in FIGS. 4A, 4B, 4C and 4D, FIG. 4A is a cross-sectional view along an aa' direction after the sidewall of the semiconductor pillar 10 is exposed according to some embodiments, FIG. 4B is a cross-sectional view along a bb' direction after the sidewall of the semiconductor pillar 10 is exposed according to some embodiments, FIG. 4C is a cross-sectional view along a cc' direction after the sidewall of the semiconductor pillar 10 is exposed according to some embodiments, and FIG. 4D is a cross-sectional view along a dd' direction after the sidewall of the semiconductor pillar 10 is exposed according to some embodiments.

[0121] In some embodiments, the region exposed by the semiconductor pillar 10 can be doped according to the doping requirement of the channel region to form the channel region.

[0122] In some embodiments, the second insulating layer 12 exposed in the second trench T2 can be removed by wet etching.

[0123] 4) Forming the gate insulating layer 24 and the word line 40;

[0124] The gate insulating layer 24 covers the bottom wall and the sidewall of the second trench T2, and the film layer of the topmost layer outside the second trench T2 region away from the substrate 1 side. The word line 40 covers the gate insulating layer 24 away from the substrate 1 side, as shown in FIGS. 5A, 5B, 5C, and 5D, wherein FIG. 5A is a cross-sectional view along the aa' direction after forming the gate insulating layer 24 and the word line 40 in some embodiments, FIG. 5B is a cross-sectional view along the bb' direction after forming the gate insulating layer 24 and the word line 40 in some embodiments, FIG. 5C is a cross-sectional view along the cc' direction after forming the gate insulating layer 24 and the word line 40 in some embodiments, and FIG. 5D is a cross-sectional view along the dd' direction after forming the gate insulating layer 24 and the word line 40 in some embodiments.

[0125] In the exemplary embodiments of the present disclosure, the material of the gate insulating layer 24 can include one or more layers of High-K dielectric material, such as dielectric material with a dielectric constant K≥3.9. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. can be included. Exemplary, such as, but not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0126] In some embodiments, the conductive film can be one or more of the following different types of materials:

[0127] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc. metals; can be a metal alloy containing the aforementioned metals;

[0128] Or, it can be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc. conductive metal oxide materials; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc. conductive metal nitride materials;

[0129] Or, it can be a conductive polycrystalline silicon, silicon, germanium, silicon germanium, etc. after doping.

[0130] 5) Forming the third insulating layer 13 and the fourth insulating layer 14;

[0131] A third insulating film is deposited to form a third insulating layer 13 covering the word lines 40;

[0132] After the fourth insulating film is deposited, it is polished (with the third insulating layer 13 as a stop layer) to form a fourth insulating layer 14 filling the second trenches T2, as shown in FIGS. 6A, 6B, 6C and 6D, wherein FIG. 6A is a cross-sectional view along the direction of aa' after the third insulating layer 13 and the fourth insulating layer 14 are formed, FIG. 6B is a cross-sectional view along the direction of bb' after the third insulating layer 13 and the fourth insulating layer 14 are formed, FIG. 6C is a cross-sectional view along the direction of cc' after the third insulating layer 13 and the fourth insulating layer 14 are formed, and FIG. 6D is a cross-sectional view along the direction of dd' after the third insulating layer 13 and the fourth insulating layer 14 are formed.

[0133] In some embodiments, the fourth insulating film can be a low-K dielectric layer, such as SiO2, etc.

[0134] In some embodiments, the third insulating film can be a film layer having etching selectivity with the fourth insulating film, such as SiN, etc.

[0135] In some embodiments, the thickness of the third insulating layer 13 can be 10-20 nm.

[0136] 6) Etching to remove the word lines 40 outside the second trenches T2;

[0137] The gate insulating layer 24, the word lines 40, the third insulating layer 13 and the fourth insulating layer 14 outside the second trenches T2 are etched and removed, which can be removed by CMP, with the second hard mask layer 8 as an etching stop layer, to etch and remove the gate insulating layer 24, the word lines 40, the third insulating layer 13 and the fourth insulating layer 14 outside the second trenches T2, as shown in FIGS. 7A, 7B, 7C and 7D, wherein FIG. 7A is a cross-sectional view along the direction of aa' after the word lines 40 outside the second trenches T2 are etched and removed, FIG. 7B is a cross-sectional view along the direction of bb' after the word lines 40 outside the second trenches T2 are etched and removed, FIG. 7C is a cross-sectional view along the direction of cc' after the word lines 40 outside the second trenches T2 are etched and removed, and FIG. 7D is a cross-sectional view along the direction of dd' after the word lines 40 outside the second trenches T2 are etched and removed. The scheme provided in the present embodiment removes the word lines 40 at the top by polishing, without the need for a photomask, and can be realized in a self-aligned manner, thus simplifying the process.

[0138] At this time, the surface of the sacrificial layer 7 inside the first trenches T1 away from the substrate 1 is exposed.

[0139] 7) etching to remove the sacrificial layer 7;

[0140] The first hole K1 is adjacent to the first region 101 of the semiconductor pillar 10, the second hole K2 is adjacent to the second region 102 of the semiconductor pillar 10, and the lateral hole K3 is disposed between the gate insulating layer 24 and the substrate 1, and communicates the first hole K1 and the second hole K2. At this time, the bottom wall of the gate insulating layer 24 toward the substrate 1 side is exposed in the lateral hole K3, one side wall of the gate insulating layer 24 is exposed in the first hole K1, and the other side wall of the gate insulating layer 24 is exposed in the second hole K2. The gate insulating layer 24 covers the side wall of the channel region 103 of the semiconductor pillar 10 which is not exposed, as shown in FIGS. 8A, 8B, 8C, and 8D. FIG. 8A is a cross-sectional view along the direction of aa' after etching to remove the sacrificial layer 7 according to some embodiments, FIG. 8B is a cross-sectional view along the direction of bb' after etching to remove the sacrificial layer 7 according to some embodiments, FIG. 8C is a cross-sectional view along the direction of cc' after etching to remove the sacrificial layer 7 according to some embodiments, and FIG. 8D is a cross-sectional view along the direction of dd' after etching to remove the sacrificial layer 7 according to some embodiments.

[0141] In some embodiments, the sacrificial layer 7 can be removed by wet etching.

[0142] 8) disconnecting the word lines 40 of different rows;

[0143] The bottom wall of the gate insulating layer 24 toward the substrate 1 side which is exposed, and the side walls of the gate insulating layer 24 exposed in the first hole K1 and the second hole K2, respectively, are removed by wet etching. At this time, the bottom wall of the word line 40 toward the substrate 1 side is exposed, and the side walls of the word line 40 toward the first hole K1 and the second hole K2, respectively, are exposed. The bottom wall of the word line 40 toward the substrate 1 side, and the side walls of the word line 40 toward the first hole K1 and the second hole K2, respectively, are removed by wet etching, so that the word lines 40 of different rows can be disconnected, as shown in FIGS. 9A, 9B, 9C, and 9D. FIG. 9A is a cross-sectional view along the direction of aa' after disconnecting the word lines 40 of different rows according to some embodiments, FIG. 9B is a cross-sectional view along the direction of bb' after disconnecting the word lines 40 of different rows according to some embodiments, FIG. 9C is a cross-sectional view along the direction of cc' after disconnecting the word lines 40 of different rows according to some embodiments, and FIG. 9D is a cross-sectional view along the direction of dd' after disconnecting the word lines 40 of different rows according to some embodiments.

[0144] The scheme provided by the embodiment removes the conductive film between the bottom and the adjacent rows by one-time wet etching, disconnects the word lines 40 of different rows, and compared with the scheme of removing the word lines between the bottom and the adjacent rows by two processes respectively, the scheme reduces the process steps and the cost, and in the related art, the scheme of etching the word line at the bottom by dry etching is affected by the height difference and the trench aspect ratio, and has great process difficulty and small process window, and the scheme provided by the embodiment has simple process and large process window. In addition, when etching and removing the sidewalls of the word line 40 towards the first hole K1 and the second hole K2, a mask is not needed, and the etching can be realized in a self-alignment manner, and the process is simple.

[0145] In some embodiments, when etching and removing the gate insulating layer 24, the second insulating layer 12 can also be etched and removed, at this time, the source region and the drain region of the semiconductor column 10 are exposed, and the two sides of the semiconductor column 10 located in the channel region can be doped according to the doping requirements of the source region and the drain region, to form the source region and the drain region.

[0146] 9) forming a fifth insulating layer 15 and a sixth insulating layer 16;

[0147] The fifth insulating layer 15 covers the inner walls of the first hole K1, the second hole K2 and the horizontal hole K3. The sixth insulating layer 16 can fill the first hole K1, the second hole K2 and the horizontal hole K3. As shown in FIGS. 10A, 10B, 10C and 10D, wherein FIG. 10A is a cross-sectional view along the aa' direction after forming the fifth insulating layer 15 and the sixth insulating layer 16 according to some embodiments, FIG. 10B is a cross-sectional view along the bb' direction after forming the fifth insulating layer 15 and the sixth insulating layer 16 according to some embodiments, FIG. 10C is a cross-sectional view along the cc' direction after forming the fifth insulating layer 15 and the sixth insulating layer 16 according to some embodiments, and FIG. 10D is a cross-sectional view along the dd' direction after forming the fifth insulating layer 15 and the sixth insulating layer 16 according to some embodiments.

[0148] In some embodiments, the fifth insulating film can be SiN, and the sixth insulating film can be SiO2, etc.

[0149] In some embodiments, the sixth insulating layer 16 can not completely fill the first hole K1, the second hole K2 and the lateral hole K3, and a cavity 70 can be formed in the lateral hole K3, and the cavity 70 can also be distributed in the first hole K1 and the second hole K2 close to the substrate 1. As shown in FIG. 11A, FIG. 11B and FIG. 11C, wherein FIG. 11A is a cross-sectional view along the direction of bb' after forming the cavity 70 according to some embodiments, FIG. 11B is a cross-sectional view along the direction of cc' after forming the cavity 70 according to some embodiments, and FIG. 11C is a cross-sectional view along the direction of dd' after forming the cavity 70 according to some embodiments. According to the scheme provided in the present embodiment, by forming the cavity 70 in the region between the word line 40 and the substrate 1, the leakage between the word line 40 and the substrate 1 can be reduced.

[0150] In some embodiments, the fifth insulating film can not be deposited, and the sixth insulating film can be directly deposited to form the sixth insulating layer 16, which can fill the first hole K1, the second hole K2 and the lateral hole K3, or partially fill the first hole K1, the second hole K2 and the lateral hole K3 to form the cavity 70 (which can be formed in the lateral hole K3) arranged on the side of the word line 40 facing the substrate 1; or the fifth insulating film, the sixth insulating film and the seventh insulating film can be sequentially deposited, and the seventh insulating film can fill or partially fill the first hole K1, the second hole K2 and the lateral hole K3, and so on. The insulating film layers in the first hole K1, the second hole K2 and the lateral hole K3 can be arranged as needed, and the present embodiment is not limited in this regard.

[0151] The present embodiment also provides an electronic device comprising the semiconductor device according to any one of the preceding embodiments or the semiconductor device formed by the manufacturing method according to any one of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0152] Although the embodiments of the present application are disclosed as above, the content described above is only the embodiments adopted for the purpose of facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the form and details without departing from the spirit and scope of the present application disclosed, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: A plurality of transistors distributed in different layers on a substrate, word lines extending in a direction perpendicular to the substrate; A plurality of transistors in the same layer are arrayed in a first direction and a second direction; the transistors include semiconductor pillars extending in the first direction, the semiconductor pillars include a first region, a channel region and a second region distributed in the first direction in sequence, and the word lines continuously extend on sidewalls of the channel regions of the plurality of transistors in the same position in different layers; The semiconductor device further includes trenches of the transistors extending in the first direction and spaced in different rows in the second direction, the trenches are provided with a first isolation layer and a second isolation layer, the first isolation layer is distributed on sidewalls of the word lines away from the channel regions; the first isolation layer separates the trenches into first holes and second holes corresponding to the first region and the second region respectively; the first isolation layer, the word lines and the substrate are separated by a lateral hole; the first hole and the second hole are communicated through the lateral hole, and the second isolation layer continuously extends in the first hole, the second hole and the lateral hole.

2. The semiconductor device of claim 1, wherein, The second isolation layer includes a first insulating layer covering inner walls of the first hole, the second hole and the lateral hole, and a second insulating layer filling the first hole, the second hole and the lateral hole.

3. The semiconductor device of claim 1, wherein, The second isolation layer includes a first insulating layer covering inner walls of the first hole, the second hole and the lateral hole, and a second insulating layer partially filling the first hole, the second hole and the lateral hole, and the second insulating layer at least in the lateral hole is provided with a cavity.

4. The semiconductor device of claim 1, wherein, The second isolation layer fills the first hole, the second hole and the lateral hole; or the second isolation layer partially fills the first hole, the second hole and the lateral hole, and the second isolation layer at least in the lateral hole is provided with a cavity.

5. The semiconductor device according to any one of claims 1 to 4, wherein The semiconductor device further includes a gate insulating layer provided between sidewalls of the channel regions and the word lines, and continuously extending on sidewalls of the channel regions of the plurality of transistors in the same position in different layers, and the lateral hole further separates the gate insulating layer and the substrate.

6. A manufacturing method of a semiconductor device, comprising: providing a substrate, and forming a stack structure including alternately stacked first insulating layers and semiconductor layers on the substrate; forming a plurality of first trenches extending in a first direction through the stack structure, and forming semiconductor pillars between the first trenches adjacent in a second direction; the semiconductor pillars include a first region, a channel region and a second region distributed in the first direction in sequence; forming a second insulating layer covering inner walls of the first trenches and a sacrificial layer filling the first trenches; etching the second insulating layer and part of the sacrificial layer to form second trenches, the second trenches expose sidewalls of a plurality of the channel regions in the same position in different layers, and do not expose sidewalls of the first region and sidewalls of the second region, and the etching depth of the second insulating layer and the sacrificial layer is less than the thickness of the sacrificial layer to reserve a predetermined thickness of the sacrificial layer; forming a gate insulating layer and a word line covering the bottom wall and the side wall of the second trench, and a first isolation layer filling the second trench; etching the remaining sacrificial layer to form a first hole corresponding to the first region, a second hole corresponding to the second region, and a lateral hole connecting the first hole and the second hole; wet etching to remove the gate insulating layer exposed to the bottom wall of the lateral hole, the side wall of the first hole, and the side wall of the second hole; wet etching to remove the word line exposed to the bottom wall of the lateral hole, the side wall of the first hole, and the side wall of the second hole; forming a second isolation layer continuously extending in the first hole, the second hole, and the lateral hole. The forming of the second isolation layer continuously extending in the first hole, the second hole, and the lateral hole includes:

7. The method of manufacturing a semiconductor device according to claim 6, wherein forming a third insulating layer covering the inner wall of the first hole, the second hole, and the lateral hole; forming a fourth insulating layer filling the first hole, the second hole, and the lateral hole; or, forming a fourth insulating layer partially filling the first hole, the second hole, and the lateral hole, and a cavity is arranged in the fourth insulating layer in the lateral hole. The forming of the second isolation layer continuously extending in the first hole, the second hole, and the lateral hole includes:

8. The method of manufacturing a semiconductor device according to claim 6, wherein forming a third insulating layer filling the first hole, the second hole, and the lateral hole; or, forming a third insulating layer filling the first hole, the second hole, and the lateral hole, and a cavity is arranged in the third insulating layer in the lateral hole. The preset thickness is 20 nanometers to 500 nanometers.

9. The method of manufacturing a semiconductor device according to claim 6, wherein 10. The method of claim 6, wherein, Before forming a plurality of first trenches extending in a first direction through the stack structure, further comprising: forming a hard mask layer covering the alternately stacked first insulating layers and semiconductor layers; When etching the second insulating layer and the sacrificial layer to form the second trench, the hard mask layer covering the channel region is also etched, and the channel region is not exposed; The forming of the gate insulating layer and the word line covering the bottom wall and the side wall of the second trench, and the first isolation layer filling the second trench includes: sequentially depositing a gate insulating film and a conductive film; forming a first isolation layer filling the second trench; removing the gate insulating film and the conductive film outside the second trench by polishing to form the gate insulating layer and the word line covering the bottom wall and the side wall of the second trench. Before the wet etching to remove the word line exposed to the bottom wall of the lateral hole, the side wall of the first hole, and the side wall of the second hole, further comprising: wet etching to remove the second insulating layer exposed in the first hole, the second hole, and the lateral hole.

11. The method of manufacturing a semiconductor device according to claim 6, wherein 12. An electronic device comprising the semiconductor device of any one of claims 1 to 5, or the semiconductor device formed according to the method of any one of claims 6 to 11. ​

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