Optical transport network signal processing method, storage medium, and electronic apparatus

Abstract

Provided in the embodiments of the present disclosure are an optical transport network signal processing method, a storage medium, and an electronic apparatus. The method comprises: periodically adding alignment marker information to an optical transport network signal to obtain a first signal; periodically adding forward error correction information to the first signal to obtain a second signal; distributing the second signal onto a plurality of channels to obtain a plurality of channel signals; and sending the channel signal on each channel.

Description

Optical transport network signal processing method, storage medium and electronic device

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on Chinese Patent Application CN202410542517.7 entitled "Optical transport network signal processing method, storage medium and electronic device" filed on April 30, 2024, and claiming priority to the patent application, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the field of communications, and in particular, to an optical transport network signal processing method, a storage medium and an electronic device. BACKGROUND

[0004] Since the highest signal rate that a single physical channel can transmit is limited, when the rate of an optical transport network signal is greater than the highest signal rate that a single physical channel can transmit, the optical transport network signal needs to be split into multiple channel signals. For example, when the rate of an optical transport unit Cn (OTUCn for short) signal is greater than the highest transmission rate of a physical channel, the OTUCn signal needs to be converted into m channel signals to be transmitted on the physical channel, where m is an integer greater than or equal to 1, and the rate of the OTUCn signal divided by m is equal to the transmission rate on the physical channel.

[0005] Currently, before splitting the optical transport network signal into multiple channel signals, the optical transport network signal also needs to be added with forward error correction (FEC for short) information. In related technologies, in order to add forward error correction information to an optical transport network signal and then split it into multiple channel signals, the optical transport network signal needs to meet the following two conditions: condition 1 is that the frame length of the optical transport network signal must be an integer multiple of the payload bit number of the forward error correction encoding block, and condition 2 is that there must be a specific length of alignment marker (AM for short) overhead in the overhead of the optical transport network signal. Meeting these two conditions can make a part of the alignment marker overhead periodically appear on each channel signal after the optical transport signal is split into multiple channel signals.

[0006] However, the existence of the condition 1 and the condition 2 causes limitations in the frame length and the alignment flag overhead definition of the optical transport network signal. For the optical transport network signal that does not meet the condition 1 or the condition 2, the optical transport network signal cannot be directly split into multiple channel signals. In the related art, the optical transport network signal that does not meet the condition 1 or the condition 2 needs to be converted into a flexible optical transport network (FlexO for short) signal that meets the condition 1 and the condition 2, and then the FlexO signal is split into multiple channel signals. However, when the size of the forward error correction coding block changes or the number of the multiple channel signals changes, a new signal that meets the condition 1 and the condition 2 needs to be redefined, and then the optical transport signal is converted into the new signal. This scheme needs to define multiple signals with different frame structures, has poor adaptability, and the hardware implementation is also relatively complex.

[0007] In summary, there is no good solution to the above problems. SUMMARY

[0008] Embodiments of the present disclosure provide an optical transport network signal processing method, a storage medium and an electronic device to at least solve the problem of complex hardware implementation and poor adaptability of optical transport network signal multi-channel transmission in the related art.

[0009] According to an embodiment of the present disclosure, an optical transport network signal processing method is provided, which includes: periodically adding alignment flag information in an optical transport network signal to obtain a first signal; periodically adding forward error correction information in the first signal to obtain a second signal; distributing the second signal to multiple channels to obtain multiple channel signals; and transmitting the channel signal on each channel.

[0010] According to another embodiment of the present disclosure, a computer-readable storage medium is also provided, which stores a computer program, and when the computer program is run by a processor, the steps in any of the above method embodiments are executed.

[0011] According to another embodiment of the present disclosure, an electronic device is also provided, which includes a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a hardware structure block diagram of an optical transport network signal processing method according to an embodiment of the present disclosure;

[0013] FIG. 2 is a flowchart of an optical transport network signal processing method according to an embodiment of the present disclosure (I);

[0014] FIG. 3 is a flowchart of an optical transport network signal processing method according to an embodiment of the present disclosure (II);

[0015] FIG. 4 is a schematic diagram of alignment flag overhead distribution to 4 channel signals according to an embodiment of the present disclosure;

[0016] FIG. 5 is a schematic diagram of alignment flag overhead value distribution to 4 channels according to an embodiment of the present disclosure;

[0017] FIG. 6 is a schematic diagram of alignment flag overhead distribution to 8 channel signals according to an embodiment of the present disclosure;

[0018] FIG. 7 is a schematic diagram of first information value distribution in alignment flag overhead to 8 channels according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0020] It should be noted that the terms "first", "second", and the like in the description and claims of the present disclosure and the above-described accompanying drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0021] The method embodiments provided in the embodiments of the present disclosure can be executed on a network node in an optical transport network, which includes a computer terminal or similar computing device. Taking a computer terminal as an example, FIG. 1 is a hardware structure block diagram of an optical transport network signal processing method according to an embodiment of the present disclosure. As shown in FIG. 1, a hardware single board can include one or more (only one is shown in FIG. 1) processors 12 (the processor 12 can include but is not limited to a processing device such as a microprocessor MCU or programmable logic device) and a memory 14 for storing data, wherein the above-mentioned computer terminal can further include a transmission device 16 for communication function and an input and output device 18. Those skilled in the art can understand that the structure shown in FIG. 1 is only schematic, which does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal can further include more or less components than those shown in FIG. 1, or have a different configuration from that shown in FIG. 1.

[0022] The memory 14 can be used to store computer programs, such as software programs of application software and modules, such as a computer program corresponding to the OTN signal processing method in the embodiments of the present disclosure. The processor 12 can execute various functions and the OTN signal processing method, i.e., implement the method described above, by running the computer program stored in the memory 14. The memory 14 can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 14 can further include a memory remotely arranged with respect to the processor 12, and the remote memory can be connected to the computer terminal through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0023] The transmission device 16 is configured to receive or send data via a network. Examples of the network include a wireless network provided by a communication provider. In one example, the transmission device 16 includes a network adapter (NIC) that can be connected to other network devices through a base station to communicate with the Internet. In one example, the transmission device 16 can be a radio frequency (RF) module configured to communicate with the Internet in a wireless manner.

[0024] In an embodiment of the present disclosure, an OTN signal processing method is provided, which can be divided into a processing method on a sending side and a processing method on a receiving side. The processing method on the sending side and the processing method on the receiving side can be run in the same network node or in different network nodes, and the processing parameters on the sending side and the processing parameters on the receiving side are the same or cooperate with each other.

[0025] FIG. 2 is a flowchart of the OTN signal processing method according to an embodiment of the present disclosure, which is applied to the sending side. As shown in FIG. 2, the flow includes the following steps:

[0026] In step S202, alignment flag information is periodically added in an OTN signal to obtain a first signal.

[0027] In step S204, forward error correction information is periodically added in the first signal to obtain a second signal.

[0028] In step S206, the second signal is distributed to a plurality of channels to obtain a plurality of channel signals.

[0029] In step S208, the channel signal on each channel is sent.

[0030] In the embodiments of the present disclosure, through the steps S202 to S208, the alignment mark information can be actively added on the sending side of the OTN signal to realize the multi-channel transmission processing of the OTN signal, and the frame length of the OTN signal has no special restriction, and the flexible splitting of the OTN signal can be realized when the OTN signal does not meet the multi-channel transmission restriction condition, and there is no specific length alignment mark overhead in the overhead, and the embodiments of the present disclosure can be widely applied to different forward error correction encoding algorithms and different channel numbers, thereby solving the problems of complex hardware implementation and poor adaptability of the multi-channel transmission of the OTN signal in the related art.

[0031] In the related art, the frame length and the alignment mark overhead of the OTN signal are limited, and for the OTN signal whose frame length and the encoding block payload length in the forward error correction encoding algorithm do not match, or there is no specific length alignment mark overhead in the overhead, the OTN signal cannot be directly split into multi-channel signals after the forward error correction encoding processing, and it is necessary to first define a fixed-length frame signal with a specific frame length and a specific length alignment mark overhead in the overhead, then put the OTN signal into the fixed-length frame signal, and then perform the forward error correction encoding processing on the fixed-length frame signal, and then split it into multi-channel signals. In the embodiments of the present disclosure, the frame length and the alignment mark of the OTN signal are not limited, and the adaptability is stronger. The method in the embodiments of the present disclosure is especially suitable for the case that the same OTN signal needs to perform multiple forward error correction encoding algorithms, and the number of channels to be split has multiple types, wherein the number of channels has 2, 4, and 8, which corresponds to three types of channel numbers. The more the types of forward error correction encoding algorithms and the more the types of channel numbers, the greater the technical advantage of the present disclosure compared with other methods.

[0032] The embodiments of the present disclosure can be applied to different types of OTN signals. Correspondingly, the OTN signal includes but is not limited to OTUCn, OTUk, FlexO, etc.

[0033] In an exemplary embodiment, the alignment mark information is an alignment mark overhead, and the forward error correction information is check information in a forward error correction encoding block.

[0034] In some embodiments, the number of bits of the alignment mark information is a, wherein a is an integer greater than 1; the alignment mark information includes first information of b bits, wherein b is an integer greater than 1, and b is less than or equal to a, b is an integer multiple of the number of channels c, the plurality of channels include c channels, and c is a positive integer; the first information is evenly distributed to the plurality of channels to align the plurality of channel signals by identifying the position of the first information, wherein the value of the first information is a preset bit value.

[0035] In the embodiment, the first information is evenly distributed to c channels, and b / c bits in the first information are on each channel. The value of the first information can be determined according to a communication standard protocol, and the number of bits and the value of the first information can be different in transmission scenarios of different communication rates and different numbers of channels.

[0036] In some embodiments, the alignment flag information further includes second information, where the number of bits of the second information is a-b, and the second information is used to monitor or manage the first signal.

[0037] In an exemplary embodiment, the second information can represent a physical state of the first signal, where the physical state can include normal, local failure, remote time slot, etc.; the second information can also be used to record a sending address and a receiving address of the first signal; or the second information can also be used to deliver monitoring information, etc.

[0038] In an exemplary embodiment, if a=b, the alignment flag information only includes the first information and does not include the second information.

[0039] In some embodiments, the method further includes: in step S200, determining, according to a preset forward error correction encoding algorithm, that a payload length of a forward error correction encoding block is d bits, a check information length of the forward error correction encoding block is v bits, a length of the forward error correction encoding block is u bits, and a symbol length of the forward error correction encoding block is w bits, where d, v, u, and w are positive integers, u=d+v, and d, v, and u are integer multiples of w.

[0040] The embodiments of the present disclosure can be applied to different forward error correction encoding algorithms, and for different algorithms, only the related parameters d, v, u, and w need to be adjusted, and the adjustment method is simpler.

[0041] In some embodiments, step S202 can include: in the optical transport network signal, adding one alignment flag information every e*d-a bits to obtain the first signal, where the first signal includes a plurality of first bit blocks, each first bit block includes e*d bits, and the first a bits in each first bit block are the alignment flag information, and e is an integer greater than 1.

[0042] In the embodiment, the period of adding the alignment flag information can be determined according to the length of the alignment flag information and the parameters of the forward error correction encoding block, so that the number of bits of the first signal in each period meets the condition that the number of bits of the first signal is an integer multiple of the number of payload bits of the forward error correction encoding block, and thus the frame length of the original optical transport network signal does not need to be limited.

[0043] It can be understood that different forward error correction encoding algorithms can be selected for the same optical transport network signal, and the specific values of e, d, v, u and w corresponding to each forward error correction encoding algorithm can be different. For example, for forward error correction encoding algorithm 1, the specific values of e, d, v, u and w are e1, d1, v1, u1 and w1 respectively; for forward error correction encoding algorithm 2, the specific values of e, d, v, u and w are e2, d2, v2, u2 and w2 respectively.

[0044] In some embodiments, step S204 can include the following steps:

[0045] Step S2042, in the first signal, the positions of the plurality of first bit blocks are located according to the alignment mark information;

[0046] Step S2044, the first signal is evenly divided into f third signals in units of w bits, where f is a positive integer, e is an integer multiple of f, each first bit block in the first signal is evenly divided into f second bit blocks, the f second bit blocks belong to the f third signals respectively, each second bit block contains e*d / f bits, and each third signal includes a plurality of second bit blocks;

[0047] Step S2046, in each second bit block of the f third signals, the d bits are taken as the payload of one forward error correction encoding block, the v bits of the check information of the forward error correction encoding block are added after the payload of each forward error correction encoding block, to obtain f fourth signals, where the forward error correction information includes the check information of the forward error correction encoding block, the check information of the forward error correction encoding block is generated by performing the preset forward error correction encoding algorithm on the payload of the forward error correction encoding block, each fourth signal contains a plurality of third bit blocks, and each third bit block contains e*u / f bits;

[0048] Step S2048, the f fourth signals are merged in units of w bits to obtain the second signal, where the second signal contains a plurality of fourth bit blocks, each fourth bit block contains e*u bits, for the f fourth signals, each fourth signal provides one third bit block, the f third bit blocks are combined to form one fourth bit block, and the first a bits of each fourth bit block are the alignment mark information.

[0049] In the embodiment, each fourth bit block in the second signal can contain e / f forward error correction code block groups, each of which contains f*u bits corresponding to f forward error correction code blocks, and the f forward error correction code blocks are staggered together in units of w bits, that is, in the f*u bits of a forward error correction code block group, in consecutive w bits, a bit sub-block, contains f*u / w bit sub-blocks, and all bit sub-blocks are sequentially numbered, where the first bit sub-block is named bit sub-block 1, the second bit sub-block is named bit sub-block 2, and so on, and the last bit sub-block is named bit sub-block f*u / w, where the first bit sub-block, the f+1th bit sub-block, the 2*f+1th bit sub-block, and up to the f*u / w-f+1th bit sub-block, a total of u / w bit sub-blocks, are the first forward error correction code block; the second bit sub-block, the f+2th bit sub-block, the 2*f+2th bit sub-block, and up to the f*u / w-f+2th bit sub-block, a total of u / w bit sub-blocks, are the second forward error correction code block, and so on, until the fth bit sub-block, the 2fth bit sub-block, the 3*fth bit sub-block, and up to the f*u / wth bit sub-block, a total of u / w bit sub-blocks, are the fth forward error correction code block. In the above processing, f corresponds to the number of interleaved forward error correction code blocks, and w is the interleaving unit. The larger the value of f is, the stronger the ability to process continuous burst bit errors is, because continuous burst bit errors mean that there are j consecutive bit errors. If the bit stream is interleaved by f forward error correction code blocks and the interleaving unit is w bits, then each forward error correction code block has at most j / f error codes or at most j / (f*w) symbol errors, thereby reducing the number of error codes on a single forward error correction code block, so that such errors can be corrected. Through the embodiment of the present disclosure, continuous f check information can be added after continuous f payload blocks, so that the second signal can withstand longer burst errors.

[0050] In some embodiments, step S206 can include the following steps:

[0051] Step S2062, in the second signal, the position of the fourth bit block is located according to the alignment mark information;

[0052] Step S2064, in the second signal, the e*u bits in each fourth bit block are evenly distributed to the c channels in units of g bits, to obtain the c channel signals, wherein g is a positive integer, e*u is an integer multiple of c*g, each of the channel signals contains a plurality of fifth bit blocks, each of the fifth bit blocks contains e*u / c bits in the e*u bits, and the first b / c bits in each of the fifth bit blocks are bits in the first information.

[0053] In the embodiment, there is one alignment mark information in every e*u bits in the second signal. Based on the alignment mark information, especially the first information in the alignment mark information, the e*u bits can be located. The value of the first information is a preset bit value. The position of the first information, and thus the position of the e*u bits, can be determined by comparing the bit value of the second signal with the preset bit value.

[0054] In the embodiment, g is a basic unit of data distribution. The second signal is first split into g bits, and then distributed to the multiple channels one by one, so as to convert the second signal into the C channel signals.

[0055] It can be understood that the second signal can be converted into multiple channel signals according to different values of c. For example, c can be selected as 4, 5, 9, 17, etc. For each of the above values, g can also have different values. Since e*u is an integer multiple of c*g, for different values of c and g, e can also have different values.

[0056] In the embodiment, the method further includes at least one of the following:

[0057] The OTN signal is scrambled;

[0058] The first signal is scrambled, wherein the alignment mark information in the first signal is not scrambled;

[0059] The second signal is scrambled, wherein the alignment mark information in the second signal is not scrambled;

[0060] The channel signal is scrambled, wherein the first information in the channel signal is not scrambled.

[0061] In the embodiment, scrambling is performed to avoid long continuous 0 bits or continuous 1 bits in the signal. Since the channel signal can be converted into a bit stream and then transmitted on a physical medium, the binary bit stream transmitted on the physical medium generally does not allow long continuous 0 or continuous 1 bits. The scrambling in the embodiment is performed to avoid long continuous 0 or continuous 1 bits in the binary bit stream on the physical medium. In addition, the detection of the alignment mark information is based on a specific bit value. The scrambling can reduce the probability of the specific bit value appearing at the position of the non-alignment mark information, and help to accurately identify the position of the alignment mark information.

[0062] In the embodiment, the disclosure does not limit the specific implementation method of scrambling, for example, a self-synchronous scrambling mode can be used, or a specified initial scrambling position mode can be used, wherein in the specified initial scrambling position mode, the first bit after the alignment mark information is taken as the initial scrambling position, a fixed scrambling initial value is set, and the self-synchronous scrambling polynomial only needs to specify the scrambling range, without defining the initial scrambling position and the scrambling initial value; for example, the optical transport network signal can be scrambled in step S202, or the first signal can be scrambled in step S204, and generally only one scrambling process is needed.

[0063] In some embodiments, step S208 can include: transmitting the c channel signals on the c channels, wherein each channel transmits one channel signal, and the channel signal is transmitted through a physical medium after being converted into a bit stream on the channel, or the c channel signals are transmitted through the physical medium after being subjected to a preset first signal processing.

[0064] In an exemplary embodiment, the physical medium can include, but is not limited to, an optical fiber, a copper cable, or a printed circuit board (PCB) signal line, etc.

[0065] In an exemplary embodiment, the implementation method of the preset first signal processing is as follows: h channel signals are combined into one second channel signal in units of 1 bit, wherein c is an integer multiple of h, and the h consecutive bits in the second channel signal belong to the h channel signals respectively, so that the c channel signals are recombined into c / h second channel signals, and the c / h second channel signals are transmitted on c / h physical channels.

[0066] Through the embodiments of the disclosure, the signal transmission rate on a single channel can be reduced through multi-channel transmission, and the success rate of sending the optical transport network signal and the fault tolerance can be improved through forward error correction coding, and there is no any limitation condition for the frame length of the optical transport network signal and the alignment mark overhead, so the application range is more extensive, and the adaptability to different forward error correction coding algorithms and different numbers of channels is stronger. The distribution mode of the optical transport network signal in the embodiments of the disclosure is more flexible, and the implementation mode is simpler, thereby solving the problems of complex hardware implementation and poor adaptability of multi-channel transmission of the optical transport network signal in the related art.

[0067] FIG. 3 is a flowchart of an optical transport network signal processing method according to an embodiment of the disclosure, applied to a receiving side, as shown in FIG. 3, the flowchart includes the following steps:

[0068] Step S302, receiving a plurality of channel signals on a plurality of channels;

[0069] Step S304, merging the plurality of channel signals into a second signal;

[0070] Step S306, periodically deleting forward error correction information in the second signal to obtain a first signal;

[0071] Step S308, periodically deleting alignment flag information in the first signal to obtain an optical transport network signal.

[0072] In the embodiment, in order to ensure that the optical transport network signal can be correctly received and parsed, the processing parameters of the receiving side are the same as or cooperate with the processing parameters of the sending side.

[0073] In the embodiment of the present disclosure, through the above steps S302 to S308, the recovery of the optical transport network signal can be realized at the receiving side of the optical transport network signal. The recovered optical transport network signal can have no alignment flag overhead and no frame length limitation. The multi-channel transmission of the optical transport network signal can be realized when the optical transport network signal does not meet the multi-channel transmission limitation condition. The embodiment of the present disclosure can be widely applied to different forward error correction encoding algorithms, thereby solving the problems of complex hardware implementation and poor adaptability of multi-channel transmission of the optical transport network signal in the related art.

[0074] In some embodiments, step S302 can include: receiving the c channel signals on the c channels, wherein each channel receives one channel signal, the channel signal is converted from the bit stream received by the channel through the physical medium, or the channel signal is obtained after a preset second signal processing on the signal received through the physical medium.

[0075] In an exemplary embodiment, the physical medium can include but is not limited to an optical fiber, a copper cable, or a PCB signal line, etc. The physical medium of the receiving side is the same as that of the sending side.

[0076] In an exemplary embodiment, the implementation method of the preset second signal processing is as follows: receiving the c / h second channel signals on the c / h physical channels, wherein the c is an integer multiple of the h, one second channel signal is received on each physical channel, for each second channel signal, one second channel signal is split into h channel signals in units of 1 bit, i.e. the continuous h bits of the second channel signal are divided into one channel signal for each bit, to obtain h channel signals. Through the above processing, the c / h second channel signals are converted into c channel signals.

[0077] In the embodiment, the alignment flag information and the setting of the forward error correction encoding algorithm of the receiving side are the same as those of the sending side.

[0078] In some embodiments, the step S304 can include the following steps:

[0079] In step S3042, in each of the channel signals, periodically find a first sub-information, wherein each adjacent two first sub-information are separated by e*u / c bits, and each first sub-information contains b / c bits in the first information.

[0080] In step S3044, for each of the channel signals, when the multiple first sub-information are found and the repetition period of the multiple first sub-information is e*u / c bits, determine that a bit block starting with the first sub-information and having a length of e*u / c bits is the fifth bit block, and align the c channel signals according to the position of the fifth bit block in the channel signal.

[0081] In step S3046, the aligned c channel signals are merged into the second signal in the unit of g bits, wherein the second signal contains multiple fourth bit blocks, each of which contains e*u bits, and for the c channel signals, each of the channel signals provides a fifth bit block, the c fifth bit blocks form a fourth bit block, and the first a bits of each fourth bit block are the alignment flag information.

[0082] In the embodiment, g is the basic unit of data merging and the basic unit of multi-channel signal recombination. The second signal is distributed in units of g bits at the sending side and should also be merged in units of g bits at the receiving side. After the alignment of the channel signals, each channel signal is divided into bit blocks in units of g bits. Each bit block is assigned a bit block number. The first g bit blocks in the fifth bit block correspond to bit block numbers 1. The bit block numbers of each bit block are sequentially 2, 3, 4, and so on from near to far to the bit block number 1. By analogy, the bit block number of the last g bits in the fifth bit block is e*u / (c*g). For c channel signals, the bit blocks with the same number are sequentially arranged together. The arrangement order of the c bit blocks with the same number is determined by the channel number, that is, the bit block with the channel number 1 is arranged at the front, followed by the bit blocks with the channel numbers 2, 3, and 4, and so on. The last bit block is the bit block with the channel number c. In this way, c*g bits are obtained. Since there are e*u / (c*g) bits in a fifth bit block of one channel, c fifth bit blocks of c channel signals are arranged together to obtain e*u bits, which correspond to a fourth bit block of the second signal. The value of g at the receiving side is the same as that at the sending side.

[0083] In some embodiments, step S306 includes the following steps:

[0084] Step S3062, in the second signal, locating the fourth bit block according to the alignment mark information, wherein the first a bits of each fourth bit block are the alignment mark information;

[0085] Step S3064, dividing the second signal into the f fourth signals in units of the w bits, wherein each fourth bit block in the second signal is divided into the f third bit blocks, the f third bit blocks belong to the f fourth signals respectively, each third bit block contains e*u / f bits, and each fourth signal includes a plurality of third bit blocks;

[0086] Step S3066, in each third bit block of the f fourth signals, taking each u bit as a forward error correction encoding block, performing check and error correction processing according to the preset forward error correction encoding algorithm, and after the check and error correction processing is completed, deleting the check information of the forward error correction encoding block of the v bits in each forward error correction encoding block to obtain the f third signals, wherein each third signal contains a plurality of second bit blocks, and each second bit block contains e*d / f bits;

[0087] Step S3068, merging the f third signals in the w-bit unit to obtain the first signal, wherein the first signal contains a plurality of first bit blocks, each of the first bit blocks contains e*d bits, wherein for the f third signals, each of the third signals provides one second bit block, the f second bit blocks form one first bit block, and the first a bits of each of the first bit blocks are the alignment flag information.

[0088] In the embodiment, w is the symbol length of a forward error correction coding block, which is a basic unit of forward error correction coding / decoding. Step S3064 corresponds to deinterleaving of the forward error correction coding block, step S3066 corresponds to decoding processing of the forward error correction coding block, and step S3068 corresponds to processing after deinterleaving and decoding, and finally the second signal is obtained. Since the forward error correction is performed on the f sub-signals, the sub-signals need to be merged into the original signal through step S3068.

[0089] In some embodiments, step S308 includes: deleting the first a bits in each of the first bit blocks as the alignment flag information in the first signal in the e*d-bit period to obtain the optical transport network signal.

[0090] In some embodiments, the method further includes: extracting second information from the alignment flag information, wherein the alignment flag information further contains the second information, and the second information has a bit number of a-b; and monitoring or managing the first signal according to the second information.

[0091] In an exemplary embodiment, the second information can represent a physical state of the first signal, wherein the physical state can include normal, local failure, remote time slot, etc.; the second information can also be used to record a sending address and a receiving address of the first signal; or the second information can also be used to transmit monitoring information, etc.

[0092] In some embodiments, the method further includes at least one of:

[0093] de-scrambling the optical transport network signal;

[0094] de-scrambling the first signal, wherein the alignment flag information in the first signal is not de-scrambled;

[0095] de-scrambling the second signal, wherein the alignment flag information in the second signal is not de-scrambled;

[0096] de-scrambling the channel signal, wherein the first information in the channel signal is not de-scrambled.

[0097] The specific implementation method of descrambling is not limited in the present disclosure, and can be agreed by the receiving side and the sending side of the optical transport network signal, or can be preconfigured. The specific implementation method of descrambling by the receiving side must be consistent with the specific implementation method of scrambling by the sending side.

[0098] Through the embodiments of the present disclosure, the requirements of high transmission rate of the optical transport network signal can be met through multi-channel transmission, and the success rate and fault tolerance of the optical transport network signal transmission can be improved through forward error correction coding, and there is no any limitation condition for the frame length and alignment overhead of the optical transport network signal, so the application range is more extensive, and the adaptability to different forward error correction coding algorithms and different numbers of channels is also stronger. The distribution and recombination of the optical transport network signal in the embodiments of the present disclosure are more flexible, and the implementation is simpler, thereby solving the problems of complex hardware implementation and poor adaptability of multi-channel transmission of the optical transport network signal in the related art.

[0099] The optical transport network signal processing method in the embodiments of the present disclosure will be described below in combination with specific optical transport network signals and forward error correction coding modes.

[0100] In an exemplary embodiment of the present disclosure, the type of the optical transport network signal is an OTUC1 signal, the number of channels c=4, the forward error correction coding algorithm adopts Reed-Solomon (RS) coding, and the forward error correction coding block format is selected as RS(544, 514). The interleaving number of the forward error correction coding block is 1, i.e., f=1. In RS(544, 514), the first number is the number of symbols of the forward error correction coding block, and the second number is the number of symbols corresponding to the payload of the forward error correction coding block. In the forward error correction coding block of RS(544, 514), all bits exist in the form of symbols, one symbol corresponds to 10 consecutive bits of data, i.e., the symbol length w is 10, the length of the forward error correction coding block u is 5440, the payload length d is 5140, and the check information length v is 300. The above numbers are all in bits.

[0101] In the present embodiment, in order to split the OTUC1 signal into 4-channel signals after adding forward error correction information (using the forward error correction coding block RS(544, 514)), the following steps can be taken to achieve this:

[0102] Step S1, in the OTUC1, an alignment overhead of a bit is inserted every e*d-a bits, to obtain a first signal containing a plurality of first bit blocks.

[0103] In the embodiment, each first bit block contains e*d bits, which is an integer multiple of the payload length d. Assuming the bit number a of the alignment flag overhead is 1285, e is 4096, through calculation, the value of e*d can be determined as 21053440, and the value of e*d-a is 21052115, that is, an alignment flag overhead of 1285 is inserted every 21052115 bits in the OTUC1 signal, to obtain a first signal containing a plurality of first bit blocks, each first bit block contains 21053440 bits, and the first 1285 bits in each first bit block are the alignment flag overhead.

[0104] In step S2, the first signal is taken as a forward error correction coding block, the first bit of the payload of the forward error correction coding block is taken as the first bit of a first bit block of the first signal, every continuous d bits are taken as the payload of the forward error correction coding block, and v bits of check information of the forward error correction coding block are added after the payload of each forward error correction coding block of the first signal, to obtain a second signal.

[0105] In the embodiment, the second signal contains a plurality of fourth bit blocks, each fourth bit block contains e*u bits, and the first a bits of each fourth bit block are the alignment flag overhead.

[0106] In the embodiment, after the position of the payload of the forward error correction coding block is determined, 300 bits of check information can be added after the payload of each forward error correction coding block, wherein the check information is generated according to the RS(544, 514) coding algorithm.

[0107] It is noted that in the step, since the interleaving length f is 1, it is equivalent to not needing interleaving, that is, the third signal in step S2044 is the same as the first signal, and the fourth signal in step S2048 is the same as the second signal, that is, the check information of the forward error correction coding block can be directly added to the first signal to obtain the second signal. If f is greater than 1, the first signal needs to be divided into f third signals first, then the check information of the forward error correction coding block is added to the f third signals to obtain f fourth signals, and then the f fourth signals are combined to obtain the second signal.

[0108] In step S3, the second signal is split into 4 channel signals in units of g bits according to the position of the forward error correction coding block.

[0109] In the embodiment, assuming that the distribution unit g is 10 bits, e*u bits in each fourth bit block are evenly distributed to c channels, c = 4, c channel signals are obtained, e*u is an integer multiple of c*g, wherein e*u bits in the fourth bit block are divided into e*u / g bit blocks, each bit block includes g bits, each bit block has a bit block number, and the bit block numbers are numbered according to the distance from the first bit of the fourth bit block, the nearest bit block number is 1, corresponding to the first g bits, and the bit block number is constantly increased by 1 with the increasing distance from the first bit of the fourth bit block, the bit block numbers 1, 5, 9, 13, i*4+1 (i is an integer greater than or equal to 0) are distributed to the channel signal of channel 1, the bit block numbers 2, 6, 10, 14, 4*i+2 are distributed to the channel signal of channel 2, the bit block numbers 3, 7, 11, 15, 4*i+3 are distributed to the channel signal of channel 3, and the bit block numbers 4, 8, 12, 16, 4*i+4 are distributed to the channel signal of channel 4, so that the second signal can be distributed to four channel signals. Each channel signal includes a plurality of fifth bit blocks, each fifth bit block includes e*u / c bits in e*u bits, and the first b / c bits in each fifth bit block are bits in the first information, where b = 1280. The e*u bits in each fourth bit block are evenly distributed to the c channels to obtain the c channel signals, wherein g is a positive integer, e*u is an integer multiple of c*g, each channel signal includes a plurality of fifth bit blocks, each fifth bit block includes e*u / c bits in e*u bits, and the first b / c bits in each fifth bit block are bits in the first information.

[0110] In the embodiment, the alignment flag overhead (the number of bits a = 1285) can be divided into two parts, the first information (the number of bits b = 1280) which can be evenly divided by the number of channels and the second information for other purposes, wherein the number of bits of the second information is 5 bits, and in the embodiment, the 5 bits of the second information are fixed padding information without actual purpose. The first information is evenly distributed to a plurality of channels, and the number of bits distributed in each channel is b / c = 320, which can be referred to as channel alignment overhead, and is used to realize the alignment of each channel signal.

[0111] FIG. 4 is a schematic diagram of the alignment flag overhead allocated to four channel signals according to an embodiment of the present disclosure. As shown in FIG. 4, the distribution of the alignment flag overhead of 1285 bits on four channel signals.

[0112] The small square with a number in Figure 4 represents 10 bits, and the number in the square represents the sending order of the 10-bit block in one channel. The 10-bit block with the number 0 represents the 10-bit block sent first in the channel signal, the 10-bit block with the number 1 represents the second 10-bit block sent in the channel signal, and so on, and the 10-bit block with the number 32 represents the 33rd 10-bit block sent in the channel signal. From square 0 to square 33 represents 340 bits, i.e., 340 bits of data on each channel. The first 10-bit of the first channel signal corresponds to the first 10-bit of a forward error correction coding block, and is also the first 10-bit in the alignment flag overhead. Therefore, the alignment flag overhead can be used to identify the starting position of the forward error correction coding block.

[0113] After the above processing, there are 325 bits of alignment flag overhead on the first channel signal (including 320 bits of channel alignment overhead and 5 bits of second information), and there are also 320 bits of channel alignment overhead on the second to fourth channel signals, respectively.

[0114] In the second signal, the distribution process of other parts (optical transport network signal) except the alignment flag overhead is similar to that of the alignment flag overhead, and is sequentially distributed to each channel signal in units of 10 bits. The optical transport network signal in Figure 4 is only a simple identification, and the length of the optical transport network signal and the length of the channel signal are not limited in the present disclosure.

[0115] Figure 5 is a schematic diagram of the alignment flag overhead value allocated to four channels in an embodiment of the present disclosure. As shown in Figure 5, the alignment flag overhead includes first information and second information. The first information is the channel alignment overhead, which can be evenly allocated to four channels. The second information can be used for monitoring or management of the second signal, or the second information can also be fixed padding information.

[0116] In the present embodiment, the first 320 bits of the alignment flag overhead on each channel signal can be divided into five 64-bit blocks, and the last 32 bits in each 64-bit block are the inverse of the first 32 bits. In the first 32 bits of each 64-bit block, 24 bits are CM or UM, and 8 bits are BIP check values.

[0117] In the embodiment, CM represents that the values of 24 bits at the same position in the four channel signals are the same. CM can be represented by CM_y, and different values can be represented by different y values, such as CM_1 or CM_2, representing two different values. In FIG. 5, the first 24 bits in the first and fifth 64-bit blocks of the four channel signals are CM values, that is, the first 24 bits in the first 64-bit block of the four channel signals are CM_1, CM_1 represents the first 64-bit block with the same value, and CM_2 represents the second 64-bit block with the same value. Further, CM can be used to locate the position of the alignment flag overhead on all channels. Since the values of CM on each channel are the same, the same hardware processing module can be used to locate the alignment flag position on each channel. The encoding, identification, and other processes in the embodiment of the present disclosure can be directly processed by the hardware in the prior art, and the compatibility is stronger.

[0118] In the embodiment, UM represents that the values of 24 bits at the same position in the four channel signals are different. The specific value of UM can be used to identify different channel numbers. UM can be represented by UMx_y, where x represents the channel number and takes a value of 1 to 4, and y represents the appearance order of the 64-bit block of UM on one channel and takes a value of 1 to 3. For example, UM2_3 represents the third UM block on the second channel signal, corresponding to the fourth 64-bit block in the five 64-bit blocks. UM is used for channel number identification.

[0119] In the embodiment, the specific values of CM_y and UMx_y can refer to the communication standard protocol. For example, the processing of the channel alignment overhead and the processing method of the 256B / 257B encoding block of the 100G Ethernet can be completely consistent, and the same hardware as the 100G Ethernet signal processing can be shared.

[0120] In the embodiment, the BIP check value is used to detect whether there is an error code in the channel signal. When the channel signal is sent, the BIP check value is obtained by performing XOR on the bits at a specific position in the channel signal. When the channel signal is received, the bits at the specific position in the channel signal are compared with the BIP check value to determine whether there is an error code in the channel signal.

[0121] The above steps S1 to S3 are applied to the signal sending side. Correspondingly, on the signal receiving side, the four channels can identify the specific position of the alignment flag overhead according to the value of the alignment flag overhead, and identify the channel number of each channel, so as to realize channel alignment and combine the four channel signals into a second signal. For the specific implementation process, reference can be made to steps S302 to S308 in the above embodiment, which will not be described here.

[0122] In the embodiment, the content of the channel alignment overhead allocated in each channel signal is a fixed bit value. Since the fixed bit value occurs periodically, when the position of the channel alignment overhead is unknown, the position of the channel alignment overhead can be located according to the fixed bit value of the channel alignment overhead and the number of bits between the channel alignment overhead.

[0123] In any of the processes of the above steps S1 to S3, if it is necessary to ensure that there is no long continuous 0 or continuous 1 bit on each channel signal, the signal scrambling can also be performed by one or more of the following optional processing modes:

[0124] Processing mode 1: scrambling processing is performed on the OTUC1 signal. The scrambling method can refer to the scrambling method of the OTU4 signal in the related art.

[0125] Processing method 2: scrambling processing is performed on the first signal. The alignment overhead in the first signal is not scrambled. The scrambling method can refer to the scrambling method of the 256B / 257B encoding block of the 200G Ethernet signal (200GBASE-R) in the related art.

[0126] Processing method 3: scrambling processing is performed on the channel signal. The alignment overhead in the channel signal is not scrambled. The scrambling method can refer to the scrambling method of the 256B / 257B encoding block of the 200G Ethernet signal (200GBASE-R) in the related art, or the scrambling method of the OTU4 signal.

[0127] In another example embodiment of the disclosure, the type of the optical transport network signal is an OTUC2 signal, the number of channels c = 8, the forward error correction encoding algorithm uses RS encoding, and the encoding block format is selected as RS(544, 514). In the encoding mode, f = 2 is selected, that is, the number of interleaving of the forward error correction encoding block is 2, or two encoding check blocks are added after every two encoding payload blocks. The first number in RS(544, 514) is the number of symbols of the forward error correction encoding block, and the second number is the number of symbols corresponding to the payload of the forward error correction encoding block. In the forward error correction encoding block of RS(544, 514), all bits exist in the form of symbols, one symbol corresponds to 10 consecutive bits of data, the symbol length w is 10, the length of the forward error correction encoding block u is 5440, the payload length d is 5140, and the check information length v is 300. The above numbers are all in bits.

[0128] In the embodiment, in order to split the OTUC2 signal into 8 channel signals after adding forward error correction information (using the forward error correction encoding block RS(544, 514)), the following steps can be taken to achieve this:

[0129] Step S11, in the OTUC2, an alignment marker overhead of a bits is inserted every e*d-a bits, to obtain a first signal containing a plurality of first bit blocks.

[0130] In the embodiment, each first bit block contains e*d bits, which is an integer multiple of the payload length d. Assuming that the number of bits of the alignment marker overhead a=1028, e is 4096, by calculation, it can be determined that the value of e*d is 21053440, and the value of e*d-a is 21052412, that is, an alignment marker overhead of 1028 is inserted every 21052412 bits in the OTUC2 signal, to obtain a first signal containing a plurality of first bit blocks, each first bit block contains 21053440 bits, and the first 1028 bits in each first bit block is the alignment marker overhead.

[0131] Step S12, the first signal is evenly divided into 2 third signals in units of 10 bits, that is, w=10, f=2, specifically including: each first bit block is evenly divided into 2 second bit blocks, and the 2 second bit blocks belong to the 2 third signals respectively, each second bit block contains 10526720 (e*d / f) bits, each third signal includes a plurality of second bit blocks, and the specific implementation method is that the 21053440 bits of the first bit block are divided into 2105344 bit blocks, one bit block includes 10 bits, and each bit block is sequentially assigned a number, wherein the first 10 bits of the first bit block are the bit block numbered 1, the 11th to 20th bits of the first bit block are the bit block numbered 2, the 21st to 30th bits of the first bit block are the bit block numbered 3, and so on, until the 21053431st to 21053440th bits of the first bit block are the bit block numbered 2105344, the bit blocks numbered odd are sequentially assigned to the third signal numbered 1, and the bit blocks numbered even are sequentially assigned to the third signal numbered 2, each third signal includes a second bit block with a length of 10526720 bits, and the first 510 bits of the second bit block are part of the first 1020 bits in the alignment marker overhead, that is, the start position of the second bit block is aligned with the start position of the first bit block.

[0132] Step S13, in the 2 third signals, for each second bit block, the second bit block is divided into 2048 bit blocks in bit order from the first bit of the second bit block, each bit block has a length of 5140 bits, each 5140 bits is a payload of a forward error correction coding block, 300 bits of check information is added behind the payload of each forward error correction coding block to obtain a fourth signal, wherein the check information is generated according to the RS(544, 514) coding algorithm. In the 2 fourth signals, each fourth signal contains a plurality of third bit blocks, each third bit block has a length of 11141120, the third bit block is aligned with the beginning of the second bit block, that is, the first 510 bits of the third bit block are part of the first 1020 bits in the alignment marker overhead.

[0133] Step S14, the 2 fourth signals are merged in units of 10 bits to obtain a second signal, specifically including: each third bit block contains 11141120 (e*u / f) bits, each third signal includes a plurality of second bit blocks, the specific implementation method is that the 11141120 bits of the third bit block are divided into 1114112 bit blocks, one bit block includes 10 bits, and each bit block is sequentially assigned a number, wherein the first 10 bits of the third bit block are the bit block numbered 1, the 11th to 20th bits of the third bit block are the bit block numbered 2, the 21st to 30th bits of the third bit block are the bit block numbered 3, and so on, until the 11141111th to 11141120th bits of the third bit block are the bit block numbered 1114112, the 2 third signals are merged into one second signal, wherein the second signal includes a plurality of fourth bit blocks, each fourth bit block has a length of 22282240 bits, the 22282240 bits of the fourth bit block are divided into 2228224 bit blocks, one bit block includes 10 bits, and each bit block is sequentially assigned a number, wherein the first 10 bits of the fourth bit block are the bit block numbered 1, the 11th to 20th bits of the fourth bit block are the bit block numbered 2, the 21st to 30th bits of the fourth bit block are the bit block numbered 3, and so on, until the 22282231th to 22282240th bits of the fourth bit block are the bit block numbered 2228224, the 1114112 bit blocks of the third bit block of the fourth signal numbered 1 are assigned to all bit blocks numbered odd in the fourth bit block, and the 1114112 bit blocks of the third bit block of the fourth signal numbered 2 are assigned to all bit blocks numbered even in the fourth bit block, thereby realizing merging the 2 fourth signals into one second signal, in the fourth bit block of the second signal, the first 1028 bits are the alignment marker overhead.

[0134] Step S15, the second signal is averaged into 8 channel signals in units of 10 bits, i.e. g = 10, specifically including: each fourth bit block is evenly divided into 8 fifth bit blocks, and the 8 fifth bit blocks belong to the 8 channel signals respectively, each fourth bit block contains 22282240 (e*u) bits, the 22282240 bits of the fourth bit block are divided into 2228224 bit blocks, 1 bit block includes 10 bits, and each bit block is sequentially assigned a number, wherein the 1st to 10th bits of the fourth bit block are taken as the bit block numbered 1, the 11th to 20th bits of the fourth bit block are taken as the bit block numbered 2, the 21st to 30th bits of the fourth bit block are taken as the bit block numbered 3, and the like, until the 22282231st to 22282240th bits of the fourth bit block are taken as the bit block numbered 2228224, the bit blocks numbered 1, 9, 17, 25, i*8+1 (i takes values 0 from 278527) are sequentially assigned to the channel signal numbered 1, the bit blocks numbered 2, 10, 18, 26, i*8+2 (i takes values 0 from 278527) are sequentially assigned to the channel signal numbered 2, the bit blocks numbered 3, 11, 19, 27, i*8+3 (i takes values 0 from 278527) are sequentially assigned to the channel signal numbered 3, the bit blocks numbered 4, 12, 20, 28, i*8+4 (i takes values 0 from 278527) are sequentially assigned to the channel signal numbered 4, and the like, until the bit blocks numbered 8, 16, 24, 32, i*8+8 (i takes values 0 from 278527) are sequentially assigned to the channel signal numbered 8, after the above processing, each channel signal contains a plurality of fifth bit blocks, each fifth bit block contains 2785280 bits, the starting position of each fifth bit block is aligned with the fourth bit block, and the first 120 bits of each fifth bit block are part of the first 960 bits of the fourth bit block.

[0135] In the embodiment, the alignment mark overhead (bit number a = 1028) can be divided into two parts, the first information (bit number b = 960) which can be evenly divided by the number of channels and the second information (bit number a-b = 68) which is used for monitoring the first signal or other purposes. Among them, the first information is evenly distributed to 8 channels, and the number of bits in each channel is b / c = 120. These 120 bits can be called channel alignment overhead, which is used to realize the alignment of each channel signal. For the second information, 67 bits can be defined as fixed padding bits, and 1 bit represents whether the current optical transport network signal is invalid.

[0136] FIG. 6 is a schematic diagram of the alignment mark overhead allocated to 8 channel signals according to an embodiment of the present disclosure. As shown in FIG. 6, the distribution of the alignment mark overhead of 1028 bits on the 8 channel signals.

[0137] In FIG. 6, one small square with a number represents 10 bits, the number in the square represents the sending order of the 10-bit block in one channel, the 10-bit block with the number 0 represents the 10-bit block sent first in the channel signal, the 10-bit block with the number 1 represents the second 10-bit block sent in the channel signal, and so on, the 10-bit block with the number 12 represents the 13th 10-bit block sent in the channel signal. From square 0 to square 13 represents 140 bits, that is, 140 bits of data on each channel, wherein the first 10-bit of the first channel signal corresponds to the first 10-bit of a first FEC block group, and thus the alignment flag overhead can be used to identify the starting position of the FEC block group.

[0138] After the above processing, there are 130 bits of alignment flag overhead (including 120 bits of first information and 10 bits of second information) on the first channel signal to the sixth channel signal, 128 bits of channel alignment overhead (including 120 bits of first information and 8 bits of second information) on the seventh channel signal, and 120 bits of channel alignment overhead (only including 120 bits of first information) on the eighth channel signal.

[0139] In the second signal, the distribution process of other parts (OTN signal) except the alignment flag overhead is similar to that of the alignment flag overhead, and is sequentially distributed to each channel signal in units of 10 bits. The OTN signal in FIG. 6 is only a simple identification, and the length of the OTN signal and the length of the channel signal are not limited in the disclosure.

[0140] FIG. 7 is a schematic diagram of the value of the first information in the alignment flag overhead allocated to 8 channels in an embodiment of the disclosure. As shown in FIG. 7, the alignment flag overhead includes first information and second information, and the first information can be evenly allocated to 8 channels. The second information can be used for monitoring or management of the second signal, or the second information can also be fixed padding information, which is not limited in the disclosure.

[0141] In this embodiment, the first 120 bits of the alignment flag overhead on each channel signal can be divided into 15 bytes, one byte represents 8 bits, and the 15 bytes include 6 bytes of CM, 6 bytes of UM, and 3 bytes of UP. Among them, CM represents that the values of the bytes at the same position in the 8 channel signals are the same, UM and UP represent that the values of the bytes at the same position in the 8 channels are different, the value of UM can be used to identify different channel numbers, UP is used for fixed padding and has no identification function, and the value of UP can be ignored by the receiving side.

[0142] The first row in FIG. 7 is only an example of the order of the above three bytes in 120 bits, wherein the first byte in the 120 bits is CM0, and the 15th byte is UM5, wherein CM is represented by CM0 to CM5, CM represents that the values of the bytes at the same position in the 8 channel signals are the same, the first to third bytes and the fifth to seventh bytes of the 8 channel signals are CM, that is, the values of the above bytes in the 8 channel signals are the same, and the value of UM can be used to identify different channel numbers, and UM is represented by UM0 to UM5, and the values of UM at the same byte position on each channel are different.

[0143] In the embodiment, CM can be used to locate the position of the alignment flag overhead on all channels, and since the values of CM on each channel are the same, the same hardware processing module can be used to locate the alignment flag position on each channel. UM can be used for channel number identification.

[0144] The above steps S11 to S15 are applied to the signal sending side, and correspondingly, on the signal receiving side, the specific positions of the alignment flag overheads of the 8 channels are identified, and after the channel numbers of the 8 channels are identified, the channel alignment can be realized, so that the 8 channel signals are combined into the second signal, then the forward error correction information of the second signal is processed, the second signal is decoded according to RS(544, 514), the second signal is checked and corrected, and the forward error correction information is removed to obtain the first signal, and the first signal is removed from the alignment flag overhead to obtain the optical transmission signal. The specific implementation process can refer to steps S302 to S308 in the above embodiment, and will not be described here.

[0145] In the embodiment, the content of the channel alignment overhead allocated in each channel signal is a fixed bit value, and since the fixed bit value appears periodically, when the position of the channel alignment overhead is unknown, the position of the channel alignment overhead can be located according to the fixed bit value of the channel alignment overhead and the number of bits between the channel alignment overhead.

[0146] In the embodiment of the present disclosure, the values of the first 120 bits of the channel alignment overhead on the 8 channel signals are determined according to the communication standard protocol, and the values remain consistent in order to make the processing of the channel alignment overhead completely consistent with the processing method of the 256B / 257B encoding block of the 200G Ethernet, so that the same hardware can be shared with the 200G Ethernet signal processing.

[0147] In the embodiment, the content of the channel alignment overhead allocated in each channel signal is a fixed bit value. Since the fixed bit value occurs periodically, when the position of the channel alignment overhead is unknown, the position of the channel alignment overhead can be located according to the fixed bit value of the channel alignment overhead and the number of bits between the channel alignment overhead. The channel alignment overhead also includes a specific bit value for indicating a channel number (such as UM), so that the channel signal 1 to the channel signal 8 can be identified.

[0148] In any of the processes of the steps S11 to S15, if it is necessary to ensure that there is no long continuous 0 or continuous 1 bit in each channel signal, one or more of the following optional processing methods can be used for signal scrambling:

[0149] Processing method 1, scrambling the OTUC2 signal, and the scrambling method can refer to the scrambling method of the OTU4 signal in the related art.

[0150] Processing method 2, scrambling the first signal, wherein the alignment overhead in the first signal is not scrambled, and the scrambling method can refer to the scrambling method of the 256B / 257B encoding block of the 200G Ethernet signal (200GBASE-R) in the related art.

[0151] Processing method 3, scrambling the channel signal, wherein the alignment overhead in the channel signal is not scrambled, and the scrambling method can refer to the scrambling method of the 256B / 257B encoding block of the 200G Ethernet signal (200GBASE-R) in the related art, or the scrambling method of the OTU4 signal.

[0152] The optical transport network signal processing method in the embodiment of the present disclosure makes one optical transport network signal be able to be split into multiple channel signals after adding forward error correction information. The frame length of the optical transport network signal does not need to consider the length of the payload bits in the forward error correction encoding block, and the optical transport network signal also does not need to define the alignment overhead and ensure that the alignment overhead is split into multiple channel signals. In some cases, the frame length of the optical transport network signal must be an integer multiple of the length of the payload bits in the forward error correction encoding block, and the optical transport network signal also needs to define the alignment overhead and ensure that the alignment overhead is split into multiple channel signals. If the optical transport network signal does not meet the above two requirements, an intermediate signal meeting the above two requirements must be defined first, then the optical transport network signal is loaded into the intermediate signal, and then the intermediate signal is split into multiple channel signals after adding forward error correction information. Compared with the existing method, the method in the embodiment of the present disclosure has simpler hardware implementation.

[0153] In the embodiments of the present disclosure, the process of adding the alignment flag overhead in the OTN signal and the scrambling process of the OTN signal can also be consistent with the processing method of the 256B / 257B encoding block signal of the x*100 Gbps Ethernet, so that the hardware implementation of the x*100 Gbps Ethernet can be used more, and the hardware implementation cost of the OTN signal processing method is further reduced. At present, the value of x is 1, 2, 4, and with the development and supplement of the Ethernet standard, the value of x may support 8, 16, 32 and the like in the future, so that the processing of the higher rate OTN signal can continue to be consistent with the processing of the Ethernet signal of the same rate as much as possible.

[0154] The embodiments of the present disclosure further provide a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is run by a processor, the steps in any of the method embodiments described above are performed.

[0155] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0156] The embodiments of the present disclosure further provide an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the method embodiments described above.

[0157] In an example embodiment, the electronic device described above can further include a transmission device and an input / output device. The transmission device is connected to the processor, and the input / output device is connected to the processor.

[0158] The specific examples in the embodiments can refer to the examples described in the above embodiments and example implementations, and the embodiments will not be described here again.

[0159] It is apparent that those skilled in the art should understand that the modules or steps of the present disclosure described above can be realized by general computing devices, which can be centralized on a single computing device or distributed on a network composed of multiple computing devices, and can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different orders, or they can be respectively manufactured into individual integrated circuit modules, or multiple modules or steps thereof can be manufactured into a single integrated circuit module. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0160] The preferred embodiments of the present disclosure are described above, but the present disclosure is not limited to the above. Those skilled in the art can make various modifications and changes to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for OTN signal processing, the method comprising: adding periodically alignment flag information in an OTN signal to obtain a first signal; adding periodically forward error correction information in the first signal to obtain a second signal; distributing the second signal to a plurality of lanes to obtain a plurality of lane signals; and transmitting the lane signals on each of the lanes.

2. The method of claim 1, wherein: a number of bits of the alignment flag information is a, wherein the a is an integer greater than 1; a first information of b bits is included in the alignment flag information, wherein the b is an integer greater than 1, the b is less than or equal to the a, the b is an integer multiple of a number c of lanes, the plurality of lanes includes the c lanes, and the c is a positive integer; the first information is evenly distributed to the plurality of lanes to enable the plurality of lanes to align the plurality of lane signals by identifying positions of the first information, wherein a value of the first information is a preset bit value.

3. The method of claim 2, wherein: a second information is further included in the alignment flag information, wherein a number of bits of the second information is a-b, and the second information is used for monitoring or managing the first signal; and 4. The method of claim 2, wherein, the method further comprises: determining, according to a preset forward error correction encoding algorithm, that a payload length of a forward error correction encoding block is d bits, a check information length of the forward error correction encoding block is v bits, a length of the forward error correction encoding block is u bits, and a symbol length of the forward error correction encoding block is w bits, wherein the d, v, u, and w are positive integers, u = d + v, and the d, v, and u are integer multiples of the w.

5. The method of claim 4, wherein, the adding periodically alignment flag information in an OTN signal to obtain a first signal comprises: adding one of the alignment flag information every e*d-a bits in the OTN signal to obtain the first signal, wherein the first signal includes a plurality of first bit blocks, each of the first bit blocks includes e*d bits, and a first a bits in each of the first bit blocks is the alignment flag information, and the e is an integer greater than 1.

6. The method of claim 5, wherein, the adding periodically forward error correction information in the first signal to obtain a second signal comprises: locating positions of the plurality of first bit blocks according to the alignment flag information in the first signal; and evenly dividing the first signal into f third signals in units of the w bits, wherein the f is a positive integer, the e is an integer multiple of the f, each of the first bit blocks in the first signal is evenly divided into f second bit blocks, the f second bit blocks belong to the f third signals respectively, each of the second bit blocks includes e*d / f bits, and each of the third signals includes a plurality of the second bit blocks. In each of the second bit blocks of the f third signals, each of the d bits is taken as a payload of a forward error correction coding block, and check information of the forward error correction coding block is added after the payload of the forward error correction coding block to obtain the f fourth signals, wherein the forward error correction information comprises the check information of the forward error correction coding block, the check information of the forward error correction coding block is generated by performing the preset forward error correction coding algorithm on the payload of the forward error correction coding block, and each of the fourth signals comprises a plurality of third bit blocks, and each of the third bit blocks comprises e*u / f bits; The f fourth signals are merged in the w-bit unit to obtain the second signal, wherein the second signal comprises a plurality of fourth bit blocks, and each of the fourth bit blocks comprises e*u bits, and for the f fourth signals, each of the fourth signals provides one of the third bit blocks, and the f third bit blocks form one of the fourth bit blocks, and the first a bits of each of the fourth bit blocks are the alignment mark information.

7. The method of claim 6, wherein, The method further comprises the following at least one of the following: The method further comprises the following at least one of the following: The method further comprises the following at least one of the following:

8. The method of claim 7, wherein, The method further comprises the following at least one of the following: The method further comprises the following at least one of the following:

9. The method according to any one of claims 1 to 8, wherein, The method further comprises the following at least one of the following: The method further comprises the following at least one of the following: ​ ​ ​ 10. The method of claim 8, wherein, ​ ​ ​ ​ ​ 11. The method of claim 10, wherein, ​ Receiving c channel signals on c channels, wherein each channel receives one channel signal, and wherein the channel signal is converted from the bit stream received by the channel through the physical medium, or the channel signal is obtained after a preset second signal processing on the signal received through the physical medium.

12. The method of claim 11, wherein, The combining of the plurality of channel signals into the second signal comprises: Periodically searching for first sub-information in each channel signal, wherein each adjacent two first sub-information are separated by e*u / c bits, and each first sub-information contains b / c bits in the first information; In the case that the plurality of first sub-information is found and the repetition period of the plurality of first sub-information is e*u / c bits, determining that a bit block with the first sub-information as the beginning and the length of e*u / c bits is the fifth bit block, and aligning the c channel signals according to the position of the fifth bit block in the channel signal; Combining the aligned c channel signals into the second signal in the unit of g bits, wherein the second signal contains a plurality of fourth bit blocks, each fourth bit block contains e*u bits, wherein for the c channel signals, each channel signal provides a fifth bit block, the c fifth bit blocks form a fourth bit block, and the first a bits of each fourth bit block are the alignment mark information.

13. The method of claim 12, wherein, The periodically deleting of the forward error correction information in the second signal to obtain the first signal comprises: Locating the fourth bit block in the second signal according to the alignment mark information, wherein the first a bits of each fourth bit block are the alignment mark information; Dividing the second signal into f fourth signals in the unit of w bits, wherein each fourth bit block in the second signal is divided into f third bit blocks, the f third bit blocks belong to the f fourth signals respectively, each third bit block contains e*u / f bits, and each fourth signal includes a plurality of third bit blocks; In each third bit block of the f fourth signals, each u bits are a forward error correction encoding block, and the forward error correction encoding algorithm is used for check and error correction processing, and after the check and error correction processing is completed, the check information of the forward error correction encoding block of the v bits is deleted in each forward error correction encoding block to obtain f third signals, wherein each third signal contains a plurality of second bit blocks, and each second bit block contains e*d / f bits. combining the f third signals in the w-bit unit to obtain the first signal, wherein the first signal comprises a plurality of first bit blocks, each of the first bit blocks comprises e*d bits, wherein for the f third signals, each of the third signals provides one second bit block, the f second bit blocks form one first bit block, and the first a bits of each of the first bit blocks are the alignment flag information.

14. The method of claim 13, wherein, The periodically deleting the alignment flag information in the first signal to obtain the OTN signal comprises: deleting the first a bits of each of the first bit blocks in the first signal as the alignment flag information in the e*d-bit period to obtain the OTN signal.

15. The method of claim 3, wherein, The method further comprises: extracting the second information from the alignment flag information, wherein the alignment flag information further comprises second information, and the second information comprises a-bit number of bits; monitoring or managing the first signal according to the second information.

16. The method of claim 9, wherein, The method further comprises at least one of: performing descrambling on the OTN signal; performing descrambling on the first signal, wherein the alignment flag information in the first signal is not descrambled; performing descrambling on the second signal, wherein the alignment flag information in the second signal is not descrambled; performing descrambling on the channel signal, wherein the first information in the channel signal is not descrambled.

17. A computer-readable storage medium having stored therein a computer program, wherein, The computer program is executed by the processor to perform the method in any one of claims 1 to 16. 18.An electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to perform the method in any one of claims 1 to 16.

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