Underlayer film forming method, substrate processing apparatus, and substrate processing system

Abstract

A method for forming an underlayer film according to the present disclosure includes: a first step for supplying a first coating liquid to a surface of a substrate and forming a polysilane film that will serve as an underlayer film of a resist film; a second step for heating the substrate after the first step; and a third step for, after the second step, modifying the polysilane film by exposing the polysilane film to plasma of a gas that includes an inert gas.

Description

Underlayer film forming method, substrate processing apparatus, and substrate processing system

[0001] The present disclosure relates to an underlayer film forming method, a substrate processing apparatus, and a substrate processing system.

[0002] In the manufacturing process of semiconductor devices, a pattern is formed on a resist film on a semiconductor wafer (hereinafter referred to as a wafer) as a substrate, and then the pattern is transferred to a film underlying the resist film by etching. The underlying film may be used as an etching mask for etching a film formed further below the underlying film. Patent Document 1 discloses that this etching mask is formed from a polycarbosilane film.

[0003] JP 2008-210929 A

[0004] The present disclosure provides an underlayer film that is easy to pattern.

[0005] The method for forming an underlayer film disclosed herein includes a first step of supplying a first coating liquid to a surface of a substrate and forming a polysilane film that will serve as an underlayer film of a resist film; a second step of heating the substrate after the first step; and a third step of modifying the polysilane film by exposing it to plasma of a gas that includes an inert gas after the second step.

[0006] The present disclosure can provide an underlayer film that is easy to pattern.

[0007] 1 is a process diagram showing a series of processes for a wafer including an underlayer film formation process according to a first embodiment of the present disclosure. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 1 is a process diagram showing the series of processes. FIG. 10 is a graph showing the results of Evaluation Test 5 and Comparative Test 5.

[0008] [Wafer Processing Including Underlayer Film Formation Processing of First Embodiment] An overview of this processing will be described with reference to the longitudinal side views of FIGS. 1 to 3, which show a series of processing steps performed on a wafer W, including an underlayer film formation processing according to a first embodiment of the present disclosure. The wafer W is, for example, a silicon (Si) wafer, and 11 in FIG. 1A indicates a Si layer. A film 12 is formed on the Si layer 11. The film 12 is, for example, composed of one of a silicon oxide film, a titanium nitride film, and a silicon nitride film, or a stack of several of these films.

[0009] First, as shown in FIG. 1B , film 13 is formed so as to be laminated on film 12. This film 13 is a carbon-based organic film called a SOC (Spin on Carbon) film, and will be referred to as SOC film 13 hereinafter. The SOC film 13 is formed by applying a coating liquid (second coating liquid) for forming the organic film to the wafer W. After the SOC film 13 is formed, the wafer W is heated to remove the solvent remaining in the SOC film 13 and constituting the coating liquid for forming the organic film. This heating also causes, for example, a chemical reaction to proceed within the film. This chemical reaction is, for example, the formation of a polymer, which is a carbon compound, due to the action of a cross-linking agent contained in the film.

[0010] Next, a coating liquid (first coating liquid) for forming a polysilane film is applied to the wafer W. As a result, a polysilane film 14 is formed and laminated on the SOC film 13 (FIG. 1C). After the polysilane film 14 is formed, the wafer W is heated to remove the solvent that remains in the polysilane film 14 and that constitutes the coating liquid for forming the polysilane film.

[0011] The wafer W is then transferred into a processing chamber where a vacuum atmosphere is formed, and the polysilane film 14 is exposed to plasma of a gas containing an inert gas within the processing chamber. This modifies the polysilane film 14, causing it to become denser. The modified polysilane film 14 is shown in Figure 2A with hatching different from that of the polysilane film 14 in Figure 1C. The deposition of the polysilane film 14 on the surface of the wafer W, the heating of the wafer W, and the modification of the polysilane film 14 by plasma correspond to the first, second, and third steps, respectively.

[0012] After the plasma modification, a resist is applied to the wafer W. This forms a resist film 15, which is then laminated on the polysilane film 14 (FIG. 2B). The resist film 15 is then heated to remove the solvent contained in the resist film 15, exposed, and baked after exposure (PEB). A developer fluid is then supplied to the wafer W, dissolving a portion of the resist film 15 along the exposed pattern, forming a resist pattern as shown in FIG. 2C. This developer fluid may be a developer or a developing gas. The polysilane film 14 is then etched using the resist film 15 as a mask, and the pattern of the resist film 15 is transferred to the polysilane film 14 as shown in FIG. 3A. The SOC film 13 is then etched using the polysilane film 14 as a mask as shown in FIG. 3B. The film 12 is then etched using the SOC film 13 as a mask.

[0013] The reason why the polysilane film 14 is used as the underlying film of the resist film 15 and serves as an etching mask for the SOC film 13 will be described below. The CD (Critical Dimension), which is the line width of the pattern of the resist film 15, is being reduced. If the CD is reduced while the height of the resist pattern is increased, the resist film 15 forming the resist pattern is more likely to collapse (pattern collapse). Therefore, the height of the resist pattern (i.e., the thickness of the resist film 15) is also being reduced.

[0014] Then, when a pattern is transferred to the underlying film by etching using the resist film 15 having such a relatively small thickness as a mask, and the underlying film is formed as a mask for etching the SOC film 13, it is necessary to complete the transfer of the pattern to the underlying film before the resist film 15 disappears. Therefore, the thickness of this underlying film is also required to be relatively small. On the other hand, since the underlying film must serve as an etching mask when etching the SOC film 13, it is required to have relatively high etching resistance. As shown in the evaluation test described below, it has been confirmed that the polysilane film 14 has such high etching resistance, and therefore, by using it as the underlying film, it is possible to reduce the thickness while preventing the problem of the polysilane film 14 disappearing before the patterning of the SOC film 13 is completed.

[0015] Furthermore, using the polysilane film 14 as the underlayer film has the advantage of preventing problems that may occur when developing using a developer or developing gas (i.e., patterning the resist film 15). More specifically, when using a developer, since the polysilane film 14 is a densified film, the developer is prevented from seeping into a portion of the polysilane film 14 near the interface with the resist film 15, thereby preventing that portion from softening. Therefore, pattern collapse of the resist film 15 due to that softening is prevented.

[0016] Furthermore, when a developing gas is used, the polysilane film 14 is densified, so that chemical changes in the polysilane film 14 due to the developing gas are unlikely to occur. That is, the resistance of the polysilane film 14 to the developing gas is relatively high, so that the polysilane film 14 is prevented from being altered or removed by the developing gas. Therefore, the pattern collapse of the resist film 15 that would accompany this alteration or removal is prevented.

[0017] [Polysilane Structure] The polysilane used to form the polysilane film 14 is a polymeric compound containing a large number of Si-Si bonded silicon (Si) atoms, and any known polysilane can be used. Therefore, a compound having a linear or branched structure with a large number of Si-Si bonded Si atoms as the main chain may be used, or a compound having a large number of Si-Si bonded Si atoms forming a cyclic structure may be used. Furthermore, a compound in which the large number of Si atoms are bonded in a network pattern may also be used. Therefore, compounds having structural units shown in Chemical Formulas 1, 2, and 3 below may be used. The R representing the substituent in Chemical Formulas 1 to 3 is not limited to a specific group, but may be, for example, a hydrogen atom, an organic substituent, a silyl group, or a hydroxyl group. These R groups may be the same or different from one another. That is, R groups connected to the same Si atom may be the same or different, and R groups connected to different Si atoms may be the same or different. The organic substituent is, for example, a group containing carbon atoms, such as a hydrocarbon group.

[0018]

[0019] The molecular weight of the polysilane contained in the coating solution supplied to the wafer W is preferably relatively small. This is because if the molecular weight of the polysilane is too large, interference between and within molecules may prevent a sufficiently high density of polysilane molecules in the polysilane film after plasma processing, potentially preventing sufficient etching resistance. As an example, the polysilane film 14 can be formed using a coating solution containing a polysilane having a structure represented by Chemical Formula 4 below, which has a number-average molecular weight of 2100 and a weight-average molecular weight of 12700, or a polysilane having a structure represented by Chemical Formula 5 below, which has a number-average molecular weight of 900 and a weight-average molecular weight of 1200. The terminal substituent R in Chemical Formulas 4 and 5 is not limited to a specific group, but may be, for example, a hydrogen atom, a halogen atom, an organic substituent, a silyl group, or a hydroxyl group.

[0020] As shown by the evaluation tests, it has been shown that a polysilane film 14 suitable for carrying out the treatments described with reference to Figures 1 to 3 can be formed regardless of whether the polysilane contained in the coating liquid has the structure of Chemical Formula 4 or Chemical Formula 5. When forming the polysilane film 14, a comparison is made between the case where the polysilane of Chemical Formula 4 is used and the case where the polysilane of Chemical Formula 5 is used, and the result is that more suitable etching resistance is obtained when the polysilane of Chemical Formula 5 is used. In this specification, the formation of the polysilane film 14 means that in addition to the formation of the polysilane film 14 by supplying the coating liquid to the substrate, the aforementioned plasma modification treatment is also carried out.

[0021] From the above, it can be said that the number average molecular weight of the polysilane is preferably 2100 or less and the weight average molecular weight is preferably 12700 or less, and more preferably the number average molecular weight is 900 or less and the weight average molecular weight is 1200 or less.

[0022] [Details of the Process in the First Embodiment] The process from film formation to modification of the polysilane film 14 in the first embodiment will be described in more detail with reference to the process diagrams of Figures 4 to 6. The process described in Figures 4 to 6 corresponds to the steps described in Figures 1C to 2A.

[0023] 4, a coating liquid 20A for forming a polysilane film is first supplied from a nozzle 21 to the center of the surface of the wafer W, and the wafer W is rotated to spread the coating liquid 20A over the surface of the wafer W toward the periphery, i.e., spin coating is performed. In the figure, reference numeral 22 denotes a spin chuck that suction-holds the center of the back surface of the horizontally placed wafer W, reference numeral 23 denotes a rotation mechanism for rotating the wafer W together with the spin chuck 22, and reference numeral 24 denotes a cup that surrounds the wafer W on the spin chuck 22 to prevent the coating liquid 20A from scattering. After the coating liquid 20A has been discharged from the nozzle 21, the rotation continues, and the coating liquid 20A remaining on the wafer W dries, forming a polysilane film 14.

[0024] In this manner, when the coating liquid 20A, which is the first coating liquid, is spread from the center to the periphery of the wafer W and then dried on the wafer W to form the polysilane film 14, the wafer W is rotated at, for example, 1000 rpm to 2000 rpm. The time for rotating the wafer W at this rotation speed range is, for example, 15 to 60 seconds. Before supplying the coating liquid 20A to the wafer W, an organic solvent may be supplied from a nozzle to the center of the wafer W and spread by spin coating to coat the entire surface of the wafer W, thereby increasing the wettability of the coating liquid 20A on the surface of the wafer W, and then the coating liquid 20A may be applied to the wafer W.

[0025] The wafer W on which the polysilane film 14 has been formed is placed on a hot plate 25 equipped with a heater 26 as shown in Fig. 5, and heated as described above. This heating is performed, for example, so that the wafer W reaches a temperature of 80°C or higher. After this heating, the wafer W is placed on a stage 72 provided in a processing chamber 71 under a vacuum atmosphere as shown in Fig. 6, and the polysilane film 14 is exposed to plasma (indicated as P in the drawing) formed in the processing chamber 28. In the first embodiment, this plasma is plasma of helium (He) gas, which is an inert gas.

[0026] As shown in the evaluation test, the plasma of this He gas not only densifies the polysilane film 14 as described above, but also densifies the SOC film 13. This is because, among the components constituting the plasma, ions mainly act on each film, and because He atoms are relatively small, the He ions constituting the plasma are also relatively small. Therefore, a relatively large number of He ions pass between the molecules constituting the polysilane film 14 and are supplied to the SOC film 13.

[0027] As described with reference to FIG. 3 , the SOC film 13 serves as a mask when etching the film 12. Therefore, densification in this manner is preferable because it increases the resistance during etching and prevents the film 12 from disappearing before etching is complete, thereby preventing defects in the patterning of the film 12. Furthermore, as described above, the wafer W is heated to remove the solvent after the SOC film 13 is formed, and this heating is also intended to densify the SOC film. The ability to densify the SOC film 13 using He gas plasma as described above is also preferable because it reduces the heating temperature of the wafer W after the SOC film 13 is formed. Furthermore, as shown in evaluation tests, when the SOC film 13 is densified using He gas plasma, etching of the SOC film 13 is suppressed. This suppression of etching is thought to be due to the fact that He ions are relatively small and therefore have a relatively small mass, resulting in a small etching effect.

[0028] The deposition of the SOC film 13 and the subsequent heating of the SOC film 13 described with reference to FIG. 1 are performed similarly to the deposition and subsequent heating of the polysilane film 14 shown in FIG. 4 , except that, for example, a coating liquid for depositing the SOC film 13 is used. First, the SOC film 13 is deposited by spin coating, similar to the deposition of the polysilane film 14, using a coating liquid different from the coating liquid 20A. The wafer W is then heated by being placed on the hot plate 25 to remove the solvent from the SOC film 13. This heating does not need to be excessively high, as described above; for example, the wafer W is heated to a temperature lower than 500° C. The deposition and heating of the resist film 15 (post-apply bake) are also performed by spin coating and placing the wafer on the hot plate 25, similar to the deposition and heating of the SOC film 13, except that a resist is used as the coating liquid.

[0029] [Substrate Processing Apparatus Performing Processing of First Embodiment] A substrate processing apparatus 3 that performs the processing from the deposition of the SOC film 13 to the modification of the polysilane film 14, among the series of processing steps described with reference to FIGS. 1 to 3, will be described with reference to FIG. 7, which is a plan view. The substrate processing apparatus 3 is formed by connecting a carrier block D1, a processing block D2, and a plasma processing block D3 in a row. In the following description, the direction along the row of blocks is referred to as the left-right direction, with the carrier block D1 side being the left side and the plasma processing block D3 side being the right side. When viewing the carrier block D1 side from the left side and the plasma processing block D3 side from the right side, the near side will be referred to as the front side and the far side will be referred to as the rear side. The left and right sides are the -X and +X sides, respectively, in the figure, and the front and rear sides are the -Y and +Y sides, respectively, in the figure.

[0030] The carrier block D1 includes a plurality of stages 31 for carriers C, for example, four of which are arranged side by side in the front-to-rear direction, and a transfer mechanism 32 that transfers wafers W into and out of the carriers C placed on each stage 31. The carriers C are transfer containers, for example, called FOUPs (Front Opening Unity Pods), that can store a plurality of wafers W. In the drawing, 33 denotes a transfer area that extends back and forth to allow the transfer mechanism 32 to move.

[0031] Processing block D2 will now be described with reference to the longitudinal side view of Figure 8. Processing block D2 includes a liquid processing unit F1 on the front side and a heating processing unit F2 on the rear side, and a wafer W transfer region 34 extending laterally in a plan view is configured between liquid processing unit F1 and heating processing unit F2, and transfer region 34 is located in the center of processing block D2 in the front-to-rear direction.

[0032] The liquid processing unit F1 is configured by stacking an SOC film deposition module 35 and a polysilane film deposition module 36. The SOC film deposition module 35 and the polysilane film deposition module 36 each include the nozzle 21, the spin chuck 22, the rotation mechanism 23, and the cup 24 shown in FIG.

[0033] The heating process unit F2 is configured by stacking multiple heating modules to form a stack, with multiple stacks arranged side by side. Each heating module includes the hot plate 25 shown in FIG. 5 and a transfer body capable of supporting and moving the wafer W to transfer the wafer W between the hot plate 25 and a transfer mechanism 41 (described later). The transfer body has a coolant flow path, which cools the wafer W heated by the hot plate 25 before it is received by the transfer mechanism 41 (described later). The heating module for heating the wafer W on which the SOC film 13 has been formed and the heating module for heating the wafer W on which the polysilane film 14 has been formed are designated 37 and 38, respectively. The number of film-forming modules 35 and 36 included in the liquid processing unit F1 and the number of stacked heating modules in the heating process unit F2 are not limited to those shown in FIG. 8.

[0034] A transfer mechanism 41 is provided in the transfer region 34. The transfer mechanism 41 includes a base 42, a support 43 that can move back and forth on the base 42 and support a wafer W, and a movement mechanism 44 that moves the base 42. The movement mechanism 44 allows the base 42 to move left and right, move up and down, and rotate about a vertical axis. With this configuration, the transfer mechanism 41 can deliver the wafer W to and from each module of the liquid processing unit F1 and the heating processing unit F2, each module of the tower T1 described below, and a load lock module 5 described below.

[0035] A tower T1 is provided on the left side of the transfer region 34. The tower T1 is configured by multiple stages of modules on which wafers W are temporarily placed. Some of the multiple temporary placement modules are transfer modules TRS, and others are temperature adjustment modules SCPL. The temperature adjustment module SCPL is provided with a stage having a fluid flow path, and a fluid whose temperature is adjusted by a chiller is supplied to the flow path. This adjusts the temperature of the wafer W placed on the stage.

[0036] A transfer mechanism 45 is provided on the rear side of the tower T1. The transfer mechanisms 32, 41, and 45 access each module of the tower T1, and wafers W can be transferred between these transfer mechanisms. Note that the transfer mechanism 32 has the same configuration as the transfer mechanism 41, except that the transfer mechanism 44 is configured so that the base 42 moves back and forth instead of left and right, and the support 43 has a shape that allows access to the carrier C, and the transfer mechanism 45 does not move the base 42 left and right by the transfer mechanism 44.

[0037] In the figure, reference numeral 46 denotes a housing provided for the carrier block D1 and the processing block D2, which encloses the aforementioned transfer regions and modules formed in the carrier block D1 and the processing block D2. The interior of the housing 46 is an air atmosphere, with a pressure at or near atmospheric pressure. Reference numeral 47 denotes a door constituting a load port, which opens and closes an opening formed in the sidewall of the housing 46 on the carrier block D1 side to load and unload wafers W into and from the substrate processing apparatus 3. A transfer port 49 is formed in the sidewall of the housing 46 on the plasma processing block D3 side (right side), and opens to the transfer region 34. The transfer port 49 is used to transfer wafers W between the processing block D2 and the plasma processing block D3, and is opened and closed by a gate valve G1, which will be described later.

[0038] Next, the plasma processing block D3 will be described. The plasma processing block D3 is a block that can form a vacuum pressure atmosphere lower than the pressure inside the housing 46 by exhausting air and includes modules for performing vacuum plasma processing. The block D3 is composed of two load lock modules 5, a vacuum transfer module 6, and three plasma processing modules 7 arranged in a front-to-rear direction.

[0039] Two load lock modules 5 are arranged side by side on the right side of the center between the front and rear of the processing block D2. A vacuum transfer module 6 is provided to the right of these two load lock modules 5. Plasma processing modules 7 are arranged in front, behind, and to the right of the vacuum transfer module 6. The load lock modules 5 are connected to the processing block D2 and the vacuum transfer module 6 via gate valves G1 and G2, respectively. The plasma processing modules 7 are connected to the vacuum transfer module 6 via gate valve G3, and are arranged in front, behind, and to the right of the vacuum transfer module 6.

[0040] The gate valve G1 opens and closes the transfer port 49 of the housing 46 and the transfer port of the housing 51 of the load lock module 5. Closing the gate valve G1 separates the atmosphere in the processing block D2 from the atmosphere inside the load lock module 5 (more specifically, inside the housing 51). When the gate valve G1 is open, the wafer W can be transferred through each transfer port.

[0041] Similar to the case between the processing block D2 and the load lock module 5, between the load lock module 5 and the vacuum transfer module 6, and between the vacuum transfer module 6 and the plasma processing module 7, gate valves G2 and G3 open and close the transfer ports of the housings, respectively, to switch between a state in which a wafer W can be transferred and a state in which the atmospheres are separated. That is, closing gate valve G2 separates the atmosphere in the load lock module 5 from the atmosphere in the vacuum transfer module 6 (more specifically, in the housing 61 described below). Opening gate valve G2 allows the transfer of a wafer W between the load lock module 5 and the vacuum transfer module 6. Closing gate valve G3 separates the atmosphere in the load lock module 5 from the atmosphere in the plasma processing module 7 (more specifically, in the processing vessel 71, which is the housing described below). Opening gate valve G3 allows the transfer of a wafer W between the vacuum transfer module 6 and the plasma processing module 7. Gate valves G1 to G3 are all closed except when necessary for transferring a wafer W.

[0042] The load lock module 5 includes a housing 51 and a stage 52 located within the housing 51 on which a wafer W is placed, and is provided with an air supply mechanism for supplying, for example, an inert gas into the housing 51 and an exhaust mechanism for exhausting the gas. By supplying or exhausting the gas while the gate valves G1 and G2 are closed, the pressure within the housing 51 can be changed, and the pressure can be switched between atmospheric pressure and a desired vacuum pressure. The stage 52 is provided with pins 53 that protrude and retract from a mounting surface (top surface) of the stage 52 on which the wafer W is placed, and the transfer mechanism 41 and a transfer mechanism 62 (described later) can transfer the wafer W to the mounting surface via the pins 53.

[0043] The vacuum transfer module 6 includes a housing 61 and a transfer mechanism 62 provided within the housing 61. An exhaust mechanism is provided to exhaust the interior of the housing 61, and the interior of the housing 61 is maintained at a vacuum atmosphere of a desired pressure. The transfer mechanism 62 is configured as an articulated arm, and accesses the load lock module 5 and each plasma processing module 7 to transfer wafers W between these modules. The transfer mechanisms 32, 41, 45, and 62 form a transfer section, with the transfer mechanisms 41 and 45 provided in the processing blocks (processing sections) forming a first transfer section, and the transfer mechanism 62 provided in the vacuum transfer module 6 (vacuum transfer chamber) forming a second transfer section.

[0044] [Configuration of Plasma Processing Module] Next, the plasma processing module 7 will be described with reference to the vertical cross-sectional side view of FIG. 9. As shown in FIG. 6, the plasma processing module 7 includes a processing vessel 71 and a stage 72 disposed therein. In the figure, reference numeral 73 denotes a wafer W transfer port disposed in the sidewall of the processing vessel 71, which is opened and closed by the gate valve G3 described above. The upper central portion of the stage 72 is configured as an electrostatic chuck 74, which attracts the backside of the wafer W during plasma processing, as described above. A focus ring 75 surrounding the wafer W on the electrostatic chuck 74 is disposed on the upper peripheral edge of the stage 72, and adjusts the distribution of plasma formed in the processing space 70 above the wafer W.

[0045] A temperature adjustment unit 76 is embedded in the stage 72 to adjust the temperature of the wafer W on the electrostatic chuck 74. The temperature adjustment unit 76 is configured with a flow path to which a fluid whose temperature is adjusted by, for example, a heater or a chiller is supplied. Note that, similar to the pins 53 of the load lock module 5, the stage 72 is provided with pins that protrude into and retract from the wafer W mounting surface (the upper surface of the electrostatic chuck 74) of the stage 72 to transfer the wafer W between the transfer mechanism 62 and the stage 72, but these are not shown in the figure.

[0046] In the figure, reference numeral 78 denotes a support pillar that supports the stage 72 within the processing vessel 71. Reference numeral 79 denotes an exhaust pipe that has an upstream end that opens at the bottom of the processing vessel 71 and a downstream end that is connected to an exhaust mechanism 81 composed of a turbomolecular pump, a dry pump, or the like. The inside of the processing vessel 71 (i.e., the processing space 70) is evacuated to a vacuum atmosphere of a desired pressure by the exhaust mechanism 81. To improve the uniformity of exhaust at each portion along the periphery of the stage 72, a baffle plate 83 having a number of through-holes 82 drilled in the thickness direction is provided. This baffle plate 83 surrounds the stage 72 and divides the inside of the processing vessel 71 into upper and lower sections.

[0047] The downstream end of a gas supply pipe 84 is connected to the ceiling of the processing vessel 71. Gas supplied from a gas supply mechanism 85 provided upstream of the gas supply pipe 84 is discharged into the processing space 70 from a discharge port (not shown) formed in the ceiling via the gas supply pipe 84. As described above, in the first embodiment, this gas is He gas.

[0048] In the plasma processing module 7, a capacitively coupled plasma is generated using the ceiling of the processing vessel 71 as an upper electrode and the stage 72 as a lower electrode. High frequency powers of different frequencies are applied to the stage 72, more specifically, to the electrodes included in the stage 72, from a first high frequency power supply 86 and a second high frequency power supply 87. The frequency of the power supplied from the first high frequency power supply 86 (referred to as the first frequency) is higher than the frequency of the power supplied from the second high frequency power supply 87 (referred to as the second frequency). For example, the first frequency is 100 MHz and the second frequency is 13 MHz.

[0049] The wafer W may be processed by supplying high frequency power to the stage 72 from both the first high frequency power supply 86 and the second high frequency power supply 87. In this case, the first high frequency power supply 86, which supplies power at a higher frequency, corresponds to the high frequency power supply for plasma generation that converts the processing gas into plasma in the processing space 70. The electrode of the stage 72 to which power is supplied from the first high frequency power supply 86 is the electrode for plasma generation. The second high frequency power supply 87, which supplies power at a lower frequency, corresponds to the high frequency power supply for bias application. The supply of bias application power from the second high frequency power supply 87 attracts ions in the plasma to the stage 72 and irradiates the wafer W on the stage 72.

[0050] The wafer W may be processed by generating plasma by supplying high-frequency power from only one of the first and second high-frequency power supplies 86 and 87. That is, processing may be performed without supplying power for bias application. In this case, the high-frequency power supply for generating high-frequency power from either the first or second high-frequency power supply 86 or 87 is the high-frequency power supply for plasma generation. The high-frequency power supplied from the first high-frequency power supply 86 is, for example, 0 W to 500 W, and the high-frequency power supplied from the second high-frequency power supply 87 is, for example, 500 W to 3000 W. Experiments have confirmed that plasma can be generated and the wafer W can be modified with such power settings from the high-frequency power supplies 86 and 87. Therefore, when processing the wafer W, the high-frequency power supplied from the high-frequency power supply for plasma generation is 3000 W or less, and the high-frequency power for bias application is 500 W to 3000 W, which is the high-frequency power supplied from the second high-frequency power supply 87.

[0051] In the following description, "while a wafer W is being processed in the plasma processing module 7" refers to the time during which the high frequency power supply for plasma generation is turned on so that the wafer W can be plasma processed while the wafer W is placed on the stage 72. The processing time for the wafer W refers to the time during which the high frequency power supply for plasma generation is turned on to process the wafer W.

[0052] [Processing Procedure in Plasma Processing Module] An example of a processing procedure for wafers W in the plasma processing module 7 will be described below. In this example, similar to the setting when He gas plasma was used in the evaluation test, the setting is such that no power is supplied from the first high frequency power supply 86, i.e., no power for bias application is supplied.

[0053] First, a wafer W is transferred into the processing chamber 71, which is set at a predetermined vacuum pressure lower than the pressure inside the housing 46 constituting the carrier block D1 and processing block D2, and placed on the electrostatic chuck 74. Then, He gas is supplied to the processing space 70, and power is supplied from the second high-frequency power supply 87 to the stage 72. This converts the He gas into plasma. Of the components constituting the plasma, He ions primarily act on the polysilane film 14, densifying the polysilane film 14. As described above, the He ions also penetrate the polysilane film 14 and act on the SOC film 13, thereby densifying the SOC film 13.

[0054] Thereafter, when a predetermined processing time for the wafer W has elapsed since the start of plasma generation by power supply from the second high frequency power supply 87, power supply from the second high frequency power supply 87 is stopped, and the supply of He gas to the processing space 70 is stopped, thereby ending the processing, and the wafer W is unloaded from the processing vessel 71. Note that when processing is performed by supplying high frequency power from each of the first high frequency power supply 86 and the second high frequency power supply 87, He ions are attracted toward the stage 72 during the above-described plasma generation and are supplied to the wafer W.

[0055] As described above, in the plasma processing module 7, the processing space 70 is evacuated during processing of the wafer W, and no oxygen-containing gas is supplied to the processing space 70. Therefore, the proportion of oxygen in the processing vessel 71 during processing is lower than the proportion of oxygen in the air atmosphere, and plasma is generated. This is preferable because it prevents oxygen remaining in the processing space 70 from becoming plasma and permeating the polysilane film 14, thereby etching the SOC film 13.

[0056] In the plasma processing module 7, an experiment was conducted to examine the etching rate of the SOC film 13 by exposing multiple wafers W, each having an exposed SOC film 13 on its surface without a polysilane film 14, to He gas plasma under various processing conditions. In the experiment, the pressure inside the processing chamber 71 was set to a range of 30 mTorr to 300 mTorr, and the etching rate was relatively low in the range of 100 mTorr to 300 mTorr. The processing time was set to a range of 10 seconds to 240 seconds, and the etching rate was relatively low in the range of 10 seconds to 120 seconds. The temperature of the wafers W during processing was set to a range of 20°C to 80°C, and the etching rate was relatively low in the range of 20°C to 60°C.

[0057] Even when a polysilane film 14 is formed on the SOC film 13, it is believed that the action of ions penetrating the polysilane film 14 can be suppressed by the same settings, and etching of the SOC film 13 can be more reliably suppressed. That is, as described above, when modifying a wafer W on which a polysilane film 14 has been formed in the plasma processing module 7, it is believed that the processing time for the wafer W is preferably set to, for example, 10 to 120 seconds. That is, it is preferable that the processing time be 10 seconds or more and 120 seconds or less. Furthermore, it is believed that the temperature of the wafer W on the stage 72 during processing is preferably maintained at, for example, 20°C to 60°C, and the pressure within the processing chamber 71 is preferably maintained at 100 mTorr (13.3 Pa) to 300 mTorr (40 Pa). That is, it is preferable that the pressure be 13.3 Pa or more.

[0058] [Configuration of Control Unit] Returning to FIG. 7 , the substrate processing apparatus 3 is provided with a control unit 100. The control unit 100 is, for example, a computer, and has a program storage unit (not shown). The program storage unit stores a program for controlling the processing of wafers W in the substrate processing apparatus 3. The control unit 100 has one or more control circuits so as to execute the steps of the program. The program may be recorded on a computer-readable storage medium and installed into the control unit 100 from the storage medium. The installed program incorporates instructions (each step) so that the control unit 100 outputs a control signal to each unit of the substrate processing apparatus 3, and the processing operation of wafers W in each transfer mechanism and each module is controlled by this control signal.

[0059] [Transportation of Wafer in Substrate Processing Apparatus 3] The wafer W unloaded from the carrier C on the stage 31 is transported in the following order: transfer module TRS of tower T1 → temperature adjustment module SCPL of tower T1 → SOC film deposition module 35 → heating module 37 → temperature adjustment module SCPL of tower T1 → polysilane film deposition module 36 → heating module 38. As a result, an SOC film 13 and a polysilane film 14 are deposited in this order, as described with reference to FIGS. 1A to 1C.

[0060] The wafer W is then transferred to the load lock module 5, the interior of which is under atmospheric pressure. Once the load lock module 5 reaches a predetermined vacuum pressure, the wafer W is transferred via the vacuum transfer module 6 to the plasma processing module 7, where it undergoes plasma processing. As described with reference to FIG. 2A , the polysilane film 14 and the SOC film 13 are modified, changing the structures of these films. The wafer W is then transferred via the vacuum transfer module 6 to the load lock module 5, the interior of which is under a predetermined vacuum pressure. Once the load lock module 5 reaches atmospheric pressure, the wafer W is returned to the carrier C via the tower T1 of the processing block D2. The carrier C, to which the wafer W has been returned, is then transferred to another substrate processing apparatus within the clean room by a transfer mechanism for the carrier C, which is installed within the clean room, so that the wafer W can undergo the processing described with reference to FIGS. 2B to 3B .

[0061] 1 to 3, including the process for forming the polysilane film 14 according to the first embodiment, as described above, prevents problems such as pattern collapse during development of the resist film 15 and problems such as the polysilane film 14 being etched away and lost before the patterning of the SOC film 13 using the polysilane film 14 as an etching mask is completed. Therefore, by forming the polysilane film 14 as described in the first embodiment, the degree of freedom in setting the thicknesses of the resist film 15 and the SOC film 13 is increased, making it easier to pattern these films.

[0062] Furthermore, in the process of forming the polysilane film 14 according to the first embodiment, the SOC film 13 is also densified along with the polysilane film 14. This is advantageous in that it prevents the SOC film 13 from disappearing before the patterning of the film 12 is completed. Therefore, it can be said that the formation of the polysilane film 14 according to the first embodiment also facilitates the patterning of the film 12.

[0063] [Substrate Processing System] An example of the configuration of the substrate processing apparatus to which the carrier C is transferred from the substrate processing apparatus 3 will now be described. The formation of the resist film 15 may be performed using a module configured similarly to the polysilane film deposition module 36, except that a resist is supplied as a coating liquid. The removal of the solvent in the resist film 15 by heating and the PEB may be performed using a module configured similarly to the heating module 38. Development using a developer may be performed using, for example, a module configured to supply the developer to the wafer W from a nozzle. Development using a developer gas may be performed using, for example, a module configured similarly to the plasma processing module 7, except that no plasma is generated and a developer gas is supplied to the processing space 70 as a gas. That is, development may be performed using a module configured to supply a developer gas into a processing chamber 71 whose interior can be evacuated. Because plasma generation is not required, the pressure inside the processing chamber 71 during processing of the wafer W may be set higher than the pressure during plasma processing in the plasma processing module 7.

[0064] 10 shows a plan view of a substrate processing system 30 including a substrate processing apparatus 3 and a substrate processing apparatus 3A. The substrate processing apparatus 3A is the destination of a carrier C from the substrate processing apparatus 3. The substrate processing apparatus 3A includes a carrier block D1, a processing block D20, and an interface block D4. An exposure machine D5 that exposes a resist film 15 is connected to the interface block D4. In the processing block D20, similar to the processing block D2, modules for processing wafers W are arranged before and after the transfer region 34, and wafers W can be transferred between each module by a transfer mechanism 41. Furthermore, wafers W are transferred between the processing block D20 and the exposure machine D5 by a transfer mechanism provided in the interface block D4. Temporary storage modules for temporarily storing wafers W are appropriately arranged in each block to enable transfer of wafers W between the blocks.

[0065] The processing block D20 of the substrate processing apparatus 3A is provided with the resist film deposition module, the heating module for PEB, and the developing module using a developing gas or a developing solution, and is capable of forming the resist film 15 and patterning the resist film 15, as described with reference to Figures 2B and 2C. Note that the processing of the wafer W from Figure 3A onward is performed, for example, by transporting the carrier C to another substrate processing apparatus.

[0066] 1 to 3, which steps are performed in one substrate processing apparatus, i.e., which steps are performed until the wafer W unloaded from the carrier C is returned to the carrier C, can be set as appropriate. Specifically, the substrate processing apparatus 3 is shown configured to perform the formation of the polysilane film 14 as shown in FIGS. 1C to 2A, as well as the formation and heating of the SOC film 13, but this configuration is not limiting. The carrier C storing the wafer W on which the SOC film 13 has been formed and heated may be transported to the substrate processing apparatus 3, and only the formation of the polysilane film 14 as shown in FIGS. 1C to 2A may be performed in the substrate processing apparatus 3. Regarding the processes from the formation of the resist film after the formation of the polysilane film 14 to the development, although FIG. 10 shows the processes being performed solely by the substrate processing apparatus 3A, they may also be performed sequentially by transporting the carrier C between multiple substrate processing apparatuses.

[0067] 1C to 2A may also be performed in separate substrate processing apparatuses. Fig. 11 shows a plan view of a substrate processing system 9 made up of substrate processing apparatuses 9A and 9B. The substrate processing apparatus 9A includes a carrier block D1 and a processing block D2. The substrate processing apparatus 9A corresponds to a first substrate processing apparatus, and the transport mechanisms 32, 41, and 45 provided in the substrate processing apparatus 9A correspond to one transport section.

[0068] The substrate processing apparatus 9B includes a carrier block D1 and a plasma processing block D3, and a transfer mechanism 32 transfers wafers W between the carrier block D1 and the load lock module 5. The substrate processing apparatus 9B corresponds to a second substrate processing apparatus, and the transfer mechanisms 32 and 62 provided in the substrate processing apparatus 9B correspond to another transfer unit.

[0069] In the substrate processing apparatus 9A, a polysilane film 14 is formed on the wafer W unloaded from the carrier C, the wafer W is heated after the film formation, and the wafer W is returned to the carrier C. The carrier C is then transported to the substrate processing apparatus 9B by a transport mechanism for the carrier C. The wafer W unloaded from the carrier C in the substrate processing apparatus 9B is then modified with the polysilane film 14 and returned to the carrier C. In this way, the substrate processing system 9 can also perform the same processing on the wafer W as in the substrate processing apparatus 3. However, since the substrate processing system 9 requires two carrier blocks D1, the configuration of the substrate processing apparatus 3 is more preferable from the viewpoint of reducing the occupied floor space.

[0070] Second Embodiment A second embodiment will be described, focusing on the differences from the first embodiment. In the second embodiment, the processing gas supplied from the gas supply mechanism 85 to the processing space 70 in the plasma processing module 7 is H ２ (hydrogen) gas and inert gas N ２ (nitrogen) gas, and these H ２ Gas and N ２ The gas mixture is turned into a plasma.

[0071] The high frequency power supplied from the first high frequency power supply 86 is, for example, 0 W to 500 W, and the high frequency power supplied from the second high frequency power supply 87 is, for example, 100 W to 1500 W. Therefore, when processing the wafer W, the high frequency power supplied from the high frequency power supply for plasma generation is, for example, 1500 W or less. The high frequency power for bias application is, for example, 100 W to 1500 W, which is the high frequency power supplied from the second high frequency power supply 87. Experiments have confirmed that plasma can be generated and modification processing of the wafer W can be performed with such high frequency power settings of the high frequency power supplies. Note that, as described above, the high frequency power for bias application is, for example, 500 W or more in the first embodiment and, for example, 100 W or more in the second embodiment, and therefore, in this technology, it is set to, for example, 100 W or more.

[0072] As in the first embodiment, high frequency power does not have to be supplied from the first high frequency power supply 86, but when high frequency power is supplied from each of the first high frequency power supply 86 and the second high frequency power supply 87, hydrogen ions and nitrogen ions in the plasma are drawn toward the stage 73, thereby processing the wafer W.

[0073] An experiment was conducted in which the pressure inside the processing vessel 71 during processing of the wafer W was set to 20 mTorr (2.67 Pa) to 100 mTorr, the temperature of the wafer W was set to 20°C to 50°C, and the processing time of the wafer W was set to 10 seconds to 120 seconds, and within these ranges, it was possible to sufficiently modify the polysilane film 14 while suppressing etching of the SOC film 13. Therefore, it is preferable to maintain the pressure and temperature within these ranges during processing of the wafer W, and it is also preferable to set the processing time within these ranges.

[0074] In the second embodiment, the polysilane film 14 can be modified in the same manner as in the first embodiment. However, as shown in the evaluation test, the first embodiment using the plasma of He gas is more preferable because it can reduce the amount of etching of the SOC film 13 and modify the SOC film 13 as described above.

[0075] [Additional Notes] Incidentally, in the above-described embodiments, the polysilane film 14 is formed adjacent to the SOC film 13, but the polysilane film 14 and the SOC film 13 are not limited to being adjacent to each other in this manner, and another film may be interposed between these films. Therefore, stacking the polysilane film 14 on the SOC film 13 also includes stacking the polysilane film 14 with another film interposed therebetween. Similarly, another film may be interposed between the polysilane film 14 and the resist film 15.

[0076] The film 12 formed below the polysilane film 14 is not limited to the exemplified film, and may be any type of film. In describing the wafer W, the side on which the film 12 is formed relative to the Si layer 11 is described as the upper side, but the orientation of each wafer W during processing is arbitrary, and the wafer W is not limited to being processed with the side on which the film 12 is formed facing upward.

[0077] When forming capacitively coupled plasma in plasma processing module 7, power may be supplied to the upper electrode from a high-frequency power supply for plasma generation. Furthermore, plasma processing module 7 is not limited to being configured to perform processing using capacitively coupled plasma, and may be configured to perform processing using, for example, inductively coupled plasma. Furthermore, processing using so-called remote plasma may be performed by supplying plasma formed outside processing vessel 71 into processing vessel 71.

[0078] Furthermore, in each embodiment, the substrate to be processed is not limited to a wafer, but may be, for example, a substrate for manufacturing a flat panel display or a mask substrate for manufacturing an exposure mask. Therefore, a rectangular substrate may be processed.

[0079] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive, and various omissions, substitutions, modifications, and combinations may be made to the above-described embodiments without departing from the scope and spirit of the appended claims.

[0080] [Evaluation Tests] Evaluation tests carried out in relation to the present technology will be described below.

[0081] Evaluation Test 1 In Evaluation Test 1, a polysilane film was formed on each of a plurality of wafers W in the polysilane film forming module 36 using an organic solvent containing the compound shown in Chemical Formula 5 as a coating liquid. Then, in the heating module 38, each wafer W was heated at 130° C. for 60 seconds in an air atmosphere. Thereafter, in the plasma processing module 7, each wafer W was heated under the first condition using plasma of He gas as described in the first embodiment, or under the second condition using plasma of N gas as described in the second embodiment. ２ Gas and H ２ The film was modified by treatment under the second condition using a gas plasma.

[0082] Each of the wafers W thus modified was subjected to plasma etching in the plasma processing module 7. After the plasma etching was completed, the amount of etching of the polysilane film on each wafer W was measured, and the etching rate (unit: nm / min) was calculated. The processing conditions for this plasma etching are referred to as first etching conditions. These first etching conditions are processing conditions capable of etching the SOC film 13 and are different from the second conditions for modification described above. In other words, the first etching conditions and the second conditions have different settings for each parameter, such as the supply power of each high-frequency power supply.

[0083] In Comparative Test 1, films other than the polysilane film modified as described above were also plasma etched under the same processing conditions as those used for etching the polysilane film, and the etching rates were calculated. The films other than the modified polysilane film were specifically SOC film, SiOCN film, SiC film, SOG (spin on glass) film, and unmodified polysilane film. The unmodified polysilane film was a film that was deposited and heated using modules 36 and 38 under the same processing conditions as the modified polysilane film, but was not subjected to plasma processing under the first or second conditions.

[0084] To describe the first condition in detail, the pressure inside the processing vessel 71 was set to 300 mTorr, the power supplied by the first high frequency power supply 86 was set to 0 W, the power supplied by the second high frequency power supply 87 was set to 3000 W, the flow rate of He gas supplied into the processing vessel 71 was set to 900 sccm, the temperature of the wafer W during the plasma processing time was set to 20° C., and the plasma processing time was set to 10 seconds.

[0085] The second condition is described in detail as follows: the pressure inside the processing vessel 71 is 25 mTorr, the power supplied from the first high frequency power supply 86 is 100 W, the power supplied from the second high frequency power supply 87 is 1300 W, and N 2 is introduced into the processing vessel 71. ２ The gas supply flow rate was 300 sccm, and H ２ The gas supply flow rate was set to 300 sccm, the temperature of the wafer W during the plasma processing time was set to 30° C., and the plasma processing time was set to 60 seconds. Therefore, the first condition was set to not apply bias power, and the second condition was set to apply bias power.

[0086] The graphs in Figures 12 and 13 show the results of Evaluation Test 1 and Comparative Test 1. Figure 12 shows the etching rate of each film. Figure 13 shows the value obtained by dividing the etching rate of each film other than the SOC film by the etching rate of the SOC film, and this value is taken as the etching selectivity of the SOC film. Therefore, for each film, the lower the etching rate in Figure 12 and the higher the etching selectivity of the SOC film in Figure 13, the higher the etching resistance during the above-mentioned plasma etching.

[0087] As is clear from Figures 12 and 13, the etching resistance of the unmodified polysilane film is lower than the etching rates of the SiOCN film, SiC film, and SOG film, and the etching resistance of the SOC film. However, the etching resistance of the polysilane film modified under the second condition is equivalent to that of the SOG film, which has the highest etching resistance among the SiOCN film, SiC film, and SOG film. Furthermore, the etching resistance of the polysilane film modified under the first condition is higher than that of the SOG film. Therefore, it has been shown that using a modified polysilane film as an etching mask is effective when etching the SOC film 13 as described in the embodiment.

[0088] Evaluation Test 2 Evaluation Test 2 was performed in a similar manner to Evaluation Test 1, in which polysilane film deposition, heating, modification, and plasma etching were performed on a plurality of wafers W. The thickness of the polysilane film was measured at the following times in this series of processes: after heating and before modification, after modification and before plasma etching, and after plasma etching. In the following description of Evaluation Test 2, the times after heating and before modification, and after modification and before plasma etching in the series of processes described above may sometimes be referred to as "before modification" and "after modification," respectively.

[0089] The series of processes in the above-described evaluation test 2 differs from the series of processes performed in evaluation test 1 in that, when forming a polysilane film, either a coating liquid containing the compound shown in Chemical Formula 4 or a coating liquid containing the compound shown in Chemical Formula 5 was supplied to each wafer W. The polysilane film on each wafer W was modified under the second condition. The test performed using the compound shown in Chemical Formula 4 and the test performed using the compound shown in Chemical Formula 5 are designated evaluation tests 2-1 and 2-2, respectively.

[0090] The graphs in Figure 14 show the results of Evaluation Tests 2-1 and 2-2, respectively. The vertical axis of each graph represents the normalized value obtained by dividing the measured film thickness by a predetermined value. When comparing [film thickness after modification - film thickness after plasma etching], i.e., the amount of reduction in film thickness of the polysilane film due to plasma etching, between Evaluation Tests 2-1 and 2-2, Evaluation Test 2-2 was smaller. Therefore, Evaluation Test 2-2 had higher etching resistance, resulting in favorable results. This is presumably because the compound of Chemical Formula 5 has smaller number molecular weight and weight molecular weight than the compound of Chemical Formula 4, resulting in a higher density of polysilane molecules in the film.

[0091] Evaluation Test 3: In Evaluation Test 3, similarly to Evaluation Test 2-2, a polysilane film made of the compound of Chemical Formula 5 was formed on a wafer W, heated, modified, and plasma etched. The thickness of the polysilane film was measured after modification and before plasma etching, and after plasma etching. Unlike Evaluation Test 2-2, however, Evaluation Test 3 was modified under the first conditions using He gas plasma. Furthermore, plasma etching was performed under either the first or second etching conditions. The second etching conditions differed from the first etching conditions in terms of the etching gas and parameters used, and are process conditions capable of etching a SiC film by using a fluorocarbon compound as the etching gas. The etching time under the first etching conditions was set to be the same as that under the second etching conditions.

[0092] In Comparative Test 3, wafers W were treated in the same manner as in Evaluation Test 3 except that no modification was performed, and the thickness of the polysilane film was measured after heating and before plasma etching, and after plasma etching.

[0093] FIG. 15 is a graph showing the results of Evaluation Test 3 and Comparative Test 3. In addition to FIG. 15, the results of the aforementioned Evaluation Test 2-2, which used the compound of Chemical Formula 5 as in Evaluation Test 3 and Comparative Test 3, will also be referred to for the discussion. ２ Gas and N ２ The difference in film thickness of the polysilane film before and after treatment with He gas plasma is shown as ΔT1. Meanwhile, the difference in film thickness due to He gas plasma treatment obtained from Evaluation Test 3 and Comparative Test 3 is shown as ΔT2. This ΔT2 was suppressed to a very low value, about 1 / 75 of ΔT1. Therefore, it was confirmed that modification using He gas plasma is preferable from the viewpoint of suppressing a decrease in the film thickness of the polysilane film and increasing the controllability of the film thickness.

[0094] 15 , the result of Evaluation Test 3 shows that [thickness of polysilane film before etching - thickness of polysilane film after etching under the first etching conditions] is smaller than [thickness of polysilane film before etching - thickness of polysilane film after etching under the second etching conditions]. Therefore, it was confirmed that polysilane films exhibit high etching resistance under the etching conditions for etching SOC films, and therefore can be preferably used as an etching mask for SOC films. However, [thickness of polysilane film before etching - thickness of polysilane film after etching under the second etching conditions] is also a practically sufficient value, and polysilane films can also be preferably used as an etching mask for this SiC film.

[0095] Evaluation Test 4 In Evaluation Test 4, a polysilane film was formed on a wafer W using a coating liquid containing the compound shown in Chemical Formula 5, followed by heating and modification under the first condition. Each of these processes was performed under the processing conditions described in Evaluation Test 1. After modification, an image of the vertical cross section of the wafer W was acquired, and the total film thickness of the polysilane film and the SOC film was measured. The wafer W used in Evaluation Test 4 differed from that described in FIG. 1 and other figures, in that an SOC film of a predetermined film thickness was formed directly on the Si layer 11. In other words, an SOC film was formed adjacent to the Si layer 11, and the polysilane film was formed on this SOC film. In addition, as Comparative Test 4, a test similar to Evaluation Test 4 was performed except that modification was not performed.

[0096] 16 and 17 show images obtained in Evaluation Test 4 and Comparative Test 4, respectively. The straight lines shown in these images indicate the boundary between the polysilane film and the SOC film. The difference in the total thickness of the polysilane film and the SOC film between Evaluation Test 4 and Comparative Test 4 was extremely small, at 10 nm or less. Furthermore, the particles constituting the polysilane film and the SOC film in Evaluation Test 4 were finer and denser than those in Comparative Test 4. As described above, Evaluation Test 4 confirmed that the use of He gas plasma can densify the polysilane film and the SOC film while suppressing etching of each film.

[0097] Evaluation Test 5 In Evaluation Test 5, a polysilane film was formed on a wafer W using a coating liquid containing the compound of Chemical Formula 5, followed by heating and modification under the second condition. As in Evaluation Test 4, in Evaluation Test 5, the polysilane film was formed on an SOC film formed directly on a Si layer. In addition, the wafer W before and after modification was measured by XPS (X-ray photoelectric spectroscopy) to measure the atomic concentrations in the surface layer of the wafer W on which the polysilane film and SOC film were formed. In Comparative Test 5, a test similar to Evaluation Test 5 was conducted except that no modification was performed.

[0098] The graph in FIG. 18 shows the results of Evaluation Test 5 and Comparative Test 5 obtained by XPS. As shown in this graph, the carbon atom concentration ratio is smaller in Evaluation Test 5. This is because in Evaluation Test 5, H ２ Gas and N ２ This is thought to be because the SOC film was etched by exposure to the gas plasma.

[0099] In addition to Evaluation Test 5, a test (confirmation test) was conducted in which the processing time of wafers W in the plasma processing module 7 was set longer and wafers W were processed in the same manner as in Evaluation Test 5. It was confirmed that the SOC film disappeared. ２ Gas and N ２ It was confirmed that the SOC film was etched by exposure to the plasma of the gas. ２ Gas and N ２ It was confirmed that the use of He gas plasma was more preferable than the use of gas plasma.

[0100] Thus, evaluation tests 4 and 5 demonstrated the superiority of the first condition, which uses He gas plasma. The reason why etching of the SOC film was suppressed under the first condition is thought to be that, as described above, He ions are relatively small and therefore easily pass through polysilane films, but the small mass of the He ions means that their etching effect on the SOC film is small. Note that, although the first condition is a condition in which bias power is not applied, because, as described above, He ions have low etching ability on the SOC film due to their small mass, it is thought that etching of the SOC film can be suppressed even when bias power is applied.

[0101] P: Plasma W: Wafer 14: Polysilane film 15: Resist film 20A: Coating liquid

Claims

1. A method for forming an underlayer film, comprising: a first step of supplying a first coating liquid to a surface of a substrate and forming a polysilane film that will serve as an underlayer film of a resist film; a second step of heating the substrate after the first step; and a third step of modifying the polysilane film by exposing it to plasma of a gas that includes an inert gas after the second step.

2. The method for forming an underlayer film according to claim 1, wherein the plasma of the gas containing the inert gas is plasma of helium gas.

3. The method for forming an underlayer film according to claim 1, wherein the plasma of the gas containing an inert gas is plasma of a mixed gas of nitrogen gas and hydrogen gas.

4. The method for forming an underlayer film according to any one of claims 1 to 3, wherein the polysilane contained in the coating liquid has a number average molecular weight of 2,100 or less and a weight average molecular weight of 12,700 or less.

5. The method for forming an underlayer film according to any one of claims 1 to 3, wherein the third step includes a step of maintaining the temperature of the substrate exposed to the plasma at 60°C or less.

6. The method for forming an underlayer film according to any one of claims 1 to 3, wherein the third step includes a step of maintaining the temperature of the substrate exposed to the plasma at 20°C or higher.

7. A method for forming an underlayer film according to any one of claims 1 to 3, wherein the third step includes a step of setting the power supplied from the high frequency power source for forming the plasma to 3000 W or less to the electrode for forming the plasma.

8. A method for forming an underlayer film according to any one of claims 1 to 3, wherein the third step includes the steps of: supplying high frequency power of a first frequency from a high frequency power supply for forming the plasma to an electrode for forming the plasma; and supplying high frequency power of a second frequency lower than the first frequency from a high frequency power supply for applying a bias to a stage on which the substrate is placed in order to attract ions contained in the plasma.

9. The method for forming an underlayer film according to claim 8, wherein the high frequency power supplied from the high frequency power source for applying the bias is 100 W or more.

10. The method for forming an underlayer film according to any one of claims 1 to 3, wherein in the third step, the substrate is exposed to the plasma for a treatment time of 10 seconds or more.

11. The method for forming an underlayer film according to any one of claims 1 to 3, wherein in the third step, the substrate is exposed to the plasma for a treatment time of 120 seconds or less.

12. A method for forming an underlayer film according to claim 2, wherein the third step includes a step of maintaining the internal pressure of a processing vessel that contains the substrate and in which the plasma is generated at 13.3 Pa or higher during the generation of the plasma.

13. A method for forming an underlayer film according to any one of claims 1 to 3, wherein the third step includes forming the plasma with a lower oxygen content inside a processing vessel containing the substrate than the oxygen content in the atmospheric air.

14. A method for forming an underlayer film according to any one of claims 1 to 3, comprising: a step of supplying a second coating liquid to the surface of the substrate and forming a carbon-containing film before the first step; and a step of heating the substrate on which the carbon-containing film has been formed before the first step, wherein the first step is a step of laminating the polysilane film on the carbon-containing film.

15. A method for forming an underlayer film according to any one of claims 1 to 3, comprising the steps of: laminating the resist film on the polysilane film after the third step; and exposing and heating the substrate on which the resist film has been formed, and then supplying a developing gas to the substrate to develop the resist film.

16. A substrate processing apparatus comprising: a film formation module that supplies a first coating liquid to a surface of a substrate and forms a polysilane film that will serve as an underlying film of a resist film; a heating module that heats the substrate on which the polysilane film has been formed; a plasma processing module that exposes the polysilane film, after heating by the heating module, to plasma of a gas containing an inert gas to modify it; a transfer container that stores the substrate; and a transfer unit that transfers the substrate between the film formation module, the heating module, and the plasma processing module.

17. The substrate processing apparatus according to claim 16, wherein the plasma of the gas containing the inert gas is plasma of helium gas.

18. The substrate processing apparatus according to claim 16, wherein the plasma of the gas containing the inert gas is plasma of a mixed gas of nitrogen gas and hydrogen gas.

19. A substrate processing apparatus as described in any one of claims 16 to 18, wherein the transport units include a first transport unit and a second transport unit that transport the substrates, the plasma processing module has a processing vessel in which a vacuum atmosphere is formed and in which the substrates are stored, the processing vessel is connected to a vacuum transfer chamber in which the second transport unit is provided and in which a vacuum atmosphere is formed, and a load lock module is provided that connects the vacuum transfer chamber to a processing unit in which the film formation module, the heating module and the first transport unit are provided.

20. The substrate processing apparatus according to any one of claims 16 to 18, wherein the polysilane film is laminated on a carbon-containing film formed on the substrate.

21. A substrate processing system comprising: a first substrate processing apparatus comprising: a film formation module that supplies a first coating liquid to a surface of a substrate to form a polysilane film that will serve as an underlayer film of a resist film; a heating module that heats the substrate on which the polysilane film has been formed; a transport container that stores the substrate; and a transport unit that transports the substrate between the film formation module and the heating module; and a second substrate processing apparatus comprising: a plasma processing module that exposes the polysilane film after heating by the heating module to plasma of a gas including an inert gas to modify it, and another transport unit that transports the substrate between the plasma processing module and the transport container.

Images