Emitter-follower driver for power amplifier

Abstract

An emitter-follower driver amplifier for a power amplifier in a wireless communication device is disclosed. In one aspect, a wireless communication device may have a transmission chain with an output stage power amplifier. The load driven by the output stage power amplifier is variable. Nevertheless, an emitter-follower amplifier may be used to drive the output stage power amplifier. To assist in maintaining stable operation for the emitter-follower driver amplifier, adaptive circuitry with tunable elements that cancel capacitive changes in the emitter-follower driver amplifier is provided. When implemented in this fashion, the footprint of the amplifier chain may be substantially reduced while still providing stable operation over the frequencies of interest.

Description

EMITTER-FOLLOWER DRIVER FOR POWER AMPLIFIERPRIORITY APPLICATION

[0001] The present application is related to U. S . Provisional Patent Application Serial No. 63 / 645,663, filed on May 10, 2024, and entitled “EMITTER-FOLLOWER DRIVER FOR POWER AMPLIFIER,” the contents of which are incorporated herein by reference in its entirety.RELATED APPLICATIONS

[0002] The present application is related to U. S . Provisional Patent Application Serial No. 63 / 641,687 filed on May 2, 2024, and entitled “POWER AMPLIFIER COMPRESSION COMPENSATION CIRCUIT,” the contents of which are incorporated herein by reference in its entirety.

[0003] The present application is related to U. S . Provisional Patent Application Serial No. 63 / 562,301 filed on March 7, 2024, and entitled “ACTIVE BALUN,” the contents of which are incorporated herein by reference in its entirety.BACKGROUNDI. Field of the Disclosure

[0003] The technology of the disclosure relates generally to power amplifiers for wireless communication devices and, more particularly, to driver amplifiers for power amplifiers.IL Background

[0004] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. To support the myriad functions, the amount of circuitry within the mobile communication device has increased. However, there is pressure to keep the general size of the mobile communication device relatively constant (if not smaller). When the sizing pressure iscombined with the need to provide additional circuitry to support the new features, the end result is an opportunity for innovation to find new ways to decrease component size.SUMMARY

[0005] Aspects disclosed in the detailed description include an emitter-follower driver amplifier for a power amplifier in a wireless communication device. In particular, a wireless communication device may have a transmission chain with an output stage power amplifier. The load driven by the output stage power amplifier is variable. Nevertheless, an emitter-follower amplifier may be used to drive the output stage power amplifier. To assist in maintaining stable operation for the emitter-follower driver amplifier, adaptive circuitry with tunable elements that cancel capacitive changes in the emitter-follower driver amplifier is provided. When implemented in this fashion, the footprint of the amplifier chain may be substantially reduced while still providing stable operation over the frequencies of interest.

[0006] In this regard, in one aspect, an amplifier chain is disclosed. The amplifier chain includes an input node and an output node configured to be coupled to an antenna for wireless transmission of an amplified signal. The amplifier chain also includes an emitter-follower (EF) driver amplifier coupled indirectly to the input node and an output amplifier coupled to the EF driver amplifier and the output node.

[0007] In another aspect, a wireless communication device is disclosed. The wireless communication device includes a baseband processor (BBP), a distribution switch, an antenna coupled to the distribution switch for wireless transmission of amplified signals, and an amplifier chain positioned between the BBP and the distribution switch. The wireless communication devices’ amplifier chain comprising an input node, an output node configured to be coupled to a distribution switch, an EF driver amplifier coupled indirectly to the input node, and an output amplifier coupled to the EF driver amplifier and the output node.

[0008] In another aspect, a method of controlling an amplifier chain is disclosed. The method includes boosting a signal with an EF driver amplifier, stabilizing the EF driver amplifier, and boosting the signal with an output amplifier coupled to the EF driver amplifier.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a conventional amplifier chain for use in a wireless communication device;

[0010] Figure 2 is a block diagram of an amplifier chain using an emitter-follower driver amplifier according to exemplary aspects of the present disclosure;

[0011] Figure 3 is a block diagram of an amplifier chain using an emitter-follower driver amplifier with a monolithic die according to exemplary aspects of the present disclosure;

[0012] Figure 4 is a block diagram of an amplifier chain highlighting the variable capacitance that occurs for an emitter- follower driver amplifier that needs to be stabilized by the adaptive circuitry of the present disclosure

[0013] Figure 5 is a block diagram showing a first stabilization technique for an emitter- follower driver amplifier using resistors;

[0014] Figure 6 is a block diagram of an amplifier chain formed from hybrid complementary metal oxide semiconductor (CMOS)-bipolar technologies with adaptive stabilization circuitry added to stabilize the emitter- follower driver amplifier;

[0015] Figure 7 is a block diagram of the amplifier chain with additional details of the adaptive circuitry of the present disclosure;

[0016] Figure 8 is a block diagram of an amplifier where many aspects of the adaptive circuitry are implemented in CMOS technology;

[0017] Figure 9 is a circuit diagram of an adaptive capacitor implemented in bipolar technology;

[0018] Figures 10A and 10B illustrate two possible differential-ended aspects of the amplifier chains using adaptive circuitry for the emitter-follower driver amplifier of the present disclosure;

[0019] Figure 11 is a block diagram of an expanded amplifier having an emitterfollower driver amplifier and adaptive technology coupled with additional improvement concepts found in related disclosures of the present inventors;

[0020] Figure 12 is a flowchart illustrating an exemplary process for controlling an amplifier chain using an emitter-follower driver amplifier according to aspects of the present disclosure; and

[0021] Figure 13 is a block diagram of a wireless communication device, which may include the amplifier chain of Figures 2-11 according to the present disclosure.DETAILED DESCRIPTION

[0022] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0023] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0024] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0025] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It willbe understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] In keeping with the above admonition about definitions, the present disclosure uses transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, refers to a circuit positioned between a baseband processor and a power amplifier circuit as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0029] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0030] Aspects disclosed in the detailed description include an emitter-follower driver amplifier for a power amplifier in a wireless communication device. In particular, a wireless communication device may have a transmission chain with an output stagepower amplifier. The load driven by the output stage power amplifier is variable. Nevertheless, an emitter-follower amplifier may be used to drive the output stage power amplifier. To assist in maintaining stable operation for the emitter-follower (EF) driver amplifier, adaptive circuitry with tunable elements that cancel capacitive changes in the emitter-follower driver amplifier is provided. When implemented in this fashion, the footprint of the amplifier chain may be substantially reduced while still providing stable operation over the frequencies of interest.

[0031] Before addressing aspects of the present disclosure, a brief overview of a conventional amplifier chain is provided with reference to Figure 1. A discussion of amplifier chains with emitter-follower driver amplifiers according to aspects of the present disclosure begins below with reference to Figure 2.

[0032] In this regard, Figure 1 illustrates a conventional amplifier chain 100. The amplifier chain 100 may include an input node 102 and an output node 104. The output node 104 is coupled to a distribution switch (DSW) 106, which in turn is coupled to an antenna 108. The DSW 106 may be implemented in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS). The input node 102 is coupled to a driver stage 110, which may include a driver amplifier 112 and a transmit controller 114. The driver amplifier 112 may be a medium to high-power driver and typically cannot be implemented in SOI-CMOS due to thermal issues. Accordingly, the driver stage 110 may be implemented in bulk CMOS.

[0033] The driver stage 110 may be coupled to an inter-stage match circuit 116. The inter-stage match circuit 116 may be coupled to an output stage 118, which has an output amplifier 120. The output stage 118 may be implemented in bipolar technology such as gallium arsenide (GaAs).

[0034] With conventional technologies, the inter-stage match circuit 116 has a fairly large number of elements and is consequently typically as large as, or in some cases, larger than the output amplifier 120. Thus, the size penalty of the inter-stage match circuit 116 is difficult to accept with emerging requirements for amplifier chain size reductions (e.g., some designers are dictating a twenty percent size reduction).

[0035] Exemplary aspects of the present disclosure contemplate adding an emitterfollower driver amplifier in the output stage. By adding this additional driver amplifier, the need to boost the signal with the first driver amplifier is lowered. The lower power requirement makes it possible to implement the first driver amplifier in SOI-CMOS,thereby allowing part of a single die that includes the first driver amplifier, the controller, and DSW. Reducing the number of dies on a front-end module containing the amplifier chain will also help lower the cost of assembly. Still further, by having a single SOI- CMOS die, a larger number of interconnect signals between the controller, the amplifier chain, and the DSW are possible to provide a more sophisticated load line tuning scheme. The size of the first driver amplifier may be an order of magnitude smaller than the prior larger bulk-CMOS driver amplifier 112. Further, the inter-stage match circuit 116 may be replaced with a pull-up inductor (or pair of pull-up inductors for differential-ended signal paths).

[0036] While much of the discussion below is focused on single-ended signal paths, it should be appreciated that the present disclosure is readily modified for use with differential signal paths, and a few examples are provided below with reference to 10A & 10B.

[0037] Cellular and other wireless standards require amplifier chains to operate over a wide power range, operate over a large frequency range, and endure large load voltage- to-standing wave ratio (VSWR) variations. In particular, in most instances, the load at the antenna is frequently not known a priori and may vary substantially. This load variation may lead to a large capacitance being present at an input of the output stage. Emitter-follower (EF) drivers have difficulty being stable in such conditions. Nevertheless, aspects of the present disclosure provide solutions to make the EF drivers stable.

[0038] In this regard, Figure 2 illustrates an amplifier chain 200 according to an aspect of the present disclosure. More specifically, the amplifier chain 200 includes an input node 202 and an output node 204. As with amplifier chain 100, the output node 204 is coupled to a DSW 206, which may be implemented in SOI-CMOS as part of a die 208. The input node 202 is coupled to a first driver amplifier 212, which may also be part of the die 208. The transmit controller 214 may also be part of the die 208. An impedance match circuit 216 couples the first driver amplifier 212 to the output stage 218.

[0039] The output stage 218 includes an EF driver amplifier 220 that couples to an output stage amplifier 222 through a small match circuit 224 that may be an analog tunable capacitor 226. Additionally, adaptive stabilization circuitry 228 is provided to stabilize the EF driver amplifier 220. The output stage 218 may be implemented in bipolar technology such as GaAs.

[0040] The adaptive stabilization circuity 228 changes with the power level in the output stage amplifier 222 and minimizes a gain loss from the stabilizing circuit, resulting in higher overall efficiency for the amplifier chain 200. Using a small power CMOSbased first driver stage 212 helps reduce the size of the match network 216. Because the EF driver amplifier 220 has a relatively large impedance, the match network 216 may be reduced to a simple pull-up inductor (compared to a multi-component inter-stage match circuit 116). This simple solution leads to significant area reduction on the laminate and also cost savings from fewer components.

[0041] Instead of implementing the first driver amplifier in SOI-CMOS, it may also be possible to implement the first driver amplifier in bipolar technology, as illustrated by amplifier chain 300 in Figure 3. The amplifier chain 300 may include an input node 302 and an output node 304. A die 308 may include the DSW 306 and the transmit controller 314. A die 318 includes a first driver amplifier 312, a matching circuit 316, and an EF driver amplifier 320 that couples to an output amplifier 322 through a small match circuit 324 that may be a tunable capacitor 326. Additionally, adaptive stabilization circuitry 328 is provided to stabilize the EF driver amplifier 320. The die 318 may be implemented in bipolar technology such as GaAs.

[0042] Before addressing details about the adaptive stabilization circuitry, a brief overview of the nature of the problem created by having a variable load is discussed. In this regard, Figure 4 illustrates an amplifier chain 400 having an input node 402 and an output node 404. The amplifier chain 400 is similar to amplifier chains 200 or 300, but some elements are omitted for simplicity, while a few elements present, but not shown in amplifier chains 200 or 300, are shown. The input node 402 is coupled to the first driver amplifier 412. The first driver amplifier 412 couples to an interstage match circuit 416. The interstage match circuit 416 is coupled to an EF driver amplifier 420, which has been stylistically replaced with an equivalent circuit. More specifically, the EF driver amplifier 420 has a first equivalent capacitor 422 and a variable negative resistor 424 in series with a variable negative capacitor 426. The values of the negative components depend on an average transconductance value of the output common-emitter, which in turn depends on the output power level at the output node 404. A resonant inductor 428 cancels an equivalent capacitance 430 of the output amplifier 432. The output amplifier 432 has a blocking capacitor 434 and a bias circuit 436, which has a ballast resistor 438.

[0043] A first technique to stabilize is the use of damping resistors , as shown in Figure 5. That is, Figure 5 illustrates an amplifier chain 500 similar to amplifier chain 400, with similar elements keeping similar reference numbers. The amplifier chain 500 includes damping resistors 502 and 504 at an input and an output of the EF driver amplifier 420, respectively. Isolating with significant sized resistors 502 and 504 helps stability but also results in significant signal loss in the signal path. Recovering the gain loss requires burning more power and thus results in a less efficient amplifier chain.

[0044] Instead of using large series resistors 502 and 504, aspects of the present disclosure may use the adaptive stabilization circuitry 228, 328. Given the equivalent circuit shown in Figure 4, it can be seen that a complementary RC circuit could be used to compensate each other and result in stabilization, as better seen in Figures 6-8.

[0045] It should be noted that the larger the capacitance presented at the output node, the more unstable the EF driver amplifier is and the harder it is to stabilize the EF driver amplifier. Aspects of the present disclosure contemplate a shunt inductor (e.g., inductor 428) that first order resonates the input capacitance of the output amplifier. In contrast with a standard class A EF driver amplifier that has current through its entire RF cycle, an EF driver amplifier of the present disclosure operates in class B. When the EF driver amplifier is cut off, and has no current through it, the impedance of the EF driver amplifier is high, and the parallel LC circuit will become poorly damped and can lead to ringing. To prevent such undesirable ringing, a small resistance can be present to isolate the inductor from the equivalent capacitance of the output amplifier (as better seen in Figure 7 discussed below).

[0046] In this regard, Figure 6 illustrates a moderately high-level view of an amplifier chain 600. The amplifier chain 600 may include an input node 602 and an output node 604. The output node 604 is coupled to a DSW 606, which may be in an SOI-CMOS (or bulk CMOS) die 608. The input node 602 is coupled to a first driver amplifier 612, which may also be part of the die 608. An inter-stage match circuit 616 is positioned between the first driver amplifier 612 and an output stage 618, which may be a bipolar technology die. The inter-stage match circuit 616 may be a pull-up inductor.

[0047] The output stage 618 may include an EF driver amplifier 620 and the output amplifier 622 coupled through a match circuit 624, which may be a tunable capacitor 626. Adaptive stabilization circuitry 628 may provide further stabilization for the EF driver amplifier 620. Providing a tunable capacitor in a bipolar die is a non-trivial task.

[0048] Aspects of the present disclosure contemplate a transmit controller 614 receiving information from a baseband processor 630, such as through a digital bus 632 (e.g., a radio frequency front end (RFFE) bus whose standard is published by MIPI). Information about the operating band or other information may be used to set a digital to analog control (DAC) voltage controller 634, which outputs a multi-state voltage signal to an analog switching control circuit 636. The analog switching control circuit 636 turns on selected capacitors in a bank to provide a desired capacitance for the tunable capacitor 626. An exemplary analog switching control circuit 636 is discussed in greater detail below with reference to Figure 9.

[0049] Figure 7 provides additional details about the adaptive stabilization circuit 628 and more details about the isolation circuit for the resonant inductance. The amplifier chain 600 includes a bias circuit 700 coupling to an input of the output amplifier 622 through a ballast resistor 702. The input of the output amplifier 622 is also coupled to a blocking capacitor 704. Note that these elements may be present in other amplifier chains (e.g., chains 200, 300 but were not shown in the relevant figures for simplicity). The output amplifier 622 has an equivalent capacitance 706 (see also the discussion of capacitance 430 above). A resonant inductance 708 is provided to first order resonate the equivalent capacitance 706 (see also the discussion of inductor 428 above). Small resistor 710 (e.g., one ohm) helps isolate the inductance 708. Another small resistor (e.g., twenty- five ohms) 712 may also be provided at an input to the EF driver amplifier 620.

[0050] The adaptive stabilization circuit 628 may be DAC-controlled variable resistor 714 and DAC-controlled variable capacitor 716, where the DACs are set by the transmit controller 614. In this aspect, the adaptive stabilization circuit 628 is digital and implemented in the SOI-CMOS die 608.

[0051] Still, other details about the amplifier chain 600 are shown in Figure 8. In particular, Figure 8 shows the BBP 800, which may include a bus interface 802, which may, for example, be an RFFE bus interface and is configured to provide information over the bus 632 to the transmission controller 614. In an exemplary aspect, the BBP 800 may provide target supply voltage (Vcc) information to the controller 614. This target supply voltage information may also be provided to a power management circuit 804. Based on the target supply voltage information, the power management circuit 804 may provide the supply voltage to the first driver amplifier 612, the inter-stage match circuit 616, and the output amplifier 622. Further, the target supply voltage information may beprovided to a controller 806 of the adaptive stabilization circuit 628. The controller may use this information to access settings in a look-up table 808 for the DACs 714, 716. Alternatively, a detector 810 may detect the supply voltage and provide this information to controller 806 for the same purpose.

[0052] Figure 9 provides a circuit diagram for an exemplary multi-stage analog switching control circuit 636. Other circuits could be used, and this is included for completeness, but in principle, a voltage signal arrives from the voltage controller 634. At low voltages, a diode 900 and the transistors 902 (Q2) and 904 (Q4) are off, and only the capacitance from capacitor 906 (C3) is provided. However, as the voltage increases, the diode 900 will turn on, providing voltage to the bases of transistors 908 (Q3), 910 (QI). Likewise, transistor 902 will turn on, activating the capacitor 912 (C2). The transistor 904 will turn as well. When the voltage is high enough transistors 908, 910 will also turn on and the capacitance from the capacitor 914 (Cl) will also activate. In this fashion, the transistors act as switches that will allow selective activation of capacitors and create a tunable capacitance in an analog circuit. While the circuit 636, illustrated in Figure 9, contemplates a three-level voltage signal, it should be appreciated that more or fewer voltage levels may be used with corresponding capacitors to provide more granular capacitive options.

[0053] As noted above, the above discussion has been presented without reference to whether elements were single-ended or differential. Appreciating that the single lines of the Figures may suggest that the elements are single-ended, the present disclosure also makes explicit that the discussions above are also applicable to differential elements. Two possible differential structures are set forth in Figures 10A & 10B, but it should be appreciated that other arrangements are possible.

[0054] In this regard, Figure 10A illustrates an amplifier chain 1000 that receives a single-ended signal at input node 1002 and outputs a single-ended signal at an output node 1004. However, a predriver stage 1006, which may be implemented in CMOS, may include a converter 1008 to convert to a differential signal, with driver amplifiers 1010A, 1010B in respective paths. An inter-stage match circuit 1012A, 1012B is present in each path. The signals then pass to a bipolar die 1014 that includes EF driver amplifiers 1016A, 1016B. An inter-stage match circuit and second harmonic rejection circuit 1018 may have separate circuits or combined circuitry but pass the differential signal to the output amplifier 1020. While shown as a monolithic amplifier, the output amplifier 1020includes two distinct transistors and provides an output differential signal that is converted to a single-ended signal by a balun 1022.

[0055] Alternatively, the conversion to a differential system may take place after the driver amplifier, as shown by amplifier chain 1050 in Figure 10B. The amplifier chain 1050 receives a single-ended signal at input node 1052 and outputs a single-ended signal at an output node 1054. However, a predriver stage 1056, which may be implemented in CMOS, may include a driver amplifier 1058 and a converter 1060 to convert to a differential signal. An inter-stage match circuit 1062A, 1062B is present in each path. The signals then pass to a bipolar die 1064 that includes EF driver amplifiers 1066A, 1066B. An inter-stage match circuit and second harmonic rejection circuit 1068 may have separate circuits or combined circuitry but pass the differential signal to the output amplifier 1070. While shown as a monolithic amplifier, the output amplifier 1070 includes two distinct transistors and provides an output differential signal that is converted to a single-ended signal by a balun 1072.

[0056] Differential amplifier output stages may be advantageous due to their better harmonic performance and potential to drive a higher output power from a set supply voltage. The conversion, particularly when implemented as a balun, for single-ended to differential may be challenging. Such conversion may be more advantageously done early in the amplifier chain when the signal has lower power levels. This early placement may necessitate changes to the EF driver amplifier. That is, better performance may result from the use of a pseudo-differential EF driver. A common-mode rejection may be improved using coupled differential load inductance. This asymmetry may cause a second harmonic to exceed design tolerances. This second harmonic may be removed by the circuits 1018, 1068 introduced above.

[0057] Figure 11 illustrates an amplifier chain 1100 that includes teachings from a number of disclosures that result in substantial size savings and better efficiency. In this regard, the amplifier chain 1100 has an input node 1102 that receives a signal to be amplified. The input node 1102 may be coupled to an active balun 1104 such as that taught by U.S. Provisional Patent Application serial number 63 / 562,301, filed March 7, 2024, entitled ACTIVE BALUN, the contents of which are incorporated herein by reference in their entirety (2867-3408PF). While the remaining portions of the amplifier chain 1100 are shown as single-ended, it should be appreciated that the elements are, in fact, in this aspect, differential.

[0058] The active balun 1104 is coupled to a blocking capacitor 1106. A bias circuit 1108 is coupled to the signal line at node 1110 through a ballast resistor 1112. A phase distortion correction circuit 1114 couples to the node 1110 as well to correct downstream phase distortion. A driver amplifier 1116 also couples to the node 1110 and receives the biased, phase distortion-corrected signal. Cascoded transistors 1118(1)-1118(G) are stacked above a transconductance transistor 1120. An output node 1122 has a supply voltage (Vcc) supplied from a power management circuit (not shown) through an inductor 1124. The driver amplifier 1116 has an automatic gain control function implemented through a degenerative resistive transistor 1126 that is controlled by an amplitude modulation-amplitude modulation (AM- AM) slope control circuit 1128. Similarly, the phase distortion correction circuit 1114 is controlled by an AM-phase modulation (AM- PM) slope control circuit 1130.

[0059] The output node 1122 couples to an adaptive stabilization circuit 1132, which may be the RDACs 714 and CDACs 716 of Figure 7. The adaptive stabilization circuit 1132 couples to the EF driver amplifier 1134. An inter-stage match circuit 1136 may include the tunable capacitor 1138 (e.g., circuit 636) with a small bias inductor 1140. An output amplifier 1142 is coupled to the EF driver amplifier 1134 through a blocking capacitor 1144. An output of the driver amplifier 1142 couples to an output node 1146. Compression or saturation detectors 1148, 1150 also measure the voltage at the output node 1146 and provide information that is used by circuits 1128, 1130 respectively. More information about the compression detectors and the gain control / phase adjustments that they make can be found in U.S. Provisional Patent Application serial number 63 / 641,687, entitled Power Amplifier Compression Compensation Circuit, filed May 2, 2024, which is herein incorporated by reference in its entirety.

[0060] A process 1200 for using the amplifier chain of the present disclosure is provided with reference to Figure 12. A signal to be amplified is provided to an amplifier chain and the amplifier chain uses a driver amplifier to boost the signal (block 1202). Optionally, the signal may be turned from a single ended signal to a differential signal. The boosted signal is passed to a bipolar die and an EF driver amplifier is used to boost the signal (block 1204). The EF driver amplifier is stabilized (block 1206) and an output amplifier is used to generate a desired output signal (block 1208).

[0061] The EF driver for power amplifier in an amplifier chain according to aspects disclosed herein, may be provided in or integrated into any processor-based device.Examples, without limitation, include a set- top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0062] Figure 13 is a schematic diagram of an exemplary communication device 1300 wherein the amplifier chains having EF driver amplifiers can be provided. Herein, the communication device 1300 can be any type of communication devices wired or wireless, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra- wideband (UWB), and near field communications.

[0063] More particularly, the communication device 1300 will generally include a control system 1302, a baseband processor 1304, transmit circuitry 1306, receive circuitry 1308, antenna switching circuitry 1310, multiple antennas 1312, and user interface circuitry 1314. In a non-limiting example, the control system 1302 can be a field- programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1302 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1308 receives radio frequency signals via the antennas 1312 and through the antenna switching circuitry 1310 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 1308 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0064] The baseband processor 1304 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typicallycomprises demodulation, decoding, and error correction operations. The baseband processor 1304 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0065] For transmission, the baseband processor 1304 receives digitized data, which may represent voice, data, or control information, from the control system 1302, which it encodes for transmission. The encoded data is output to the transmit circuitry 1306, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier in an amplifier chain with an EF driver amplifier according to the present disclosure will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1312 through the antenna switching circuitry 1310. The multiple antennas 1312 and the replicated transmit and receive circuitries 1306, 1308 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0066] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0067] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited tothe examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMS received by the International Bureau on 30 July 2025What is claimed is:

1. (Previously Presented) An amplifier chain comprising: an input node; an output node configured to be coupled to an antenna for wireless transmission of an amplified signal; an emitter-follower (EF) driver amplifier coupled indirectly to the input node; a stabilization circuit comprising either:1 ) a first damping resistor serially positioned between the EF driver amplifier and the input; and a second damping resistor serially positioned between the EF driver amplifier and an output amplifier; or2) an adaptive circuit comprising a variable resistor serially positioned with a variable capacitor, the adaptive circuit degeneratively coupled between an input of the EF driver amplifier and ground; and an output amplifier coupled to the EF driver amplifier and the output node.

2. (Original) The amplifier chain of claim 1, further comprising an inter-stage match circuit positioned between the EF driver amplifier and the output amplifier.

3. (Original) The amplifier chain of claim 2, wherein the inter-stage match circuit comprises a variable capacitor.

4. (Original) The amplifier chain of claim 3, wherein the variable capacitor comprises an analog circuit.

5. Canceled.

6. (Original) The amplifier chain of claim 1, further comprising a driver amplifier serially positioned between the input node and the EF driver amplifier.

7. (Original) The amplifier chain of claim 6, wherein the driver amplifier is implemented on a complementary metal oxide semiconductor (CMOS) die.

8. (Original) The amplifier chain of claim 7, wherein the EF driver amplifier and the output amplifier are implemented on a bipolar technology die.

9. (Original) The amplifier chain of claim 6, wherein the driver amplifier is implemented on a bipolar technology die.

10. (Previously Presented) The amplifier chain of claim 7, wherein the adaptive stabilization circuit is implemented in the CMOS die.

11. (Original) The amplifier chain of claim 1 , further comprising a distribution switch coupled to the output node.

12. (Previously Presented) A wireless communication device comprising: a baseband processor (BBP); a distribution switch; an antenna coupled to the distribution switch for wireless transmission of amplified signals; and an amplifier chain positioned between the BBP and the distribution switch, the amplifier chain comprising the amplifier chain of claim 1.

13. (Original) The wireless communication device of claim 12, further comprising a driver amplifier positioned between the input node and the EF driver amplifier.

14. (Original) The wireless communication device of claim 13, wherein the distribution switch and the driver amplifier are implemented on a silicon-on-insulator (SOI) die.

15. (Original) The wireless communication device of claim 14, wherein the EF driver amplifier and the output amplifier are implemented on a bipolar technology die.

16. (Previously Presented) A method of controlling an amplifier chain, comprising: boosting a signal with an emitter-follower (EF) driver amplifier; stabilizing the EF driver amplifier using a stabilization circuit, the stabilization circuit comprising either:1 ) a first damping resistor serially positioned between the EF driver amplifier and the input; and a second damping resistor serially positioned between the EF driver amplifier and an output amplifier; or2) a variable resistor serially positioned with a variable capacitor coupled between an input of the EF driver amplifier and ground; and boosting the signal with the output amplifier.

17. (Original) The method of claim 16, further comprising initially boosting the signal with a driver amplifier.

18. Canceled.

19. (Original) The method of claim 16, further comprising using a variable capacitor to provide an interstage match.

20. (Original) The method of claim 16, wherein the output amplifier comprises a gallium arsenide (GaAs) bipolar junction transistor.Dear Sir or Madam,STATEMENT UNDER ARTICLE 19(1)Claims 1, 10, 12, and 16 are amendedClaims 5 and 18 are canceled.Claims 1 and 16 are amended to include details of the stabilization circuit. Support for this can be found in Figures 5 and 6 and supporting paragraphs 0043-44, 0047, & 0050.Claim 10 is amended to conform to the amendments to claim 1.Claim 12 is amended to depend from claim 1.The remaining claims are unchanged.If you have any questions, please do not hesitate to contact me.Very truly yours, / Taylor M. Davenport Reg. No. 42466 / Taylor M. Davenport

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