Micro-display device and manufacturing method therefor

Abstract

The present invention relates to the technical field of semiconductors. Disclosed are a micro-display device and a manufacturing method therefor. The micro-display device comprises: a driving wafer, the driving wafer comprising anode contacts; and a display module integrated with the driving wafer by means of a bonding metal layer, wherein the display module comprises pixel units corresponding to the anode contacts and metal fences surrounding the pixel units, and each metal fence is of a fence style structure generated in the process of etching the bonding metal layer by means of an ion beam. Each metal fence forms a cylindrical optical resonant cavity for the corresponding pixel unit, and the optical resonant cavity is used for allowing a light wave emitted by the corresponding pixel unit to be reflected back and forth in the optical resonant cavity so as to provide optical positive feedback. The structure shown in the present invention eliminates the metal fence elimination process, greatly simplifying the process.

Description

Micro display device and manufacturing method thereof

[0001] The present application claims priority to the Chinese Patent Application No. 2024106016312, entitled "Micro display device with metal fence and manufacturing method thereof", filed on May 15, 2024, and the Chinese Patent Application No. 2024106016539, entitled "Micro display device with resonant cavity combination structure and manufacturing method thereof", filed on May 15, 2024, and the Chinese Patent Application No. 2024106016276, entitled "Anti-crosstalk full-color micro display device and manufacturing method thereof", filed on May 15, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor technology, and in particular to a micro display device and a manufacturing method thereof. BACKGROUND

[0003] In the field of monolithic integrated micro display devices (Micro-LED), non-alignment wafer bonding processes are increasingly widely used. In the conventional chip preparation process, after completing the thermal pressure bonding of the compound semiconductor and the driving wafer, the metal of the bonding layer needs to be completely etched clean through etching process, so as to form electrical isolation between pixels.

[0004] Since the metal used for thermal pressure bonding is usually a "non-volatile metal", its etching usually adopts ion beam etching (IBE) etching technology. In the IBE etching process, the etching system ionizes inert gas and forms a neutral ion beam through multiple systems such as ion optical systems, which bombards the metal surface, thereby sputtering the atoms on the metal surface, to complete the etching process, which is a pure physical bombardment process. Since the etched metal is a "non-volatile metal", as shown in FIG. 1, metal atoms are easily re-sputtered and deposited on the sidewall of the photoresist mask to form a metal fence. The metal fence formed in the IBE etching process cannot be well treated and eliminated after etching and glue removal, and the fence will cause short circuit between the P and N poles of the device in the subsequent interconnection process, resulting in leakage, thereby greatly reducing the photoelectric performance of the device, and even causing device failure in severe cases.

[0005] Therefore, fence elimination means is generally adopted, but various fence elimination means not only have complex and tedious process, but also cannot completely eliminate the metal fence, thereby affecting the performance of the device. SUMMARY

[0006] The micro display device and the manufacturing method thereof make full use of the metal fence generated in the IBE metal etching process to improve the display performance of the micro display device.

[0007] To achieve the above-mentioned purposes, the present application provides the following technical solutions.

[0008] In one aspect, the present application provides a micro display device, which comprises:

[0009] a driving wafer comprising an anode contact; a display module integrated with the driving wafer through a bonding metal layer, the display module comprising a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, the metal fence being a fence-shaped structure generated in the process of ion beam etching the bonding metal layer;

[0010] The metal fence forms a columnar optical resonant cavity for the pixel unit, and the optical resonant cavity is used for reflecting the light waves emitted by the pixel unit back and forth to provide optical positive feedback.

[0011] In another aspect, the present application provides a manufacturing method of a micro display device, which is used for manufacturing the micro display device as described in the above aspect, and the method comprises:

[0012] preparing a driving wafer comprising an anode contact;

[0013] manufacturing a display module integrated with the driving wafer through a bonding metal layer, the display module comprising a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, the metal fence being a fence-shaped structure generated in the process of ion beam etching the bonding metal layer;

[0014] The metal fence forms a columnar optical resonant cavity for the pixel unit, and the optical resonant cavity is used for reflecting the light waves emitted by the pixel unit back and forth to provide optical positive feedback.

[0015] Compared with the prior art, the present application has the following beneficial effects:

[0016] The driving wafer and the display module in the micro display device are bonded and integrated through the bonding metal layer, and the metal fence is inevitably formed in the process of etching the bonding metal layer due to the physical characteristics. The metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display module, without performing fence removal processing technology, which simplifies the overall process flow, greatly improves the process stability, production efficiency and production capacity, and at the same time, the formation of the optical resonant cavity can also improve the brightness of the micro display device.

[0017] Further, the side wall of the metal fence is in contact with the side wall of the bonding metal layer and the P-type ohmic contact layer in the pixel unit, and is spaced apart from the side wall of the compound semiconductor layer and the N-type ohmic contact layer, and the space between the metal fence and the pixel unit is filled with the first insulating layer, so as to avoid the short circuit of the P pole and the N pole of each pixel unit, thereby realizing the minimization of the pixel spacing, the maximization of the pixel light-emitting area, the improvement of the pixel density, and the improvement of the resolution of the micro display device. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a schematic diagram of a metal fence formed in a process of ion beam etching a bonding metal according to the related art;

[0019] FIG. 2 is a structural schematic diagram of a micro display device with a large pixel spacing according to the related art;

[0020] FIG. 3 is a structural schematic diagram of a micro display device according to an embodiment of the present application;

[0021] FIG. 4 is a structural schematic diagram of another micro display device according to an embodiment of the present application;

[0022] FIG. 5 is a structural schematic diagram of another micro display device according to an embodiment of the present application;

[0023] FIG. 6 is a structural schematic diagram of a micro display device with a second cathode connection structure according to an embodiment of the present application;

[0024] FIG. 7 is a structural schematic diagram of a micro display device with a second cathode connection structure according to an embodiment of the present application;

[0025] FIG. 8 is a structural schematic diagram of a micro display device with a microlens structure according to an embodiment of the present application;

[0026] FIG. 9 is a structural schematic diagram of a micro display device with a microlens structure according to an embodiment of the present application;

[0027] FIG. 10 is a method flow chart of a preparation method of a micro display device according to an embodiment of the present application;

[0028] FIG. 11 is a structural schematic diagram of a compound wafer and a driving wafer integrated after bonding according to an embodiment of the present application;

[0029] FIG. 12 is a structural schematic diagram of a compound wafer after preparation of a P-type ohmic contact layer and a bonding metal layer according to an embodiment of the present application;

[0030] FIG. 13 is a structural schematic diagram of a driving wafer after preparation of a bonding metal layer according to an embodiment of the present application;

[0031] FIG. 14 is a structure schematic diagram of a compound wafer and a driving wafer integrated after bonding according to an embodiment of the present application;

[0032] FIG. 15 is a structure schematic diagram of a display area continuous film layer according to an embodiment of the present application;

[0033] FIG. 16 is a structure schematic diagram of a micro display device after pixelization of a compound wafer according to an embodiment of the present application;

[0034] FIG. 17 is a structure schematic diagram of a preparation process of a metal fence according to an embodiment of the present application;

[0035] FIG. 18 is a structure schematic diagram of another preparation process of a metal fence according to an embodiment of the present application;

[0036] FIG. 19 is a structure schematic diagram of another preparation process of a metal fence according to an embodiment of the present application;

[0037] FIG. 20 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0038] FIG. 21 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0039] FIG. 22 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0040] FIG. 23 is a schematic diagram of a projection of a metal fence and a projection of an upper resonant cavity according to an embodiment of the present application;

[0041] FIG. 24 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0042] FIG. 25 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0043] FIG. 26 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0044] FIG. 27 is a structure schematic diagram of another micro display device according to an embodiment of the present application;

[0045] FIG. 28 is a structure schematic diagram of a connected common cathode according to an embodiment of the present application;

[0046] FIG. 29 is a structure schematic diagram of a disconnected common cathode according to an embodiment of the present application;

[0047] FIG. 30 is a structure schematic diagram of a micro display device after preparation of an upper optical cavity according to an embodiment of the present application;

[0048] Fig. 31 is a size diagram of a micro display device provided in an embodiment of the present application.

[0049] Fig. 31 is a size diagram of a micro display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0051] In the description of the present application, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0052] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the communication between the two elements inside. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0053] In the field of monolithic integrated micro-display devices (Micro-LED), non-alignment wafer bonding process has been increasingly widely used, and the conventional chip preparation process flow can be summarized as the following main steps: (1) depositing bonding metal on the surface of compound (such as GaN, etc.) wafer and driving wafer → (2) hot-press bonding the compound wafer and the CMOS driving wafer → (3) device preparation through semiconductor processes such as photolithography and etching → (4) electrical interconnection of the device and the driving wafer through semiconductor interconnection process.

[0054] For example, first, the bonding metal is deposited on the silicon-based GaN wafer or sapphire-based GaN wafer and the driving wafer by electron beam evaporation, then the GaN wafer (silicon-based or sapphire-based) and the driving wafer are integrated together by hot-press bonding, then the GaN substrate is removed by wet etching or by laser ablation, then the GaN is etched into independent pixels by photolithography and etching process, and the bonding metal is completely etched clean by etching process, so that the pixels are electrically isolated, and finally the N pole of GaN is interconnected by a transparent conductive electrode.

[0055] In the above process, an important step is "the bonding metal is completely etched clean by etching process, so that the pixels are electrically isolated". In the IBE etching process corresponding to etching, metal atoms are easy to form re-sputtering and deposit on the sidewall of the photoresist mask, forming a metal fence as shown in FIG. 1.

[0056] Since the 1970s, the metal fence formed by IBE etching metal has been a very disturbing defect in the field of semiconductor chip manufacturing, although the industry, academia and research have long been committed to seeking ways to eliminate the fence, and have not made a good breakthrough due to its physical properties. Commonly used methods to eliminate the fence include: (1) photoresist topography adjustment: the main principle is to adjust the topography of the photoresist to make it semi-spherical, so that the fence sputtered on the sidewall of the photoresist is etched away during etching; (2) IBE ion beam incident angle adjustment: the main principle is to adjust the IBE ion beam incident angle, so that the fence sputtered on the sidewall of the photoresist is etched away during etching; (3) physical treatment elimination: the main principle is to repeatedly heat / cool the photoresist, so that the fence is physically disconnected by thermal expansion and contraction, and the fence is cleaned in the subsequent photoresist removal process.

[0057] The various fence elimination methods described above not only have complex and tedious process, but also cannot completely eliminate the fence. Therefore, in the field of manufacturing micro-LED single chip integrated micro display devices, in addition to the above fence elimination methods, the distance between pixels needs to be increased, thereby reducing the risk of short circuit caused by metal fence (as shown in FIG. 2). The consequences of increasing the pixel pitch include: (1) reduction of pixel light emitting area, thereby affecting the brightness performance of the device; (2) reduction of pixel density, thereby affecting the resolution of the micro display device.

[0058] In order to avoid the above problems, in the embodiments of the present application, a technical solution is proposed for retaining the metal fence generated in the IBE metal etching process and fully utilizing the metal fence. The structure cancels the elimination process of the metal fence, greatly simplifying the process.

[0059] Embodiment 1

[0060] First, the specific structure of the micro display device proposed in the present application is described.

[0061] The present application provides a micro display device, as shown in FIGS. 3 to 5, which comprises:

[0062] The driving wafer 100 comprises an anode contact; the display module 200 integrated with the driving wafer 100 through the bonding metal layer 11, the display module 200 comprises the pixel unit 10 corresponding to the anode contact, and the metal fence 20 surrounding the pixel unit 10, the metal fence 20 is a fence pattern structure generated in the process of ion beam etching the bonding metal layer.

[0063] The metal fence 20 forms a columnar optical resonant cavity for the pixel unit 10, and the optical resonant cavity is used for reflecting the light wave emitted by the pixel unit 10 back and forth to provide optical positive feedback and confine the light energy corresponding to the light wave in the optical resonant cavity.

[0064] It can be understood that the driving wafer 100 and the pixel unit 10 can have a one-to-one relationship or a one-to-many relationship, that is, the driving wafer 100 can only include one anode contact, and correspondingly, one pixel unit 10 electrically connected to the anode contact is provided, or the driving wafer 100 can include a plurality of anode contacts, and correspondingly, a plurality of pixel units 10 respectively electrically connected to the anode contacts are provided. In addition, the corresponding relationship between the anode contact and the pixel unit 10 can be one-to-one or a plurality of anode contacts corresponding to one pixel unit 10.

[0065] The driving wafer 100 can be an active design of one or more of thin-film transistor (TFT), low-temperature polysilicon (LTPS), CMOS integrated circuit, high electron mobility transistor (HEMT), etc. Specifically, the driving wafer 100 is provided with a driving circuit, the driving circuit is provided with at least one anode contact, and the driving circuit can include an active, passive or semi-passive control circuit. All anode contacts included in the driving circuit can be linearly arranged or arrayed, and any anode contact can be located at the middle or edge of the driving wafer 100, which is not limited in the embodiment.

[0066] The pixel unit 10 in the display module 200 is usually a compound wafer or a region of appropriate size cut from the compound wafer. Taking the compound wafer as an example, the wafer refers to a compound formed by two or more elements, including crystalline inorganic compounds (such as III-V group, II-VI group compound semiconductors) and oxide semiconductors, etc. The compound wafer involved in the embodiment of the application is mainly an LED epitaxial material, such as an InGaN ternary material system or an AlGaInP quaternary material system, etc., which can cover the full wavelength band from ultraviolet, visible light and infrared, and the substrate material can be GaN, Si, SiC, sapphire, etc.

[0067] It can be understood that FIGS. 3 to 5 only exemplarily illustrate that one metal fence 20 surrounds one pixel unit 10, and one metal fence 20 can also surround multiple pixel units 10, which is not limited in the embodiment. For example, in a parent pixel stacked with multiple layers, one metal fence 20 is used to surround the sub-pixels in the same layer in the parent pixel.

[0068] Taking the field of Micro-LED as an example, the materials of some compound wafers involved in the application are shown in the following table, and in some actual applications, the film layers of the compound wafer can be more complex, or there is cross use of materials. Typically, it mainly includes a P-type ohmic contact layer, an N-type ohmic contact layer, and a multiple quantum well (MQW) and other functional layers sandwiched between the two, and the functional layer between the P-type ohmic contact layer and the N-type ohmic contact layer is recorded as a compound semiconductor layer in the application:

[0069] The driving wafer 100 and the display module 200 are bonded by the bonding metal layer 11. The bonding metal layer 11 can be a combination of multiple metal materials, such as Ni and Sn, Au and Sn, Cu and Sn, Au and In, Au and Au, Al and Al, Cu and Cu, ITO and ITO, or the like. In addition, the bonding metal layer 11 and the driving wafer 100 / display module 200 can further include an adhesion layer and a barrier depletion layer to form a bonding structure. The adhesion layer can be made of Cr, Ti, Ni, or the like to increase the adhesion between the upper and lower layers. The barrier depletion layer can be made of Ni, Pt, Cu, or the like to prevent the migration of metal. In addition, the bonding structure on the driving wafer 100 and the display module 200 can be symmetrical or asymmetrical. If necessary, a reflective layer such as Al, Ag, Au, or the like can be introduced into the bonding structure.

[0070] For example, AuSn bonding is used, the bonding structure on the surface of the display module 200 is Ni (10A, adhesion layer) / AlCu (80nm, reflective layer) / NiV (10nm, barrier layer) / Au (100nm) / Sn (150nm) / Au (50nm), and the bonding structure on the surface of the driving wafer 100 is Cr (10nm, adhesion layer) / Pt (50nm, barrier depletion layer) / Au (100nm) / Sn (150nm) / Au (50nm).

[0071] For example, CuCu bonding is used, the bonding structure on the surface of the display module 200 is Ni (10A, adhesion layer) / AlCu (80nm, reflective layer) / NiV (10nm, barrier layer) / Cu (300nm, bonding layer), and the bonding structure on the surface of the driving wafer 100 is Ti (20nm, adhesion layer) / Cu (300nm, bonding layer).

[0072] The display module 200 is provided with a metal fence 20 surrounding the pixel unit 10. The metal fence 20 is a fence-shaped structure generated in the process of IBE isolation of the bonding metal layer 11. Specifically, after the display module 200 and the driving wafer 100 are integrated by the bonding metal layer 11 and the pixelization of the pixel unit 10 is completed, the bonding metal layer 11 is patterned by IBE etching. The metal atoms corresponding to the bonding metal layer 11 are deposited by re-sputtering to form the metal fence 20 surrounding the pixel unit 10.

[0073] In the present application, the metal fence 20 is fully utilized to form a columnar optical resonant cavity for the pixel unit 10, which is a cavity in which light waves can be reflected back and forth to provide optical positive feedback, usually composed of two or more optical mirrors (implemented by the metal fence 20 in the present application), and is widely used in the field of laser and other optical fields due to its effects of enhancing and regulating light energy. In the present application, the light waves emitted by the pixel unit 10 circulate around the optical resonant cavity, and the head and tail are connected to form constructive interference, and the light energy is completely confined in the resonant cavity, thereby improving the energy density per unit volume of the resonant cavity, and greatly improving the light-emitting efficiency of the micro display device, and the structure completely eliminates the need for fence processing. It can be understood that the present application does not limit the specific style of the optical resonant cavity formed by the metal fence 20, which can be a rectangular column style or a cylindrical style.

[0074] In one possible implementation, as shown in FIGS. 3-5, the pixel unit 10 at least includes, in sequence and vertically stacked in a direction away from the driving wafer 100: a bonding metal layer 11, a P-type ohmic contact layer 12, a compound semiconductor layer 13, and an N-type ohmic contact layer 14; the bottom of the metal fence 20 is connected to the side of the driving wafer 100 close to the display module 200; the sidewall of the metal fence 20 is in contact with the sidewall of the bonding metal layer 11 and the P-type ohmic contact layer 12, and is spaced apart from the sidewall of the compound semiconductor layer 13 and the N-type ohmic contact layer 14.

[0075] As shown in FIGS. 3-5, the corresponding surface size of the bonding metal layer 11 and the P-type ohmic contact layer 12 is greater than the corresponding surface size of the compound semiconductor layer 13 and the N-type ohmic contact layer 14, and the outer contour of the projection of the compound semiconductor layer 13 and the N-type ohmic contact layer 14 on the driving wafer 100 is within the outer contour of the projection of the bonding metal layer 11 and the P-type ohmic contact layer 12 on the driving wafer 100. Therefore, the sidewall of the bottom of the metal fence 20 extending in the vertical direction can be in contact with the sidewall of the bonding metal layer 11 and the P-type ohmic contact layer 12, and the sidewall of the top of the metal fence 20 can be spaced apart from the sidewall of the compound semiconductor layer 13 and the N-type ohmic contact layer 14, thereby avoiding the situation that the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 are connected by the metal fence 20 to form a short circuit and cause a leakage.

[0076] It can be understood that, since the metal fence 20 is formed by the way of back sputtering and deposition of metal atoms in the IBE etching process, in practice, the thickness of the metal fence 20 can vary in the vertical direction, specifically, the thickness gradually thins from the bottom to the top.

[0077] Further, the top of the metal fence 20 is not lower than the top of the compound semiconductor layer 13. Since the light emission of the pixel unit 10 is emitted through the compound semiconductor layer 13, under the arrangement that the top of the metal fence 20 is not lower than the top of the compound semiconductor layer 13, the metal fence 20 can effectively reflect the light emission of the pixel unit 10, and further enhance and regulate the light energy.

[0078] In a possible implementation, the display module 200 further includes: a first insulating layer 30, the first insulating layer 30 is filled in the blank space of the display module 200, and is filled around the pixel unit 10; and a common cathode, the common cathode includes: a first cathode connecting structure 41, the first cathode connecting structure 41 is arranged on the side surface of the insulating layer 30 away from the driving wafer 100, and is connected with the N-type ohmic contact layer 14.

[0079] As shown in FIGS. 3-5, the first insulating layer 30 is filled in the display module 200, the optical resonant cavity formed by the metal fence 20 is fixed, the metal fence 20 at the top is insulated and isolated from the pixel unit 10, and the short circuit between the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 through the metal fence 20 is avoided, and the leakage is avoided. The first insulating layer 30 is mainly silicon oxide, and optionally includes silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, and combinations of the above, which are not limited in the present application.

[0080] As shown in FIGS. 3-5, the N-type ohmic contact layer 14 is exposed at the top of the pixel unit 10, and the first cathode connecting structure 41 connected with the exposed N-type ohmic contact layer 14 is prepared as a common cathode on the side surface of the insulating layer 30 away from the driving wafer 100. The common cathode can be a transparent conductive film, which avoids the common cathode from blocking the light emission of the pixel unit 10, and improves the brightness of the pixel unit 10. The film layer of the transparent conductive film can be one or a combination of ITO (Indium Tin Oxide) film, AZO (Antimony doped Zinc Oxide) film, ATO (Antimony doped Tin Oxide) film, and FTO (Fluorine doped Tin Oxide) film. Further, the ITO surface can be coated with thin Al, Au, and Ag, and then annealed to form a metal-doped ITO, so as to enhance the current transmission capacity of the common cathode.

[0081] Further, the first cathode connection structure 41 can be implemented as follows: as shown in FIG. 3, the first insulating layer 30 includes a portion whose top is flush with the top of the N-type ohmic contact layer 14, and the first cathode connection structure 41 covers the outer surface of this portion and the top of the N-type ohmic contact layer 14. The first cathode connection structure 41 can also be implemented as follows: as shown in FIG. 4, the first insulating layer 30 includes a portion whose top is higher than the top of the N-type ohmic contact layer 14, and the first cathode connection structure 41 covers the outer surface of this portion and the top of the N-type ohmic contact layer 14. The first cathode connection structure 41 can also be implemented as follows: as shown in FIG. 5, the first insulating layer 30 includes a portion that is attached to the sidewall of the pixel unit 10, and the first cathode connection structure 41 covers the outer surface of this portion and the top of the N-type ohmic contact layer 14.

[0082] Further, as shown in FIG. 6 and FIG. 7, the common cathode further includes a second cathode connection structure 42, which is embedded in the first insulating layer 30 between two adjacent pixel units 10, and one end of the second cathode connection structure 42 away from the driving wafer 100 is connected to the first cathode connection structure 41.

[0083] In the insulating layer 30 between two adjacent pixel units 10, the second cathode connection structure 42 connected to the first cathode connection structure 41 is also prepared. Specifically, the top of the second cathode connection structure 42 is connected to the first cathode connection structure 41 and extends in the direction toward the driving wafer 100, thereby having a certain depth. The second cathode connection structure 42 can be used for common cathode current expansion enhancement. For example, FIG. 6 shows a schematic diagram of adding the second cathode connection structure 42 to the structure corresponding to FIG. 3, and FIG. 7 shows a schematic diagram of adding the second cathode connection structure 42 to the structure corresponding to FIG. 4. The specific depth of the second cathode connection structure 42 is not limited in the present application. The depth of the second cathode connection structure 42 can be flush with the bottom of the N-type ohmic contact layer 14 of the pixel unit 10, or can have a greater depth than the bottom of the N-type ohmic contact layer 14 of the pixel unit 10.

[0084] In a possible implementation, as shown in FIG. 8 and FIG. 9, the first cathode connection structure 41 is provided with a microlens structure 50 away from the side surface of the driving wafer 100, and the projection of the metal fence 20 on the driving wafer 100 is within the projection of the microlens structure 50 on the driving wafer 100. The top of the display module 200 can be provided with the microlens structure 50, which can further improve the brightness of the light emitted by the pixel unit 10. The material of the microlens structure 50 can be a compound semiconductor, or a deposited dielectric material such as silicon oxide and silicon nitride.

[0085] For example, as shown in FIG. 31, the size data of the micro display device described in the above embodiment is exemplified, the width of the insulating layer between the metal fence 20 and the sidewall of the pixel unit 10 is denoted as D1, the width of the metal fence 20 is denoted as d, the height is denoted as h, the width of the pixel unit 10 is denoted as D2, the height is denoted as H, and the spacing between the outer portions of two adjacent metal fences 20 is denoted as D3, which can have the following size data: 50nm≤D1≤D2 / 2; 110nm≤D2≤1000um; 28nm≤d≤1um; 50nm≤h≤H; 180nm≤H≤5um; 90nm≤D3≤D2 / 2.

[0086] In summary, the micro display device provided by the embodiment of the present application, the driving wafer and the display module in the micro display device are integrated by bonding the metal layer, and the metal fence is inevitably formed in the process of bonding the metal layer by ion beam etching due to physical characteristics. The metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display module, and the fence removal process is not required, which simplifies the overall process flow, greatly improves the process stability, production efficiency and capacity, and meanwhile, the formation of the optical resonant cavity can also improve the brightness of the micro display device.

[0087] Further, the sidewall of the metal fence is in contact with the sidewall of the bonding metal layer and the P-type ohmic contact layer in the pixel unit, is spaced apart from the sidewall of the compound semiconductor layer and the N-type ohmic contact layer, and the metal fence and the pixel unit are filled with the first insulating layer in the spacing therebetween, so as to avoid the short circuit of the P pole and the N pole of each pixel unit, thereby minimizing the pixel spacing, maximizing the pixel light-emitting area, improving the pixel density, and improving the resolution of the micro display device.

[0088] Next, the preparation method of the micro display device described in the above embodiment is described. As shown in FIG. 10, the method can include the following steps:

[0089] S1: preparing a driving wafer, the driving wafer including an anode contact in the vertical direction.

[0090] Specifically, the driving wafer includes an anode contact in the vertical direction, and an insulating medium is arranged around the anode contact.

[0091] S2: preparing a display module, the display module being integrated with the driving wafer through a bonding metal layer, the display module including a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, the metal fence being a fence style structure generated in the process of ion beam etching the bonding metal layer.

[0092] The metal fence forms a columnar optical resonant cavity for the pixel unit, and the optical resonant cavity is used to form constructive interference of the light waves emitted by the pixel unit and to confine the light energy corresponding to the light waves in the optical resonant cavity.

[0093] S2: Bonding the compound wafer and the driving wafer through the bonding metal layer.

[0094] S21: Bonding the compound wafer and the driving wafer through the bonding metal layer.

[0095] Specifically, since the compound wafer and the driving wafer are both deposited with the bonding metal, the two wafers are integrated through wafer-level thermal compression bonding by using the bonding metal on the surfaces of the two wafers to form a bonding metal layer, to form a structure as shown in FIG. 11, in which the bonding metal layer is continuously and evenly distributed on the wafer.

[0096] In a possible implementation, step S21 specifically includes the following steps.

[0097] (1) Preparing a P-type ohmic contact layer on the P surface of the compound wafer

[0098] Specifically, as shown in part (a) of FIG. 12, a P-type ohmic contact layer 12 is prepared on the P surface of the compound wafer 300, and the P-type contact material can be ITO, ZnO, or other transparent conductive material, or a metal material with a work function greater than that of the P-type semiconductor, such as Ni.

[0099] In an embodiment, a Si-based blue InGaN compound is selected as the compound wafer, ITO is plated on the P surface of the compound wafer by evaporation, sputtering, or other methods, the ITO film has a thickness of 70 nm, and ohmic contact is formed by high-temperature annealing at 550°C in a N2 environment. The thickness of the P-type ohmic contact layer on the surface of the compound wafer and the conditions for forming the contact can be adjusted and changed as needed.

[0100] (2) Preparing a bonding metal layer on the surface of the P-type ohmic contact layer of the compound wafer and the surface of the driving wafer, at least one of the two bonding metal layers is continuous in the pixel area and is supported by an insulating medium in the non-pixel area.

[0101] Specifically, as shown in part (b) of FIG. 12, the bonding metal is deposited on the P-type ohmic contact layer 12 by plasma vapor deposition, evaporation, sputtering, atomic layer deposition (ALD), or other general semiconductor thin film growth methods to form a bonding metal layer 11. Correspondingly, as shown in FIG. 13, the bonding metal is also deposited on the surface of the driving wafer 100 to form another bonding metal layer 11.

[0102] The bonding metal layer can be continuous only in the pixel region, which is the region for pixel unit preparation, but discontinuous in the non-pixel region, which is filled with insulating medium for support, as shown in FIG. 14. The bonding metal layer on the surface of the compound wafer 300 is continuous only in the pixel region, and the bonding metal layer on the surface of the driving wafer 100 is continuous throughout the wafer. Further, as shown in FIG. 15, the continuous film layer can have a granularity of a single display region and multiple display regions, each corresponding to a micro display chip.

[0103] (3) Bonding the compound wafer and the driving wafer through the bonding metal layer on the surface of each wafer.

[0104] S22: Remove the substrate of the compound wafer to expose the N-type ohmic contact layer in the compound wafer.

[0105] Specifically, the substrate of the compound wafer is removed by a substrate removal method. After the substrate is removed, as shown in (a) of FIG. 16, the N-type ohmic contact layer 14 in the compound wafer 300 is exposed on the surface of the compound wafer 300. The substrate removal method can be selected according to the substrate material, such as laser stripping for sapphire substrate and HNA wet etching for silicon substrate, which is not limited in the present application.

[0106] S23: Etching to obtain a pixel unit with the P-type ohmic contact layer in the compound wafer as the etching stop layer.

[0107] Specifically, after the N-type ohmic contact layer of the compound wafer is exposed, as shown in (b) of FIG. 16, the compound wafer is patterned for pixel preparation by semiconductor lithography and etching process with the P-type ohmic contact layer 12 as the etching stop layer. The pixel unit 10 corresponds to the anode contact in the driving wafer 100, and the pixel unit 10 can cover the corresponding anode contact.

[0108] S24: Graphical processing of the bonding metal layer by ion beam etching to form a metal fence surrounding the pixel unit.

[0109] The formation of the metal fence can be specifically implemented by any one of the following three schemes.

[0110] Scheme one:

[0111] (1) As shown in (a) of FIG. 17, a first photoresist layer is formed by covering the top and side of the pixel unit 10 with a photoresist mask.

[0112] The photoresist can be positive or negative, which is not limited in the present application.

[0113] (2) As shown in (b) of FIG. 17, taking the first photoresist layer as a mask, the bonding metal layer 11 is patterned by ion beam etching, to produce the metal fence 20 surrounding the pixel unit 10.

[0114] (3) As shown in (c) of FIG. 17, the first photoresist layer is removed.

[0115] Scheme II:

[0116] (1) As shown in (a) of FIG. 18, the top and side of the pixel unit 10 and the outer surface of the P-type ohmic contact layer 12 are filled with insulating material.

[0117] The film forming method of the insulating material can be chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, spin coating, etc.

[0118] (2) As shown in (b) of FIG. 18, the insulating material on the top of the pixel unit 10 is covered with a photoresist mask to form a second photoresist layer.

[0119] The photoresist can be positive or negative, which is not limited in the present application.

[0120] (3) As shown in (c) of FIG. 18, taking the second photoresist layer as a mask, the bonding metal layer 11 is patterned by ion beam etching, to produce the metal fence 20 surrounding the pixel unit 10.

[0121] (4) As shown in (d) of FIG. 18, the second photoresist layer is removed.

[0122] Scheme III:

[0123] (1) As shown in (a) of FIG. 19, the top and side of the pixel unit 10 and the outer surface of the P-type ohmic contact layer 12 are filled with insulating material.

[0124] The film forming method of the insulating material can be CVD, PVD, ALD, spin coating, etc.

[0125] (2) As shown in (b) of FIG. 19, on the basis of the insulating material remaining on the side of the pixel unit 10, the insulating material on the top of the pixel unit 10 is taken as a mask, the bonding metal layer 11 is patterned by ion beam etching, to produce the metal fence 20 surrounding the pixel unit 10.

[0126] In a possible implementation, after the metal fence is generated through step S24, electrical connection of the pixel units is further needed, which can be implemented by the following steps:

[0127] S25: filling the overall blank area of the display module with insulating material.

[0128] The film forming mode of the insulating material can be CVD, PVD, ALD, spin coating, etc.

[0129] S26: performing planarization processing or patterned etching processing on the insulating material to expose the N-type ohmic contact layer of the pixel unit.

[0130] S27: depositing a transparent conductive film on the surface of the N-type ohmic contact layer and the surface of the insulating material to construct a first cathode connection structure.

[0131] Specifically, the transparent conductive film can be deposited by sputtering, evaporation, etc., so as to form the first cathode connection structure on the surface of the N-type ohmic contact layer and the surface of the insulating material, and the first cathode connection structure is entirely arranged on the outer surface of the display module away from the driving wafer.

[0132] In an embodiment, as shown in FIG. 3, surface planarization is performed by using chemical mechanical polishing (CMP) to expose the N-type ohmic contact layer 14, and then transparent conductive film deposition is performed to form the first cathode connection structure 41. In an embodiment, as shown in FIG. 4 and FIG. 5, patterned etching is used to expose the N-type ohmic contact layer 14, and then transparent conductive film deposition is performed to form the first cathode connection structure 41.

[0133] Further, after step S27, the following step is further included: constructing a microlens structure on the side surface of the first cathode connection structure away from the driving wafer.

[0134] Specifically, as shown in FIG. 8 and FIG. 9, the brightness is improved by preparing the microlens structure 50 on the first cathode connection structure 41. The inorganic silicon oxide or nitrogen oxide prepared by using PSG (phosphate glass), BPSG (boron phosphorus silicate glass) process or deposition source such as TEOS (tetraethoxysilane) and TEPO (triethyl phosphate) has the characteristic of fluidity, and the deposited inorganic transparent material naturally grows into a microlens structure.

[0135] Further, at the stage of constructing the first cathode connection structure through step S27, the following step can also be performed: for the trench structure in the insulating material between the two adjacent pixel units, transparent conductive film deposition is performed on the trench structure to construct a second cathode connection structure.

[0136] Specifically, as shown in FIG. 6 and FIG. 7, the trench structure can be deposited with a transparent conductive film by sputtering, evaporation or the like, so as to form the second cathode connecting structure 42 embedded between the two adjacent pixel units, and the second cathode connecting structure 42 is connected with the first cathode connecting structure 41, so as to enhance the electrical characteristics of the common cathode.

[0137] The trench structure can be formed by etching the insulating material, or can be naturally formed between the two adjacent pixel units in the filling process of the insulating material due to the thickness design of the insulating material, which is not limited in the present application.

[0138] In summary, the preparation method of the micro display device provided by the embodiments of the present application, the driving wafer and the display module in the micro display device are bonded and integrated through the bonding metal layer. The metal fence formed by the process of etching the bonding metal layer by the ion beam due to the physical characteristics is fully utilized to form an optical resonant cavity for the pixel unit in the display module. The fence elimination process is not needed, the overall process flow is simplified, the process stability, production efficiency and production capacity are greatly improved. At the same time, the formation of the optical resonant cavity can also improve the brightness of the micro display device.

[0139] Further, the sidewall of the metal fence is in contact with the sidewall of the bonding metal layer and the P-type ohmic contact layer in the pixel unit, and is spaced apart from the sidewall of the compound semiconductor layer and the N-type ohmic contact layer. The space between the metal fence and the pixel unit is filled with an insulating layer to avoid short circuit between the P-type and N-type of each pixel unit, so as to minimize the pixel spacing, maximize the pixel light-emitting area, improve the pixel density, and improve the resolution of the micro display device.

[0140] Embodiment 2

[0141] The difference between the present embodiment and embodiment 1 is that, as shown in FIG. 20 to FIG. 22, the display module further includes an upper resonant cavity 60 surrounding the top 10 of the pixel unit.

[0142] The upper resonant cavity 60 can be made of a metal material, such as Al / Ti / Cu, or Al / TiN / Cu, or Al / Ni / Cu, or Al / NiV / Cu, or Al / Ta / Cu, or Al / TaN / Cu, and the above Cu can be replaced by W, and the above structure can also be without Al, and the specific type of metal material is not limited in the present application.

[0143] In the present embodiment, the fence-like structure produced by IBE etching is fully utilized to form a columnar metal fence 20 surrounding the bottom of the pixel unit 10, and an upper resonant cavity 60 surrounding the top of the pixel unit 10 is also provided for the pixel unit 10, and the upper resonant cavity 60 and the metal fence 20 form a resonant cavity combination structure. It can be understood that the present application does not limit the specific pattern of the upper resonant cavity 60 and the metal fence 20, which can be a rectangular column pattern or a cylindrical pattern.

[0144] It can be understood that FIGS. 20 to 22 only exemplarily illustrate that the resonant cavity combination structure formed by the upper resonant cavity 60 and the metal fence 20 surrounds one pixel unit 10, and one resonant cavity combination can also surround multiple pixel units 10, which is not limited in the present embodiment. For example, in a mother pixel stacked with multiple layers, for the sub-pixels in the same layer in the mother pixel, a resonant cavity combination structure is used to surround the sub-pixels in the layer.

[0145] Further, the projection of the metal fence 20 on the driving wafer 100 is located within the projection of the upper resonant cavity 60 on the driving wafer 100. Since the metal fence 20 is produced by IBE etching, the metal fence 20 closely adheres to the sidewall of the pixel unit 10, and therefore, setting the projection range of the upper optical cavity to be greater than the projection range of the metal fence 20 can avoid the situation that the light emitting area of the corresponding part is too small after the upper optical cavity processing. Further, as shown in (a) of FIG. 23, the projection of the metal fence 20 can be located within the projection of the upper resonant cavity 60, the projection of the metal fence 20 and the projection of the upper resonant cavity 60 do not overlap, or as shown in (b) of FIG. 23, the projection of the metal fence 20 can be located between the inner and outer projections of the upper resonant cavity 60, and the projection of the metal fence 20 and the projection of the upper resonant cavity 60 partially overlap.

[0146] It can be understood that if the metal fence 20 is spaced apart from the pixel unit 10, the projection of the metal fence 20 on the driving wafer 100 can be located within the projection of the upper resonant cavity 60 on the driving wafer 100, or outside the projection of the upper resonant cavity 60 on the driving wafer 100.

[0147] Further, the pixel unit 10 comprises a compound semiconductor layer 13; any point of the compound semiconductor layer 13 and the extension line of the line connecting the inner vertex or the outer vertex of the metal fence 20 are in contact with the upper resonant cavity 60, the inner vertex refers to the end point of the inner wall adjacent to the compound semiconductor layer 13 at the top of the metal fence 20, and the outer vertex refers to the end point of the outer wall not adjacent to the compound semiconductor layer 13 at the top of the metal fence 20. In the case that the above-mentioned extension line is in contact with the upper resonant cavity, the light emitted from the compound semiconductor layer 13 can be effectively regulated by the resonant cavity combination composed of the metal fence 10 and the upper resonant cavity 60.

[0148] Further, the bottom height of the upper resonant cavity 60 is not higher than the top height of the metal fence 20. In the case that the bottom height of the upper resonant cavity 60 is not higher than the top height of the metal fence 20, the upper resonant cavity 60 and the metal fence 20 are designed to be in contact or further cross in the vertical direction, so that the resonant cavity combination can completely surround the pixel unit 10 in the vertical direction, and the light emitted by the pixel unit 10 can be completely regulated.

[0149] Further, the top height of the metal fence 20 is not lower than the top height of the compound semiconductor layer 13 in the pixel unit 10. Since the light emitted by the pixel unit 10 is emitted through the compound semiconductor layer 13, in the case that the top height of the metal fence 20 is not lower than the top height of the compound semiconductor layer 13, the metal fence 20 can effectively reflect the light emitted by the pixel unit 10, and further enhance and regulate the light energy.

[0150] Further, the distance between the metal fence 20 and the upper resonant cavity 60 in the horizontal direction is not less than 100 nanometers and not more than 10 micrometers. If the distance between the metal fence 20 and the upper resonant cavity 60 in the horizontal direction is too small, the metal fence 20 and the upper resonant cavity 60 may be in contact, causing a short circuit problem of the micro display device, and if the distance between the metal fence 20 and the upper resonant cavity 60 in the horizontal direction is too large, the distance between adjacent pixel units 10 is affected, and further, the pixel unit 10 density is too low, which affects the display effect. Therefore, in the case that the distance is not less than 100 nanometers and not more than 10 micrometers, the above-mentioned problems can be effectively avoided.

[0151] Further, the thickness of the upper resonant cavity 60 away from one end of the driving wafer 100 is greater than the thickness of the upper resonant cavity 60 close to one end of the driving wafer 100. In the case that the upper resonant cavity 60 is obtained by etching, the upper resonant cavity 60 is designed to be large at the top and small at the bottom, which is beneficial to reduce the preparation difficulty of the upper resonant cavity.

[0152] In a possible implementation, the display module 200 further includes a first insulating layer 30, the first insulating layer 30 is filled in the blank space of the display module 200 and fills the outer periphery of the pixel unit 10; and a common cathode, the common cathode includes a first cathode connecting structure 41, the first cathode connecting structure 41 is arranged on the side surface of the first insulating layer 30 away from the driving wafer 100 and is connected with the N-type ohmic contact layer 14 on the top of the pixel unit 10; and the upper resonant cavity 60 is embedded in the first insulating layer 30, and the top of the upper resonant cavity 60 is connected with the first cathode connecting structure 41.

[0153] As shown in FIGS. 20-22, the first insulating layer 30 is filled in the display module 200, on one hand, the upper resonant cavity 60 can be prepared in the first insulating layer 30, on the other hand, the metal fence 20 can be fixed, and the top of the metal fence 20 is insulated from the pixel unit 10, further avoiding the short circuit between the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 through the metal fence 20, and the leakage current. The first insulating layer 30 is mainly silicon oxide, and optionally includes silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, and combinations of the above, which are not limited in the present application.

[0154] As shown in FIGS. 20-22, the top of the pixel unit 10 exposes the N-type ohmic contact layer 14, and the first cathode connecting structure 41 connected with the exposed N-type ohmic contact layer 14 is prepared on the side surface of the first insulating layer 30 away from the driving wafer 100. Since the top of the upper resonant cavity 60 is connected with the common cathode, the current transmission capacity of the common cathode can be enhanced through the upper resonant cavity 60 in the case that the upper resonant cavity 60 is made of metal material. The common cathode can be a transparent conductive film, which avoids the light blocking of the common cathode to the pixel unit 10 and improves the brightness of the pixel unit 10. The film layer of the transparent conductive film can be one or a combination of ITO film, AZO film, ATO film, and FTO film. Further, the ITO surface can be coated with thin Al, Au, and Ag and then annealed to form metal-doped ITO, so as to enhance the current transmission capacity of the common cathode.

[0155] Further, the implementation of the first cathode connecting structure 41 can be that, as shown in FIG. 20, the first insulating layer 30 includes a portion whose top is flush with the top of the N-type ohmic contact layer 14, and the first cathode connecting structure 41 is horizontally arranged on the outer surface of the portion and the top of the N-type ohmic contact layer 14. The implementation of the first cathode connecting structure 41 can also be that, as shown in FIGS. 21 and 22, the first insulating layer 30 includes a portion whose top is higher than the top of the N-type ohmic contact layer 14, and the first cathode connecting structure 41 is arranged on the outer surface of the portion and the top of the N-type ohmic contact layer 14.

[0156] In summary, the micro display device provided by the embodiment of the present application, the driving wafer in the micro display device is bonded and integrated with the display module through a bonding metal layer, the display module includes a resonant cavity combination structure surrounding the pixel unit, the metal fence in the resonant cavity combination structure surrounds the bottom of the pixel unit, and the upper resonant cavity in the resonant cavity combination structure surrounds the top of the pixel unit. Through the resonant cavity combination structure, complete optical isolation is performed between the pixel units, the crosstalk problem between adjacent pixel units can be effectively avoided, and the micro display device is resonantly enhanced.

[0157] Further, the metal fence is formed by fully utilizing the metal fence generated in the IBE metal etching process, without performing fence elimination processing technology, thereby simplifying the overall process flow, and the upper resonant cavity is also a metal material, and the resonant cavity combination structure is a pure inorganic material, and the structure has high reliability.

[0158] Next, the preparation method of the micro display device described in the embodiment is described. In the embodiment, after the metal fence surrounding the pixel unit is generated through the above step S24, the following steps are further included:

[0159] S31: The display module is filled with insulating medium to form a first insulating layer.

[0160] The film forming method of the first insulating layer can be CVD, PVD, ALD, spin coating, etc.

[0161] S32: An upper resonant cavity is prepared in the first insulating layer, and the upper resonant cavity surrounds the top of the pixel unit.

[0162] In a possible implementation, the first insulating layer completely fills the space region between the two adjacent metal fences; and the step S32 specifically includes the following steps:

[0163] (1) The third insulating layer between the two adjacent metal fences is patterned and etched to form a first trench structure.

[0164] (2) The first trench structure is subjected to metal deposition to construct the upper resonant cavity.

[0165] In the implementation, the first trench structure is formed by patterned etching the first insulating layer between the pixels, and the metal filling of the trench structure can obtain the upper resonant cavity 60 as shown in FIGS. 20 and 21.

[0166] In another possible implementation, the film layer thickness of the first insulating layer is less than the spacing between two adjacent metal fences, so that the first insulating layer forms a second trench structure between the two adjacent metal fences; and the step S32 specifically includes the following step: performing metal deposition on the second trench structure to construct the upper resonant cavity.

[0167] In the implementation, the metal is filled directly inside the second trench structure formed based on the film layer thickness of the first insulating layer, to obtain the structure shown in FIG. 24.

[0168] Further, after the upper resonant cavity is generated through the step S32, electrical connection of the pixel units also needs to be performed, specifically by performing the following steps:

[0169] S33: performing cathode electrical connection on the pixel units to form a common cathode arranged above the insulating layer, and the common cathode includes a first cathode connection structure connected with the N-type ohmic contact layer at the top of the pixel units.

[0170] Specifically, the transparent conductive film can be deposited by sputtering, evaporation or the like, to form the first cathode connection structure on the surface of the N-type ohmic contact layer and the surface of the insulating layer, and the first cathode connection structure is arranged on the outer surface of the display module away from the driving wafer.

[0171] In an embodiment, as shown in FIG. 20, surface planarization is performed by using chemical mechanical polishing (CMP) to expose the N-type ohmic contact layer 14, and then transparent conductive film deposition is performed to form the first cathode connection structure 41. In an embodiment, as shown in FIG. 21 and FIG. 22, the N-type ohmic contact layer 14 is exposed by using patterned etching, and then transparent conductive film deposition is performed to form the first cathode connection structure 41.

[0172] In summary, the preparation method of the micro display device provided in the embodiments of the present application integrates the driving wafer and the display module in the micro display device by bonding through the bonding metal layer, the display module includes the resonant cavity combination structure surrounding the pixel units, the metal fence in the resonant cavity combination structure surrounds the bottom of the pixel units, the upper resonant cavity in the resonant cavity combination structure surrounds the top of the pixel units, and the resonant cavity combination structure completely optically isolates the pixel units, which can effectively avoid the crosstalk problem between the adjacent pixel units and enhance the resonance of the micro display device.

[0173] Further, the metal fence is formed by fully utilizing the metal fence generated in the IBE metal etching process, without performing the fence elimination process, thereby simplifying the overall process flow, and the upper resonant cavity is also made of metal material, and the resonant cavity combination structure is made of pure inorganic material, so that the structure has high reliability.

[0174] Embodiment 3

[0175] The difference between this embodiment and Embodiment 1 is that, as shown in FIG. 25 and FIG. 26, the pixel unit 10 and the metal fence 20 are in the display device layer, the display module further comprises: a color conversion layer 80 stacked on the display device layer; the upper optical cavity 70 is prepared on the surface of the display device layer away from the driving wafer 100, the projection of the pixel unit 10 on the driving wafer 100 is located within the projection of the upper optical cavity 70 on the driving wafer 100, and the upper optical cavity 70 is filled with the color conversion layer 80.

[0176] The metal fence 20 and the upper optical cavity 70 are used to constrain the light-emitting angle of the pixel unit 10.

[0177] In this embodiment, the upper optical cavity 70 is prepared on the surface of the display device layer away from the driving wafer 100, and the projection of the pixel unit 10 on the driving wafer 100 is located within the projection of the upper optical cavity 70 on the driving wafer 100. Under the setting, the light emitted upward from the display device layer 200 by the pixel unit 10 will pass through the upper optical cavity 70, and the upper optical cavity 70 will constrain the light-emitting angle. The upper optical cavity 70 can be an alloy or a stack of metal materials, such as an alloy of Al, AlCu, AlNi, etc., a stack of Al / TiN, AlCu / TiN, a stack of Al / Ni / Ti / Au, or an alloy or a stack of Au / Ge / Ni / Au.

[0178] It can be understood that FIG. 25 to FIG. 26 only exemplarily illustrate that a set of metal fences 20 and upper optical cavities 70 surround one pixel unit 10, and in practice, a set of metal fences 20 and upper optical cavities 70 can also surround multiple pixel units 10, which is not limited in this embodiment. For example, in a mother pixel stacked with multiple layers, for the sub-pixels in the same layer in the mother pixel, a set of metal fences 20 and upper optical cavities 70 are used to surround the sub-pixels in the layer.

[0179] Further, the projection of the metal fence 20 on the driving wafer 100 is located within the projection of the upper optical cavity 70 on the driving wafer 100. A part of the light emitted by the pixel unit 10 may not be completely constrained by the metal fence 20, therefore, the projection range of the upper optical cavity 70 is set to be larger than the projection range of the metal fence 20, so as to effectively process the light emitted upward from the display device layer 200 by the pixel unit 10 after being constrained by the metal fence 20.

[0180] Further, one end of the metal fence 20 is connected to the driving wafer 100 close to the side of the display device layer 200, and the other end is separated from the upper optical cavity 70 by a predetermined distance. In order to avoid the short circuit of the micro display device caused by the connection of the metal fence 20 and the upper optical cavity 70, the top end of the metal fence 20 is arranged to be separated from the upper optical cavity 70 by a predetermined distance. For example, the distance between the top end of the metal fence 20 and the bottom end of the upper optical cavity 70 is not less than 50 nm.

[0181] Further, the ratio between the height of the upper optical cavity 70 and the width of the upper optical cavity 70 is between 2:1 and 10:1. In this embodiment, the upper optical cavity 70 can be designed to have a large aspect ratio, specifically, the aspect ratio is between 2:1 and 10:1. The larger the aspect ratio, the larger the cavity corresponding to the upper optical cavity 70, which can be used to carry the color conversion layer 80 and other optical structures.

[0182] The color conversion layer 80 is filled in the upper optical cavity 70, and the color conversion layer 80 is used for color conversion of the light emitted by the pixel unit 10. The color conversion layer 80 can be quantum dots, fluorescent powder or other functional materials, and the specific material of the color conversion layer 80 is not limited in the present application. The color conversion layer 80 can be a full surface or a patterned surface. Further, the height of the top of the color conversion layer 80 can be higher than the height of the upper optical cavity 70, can be flush with the height of the upper optical cavity 70, or can be lower than the height of the upper optical cavity 70.

[0183] In a possible implementation, as shown in FIG. 27, the color conversion layer 80 and the display device layer 200 further include a second insulating layer 31, and the second insulating layer 31 is provided with a multi-ring structure 90. The multi-ring structure 90 refers to a sleeve ring structure formed by nesting multiple ring structures. The height of the multi-ring structure 90 is less than the height of the upper optical cavity 70.

[0184] The second insulating layer 31 is mainly silicon oxide, and optionally includes silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, and combinations thereof, which are not limited in the present application. The multi-ring structure 50 can be made of a metal material to form a metal multi-ring structure, or can be embedded in the second insulating layer 31 in the form of not filling materials inside to form a dielectric multi-ring structure.

[0185] For example, the distance between each ring structure in the multi-ring structure 90 is n*λ / 4, and the distance between each ring structure can be the same or different. The distance between the multi-ring structure 50 and the surrounding upper optical cavity 70 is also n*λ / 4, where n is a positive integer and λ is the wavelength. The sensitivity of light refraction and oscillation is high at this interval, which can further enhance the optical resonant cavity.

[0186] In a possible implementation, the display device layer further comprises: a first insulating layer 30, the first insulating layer 30 is filled in the blank space of the display device layer 200 and fills the outer periphery of the pixel unit 10; and a common cathode, the common cathode comprises: a first cathode connecting structure 41, the first cathode connecting structure 41 is arranged on the first insulating layer 30 and is connected with the N-type ohmic contact layer 14 on the top of the pixel unit 10; and the upper optical cavity 70 is prepared on the first cathode connecting structure 41.

[0187] As shown in FIG. 25 and FIG. 26, the first insulating layer 30 is filled in the display module, the optical resonant cavity formed by the metal fence 20 is fixed, the metal fence 20 on the top is insulated and separated from the pixel unit 10, and the short circuit between the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 through the metal fence 20 is avoided, and the leakage is further avoided. The first insulating layer 30 is mainly silicon oxide, and optionally comprises silicon oxide, aluminum oxide, silicon nitride, aluminum nitride and combinations of the above, which are not limited in the present application.

[0188] As shown in FIG. 25 and FIG. 26, the N-type ohmic contact layer 14 is exposed on the top of the pixel unit 10, and the first cathode connecting structure 41 connected with the exposed N-type ohmic contact layer 14 is prepared on the surface of the second insulating layer 60 away from the driving wafer 100.

[0189] Further, the first cathode connecting structure 41 and the upper optical cavity 70 are made of metal material, and the electrical performance of the cathode of the micro display device is enhanced through the first cathode connecting structure 41 and the upper optical cavity 70 made of metal material. In addition, the first cathode connecting structure 41 can form single-sided, double-sided or multi-sided contact with the N-type ohmic contact layer 14 on the N-type contact of the pixel unit 10, so that the first cathode connecting structure 41 can be continuous or discontinuous.

[0190] In a possible implementation, a third insulating layer is further arranged on the color conversion layer 80. The third insulating layer can be used for water vapor isolation of the color conversion layer 80. The third insulating layer is mainly silicon oxide, and optionally, the insulating layer is a single layer or a combination of silicon oxide, aluminum oxide, silicon nitride, aluminum nitride and other oxides, which are not limited in the present application.

[0191] In summary, the micro display device provided by the embodiment of the present application, the driving wafer in the micro display device is bonded and integrated with the display module through a bonding metal layer, the display module includes a display device layer and a color conversion layer, and the process of etching the bonding metal layer by an ion beam necessarily forms a metal fence due to physical characteristics. The metal fence is fully utilized to form an optical resonant cavity for a pixel unit in the display device layer, and the color conversion layer is arranged in an upper optical cavity of the display device layer. The combination of the metal fence and the upper optical cavity double-constrains the light-emitting angle of the pixel unit, thereby effectively avoiding crosstalk between adjacent pixel units in the micro display device.

[0192] Further, the metal fence and the upper optical cavity are both made of inorganic materials, which have high reliability and do not affect the integrity of the micro display device.

[0193] Next, the preparation method of the micro display device described in the embodiment is described. In the embodiment, after the metal fence surrounding the pixel unit is generated through the above step S24, the following steps are further included:

[0194] S41: The pixel unit is cathodically connected, and the common cathode includes a first cathode connection structure connected with the N-type ohmic contact layer at the top of the pixel unit.

[0195] S42: An upper optical cavity is prepared above the common cathode, and the outer contour of the projection of the metal fence on the driving wafer is located within the outer contour of the projection of the upper optical cavity on the driving wafer.

[0196] In a possible implementation, the common cathode and the upper optical cavity can be prepared and formed together by metal plating. Specifically, the steps S41 and S42 can be replaced by the following steps:

[0197] (1) The blank space in the display device layer is filled with an insulating medium to form a first insulating layer.

[0198] The film forming method of the first insulating layer can be CVD, PVD, ALD, spin coating, etc.

[0199] (2) The first insulating layer is subjected to planarization treatment or patterned etching treatment to expose the N-type ohmic contact layer of the pixel unit.

[0200] (3) Metal plating is performed above the N-type ohmic contact layer to form a metal layer, and the metal layer includes the common cathode.

[0201] Specifically, the metal plating can be performed by evaporation or sputtering of the entire surface to form the metal layer including the common cathode.

[0202] (4) performing patterned etching on the metal layer to obtain the upper optical cavity.

[0203] In another possible implementation, the common cathode can be prepared by a double Damascus process, and then the upper optical cavity is further prepared. Specifically, the steps S41 and S42 can be replaced by the following steps:

[0204] (1) performing insulating medium filling on the blank space in the display device layer to form a first insulating layer.

[0205] The film forming mode of the first insulating layer can be CVD, PVD, ALD, spin coating, or the like.

[0206] (2) performing pit etching on the surface of the first insulating layer to obtain at least one pit connected or disconnected, and the at least one pit is in contact with the N-type ohmic contact layer at the top of the pixel unit.

[0207] (3) performing metal filling in the pit to form the common cathode.

[0208] Specifically, the first insulating layer is subjected to pit etching, and then a metal seed layer is sputtered to realize N-type ohmic contact with the pixel unit and connection with the common cathode, and then metal filling is realized by electroplating and chemical mechanical polishing (CMP) process. On the N-type contact with the pixel unit, it can be single-sided, double-sided, or multi-sided contact with the N-type ohmic contact layer, and the first cathode connection structure 41 at the top of the pixel unit can be a full-face continuous structure as shown in FIG. 28, or a non-continuous structure as shown in FIG. 29, which is only in contact with the outer edge of the top of the pixel unit, and there is an opening at the top of the pixel unit. The metal seed layer can be Ti / Cu or Al / Ni / Cu.

[0209] (4) electroplating metal on the common cathode to form the upper optical cavity.

[0210] Specifically, as shown in FIG. 30, a high aspect ratio metal dam is formed on the first cathode connection structure 41 by electroplating as the upper optical cavity 70.

[0211] S43: filling the color conversion layer in the upper optical cavity.

[0212] Specifically, the color conversion layer is filled in the upper optical cavity to obtain the structure as shown in FIGS. 25 and 26.

[0213] In one possible implementation, the step S43 specifically includes:

[0214] (1) performing insulating medium filling in the upper optical cavity to form a second insulating layer.

[0215] (2) preparing a multi-ring structure in the second insulating layer.

[0216] Specifically, the multi-ring structure can be a dielectric multi-ring structure, and the preparation method comprises: performing ring-shaped groove etching on the second insulating layer to form the dielectric multi-ring structure. The second insulating layer is formed by film plating in the upper optical cavity, and the groove structure in the form of a ring is formed in the second insulating layer by semiconductor patterning etching as the dielectric multi-ring structure. When the light source enters the second insulating layer and is totally reflected in the air where the dielectric multi-ring structure is located, the oscillation enhancement is formed by multiple reflections and refractions of the light source inside the second insulating layer.

[0217] Specifically, the multi-ring structure can be a metal multi-ring structure, and the preparation method comprises: performing ring-shaped groove etching on the second insulating layer, and performing metal filling on the groove to form the metal multi-ring structure. After the groove structure is formed in the second insulating layer, metal filling is performed. When the light source enters the second insulating layer and is reflected in the metal where the groove is located, the oscillation enhancement is formed by multiple reflections and refractions of the light source inside the second insulating layer.

[0218] (3) filling the color conversion layer in the upper region of the second insulating layer in the upper optical cavity.

[0219] Further, after step S43, the following step can also be performed: covering the insulating medium on the color conversion layer to form a third insulating layer. The insulating medium can be film plated on the color conversion layer to perform water vapor isolation.

[0220] In summary, the preparation method of the micro display device provided by the embodiments of the present application integrates the driving wafer and the display module in the micro display device by bonding the metal layer, the display module includes the display device layer and the color conversion layer, the metal fence formed by the process of ion beam etching the metal layer due to physical characteristics is fully utilized to form the optical resonant cavity for the pixel unit in the display device layer, and the color conversion layer is arranged in the upper optical cavity of the display device layer, the combination of the metal fence and the upper optical cavity double-constrains the light-emitting angle of the pixel unit, thereby effectively avoiding the crosstalk between adjacent pixel units in the micro display device.

[0221] Further, the metal fence and the upper optical cavity are both made of inorganic materials, and the materials have high reliability, which avoids affecting the integrity of the micro display device.

[0222] All the optional technical solutions described above can be combined to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the needs of different application scenarios, which are all within the protection scope of the present application and will not be described one by one here.

[0223] It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. Accordingly, the legal scope of the application is defined only by the appended claims.

Claims

1. A microdisplay device, characterized by, The micro display device comprises: a driving wafer comprising an anode contact therein; a display module integrated with the driving wafer through a bonding metal layer, the display module comprising a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, the metal fence being a fence-shaped structure generated in the process of ion beam etching the bonding metal layer; wherein the metal fence forms a columnar optical resonant cavity for the pixel unit, the optical resonant cavity being used for reflecting light waves emitted by the pixel unit back and forth therein to provide optical positive feedback.

2. The microdisplay device of claim 1, wherein, The pixel unit comprises, in sequence and vertically stacked in a direction away from the driving wafer: the bonding metal layer, a P-type ohmic contact layer, a compound semiconductor layer, and an N-type ohmic contact layer; a bottom of the metal fence is connected to a side of the driving wafer close to the display module; a sidewall of the metal fence is in contact with sidewalls of the bonding metal layer and the P-type ohmic contact layer, and is arranged at a distance from sidewalls of the compound semiconductor layer and the N-type ohmic contact layer.

3. The micro display device of claim 2, wherein: a top of the metal fence is not lower than a top of the compound semiconductor layer.

4. The microdisplay device of claim 2, wherein, The display module further comprises: a first insulating layer filled in a blank space of the display module and around an outer periphery of the pixel unit; a common cathode comprising a first cathode connection structure arranged on a side surface of the first insulating layer away from the driving wafer and connected to the N-type ohmic contact layer.

5. The micro display device of claim 4, wherein: the common cathode further comprises a second cathode connection structure embedded in the first insulating layer between two adjacent pixel units, an end of the second cathode connection structure away from the driving wafer being connected to the first cathode connection structure.

6. The micro display device of claim 4, wherein: the first insulating layer comprises a portion with a top flat with a top of the N-type ohmic contact layer, the first cathode connection structure being horizontally arranged on an outer surface of the portion and the top of the N-type ohmic contact layer; or, the first insulating layer comprises a portion with a top higher than a top of the N-type ohmic contact layer, the first cathode connection structure being arranged on an outer surface of the portion and the top of the N-type ohmic contact layer; or, the first insulating layer comprises a portion arranged on a sidewall of the pixel unit, the first cathode connection structure being arranged on an outer surface of the portion and the top of the N-type ohmic contact layer.

7. The micro display device of claim 4, wherein: the common cathode is a transparent conductive film.

8. The micro display device of claim 4, wherein: The first cathode connection structure is provided with a microlens structure on a side surface away from the drive wafer, and a projection of the metal fence on the drive wafer is within a projection of the microlens structure on the drive wafer.

9. The micro display device of claim 1, wherein, The display module further comprises an upper resonant cavity, and the upper resonant cavity surrounds a top of the pixel unit.

10. The microdisplay device of claim 9, wherein, The display module further comprises: A first insulating layer, which is filled in a blank space of the display module and around an outer periphery of the pixel unit; A common cathode, which comprises a first cathode connection structure, the first cathode connection structure is arranged on a side surface of the first insulating layer away from the drive wafer and connected with the N-type ohmic contact layer; The upper resonant cavity is embedded in the first insulating layer, and a top of the upper resonant cavity is connected with the first cathode connection structure.

11. The micro display device of claim 9, wherein, An outer contour of the projection of the metal fence on the drive wafer is within an outer contour of the projection of the upper resonant cavity on the drive wafer.

12. The microdisplay device of claim 9, wherein, The pixel unit comprises a compound semiconductor layer; An extension line of any point of the compound semiconductor layer and an inner vertex or an outer vertex of the metal fence is in contact with the upper resonant cavity, the inner vertex refers to an end point of an inner wall adjacent to the compound semiconductor layer at the top of the metal fence, and the outer vertex refers to an end point of an outer wall not adjacent to the compound semiconductor layer at the top of the metal fence.

13. The micro display device of claim 12, wherein, A bottom height of the upper resonant cavity is not higher than a top height of the metal fence.

14. The micro display device of claim 9, wherein, A horizontal distance between the metal fence and the upper resonant cavity is not less than 100 nanometers and not more than 10 micrometers.

15. The micro display device of claim 9, wherein, A thickness of an end of the upper resonant cavity away from the drive wafer is greater than a thickness of an end close to the drive wafer.

16. The micro display device of claim 1, wherein, The pixel unit and the metal fence are in a display device layer, and the display module further comprises a color conversion layer stacked on the display device layer; A top surface of the display device layer away from the drive wafer is provided with an upper optical cavity, an outer contour of a projection of the pixel unit on the drive wafer is within an outer contour of a projection of the upper optical cavity on the drive wafer, and the color conversion layer is filled in the upper optical cavity; The metal fence and the upper optical cavity are used to constrain a light emitting angle of the pixel unit.

17. The micro display device of claim 16, wherein, An outer contour of the projection of the metal fence on the drive wafer is within an outer contour of the projection of the upper optical cavity on the drive wafer.

18. The micro display device of claim 16, wherein: one end of the metal fence is connected to a side of the driving wafer close to the display device layer, and the other end is separated from the upper optical cavity by a preset distance.

19. The micro display device of claim 16, wherein: a ratio between a height of the upper optical cavity and a width of the upper optical cavity is between 2:1 and 10:

1.

20. The micro display device of claim 16, wherein: a second insulating layer is further included between the color conversion layer and the display device layer, and a multi-ring structure is arranged in the second insulating layer.

21. The microdisplay device of claim 16, wherein, the display device layer further includes: a first insulating layer filled in a blank space of the display module and around an outer periphery of the pixel unit; a common cathode including a first cathode connection structure arranged on a side surface of the first insulating layer away from the driving wafer and connected to the N-type ohmic contact layer; wherein the upper optical cavity is prepared on the first cathode connection structure.

22. The micro display device of claim 21, wherein: the first cathode connection structure and the upper optical cavity are made of a metal material, and the common cathode is continuous or discontinuous.

23. The micro display device of claim 16, wherein: a third insulating layer is arranged on the color conversion layer.

24. A method of fabricating a microdisplay device, comprising: The method is used for preparing the micro display device of any one of claims 1 to 23, and the method includes: preparing a driving wafer including an anode contact therein; preparing a display module integrated with the driving wafer through a bonding metal layer, the display module including a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, the metal fence being a fence pattern structure generated in a process of ion beam etching the bonding metal layer; wherein the metal fence forms a columnar optical resonant cavity for the pixel unit, and the optical resonant cavity is used for reflecting light waves emitted by the pixel unit back and forth therein to provide optical positive feedback.

25. The method of claim 24, wherein, The preparation of the display module includes: bonding a compound wafer with the driving wafer through the bonding metal layer; removing a substrate of the compound wafer to expose an N-type ohmic contact layer in the compound wafer; etching the pixel unit with a P-type ohmic contact layer in the compound wafer as an etching stop layer; performing a patterning treatment on the bonding metal layer through ion beam etching to generate the metal fence surrounding the pixel unit.

26. The method of claim 25, wherein, The patterning treatment on the bonding metal layer through ion beam etching to generate the metal fence surrounding the pixel unit includes: arranging a first photoresist layer on a top and a side of the pixel unit using a photoresist mask; performing a patterning treatment on the bonding metal layer through ion beam etching using the first photoresist layer as a mask to generate the metal fence surrounding the pixel unit. Removing the first photoresist layer.

27. The method of claim 25, wherein, The patterning of the bonding metal layer by ion beam etching to generate a metal fence surrounding the pixel unit comprises: Filling the top and side of the pixel unit and the outer surface of the P-type ohmic contact layer with insulating material; Covering the insulating material on the top of the pixel unit with a photoresist mask to form a second photoresist layer; Using the second photoresist layer as a mask, the bonding metal layer is patterned by ion beam etching to generate a metal fence surrounding the pixel unit; Removing the second photoresist layer.

28. The method of claim 25, wherein, The patterning of the bonding metal layer by ion beam etching to generate a metal fence surrounding the pixel unit comprises: Filling the top and side of the pixel unit and the outer surface of the P-type ohmic contact layer with insulating material; On the basis of the insulating material remaining on the side of the pixel unit, the insulating material on the top of the pixel unit is used as a mask to pattern the bonding metal layer by ion beam etching to generate a metal fence surrounding the pixel unit.

29. The method of claim 25, wherein, After the metal fence is generated, the method further comprises: Filling the overall blank area of the display module with insulating material; Planarizing or patterning the insulating material to expose the N-type ohmic contact layer of the pixel unit; Depositing a transparent conductive film on the surface of the N-type ohmic contact layer and the surface of the insulating material to form a first cathode connection structure.

30. The method of claim 29, wherein, The insulating material between the two adjacent pixel units has a groove structure, and the method further comprises: Depositing a transparent conductive film on the groove structure to form a second cathode connection structure.

31. The method of claim 29, wherein, The method further comprises: Constructing a microlens structure on the surface of the first cathode connection structure away from the driving wafer.

32. The method of claim 25, wherein, The bonding integration of the compound wafer and the driving wafer through the bonding metal layer comprises: Preparing a P-type ohmic contact layer on the P surface of the compound wafer; Preparing a bonding metal layer on the surface of the P-type ohmic contact layer of the compound wafer and the surface of the driving wafer, respectively, at least one of the two bonding metal layers being continuous in the pixel area and being supported by insulating medium in the non-pixel area; Bonding the compound wafer and the driving wafer through the bonding metal layer on the respective surfaces.

33. The method of claim 25, wherein, After the metal fence is prepared, the method further comprises: Filling the display module with insulating medium to form a first insulating layer; Preparing an upper resonant cavity in the first insulating layer, the upper resonant cavity surrounding the top of the pixel unit.

34. The method of claim 33, wherein, The first insulating layer completely fills the space between the two adjacent metal fences; The preparation of the upper resonant cavity in the first insulating layer comprises: Patterning the first insulating layer between the two adjacent metal fences to form a first groove structure; Depositing a metal on the first groove structure to form the upper resonant cavity.

35. The method of claim 33, wherein, The film layer thickness of the first insulating layer is less than 1 / 2 of the interval between two adjacent metal fences, so that the first insulating layer forms a second trench structure between the two adjacent metal fences; The method further comprises: The method further comprises:

36. The method of claim 25, wherein, The method further comprises: The method further comprises: The method further comprises: The method further comprises:

37. The method of claim 36, wherein, The method further comprises: The method further comprises: The method further comprises: The method further comprises: The method further comprises: The method further comprises:

38. The method of claim 36, wherein, The method further comprises: The method further comprises: The method further comprises: The method further comprises: The method further comprises: The method further comprises:

39. The method of claim 36, wherein, The method further comprises: The method further comprises: The method further comprises: The method further comprises:

40. The method of claim 39, wherein, The method further comprises: The method further comprises: The method further comprises: The method further comprises:

41. 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