Display driving circuit and display apparatus

Abstract

Provided are a display driving circuit and a display apparatus. A first input terminal (IN1) of a gate driving circuit in a first gate driving cell (GDC1) and a second input terminal (IN2) of a gate driving circuit in a second gate driving cell (GDC2) are connected to a first clock line (CLK1), a second input terminal (IN2) of the gate driving circuit in the first gate driving cell (GDC1) and a first input terminal (IN1) of the gate driving circuit in the second gate driving cell (GDC2) are connected to a second clock line (CLK2), and the phase difference between same-level gate control signals output by the two gate driving cells is XnH+YH.

Description

Display driving circuit and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driving circuit and a display device. BACKGROUND

[0002] The display device will generally automatically switch the display frequency according to the specific use scene, so that the display mode of the display panel will be switched between the high-frequency display mode and the low-frequency display mode. However, when the display mode of the display panel is switched, the screen brightness will suddenly change, resulting in the problem of flicker. The reason is that in the high-frequency display mode, the sub-pixel will refresh the display data in each frame, while in the low-frequency display mode, the sub-pixel will refresh the display data in part of the frames (such as the write frame), and the remaining part of the frames (such as the holding frame) will maintain the same content as the write frame. However, the driving transistor of the sub-pixel will be subjected to different bias strengths in the holding frame and the write frame, and the driving transistor will also drift in electrical characteristics (such as the threshold voltage of the driving transistor) due to hysteresis effect, resulting in different brightness of the sub-pixel in the holding frame and the write frame, and further causing the problem of flicker.

[0003] By adjusting the reset duration of the reset of only the control end potential of the driving transistor in the write frame, the bias strength of the driving transistor in the write frame can be adjusted, so as to adjust the display brightness difference, and then adjust the severity of the flicker problem of the display panel. By controlling the gate control signals applied to the plurality of transistors included in the pixel driving circuit, the bias strength of the driving transistor can be adjusted. However, the gate driving circuit for generating the gate control signals usually uses a fixed 4H period clock signal, so that the reset duration of the reset of only the control end potential of the driving transistor in the write frame is fixed as 4nH. Therefore, the method of adjusting the reset duration to improve the flicker problem can only be implemented on part of the display panels. Wherein, n≥0. Therefore, the application of the reset duration fixed as 4nH is limited. SUMMARY

[0004] The display driving circuit and the display device provided by the embodiments of the present application can realize adjustable control of the phase difference of the two gate control signals of the same stage in the two gate driving units.

[0005] The embodiment of the present application provides a display driving circuit, which comprises a first clock line, a second clock line and a gate driving module. The first clock line is configured to transmit a first clock signal, and the second clock line is configured to transmit a second clock signal. The gate driving module comprises a first gate driving unit and a second gate driving unit. The first gate driving unit and the second gate driving unit each comprise a plurality of cascaded gate driving circuits, and each gate driving circuit is configured to output a gate control signal according to a corresponding start signal, the first clock signal and the second clock signal. Wherein, each gate driving circuit has a first input end and a second input end, the first input end of each gate driving circuit in the first gate driving unit is electrically connected with the first clock line, and the second input end of each gate driving circuit in the first gate driving unit is electrically connected with the second clock line; the first input end of each gate driving circuit in the second gate driving unit is electrically connected with the second clock line, and the second input end of each gate driving circuit in the second gate driving unit is electrically connected with the first clock line. The phase difference between the gate control signal output by the mth gate driving circuit in the first gate driving unit and the gate control signal output by the mth gate driving circuit in the second gate driving unit is (Xn+Y)H; wherein, the period of the first clock signal and the second clock signal is XH, the phase difference between the first clock signal and the second clock signal is YH; X>Y, n>=0, Y>=1, m>=1, and H represents a unit time length.

[0006] The embodiment of the present application provides a display device, which comprises a display panel and any of the above display driving circuits. The display panel comprises a plurality of sub-pixels and a plurality of scanning lines, each of the sub-pixels comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, at least one of the pixel driving circuits comprises a driving transistor, a compensation transistor and a reset transistor, the driving transistor is configured to generate a driving current to drive the light emitting device to emit light, the input end of the reset transistor is configured to receive a reset signal, the output end of the reset transistor is electrically connected with the control end of the driving transistor, and the input end of the compensation transistor is electrically connected with the output end of the driving transistor, and the output end of the compensation transistor is electrically connected with the control end of the driving transistor. Wherein, a plurality of gate control signals generated by the first gate driving unit are output to the control end of the reset transistor of a plurality of sub-pixels, and a plurality of gate control signals generated by the second gate driving unit are output to the control end of the compensation transistor of a plurality of sub-pixels; in the same sub-pixel, the reset transistor is turned on at a first time, the compensation transistor is turned on at a second time, and the time difference between the first time and the second time is XnH+YH. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 is a schematic diagram of a high-frequency and low-frequency picture display principle according to an embodiment of the present application;

[0008] FIG. 2 is a display frequency brightness change trend diagram according to an embodiment of the present application;

[0009] FIGS. 3A-3B are schematic diagrams of a display driving circuit according to an embodiment of the present application;

[0010] FIGS. 4A-4B are schematic diagrams of a gate driving circuit according to an embodiment of the present application;

[0011] FIGS. 5A-5B are timing diagrams of a first clock signal, a second clock signal, and a gate control signal according to an embodiment of the present application;

[0012] FIG. 6 is a schematic diagram of a display device according to an embodiment of the present application;

[0013] FIG. 7 is a schematic diagram of a pixel driving circuit according to an embodiment of the present application;

[0014] FIG. 8 is a timing diagram of a pixel driving circuit corresponding to a write frame and a hold frame according to an embodiment of the present application;

[0015] FIG. 9 is a contrast diagram of full gray scale brightness change at a frequency according to an embodiment of the present application. Embodiments of the present application

[0016] To make the objects, technical solutions and effects of the present application clearer and more explicit, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0017] The display driving circuit and display device according to embodiments of the present application are provided. The first input terminal of each gate driving circuit in the first gate driving unit is electrically connected to the first clock line, and the second input terminal of each gate driving circuit in the first gate driving unit is electrically connected to the second clock line. The first input terminal of each gate driving circuit in the second gate driving unit is electrically connected to the second clock line, and the second input terminal of each gate driving circuit in the second gate driving unit is electrically connected to the first clock line. The phase difference of the gate control signal output by the gate driving circuit in the first gate driving unit compared to the gate control signal output by the gate driving circuit in the second gate driving unit is no longer fixed at 4nH according to the first clock signal and the second clock signal shared by the first gate driving unit and the second gate driving unit.

[0018] Specifically, when the display panel supports the variable frequency display design, the display panel generally has a first display mode and a second display mode, the display panel has a first refresh frequency in the first display mode, and the display panel has a second refresh frequency in the second display mode, and the first refresh frequency can be greater than the second refresh frequency.

[0019] Optionally, the first display mode corresponds to a high-frequency display mode, and the second display mode corresponds to a low-frequency display mode. When the display panel is in the first display mode, a display period of the display panel can include a plurality of write frames, and when the display panel is in the second display mode, a display period of the display panel includes a write frame and at least one hold frame.

[0020] As shown in FIG. 1, which is a high-frequency and low-frequency picture display principle diagram provided by the embodiment of the present application, taking a static picture display of a display panel as an example, if the corresponding refresh frequency in the high-frequency display mode is 120 Hz, then the display panel needs to perform 120 times of refresh operation of display data within 1 second, that is, 120 frames of pictures are included within 1 second (that is, a display period), and display data refresh is performed for each frame of display. If the corresponding refresh frequency in the low-frequency display mode is 1 Hz, then 120 frames of pictures are also included within 1 second (that is, a display period), but only the first frame of picture performs the refresh operation of display data, and the next 119 frames of pictures continuously maintain the picture data signal of the first frame, and do not perform the refresh operation of display data. Among them, the frame that performs the refresh of display data can be recorded as a write frame WF, and the frame that does not perform the refresh of display data can be recorded as a hold frame HF. Therefore, the application of the low-frequency working mode can reduce the working frequency of the driving chip for writing the data signal, which is beneficial to reduce the power consumption of the driving chip. In the mobile display terminal, the application of the low-frequency display mode is also beneficial to prolong the endurance time of the display terminal.

[0021] It can be understood that the length of a display period is not limited to 1 second, and can be different according to actual use.

[0022] FIG. 2 is a display frequency brightness change trend diagram provided by the embodiment of the present application. When the display device automatically switches the display frequency according to the specific use scene, the screen brightness will generally suddenly change, which is called frequency flashing in the industry. The frequency flashing phenomenon can be characterized by testing the screen brightness, as shown in FIG. 2.

[0023] The brightness change rate AL(%) can be used to measure the severity of frequency flashing. Among them, AL(%)=(Ld-Lh) / Ld, Ld represents the brightness of the write frame WF, and Lh represents the brightness of the hold frame HF. The larger the value of AL(%) is, the more serious the frequency flashing phenomenon is.

[0024] The inventors have found that the flicker problem is caused by the different bias intensity of the driving transistor of the sub-pixel in the display panel in the writing frame WF and the holding frame HF. For example, the pixel driving circuit of the sub-pixel undergoes a first reset stage, a second reset stage, a data writing stage, a third reset stage and a light emitting stage. In the first reset stage, a first initial signal is transmitted to the anode of the light emitting device to reset the potential of the anode of the light emitting device; a second initial signal is transmitted to the input terminal and the output terminal of the driving transistor to reset the potential of the input terminal and the output terminal of the driving transistor, and the working voltage stress of the driving transistor in the first reset stage is denoted as OBS1. In the second reset stage, a reset signal is transmitted to the gate of the driving transistor to reset the potential of the control terminal of the driving transistor; the working voltage stress of the driving transistor in the second reset stage is denoted as OBS2. In the data writing stage, a data signal is transmitted to the control terminal of the driving transistor, and the working voltage stress of the driving transistor in the data writing stage is denoted as OBS3. In the third reset stage, the second initial signal is transmitted to the input terminal and the output terminal of the driving transistor to reset the potential of the input terminal and the output terminal of the driving transistor; the working voltage stress of the driving transistor in the third reset stage is denoted as OBS4. In the light emitting stage, the driving transistor generates a driving current to drive the corresponding light emitting device to emit light.

[0025] Due to the hysteresis effect, the electrical characteristics (such as threshold voltage) of the driving transistor will be shifted after the bias effect of the above five stages, and the shift degree is related to the bias intensity of the driving transistor. Table 1 is a bias intensity level table of the driving transistor corresponding to the writing frame WF and the holding frame HF according to the research of the inventors.

[0026]

[0027] As can be seen from Table 1, in the first reset stage and the third reset stage, the bias intensity of the driving transistor corresponding to the writing frame WF and the holding frame HF is the same.

[0028] Since the holding frame HF does not need to perform the refresh operation of the display data, the potential of the control terminal of the driving transistor is not reset by the reset signal in the second reset stage corresponding to the holding frame HF. The bias intensity of the driving transistor in the second reset stage corresponding to the writing frame WF OBS2 is much stronger than the bias intensity of the driving transistor in the second reset stage corresponding to the holding frame HF OBS2'.

[0029] Since the refresh operation of the display data is not needed to be performed on the holding frame HF, the control end of the driving transistor is not written with the data signal in the data writing stage corresponding to the holding frame HF. The bias voltage intensity OBS3 to which the driving transistor is subjected in the data writing stage corresponding to the writing frame WF is weaker than the bias voltage intensity OBS3' to which the driving transistor is subjected in the data writing stage corresponding to the holding frame HF.

[0030] Since the bias voltage intensity to which the driving transistor is subjected is different between the writing frame WF and the holding frame HF, the driving current generated by the driving transistor in the light emitting stage is different in performance, and the display panel displays different brightness between the writing frame WF and the holding frame HF, and flicker phenomenon occurs.

[0031] In order to reduce the brightness difference caused by the hysteresis effect of the driving transistor, it is needed to reduce the intensity difference of the bias voltage to which the driving transistor is subjected between the writing frame WF and the holding frame HF. Therefore, adjusting the intensity of the bias voltage to which the driving transistor is subjected in the second reset stage and the data writing stage becomes the key to improve the flicker problem.

[0032] Alternatively, the adjustment of the bias voltage intensity can be realized by adjusting the applied bias voltage or the length of time for applying the bias voltage. However, in order to ensure the normal operation of the display panel, the driving voltage associated with the adjustment of the bias voltage intensity in the second reset stage and the data writing stage can only be adjusted in a small range, and the adjustable range of the length of time of the data writing stage is also small due to the limitation of the data signal writing time. Therefore, under the appropriate driving voltage setting, adjusting the reset length of time for resetting only the control end potential of the driving transistor in the second reset stage becomes an effective means to improve the flicker problem.

[0033] Resetting only the control end potential of the driving transistor needs to control the time for turning on the transistor (a reset transistor as described below) which is electrically connected to the control end of the driving transistor and is used to realize the function of resetting the control end potential of the driving transistor. However, since the working states of the multiple transistors included in a sub-pixel are all controlled by the gate control signal, and the gate driving circuit for generating the gate control signal usually adopts a fixed 4H period clock signal, the reset length of time for resetting only the control end potential of the driving transistor in the writing frame WF is fixed as 4nH. Wherein, n≥0, and H represents a unit length of time, and H can be equal to the row scanning period in the display panel (i.e. the time for scanning one row of sub-pixels). Therefore, due to the limitation of the driving circuit setting, it is difficult to realize the reset length of time for resetting only the control end potential of the driving transistor as non-4nH.

[0034] Therefore, the present application provides a display driving circuit and a display device, which can adjust the reset length of time corresponding to the reset of only the control end potential of the driving transistor, so that the reset length of time can not be an integer multiple of the clock signal period.

[0035] FIGS. 3A-3B are schematic block diagrams of a display driving circuit including a first clock line CKL1, a second clock line CKL2, and a gate driving module GDC, according to embodiments of the present disclosure.

[0036] The first clock line CKL1 is configured to transmit a first clock signal CK1, and the second clock line CKL2 is configured to transmit a second clock signal CK2.

[0037] The gate driving module GDC includes a first gate driving unit GDC1 and a second gate driving unit GDC2. The first gate driving unit GDC1 and the second gate driving unit GDC2 each include a plurality of cascaded gate driving circuits GOA, and each gate driving circuit GOA is configured to output a gate control signal Scan according to a corresponding start signal stv, the first clock signal CK1, and the second clock signal CK2.

[0038] The first input end IN1 of each gate drive circuit GOA in the first gate drive unit GDC1 is electrically connected with the first clock line CKL1, and the second input end IN2 of each gate drive circuit GOA in the first gate drive unit GDC1 is electrically connected with the second clock line CKL2. The first input end IN1 of each gate drive circuit GOA in the second gate drive unit GDC2 is electrically connected with the second clock line CKL2, and the second input end IN2 of each gate drive circuit GOA in the second gate drive unit GDC2 is electrically connected with the first clock line CKL1, as shown in FIG. 3B. According to the first clock signal CK1 and the second clock signal CK2 shared by the first gate drive unit GDC1 and the second gate drive unit GDC2, the phase difference between the gate control signal (denoted as the first gate control signal Scan1) output by each stage of gate drive circuit GOA in the first gate drive unit GDC1 and the gate control signal (denoted as the second gate control signal Scan2) output by the gate drive circuit GOA of the same stage in the second gate drive unit GDC2 is (Xn+Y)H, so that the phase difference between the gate control signal output by each stage of gate drive circuit GOA in the first gate drive unit GDC1 and the gate control signal output by the gate drive circuit GOA of the same stage in the second gate drive unit GDC2 is no longer fixed as 4nH, thereby adjusting the reset time length of the write frame WF only for the control end potential of the driving transistor when the display panel applies the display driving circuit to realize display, i.e., the reset time length can be not an integer multiple of the clock signal period, and thus the flicker problem of different display panels is improved. The period of the first clock signal CK1 and the second clock signal CK2 is XH, and the phase difference between the first clock signal CK1 and the second clock signal CK2 is YH; X>Y, n≥0, Y≥1, and H represents a unit time length.

[0039] For example, the phase difference between the gate control signal output by the mth stage of gate drive circuit GOA(m) in the first gate drive unit GDC1 and the gate control signal output by the mth stage of gate drive circuit GOA(m) in the second gate drive unit GDC2 is (Xn+Y)H. Correspondingly, the gate control signal output by the mth stage of gate drive circuit GOA(m) in the first gate drive unit GDC1 has a valid level starting from the first time tm1, and the gate control signal output by the mth stage of gate drive circuit GOA(m) in the second gate drive unit GDC2 has a valid level starting from the second time tm2, and the time difference between the first time tm1 and the second time tm2 is (Xn+Y)H; wherein m≥1.

[0040] Optionally, the first time tm1 is before or after the second time tm2.

[0041] Optionally, in the same gate driving unit, the start signal stv received by the first M-stage gate driving circuit GOA in the multi-stage gate driving circuit GOA is a starting signal, and the gate control signal Scan output by the previous-stage gate driving circuit GOA is taken as the start signal stv by the multi-stage gate driving circuit GOA cascaded after the Mth-stage gate driving circuit GOA. Wherein, M≥1.

[0042] Optionally, in the same gate driving unit, the start signal stv received by the first-stage gate driving circuit GOA(1) is a starting signal, and the start signal stv received by the Nth-stage gate driving circuit GOA is the gate control signal Scan output by the N-Zth-stage gate driving circuit GOA. Wherein, N>1, Z≥1.

[0043] In the first gate driving unit GDC1, the start signal stv received by the first-stage gate driving circuit GOA(1) is the first starting signal STV1, the start signal stv received by the second-stage gate driving circuit GOA is the first gate control signal Scan1(1) output by the first-stage gate driving circuit GOA(1), and so on, so that the start signal stv received by the Nth-stage gate driving circuit GOA(N) is the first gate control signal Scan1(N-1) output by the N-1th-stage gate driving circuit GOA(N-1). In the second gate driving unit GDC2, the start signal stv received by the first-stage gate driving circuit GOA(1) is the second starting signal STV2, the start signal stv received by the second-stage gate driving circuit GOA(2) is the second gate control signal Scan2(1) output by the first-stage gate driving circuit GOA(2), and so on, so that the start signal stv received by the Nth-stage gate driving circuit GOA(N) is the second gate control signal Scan2(N-1) output by the N-1th-stage gate driving circuit GOA(N-1).

[0044] Optionally, the first start signal STV1 and the second start signal STV2 can have a phase difference. The phase difference between the first start signal STV1 and the second start signal STV2 can be determined according to a phase difference of the gate control signals output by the gate drive circuits GOA at the same stage in the first gate drive unit GDC1 compared with the gate control signals output by the gate drive circuits GOA at the same stage in the second gate drive unit GDC2. For example, if the period difference of the gate control signals output by the gate drive circuits GOA at the same stage in the first gate drive unit GDC1 compared with the gate control signals output by the gate drive circuits GOA at the same stage in the second gate drive unit GDC2 is NH, then the phase difference between the first start signal STV1 and the second start signal STV2 is NH. Wherein, N≥1.

[0045] Optionally, the timing controller can be used to provide the first clock signal CK1, the second clock signal CK2, the first start signal STV1 and the second start signal STV2 required by the first gate drive unit GDC1 and the second gate drive unit GDC2.

[0046] FIGS. 4A-4B are structural schematic diagrams of the gate drive circuit according to an embodiment of the present application, each of the gate drive circuits GOA includes a node control module 11 and an output module 12.

[0047] The node control module 11 is electrically connected with the first input end IN1, the second input end IN2, the first node N1 and the second node N2. The node control module 11 receives the corresponding start signal stv, the first clock signal CK1 and the second clock signal CK2 to control the signals transmitted to the first node N1 and the second node N2.

[0048] The output module 12 is electrically connected with the first node N1 and the second node N2. The output module 12 is configured to output the gate control signal Scan according to the signals of the first node N1 and the second node N2.

[0049] Optionally, the node control module 11 of at least one gate drive circuit GOA includes the first transistor T1 to the tenth transistor T10, the first capacitor C1 and the second capacitor C2.

[0050] The control end of the first transistor T1 is electrically connected with the first input end IN1. The input end of the first transistor T1 is electrically connected with the first voltage end VGL.

[0051] The control end of the second transistor T2 is electrically connected with the first input end IN1. The input end of the second transistor T2 is configured to receive the corresponding start signal stv.

[0052] The control end of the third transistor T3 is electrically connected with the output end of the second transistor T2, the input end of the third transistor T3 is electrically connected with the first input end IN1, and the output end of the third transistor T3 is electrically connected with the output end of the first transistor T1.

[0053] The control end of the fourth transistor T4 is electrically connected with the output end of the first transistor T1, and the input end of the fourth transistor T4 is electrically connected with the second voltage end VGH.

[0054] The control end of the fifth transistor T5 is electrically connected with the second node N2, the input end of the fifth transistor T5 is electrically connected with the second input end IN2, and the output end of the fifth transistor T5 is electrically connected with the output end of the fourth transistor T4.

[0055] The input end of the sixth transistor T6 is electrically connected with the second input end IN2.

[0056] The control end of the seventh transistor T7 is electrically connected with the second input end IN2, the input end of the seventh transistor T7 is electrically connected with the output end of the sixth transistor T6, and the output end of the seventh transistor T7 is electrically connected with the first node N1.

[0057] The control end of the eighth transistor T8 is electrically connected with the output end of the second transistor T2, the input end of the eighth transistor T8 is electrically connected with the second voltage end VGH, and the output end of the eighth transistor T8 is electrically connected with the first node N1.

[0058] The control end of the ninth transistor T9 is electrically connected with the first voltage end VGL, the input end of the ninth transistor T9 is electrically connected with the output end of the first transistor T1, and the output end of the ninth transistor T9 is electrically connected with the control end of the sixth transistor T6.

[0059] The control end of the tenth transistor T10 is electrically connected with the first voltage end VGL, the input end of the tenth transistor T10 is electrically connected with the output end of the second transistor T2, and the output end of the tenth transistor T10 is electrically connected with the second node N2.

[0060] The first end of the first capacitor C1 is electrically connected with the output end of the fifth transistor T5, and the second end of the first capacitor C1 is electrically connected with the control end of the fifth transistor T5.

[0061] The first end of the second capacitor C2 is electrically connected with the output end of the sixth transistor T6, and the second end of the second capacitor C2 is electrically connected with the control end of the sixth transistor T6.

[0062] Optionally, referring to FIG. 4B, the node control module 11 of the at least one gate drive circuit GOA includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

[0063] The control terminal of the eleventh transistor T11 is electrically connected with the control terminal of the fifth transistor T5, the input terminal of the eleventh transistor T11 is electrically connected with the control terminal of the eleventh transistor T11, and the output terminal of the eleventh transistor T11 is electrically connected with the second node N2.

[0064] The control terminal of the twelfth transistor T12 is electrically connected with the first input terminal IN1, and the input terminal of the twelfth transistor T12 is configured to receive a corresponding start signal stv.

[0065] The control terminal of the thirteenth transistor T13 is electrically connected with the first voltage terminal VGL, the input terminal of the thirteenth transistor T13 is electrically connected with the output terminal of the twelfth transistor T12, and the output terminal of the thirteenth transistor T13 is electrically connected with the control terminal of the eleventh transistor T11.

[0066] Optionally, the ninth transistor T9, the tenth transistor T10 and the thirteenth transistor T13 can always work in the on state.

[0067] Optionally, the circuit topology of the gate drive circuit GOA of the first gate drive unit GDC1 can be the same as or different from the circuit topology of the gate drive circuit GOA of the second gate drive unit GDC2.

[0068] It can be understood that the circuit topology of the node control module 11 included in the gate drive circuit GOA of the first gate drive unit GDC1 can be the same as or different from the circuit topology of the node control module 11 included in the gate drive circuit GOA of the second gate drive unit GDC2. That is, the circuit topology of the node control module 11 included in the gate drive circuit GOA of the first gate drive unit GDC1 can be as shown in FIG. 4A or FIG. 4B, and the circuit topology of the node control module 11 included in the gate drive circuit GOA of the second gate drive unit GDC2 can be as shown in FIG. 4A or as shown in FIG. 4B.

[0069] Please continue to refer to FIGS. 4A-4B. The output module 12 of at least one gate drive circuit GOA includes a first output transistor To1, a second output transistor To2 and a third capacitor C3.

[0070] The control terminal of the first output transistor To1 is electrically connected with the first node N1, the input terminal of the first output transistor To1 is electrically connected with the second voltage terminal VGH, and the output terminal of the first output transistor To1 is electrically connected with the signal output terminal of the output gate control signal Scan.

[0071] The control end of the second output transistor To2 is electrically connected with the second node N2, the input end of the second output transistor To2 is electrically connected with the first voltage end VGL, and the output end of the second output transistor To2 is electrically connected with the signal output end.

[0072] The first end of the third capacitor C3 is electrically connected with the output end of the first output transistor To1, and the second end of the third capacitor C3 is electrically connected with the control end of the first output transistor To1.

[0073] Optionally, the node control module 11 further includes a power-on reset transistor Ta, the control end of the power-on reset transistor Ta receives a power-on reset control signal CL, the input end of the power-on reset transistor Ta is electrically connected with the second voltage end VGH, and the output end of the power-on reset transistor Ta is electrically connected with the output end of the second transistor T2.

[0074] FIGS. 5A-5B are timing diagrams of the first clock signal, the second clock signal and the gate control signal provided by the embodiment of the present application. Please continue to refer to FIG. 3A and FIG. 5A, if the first input end IN1 of each gate drive circuit GOA in the first gate drive unit GDC1 and the first input end IN1 of each gate drive circuit GOA in the second gate drive unit GDC2 are electrically connected with the first clock line CKL1, and the second input end IN2 of each gate drive circuit GOA in the first gate drive unit GDC1 and the second input end IN2 of each gate drive circuit GOA in the second gate drive unit GDC2 are electrically connected with the second clock line CKL2 (for example, the control end of the first transistor T1, the control end of the second transistor T2 and the input end of the third transistor T3 of each gate drive circuit GOA in the first gate drive unit GDC1 and the second gate drive unit GDC2 all receive the first clock signal CK1, and the input end of the fifth transistor T5, the input end of the sixth transistor T6 and the control end of the seventh transistor T7 all receive the second clock signal CK2), then the phase difference between the gate control signal outputted by each stage of gate drive circuit GOA in the first gate drive unit GDC1 and the gate control signal outputted by the same stage of gate drive circuit GOA in the second gate drive unit GDC2 is fixed as an integer multiple of the clock signal period.

[0075] For example, the period of the clock signal is 4H, and each transistor included in the gate drive circuit GOA is a P-type transistor.

[0076] In the first stage S1, the first clock signal CK1 is low, the second clock signal CK2 is high, the first start signal STV1 corresponding to the first stage of gate drive circuit GOA(1) in the first gate drive unit GDC1 is low, and the second start signal STV2 corresponding to the first stage of gate drive circuit GOA(1) in the second gate drive unit GDC2 is low.

[0077] In the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 and the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the seventh transistor T7 and the first output transistor To1 are turned off, and the first gate control signal Scan1(1) output by the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 and the second gate control signal Scan2(1) output by the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 each have a low level.

[0078] The second stage S2: the first clock signal CK1 is high, the second clock signal CK2 is low, the first start signal STV1 is low, and the second start signal STV2 is low.

[0079] In the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 and the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the first output transistor To1 are turned off, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the second output transistor To2 are turned on, and the first gate control signal Scan1(1) output by the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 and the second gate control signal Scan2(1) output by the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 each have a low level.

[0080] The third stage S3: the first clock signal CK1 is low, the second clock signal CK2 is high, the first start signal STV1 is high, and the second start signal STV2 is low.

[0081] In the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned on, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the first output transistor To1, and the second output transistor To2 are turned off, and the first gate control signal Scan1(1) output by the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 has a low level.

[0082] The first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as that in the second stage S2 in the fourth stage S4, so that the second gate control signal Scan2(1) outputted by the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0083] The fourth stage S4: the first clock signal CK1 is high level, the second clock signal CK2 is low level, the first start signal STV1 is high level, and the second start signal STV2 is low level.

[0084] In the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the first output transistor To1 are turned on, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the second output transistor To2 are turned off, and the first gate control signal Scan1(1) outputted by the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 has a high level.

[0085] The first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as that in the second stage S2 in the fourth stage S4, so that the second gate control signal Scan2(1) outputted by the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0086] The fifth stage S5: the first clock signal CK1 is low level, the second clock signal CK2 is high level, the first start signal STV1 is high level, and the second start signal STV2 is high level.

[0087] In the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the first output transistor To1 are turned on, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the second output transistor To2 are turned off, and the first gate control signal Scan1(1) outputted by the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 has a high level.

[0088] The first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as that in the third stage S3 of the first-stage gate driver circuit GOA(1) of the first gate drive unit GDC1 in the fifth stage S5, so that the second gate control signal Scan2(1) outputted by the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0089] Sixth stage S6: the first clock signal CK1 is high, the second clock signal CK2 is low, the first start signal STV1 is low, and the second start signal STV2 is high.

[0090] The first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 and the second gate drive unit GDC2 performs the same operation as the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 in the fourth stage S4 in the sixth stage S6, the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 outputs the first gate control signal Scan1(1) with a high level, and the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 outputs the second gate control signal Scan2(1) with a high level.

[0091] Seventh stage S7: the first clock signal CK1 is low, the second clock signal CK2 is high, the first start signal STV1 is low, and the second start signal STV2 is high.

[0092] The first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 performs the same operation as the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 in the first stage S1 in the seventh stage S7, and the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 outputs the first gate control signal Scan1(1) with a low level. However, due to the charging rate of the first capacitor C1, the first gate control signal Scan1(1) output by the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 has a charging delay phenomenon.

[0093] The first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 in the fifth stage S5 in the seventh stage S7, and the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 outputs the second gate control signal Scan2(1) with a high level.

[0094] Eighth stage S8: the first clock signal CK1 is high, the second clock signal CK2 is low, the first start signal STV1 is low, and the second start signal STV2 is low.

[0095] The first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 performs the same operation as that of the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 in the second stage S2 in the eighth stage S8, and the first gate control signal Scan1(1) output from the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 has a low level.

[0096] The first-stage gate driver circuit GOA(1) of the second gate driver unit GDC2 performs the same operation as that of the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 in the sixth stage S6 in the eighth stage S8, and the second gate control signal Scan2(1) output from the first-stage gate driver circuit GOA(1) of the second gate driver unit GDC2 has a high level.

[0097] Ninth stage S9: the first clock signal CK1 is low, the second clock signal CK2 is high, the first start signal STV1 is low, and the second start signal STV2 is low.

[0098] The first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 performs the same operation as that of the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 in the first stage S1 in the ninth stage S9, and the first gate control signal Scan1(1) output from the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 has a low level.

[0099] The first-stage gate driver circuit GOA(1) of the second gate driver unit GDC2 performs the same operation as that of the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 in the seventh stage S7 in the ninth stage S9, and the second gate control signal Scan2(1) output from the first-stage gate driver circuit GOA(1) of the second gate driver unit GDC2 has a low level.

[0100] Therefore, the first gate control signal Scan1(1) output from the first-stage gate driver circuit GOA(1) of the first gate driver unit GDC1 and the second gate control signal Scan2(1) output from the first-stage gate driver circuit GOA(1) of the second gate driver unit GDC2 have a phase difference of 4H.

[0101] It should be noted that the phase difference between the first gate control signal Scan1 and the second gate control signal Scan2 is 4H, i.e. the corresponding time interval between the rising edge of the first gate control signal Scan1 and the rising edge of the second gate control signal Scan2 in one period is 4H, or the corresponding time interval between the falling edge of the first gate control signal Scan1 and the falling edge of the second gate control signal Scan2 in one period is 4H.

[0102] In the above embodiment, the phase difference between the first gate control signal Scan1 and the second gate control signal Scan2 is 4H. However, even if the phase difference between the first start signal STV1 and the second start signal STV2 is set to be greater than 0H and less than 4H, the phase difference between the first gate control signal Scan1 output by the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 and the second gate control signal Scan2 output by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 is also 4H. In order to make the pulse width of the effective pulse of the multi-stage gate control signal Scan consistent, the phase difference between the first start signal STV1 and the second start signal STV2 is set to be 4nH, so that the phase difference between the gate control signal output by each stage gate drive circuit GOA in the first gate drive unit GDC1 and the gate control signal output by the gate drive circuit GOA of the same stage in the second gate drive unit GDC2 is also fixed to be 4nH.

[0103] Please continue to refer to FIG. 3B and FIG. 5B, in the first stage S1, the first input end IN1 of each gate drive circuit GOA in the first gate drive unit GDC1 and the second input end IN2 of each gate drive circuit GOA in the second gate drive unit GDC2 are electrically connected with the first clock line CKL1, and the second input end IN2 of each gate drive circuit GOA in the first gate drive unit GDC1 and the first input end IN1 of each gate drive circuit GOA in the second gate drive unit GDC2 are electrically connected with the second clock line CKL2 (for example, the control end of the first transistor T1, the control end of the second transistor T2, and the input end of the third transistor T3 of the gate drive circuit GOA in the first gate drive unit GDC1 all receive the first clock signal CK1, the input end of the fifth transistor T5, the input end of the sixth transistor T6, and the control end of the seventh transistor T7 of the gate drive circuit GOA in the second gate drive unit GDC2 all receive the first clock signal CK1, the control end of the first transistor T1, the control end of the second transistor T2, and the input end of the third transistor T3 of the gate drive circuit GOA in the second gate drive unit GDC2 all receive the second clock signal CK2, the input end of the fifth transistor T5, the input end of the sixth transistor T6, and the control end of the seventh transistor T7 of the gate drive circuit GOA in the first gate drive unit GDC1 all receive the second clock signal CK2). Then, the phase difference of the gate control signal output by each stage of the gate drive circuit GOA in the first gate drive unit GDC1 compared with the gate control signal output by the same stage of the gate drive circuit GOA in the second gate drive unit GDC2 can be set as XnH+YH.

[0104] As please continue to refer to FIG. 3B and FIG. 5B, still taking the period of the clock signal as 4H and taking each transistor included in the gate drive circuit GOA as a P-type transistor as an example for description. The working principle of the first stage of the gate drive circuit GOA(1) in the first gate drive unit GDC1 corresponding to the timing of FIG. 5B can refer to the related description of FIG. 5A.

[0105] In a stage Sa before the first stage S1: the first clock signal CK1 is high, the second clock signal CK2 is low, the first start signal STV1 corresponding to the first stage of the gate drive circuit GOA(1) in the first gate drive unit GDC1 is low, and the second start signal STV2 corresponding to the first stage of the gate drive circuit GOA(1) in the second gate drive unit GDC2 is low.

[0106] In the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the seventh transistor T7 and the first output transistor To1 are turned off, and the second gate control signal Scan2(1) output from the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0107] The first stage S1: the first clock signal CK1 is low, the second clock signal CK2 is high, the first start signal STV1 is low, and the second start signal STV2 is low.

[0108] In the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the first output transistor To1 are turned off, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the second output transistor To2 are turned on, and the second gate control signal Scan2(1) output from the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0109] The second stage S2: the first clock signal CK1 is high, the second clock signal CK2 is low, the first start signal STV1 is low, and the second start signal STV2 is low.

[0110] In the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the seventh transistor T7 and the first output transistor To1 are turned off, and the second gate control signal Scan2(1) output from the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0111] The third stage S3: the first clock signal CK1 is low, the second clock signal CK2 is high, the first start signal STV1 is high, and the second start signal STV2 is low.

[0112] The first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as the first stage S1 in the third stage S3, so that the second gate control signal Scan2(1) output from the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has a low level.

[0113] The fourth stage S4: the first clock signal CK1 is high level, the second clock signal CK2 is low level, the first start signal STV1 is high level, and the second start signal STV2 is low level.

[0114] The first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as that in the second stage S2 in the fourth stage S4, so that the second gate control signal Scan2(1) output by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has low level.

[0115] The fifth stage S5: the first clock signal CK1 is low level, the second clock signal CK2 is high level, the first start signal STV1 is high level, and the second start signal STV2 is low level.

[0116] The first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as that in the third stage S3 in the fifth stage S5, so that the second gate control signal Scan2(1) output by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has low level.

[0117] The sixth stage S6: the first clock signal CK1 is high level, the second clock signal CK2 is low level, the first start signal STV1 is low level, and the second start signal STV2 is high level.

[0118] In the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned on, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the first output transistor To1, and the second output transistor To2 are turned off, and the second gate control signal Scan2(1) output by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has low level.

[0119] The seventh stage S7: the first clock signal CK1 is low level, the second clock signal CK2 is high level, the first start signal STV1 is low level, and the second start signal STV2 is high level.

[0120] In the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, and the second output transistor To2 are turned off, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the first output transistor To1 are turned on, and the second gate control signal Scan2(1) output from the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 has a high level.

[0121] The eighth stage S8: the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the first start signal STV1 is at a low level, and the second start signal STV2 is at a high level.

[0122] In the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2, the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the first output transistor To1 are turned on, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the second output transistor To2 are turned off, and the second gate control signal Scan2(1) output from the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 has a high level.

[0123] The ninth stage S9: the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the first start signal STV1 is at a low level, and the second start signal STV2 is at a low level.

[0124] The first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 performs the same operation as the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 in the seventh stage S7 in the ninth stage S9, and the second gate control signal Scan2(1) output from the first-stage gate driver circuit GOA(1) of the second gate drive unit GDC2 has a high level.

[0125] The tenth stage S10: the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the first start signal STV1 is at a low level, and the second start signal STV2 is at a low level.

[0126] The first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 performs similar operation as the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 in the second stage S2 in the tenth stage S10, and the second gate control signal Scan2(1) outputted by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has a low level. Wherein, the second gate control signal Scan2(1) outputted by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 has a charging delay phenomenon due to the influence of the first capacitor C1 charging rate.

[0127] Therefore, the phase difference between the first gate control signal Scan1(1) outputted by the first-stage gate drive circuit GOA(1) of the first gate drive unit GDC1 and the second gate control signal Scan2(1) outputted by the first-stage gate drive circuit GOA(1) of the second gate drive unit GDC2 is 6H. That is, the time difference between the rising edge of the first gate control signal Scan1 and the rising edge of the second gate control signal Scan2 in one period is 6H.

[0128] Wherein, in order to make the pulse width of the effective pulse of the multi-stage gate control signal Scan consistent, the phase difference between the first start signal STV1 and the second start signal STV2 is determined after the phase difference between the gate control signals outputted by the gate drive circuits GOA of the first gate drive unit GDC1 and the gate control signals outputted by the gate drive circuits GOA of the second gate drive unit GDC2 is determined. Therefore, the phase difference between the first start signal STV1 and the second start signal STV2 generally remains consistent with the phase difference between the first gate control signal Scan1 and the second gate control signal Scan2.

[0129] It can be understood that in the same gate drive unit, the multi-stage gate drive circuit GOA cascaded after the first-stage gate drive circuit GOA(1) takes the gate control signal Scan outputted by the previous-stage gate drive circuit GOA as the start signal stv, and then cooperates with the first clock signal CK1 and the second clock signal CK2 to realize the working principle of the gate control signal Scan outputted by the current-stage gate drive circuit GOA. The working principle can be obtained by referring to the working principle of the first-stage gate drive circuit GOA(1) applying the first start signal STV1 or the second start signal STV2 to cooperate with the first clock signal CK1 and the second clock signal CK2 to output the first gate control signal Scan1 or the second gate control signal Scan2.

[0130] Optionally, in some embodiments, X=2Y, accordingly, XnH+YH=XnH+(X / 2)H, to make the time difference between the first time tm1 and the second time tm2 adjustable in the range of (X / 2)H on the basis of the cycle of the first clock signal CK1 and the second clock signal CK2 being fixed.

[0131] Optionally, X=4, Y=2, then XnH+YH=4nH+2H. That is, to make the setting of XnH+YH equal to 2H, 6H, 10H, etc.

[0132] It can be understood that, in some embodiments, the multiple of X and Y can also not be 2. For example, X=3Y, then XnH+YH=3nH+1H; that is, to make the setting of XnH+YH equal to 1H, 4H, 7H, etc. Similarly, X=4Y, etc. can also be set. Thus, X=PY, P≥2.

[0133] Optionally, X can be 2, 4, 6, 8, 9, 10, 12, 14, 15, 16, 18, 20, etc.

[0134] FIG. 6 is a structural schematic diagram of a display device provided by an embodiment of the present application, the display device comprising any of the display driving circuits and the display panel 20 described above.

[0135] The display driving circuit is electrically connected with the display panel 20, and the display panel 20 comprises a plurality of sub-pixels Spi. The display driving circuit comprises a first gate driving unit GDC1 and a second gate driving unit GDC2, which are configured to output a plurality of gate control signals Scan to the display panel 20, so as to control the reset time length corresponding to the control end potential reset of the driving transistor Tda of the plurality of sub-pixels Spi in the display panel 20.

[0136] FIG. 7 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application. Each sub-pixel Spi comprises a light emitting device Di and a pixel driving circuit configured to drive the light emitting device Di to emit light. At least one pixel driving circuit comprises a driving transistor Tda, a compensation transistor Tc, and a reset transistor Tr. The driving transistor Tda is configured to generate a driving current to drive the light emitting device Di to emit light. The input end of the reset transistor Tr is configured to receive a reset signal Vr. The output end of the reset transistor Tr is electrically connected with the control end of the driving transistor Tda. The input end of the compensation transistor Tc is electrically connected with the output end of the driving transistor Tda. The output end of the compensation transistor Tc is electrically connected with the control end of the driving transistor Tda.

[0137] The multiple gate control signals generated by the first gate drive unit GDC1 are output to the control end of the reset transistor Tr of the multiple sub-pixels Spi, and the multiple gate control signals generated by the second gate drive unit GDC2 are output to the control end of the compensation transistor Tc of the multiple sub-pixels Spi; the reset transistor Tr in the same sub-pixel Spi is turned on earlier than the compensation transistor Tc.

[0138] By making the control end of the reset transistor Tr receive the gate control signal output by the first gate drive unit GDC1 and the control end of the compensation transistor Tc receive the gate control signal output by the second gate drive unit GDC2, the reset transistor Tr and the compensation transistor Tc can control the reset duration when only the control end of the driving transistor Tda is reset according to the received gate control signal.

[0139] Alternatively, in the same sub-pixel Spi, the reset transistor Tr is turned on at the first time tm1, and the compensation transistor Tc is turned on at the second time tm2, and the time difference between the first time tm1 and the second time tm2 is XnH+YH. That is, the gate control signal received by the control end of the reset transistor Tr has an effective level at the first time tm1, so that the reset transistor Tr can be controlled to be turned on at the first time tm1. The gate control signal received by the control end of the compensation transistor Tc has an effective level at the second time tm2, so that the compensation transistor Tc can be controlled to be turned on at the second time tm2. Therefore, according to the above description of the display driving circuit, the time difference between the first time tm1 and the second time tm2 can be XnH+YH.

[0140] Alternatively, in a sub-pixel Spi, the gate control signal received by the control end of the reset transistor Tr corresponds to the gate control signal output by the mth gate drive circuit GOA(m) in the first gate drive unit GDC1, and the gate control signal received by the control end of the compensation transistor Tc corresponds to the gate control signal output by the mth gate drive circuit GOA(m) in the second gate drive unit GDC2, so that in the same sub-pixel Spi, the time difference between the turn-on of the reset transistor Tr and the compensation transistor Tc is XnH+YH.

[0141] Alternatively, the display panel 20 includes multiple first gate lines GL1 and multiple second gate lines GL2, wherein the control end of the reset transistor Tr of the multiple sub-pixels Spi receives the corresponding gate control signal through the corresponding first gate line GL1, and the control end of the compensation transistor Tc of the multiple sub-pixels Spi receives the corresponding gate control signal through the corresponding second gate line GL2.

[0142] Optionally, the write frame WF can correspond to at least one stage in which the reset transistor Tr remains turned on and the compensation transistor Tc remains turned off, and the duration of the stage is equal to the time difference between the first time tm1 and the second time tm2. Optionally, the starting time of the stage is the same as the first time tm1, and the ending time of the stage is the same as the second time tm2. Optionally, the write frame WF including the stage can correspond to a write frame in the first display mode, or can correspond to a write frame in the second display mode.

[0143] Optionally, the stage can be a second reset stage Si2 described below. However, it can be understood that, depending on the circuit topology of the pixel driving circuit, the control method applied to the pixel driving circuit, and / or the number of devices (including transistors, capacitors, etc.) included in the pixel driving circuit, the stage can not be limited to being located between the first reset stage Si1 and the data write stage Sw described below.

[0144] Please continue to refer to FIGS. 6-7, the display panel 20 includes a plurality of first scan lines SL1, a plurality of second scan lines SL2, a plurality of light-emitting control lines EML, and a plurality of data lines DL. The pixel driving circuit includes a data transistor Tda, a first light-emitting control transistor Te1, a second light-emitting control transistor Te2, a first initial transistor Ti1, a second initial transistor Ti2, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0145] The control terminal of the data transistor Tda is electrically connected to the first scan line SL1, the input terminal of the data transistor Tda is electrically connected to the corresponding data line DL, the input terminal of the data transistor Tda is configured to receive a data signal, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the driving transistor Tda.

[0146] The control terminal of the first light-emitting control transistor Te1 is electrically connected to the light-emitting control line EML, the input terminal of the first light-emitting control transistor Te1 is electrically connected to the first power supply terminal Vdd, and the output terminal of the first light-emitting control transistor Te1 is electrically connected to the input terminal of the driving transistor Tda.

[0147] The control terminal of the second light-emitting control transistor Te2 is electrically connected to the light-emitting control line EML, the input terminal of the second light-emitting control transistor Te2 is electrically connected to the output terminal of the driving transistor Tda, and the output terminal of the second light-emitting control transistor Te2 is electrically connected to the anode of the light-emitting device Di.

[0148] The control terminal of the first initial transistor Ti1 is electrically connected with the second scan line SL2, the input terminal of the first initial transistor Ti1 is electrically connected with the first initial line VL1, the output terminal of the first initial transistor Ti1 is electrically connected with the anode of the light emitting device Di, and the cathode of the light emitting device Di is electrically connected with the second power supply end Vss.

[0149] The control terminal of the second initial transistor Ti2 is electrically connected with the second scan line SL2, the input terminal of the second initial transistor Ti2 is electrically connected with the second initial line VL2, and the output terminal of the second initial transistor Ti2 is electrically connected with the input terminal of the driving transistor Tda.

[0150] The first terminal of the first storage capacitor Cst1 is electrically connected with the control terminal of the driving transistor Tda, and the second terminal of the first storage capacitor Cst1 is electrically connected with the first power supply end Vdd.

[0151] The first terminal of the second storage capacitor Cst2 is electrically connected with the control terminal of the driving transistor Tda, and the second terminal of the second storage capacitor Cst2 is electrically connected with the control terminal of the data transistor Tda.

[0152] Optionally, in some embodiments, the pixel driving circuit can not be provided with at least one of the second initial transistor Ti2 and the second storage capacitor Cst2.

[0153] Optionally, please continue to refer to FIG. 6, the display driving circuit can further include a third gate driving unit GDC3, a fourth gate driving unit GDC4 and a fifth gate driving unit GDC5. The third gate driving unit GDC3 includes a multi-stage gate driving circuit GOA electrically connected with the plurality of first scan lines SL1, and is configured to output a plurality of first scan signals ScanF to the control end of the data transistor Tda of the plurality of sub-pixels Spi. The fourth gate driving unit GDC4 includes a multi-stage gate driving circuit GOA electrically connected with the plurality of second scan lines SL2, and is configured to output a plurality of second scan signals Scans to the control end of the first initial transistor Ti1 and the second initial transistor Ti2 of the plurality of sub-pixels Spi. The fifth gate driving unit GDC5 includes a multi-stage gate driving circuit GOA electrically connected with the plurality of emission control lines EML, and is configured to output a plurality of emission control signals EM to the control end of the first emission control transistor Te1 and the second emission control transistor Te2 of the plurality of sub-pixels Spi. The gate driving circuit GOA included in the third gate driving unit GDC3, the fourth gate driving unit GDC4 and the fifth gate driving unit GDC5 can adopt the circuit structure shown in FIGS. 4A-4B. The matching relationship between the gate driving circuit GOA included in the third gate driving unit GDC3, the fourth gate driving unit GDC4 and the fifth gate driving unit GDC5 and the first clock signal CK1 and the second clock signal CK2 can be the same as the matching design between the first gate driving unit GDC1 or the second gate driving unit GDC2 and the first clock signal CK1 and the second clock signal CK2.

[0154] FIG. 8 is a timing diagram of the pixel driving circuit corresponding to the writing frame and the holding frame according to an embodiment of the present application. Please continue to refer to FIGS. 7-8. In order to compensate for the transistor Tc and the reset transistor Tr being N-type transistors, and the driving transistor Tda, the data transistor Tda, the first emission control transistor Te1, the second emission control transistor Te2, the first initial transistor Ti1 and the second initial transistor Ti2 being P-type transistors, the working principle of the first pair of pixel driving circuits is described.

[0155] In the first reset stage Si1, the light emitting control signal EM transmitted by the light emitting control line EML, the first scan signal ScanF transmitted by the first scan line SL1, and the second scan signal Scans transmitted by the second scan line SL2 are high level, the gate control signal (i.e. the first gate control signal Scan1) received by the reset transistor Tr and the gate control signal (i.e. the second gate control signal Scan2) received by the compensation transistor Tc are low level. The first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light emitting device Di to reset the potential of the anode of the light emitting device Di; the second initial signal transmitted by the second initial line VL2 is transmitted to the input and output of the driving transistor Tda to reset the potential of the input and output of the driving transistor Tda.

[0156] In the second reset stage Si2, the first gate control signal Scan1, the light emitting control signal EM, the first scan signal ScanF, and the second scan signal Scans are high level, and the second gate control signal Scan2 is low level. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the driving transistor Tda to reset the potential of the control terminal of the driving transistor Tda.

[0157] In the data writing stage Sw, the second gate control signal Scan2, the light emitting control signal EM, and the second scan signal Scans are high level, and the first gate control signal Scan1 and the first scan signal ScanF are low level. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tda.

[0158] In the data writing stage Sw, the second gate control signal Scan2, the light emitting control signal EM, and the second scan signal Scans are high level, and the first gate control signal Scan1 and the first scan signal ScanF are low level. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tda.

[0159] In the third reset stage Si3, the light emitting control signal EM and the first scan signal ScanF are high level, the first gate control signal Scan1, the second gate control signal Scan2, and the second scan signal Scans are low level, the first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input and output of the driving transistor Tda.

[0160] In the light emitting stage Sd, the first scan signal ScanF and the second scan signal Scans are high level, the light emitting control signal EM, the first gate control signal Scan1 and the second gate control signal Scan2 are low level, the first light emitting control transistor Te1 and the second light emitting control transistor Te2 are turned on, and the driving transistor Tda generates a driving current to drive the corresponding light emitting device Di to emit light.

[0161] In the fourth reset stage Si4 and the fifth reset stage Si5, the light emitting control signal EM and the first scan signal ScanF are high level, the first gate control signal Scan1, the second gate control signal Scan2 and the second scan signal Scans are low level, the first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input end and the output end of the driving transistor Tda.

[0162] The write frame WF includes the first reset stage Si1, the second reset stage Si2, the data write stage Sw, the third reset stage Si3 and the light emitting stage Sd, and the hold frame HF includes the fourth reset stage Si4, the fifth reset stage Si5 and the light emitting stage Sd.

[0163] It can be understood that the reset duration of the write frame WF for resetting the control end potential of the driving transistor Tda is fixed as 4nH, that is, the duration of the second reset stage Si2 is 4nH (i.e., tx=4nH in FIG. 8). The time difference between the first time tm1 and the second time tm2 is (Xn+Y)H, that is, the duration of the second reset stage Si2 is XnH+YH (i.e., tx=XnH+YH in FIG. 8). Therefore, the reset duration (i.e., tx) can be changed from 4nH to XnH+YH.

[0164] Optionally, since the display panel is in the first display mode and the second display mode, a display period of the display panel includes the write frame WF, and therefore, the display period corresponding to the first display mode and the second display mode can include the second reset stage Si2. The transistor Tr is kept on in the second reset stage Si2, and the duration of the second reset stage Si2 is equal to the time difference between the first time tm1 and the second time tm2.

[0165]

[0166] Table II is a flicker experiment verification of the inventors within the allowed voltage / time range (e.g., 120Hz switching to 1Hz). That is, the bias voltage and time of the driving transistor Tda corresponding to the second reset stage Si2 and the data write stage Sw are experimentally verified, and the experimentally verified data is shown in Table II.

[0167] According to the experimental verification given in Table 2 of the inventor, within the allowable voltage / time range, adjusting the length of the second reset stage Si2 (i.e., the reset length described above) setting has a very key role in improving the flicker problem. Conditions 1, 2, and 4 are the settings in the conventional application. In conditions 1 and 2, the driving transistor Tda is subjected to a bias for a longer time in the second reset stage Si2, and the OBS2 intensity > OBS2' intensity, so the brightness after the frequency cutting increases (∆L%>0). In condition 4, the driving transistor Tda is subjected to a bias for a shorter time in the second reset stage Si2, and the OBS2 intensity < OBS2' intensity, so the brightness after the frequency cutting increases (∆L%<0).

[0168] In condition 3, the driving transistor Tda is subjected to a bias for 6H in the second reset stage Si2 (i.e., the time difference between the first time tm1 and the second time tm2 is 6H), and the brightness change rate after the frequency cutting is the smallest, so setting the time difference between the first time tm1 and the second time tm2 to 6H is beneficial to improving the flicker problem.

[0169] It can be understood that through different experimental verifications, the tx (i.e., the time difference between the first time tm1 and the second time tm2) corresponding to the different frequency cutting frequencies of the display panel can be obtained, and then by adjusting the period and phase difference of the first clock signal CK1 and the second clock signal CK2, the setting of tx=XnH+YH is obtained, and then the time difference between the first time tm1 and the second time tm2 can achieve the purpose of improving the flicker.

[0170] FIG. 9 is a full gray scale brightness change comparison chart when frequency cutting according to an embodiment of the present application. The inventor has carried out experimental verification on the display driving circuit and display device provided by the present application, and obtained the full gray scale effect of the frequency cutting flicker. Among them, the frequency cutting frequency is changed from 120Hz to 1Hz, L255 represents 255 gray scale, L128 represents 128 gray scale, L32 represents 32 gray scale, and L16 represents 16 gray scale. Nit represents the unit of brightness, i.e., nit.

[0171] As can be seen from FIG. 9, when the brightness is constant, the full gray scale brightness change rate when the time difference between the first time tm1 and the second time tm2 is fixed to 6H corresponding to the frequency cutting is smaller than the full gray scale brightness change rate when the conventional setting (i.e., shown in the control group) corresponding to the frequency cutting, so the present application can achieve the purpose of improving the flicker.

[0172] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will have changes, and the above description should not be understood as the limitation of the present application.

Claims

1. A display drive circuit, wherein, The method comprises the following steps: a first clock line configured to transmit a first clock signal; a second clock line configured to transmit a second clock signal; a gate drive module comprising a first gate drive unit and a second gate drive unit, the first gate drive unit and the second gate drive unit each comprising a plurality of cascaded gate drive circuits, each of the gate drive circuits being configured to output a gate control signal according to a corresponding start signal, the first clock signal and the second clock signal; wherein each of the gate drive circuits has a first input end and a second input end, the first input end of each of the gate drive circuits in the first gate drive unit being electrically connected with the first clock line, the second input end of each of the gate drive circuits in the first gate drive unit being electrically connected with the second clock line; the first input end of each of the gate drive circuits in the second gate drive unit being electrically connected with the second clock line, the second input end of each of the gate drive circuits in the second gate drive unit being electrically connected with the first clock line, the phase difference between the gate control signal outputted by the mth gate drive circuit in the first gate drive unit and the gate control signal outputted by the mth gate drive circuit in the second gate drive unit being (Xn+Y)H; the period of the first clock signal and the second clock signal being XH, the phase difference between the first clock signal and the second clock signal being YH; X>Y, n≥0, Y≥1, m≥1, H representing a unit time length.

2. The display drive circuit of claim 1, wherein, X=2Y.

3. The display drive circuit of claim 2, wherein, X=4, Y=2.

4. The display drive circuit of claim 1, wherein, Each of the gate drive circuits comprises: a node control module electrically connected with the first input end, the second input end, a first node and a second node, receiving the corresponding start signal, the first clock signal and the second clock signal to control the signals transmitted to the first node and the second node; an output module electrically connected with the first node and the second node, configured to output the gate control signal according to the signals of the first node and the second node.

5. The display drive circuit of claim 4, wherein, The node control module of at least one of the gate drive circuits comprises: a first transistor, the control end of the first transistor being electrically connected with the first input end, the input end of the first transistor being electrically connected with a first voltage end; a second transistor, the control end of the second transistor being electrically connected with the first input end, the input end of the second transistor being configured to receive the corresponding start signal; a third transistor, the control end of the third transistor being electrically connected with the output end of the second transistor, the input end of the third transistor being electrically connected with the first input end, the output end of the third transistor being electrically connected with the output end of the first transistor; a fourth transistor, the control end of the fourth transistor being electrically connected with the output end of the first transistor, the input end of the fourth transistor being electrically connected with a second voltage end; a fifth transistor, a control terminal of the fifth transistor being electrically connected with the second node, an input terminal of the fifth transistor being electrically connected with the second input terminal, and an output terminal of the fifth transistor being electrically connected with an output terminal of the fourth transistor; a sixth transistor, an input terminal of the sixth transistor being electrically connected with the second input terminal; a seventh transistor, a control terminal of the seventh transistor being electrically connected with the second input terminal, an input terminal of the seventh transistor being electrically connected with an output terminal of the sixth transistor, and an output terminal of the seventh transistor being electrically connected with the first node; an eighth transistor, a control terminal of the eighth transistor being electrically connected with an output terminal of the second transistor, an input terminal of the eighth transistor being electrically connected with the second voltage terminal, and an output terminal of the eighth transistor being electrically connected with the first node; a ninth transistor, a control terminal of the ninth transistor being electrically connected with the first voltage terminal, an input terminal of the ninth transistor being electrically connected with an output terminal of the first transistor, and an output terminal of the ninth transistor being electrically connected with a control terminal of the sixth transistor; a tenth transistor, a control terminal of the tenth transistor being electrically connected with the first voltage terminal, an input terminal of the tenth transistor being electrically connected with an output terminal of the second transistor, and an output terminal of the tenth transistor being electrically connected with the second node; a first capacitor, a first terminal of the first capacitor being electrically connected with an output terminal of the fifth transistor, and a second terminal of the first capacitor being electrically connected with a control terminal of the fifth transistor; and a second capacitor, a first terminal of the second capacitor being electrically connected with an output terminal of the sixth transistor, and a second terminal of the second capacitor being electrically connected with a control terminal of the sixth transistor.

6. The display drive circuit of claim 5, wherein, The node control module of at least one of the gate drive circuits further comprises: an eleventh transistor, a control terminal of the eleventh transistor being electrically connected with a control terminal of the fifth transistor, an input terminal of the eleventh transistor being electrically connected with the control terminal of the eleventh transistor, and an output terminal of the eleventh transistor being electrically connected with the second node; a twelfth transistor, a control terminal of the twelfth transistor being electrically connected with the first input terminal, and an input terminal of the twelfth transistor being configured to receive a corresponding start signal; and a thirteenth transistor, a control terminal of the thirteenth transistor being electrically connected with the first voltage terminal, an input terminal of the thirteenth transistor being electrically connected with an output terminal of the twelfth transistor, and an output terminal of the thirteenth transistor being electrically connected with the control terminal of the eleventh transistor.

7. The display drive circuit of claim 4, wherein, The output module of at least one of the gate drive circuits comprises: a first output transistor, a control terminal of the first output transistor being electrically connected with the first node, an input terminal of the first output transistor being electrically connected with the second voltage terminal, and an output terminal of the first output transistor being electrically connected with a signal output terminal outputting the gate control signal; a second output transistor, a control terminal of the second output transistor being electrically connected with the second node, an input terminal of the second output transistor being electrically connected with the first voltage terminal, and an output terminal of the second output transistor being electrically connected with the signal output terminal, and a third capacitor, a first terminal of the third capacitor being electrically connected with the output terminal of the first output transistor, and a second terminal of the third capacitor being electrically connected with the control terminal of the first output transistor.

8. The display drive circuit of claim 1, wherein, The circuit topology of the gate drive circuit included in the first gate drive unit is the same as the circuit topology of the gate drive circuit included in the second gate drive unit.

9. A display device, wherein, The display driving circuit comprises: The display driving circuit according to claim 1; and The display panel comprises a plurality of sub-pixels, each of the sub-pixels comprises a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, at least one of the pixel driving circuits comprises a driving transistor, a compensation transistor and a reset transistor, the driving transistor is configured to generate a driving current to drive the light emitting device to emit light, an input terminal of the reset transistor is configured to receive a reset signal, an output terminal of the reset transistor is electrically connected with a control terminal of the driving transistor, an input terminal of the compensation transistor is electrically connected with an output terminal of the driving transistor, and an output terminal of the compensation transistor is electrically connected with the control terminal of the driving transistor. The plurality of gate control signals generated by the first gate drive unit are output to the control terminals of the reset transistors of the plurality of sub-pixels, and the plurality of gate control signals generated by the second gate drive unit are output to the control terminals of the compensation transistors of the plurality of sub-pixels; in the same sub-pixel, the reset transistor is turned on at the first time, and the compensation transistor is turned on at the second time, and the time difference between the first time and the second time is XnH+YH.

10. The display device of claim 9, wherein, The display panel has a first display mode and a second display mode, the display panel has a first refresh frequency corresponding to the first display mode, and the display panel has a second refresh frequency corresponding to the second display mode, and the first refresh frequency is greater than the second refresh frequency. When the display panel is in the second display mode, a display period of the display panel comprises a write frame and at least one holding frame, the write frame comprises at least a second reset stage, the reset transistor is kept turned on in the second reset stage, and the time length of the second reset stage is equal to the time difference between the first time and the second time.

11. The display device of claim 9, wherein, The time difference between the first time and the second time is 6H.

12. The display device of claim 9, wherein, The pixel driving circuit comprises: a data transistor, a control terminal of the data transistor being electrically connected with a first scan line, an input terminal of the data transistor being configured to receive a data signal, and an output terminal of the data transistor being electrically connected with an input terminal of the driving transistor. a first light emitting control transistor, a control terminal of the first light emitting control transistor being electrically connected with the light emitting control line, an input terminal of the first light emitting control transistor being electrically connected with the first power supply terminal, and an output terminal of the first light emitting control transistor being electrically connected with the input terminal of the driving transistor; a second light emitting control transistor, a control terminal of the second light emitting control transistor being electrically connected with the light emitting control line, an input terminal of the second light emitting control transistor being electrically connected with the output terminal of the driving transistor, and an output terminal of the second light emitting control transistor being electrically connected with the anode of the light emitting device; a first initial transistor, a control terminal of the first initial transistor being electrically connected with the second scan line, an input terminal of the first initial transistor being electrically connected with the first initial line, and an output terminal of the first initial transistor being electrically connected with the anode of the light emitting device, the cathode of the light emitting device being electrically connected with the second power supply terminal; a second initial transistor, a control terminal of the second initial transistor being electrically connected with the second scan line, an input terminal of the second initial transistor being electrically connected with the second initial line, and an output terminal of the second initial transistor being electrically connected with the input terminal of the driving transistor; a first storage capacitor, a first terminal of the first storage capacitor being electrically connected with the control terminal of the driving transistor, and a second terminal of the first storage capacitor being electrically connected with the first power supply terminal; and a second storage capacitor, a first terminal of the second storage capacitor being electrically connected with the control terminal of the driving transistor, and a second terminal of the second storage capacitor being electrically connected with the control terminal of the data transistor.

13. The display device of claim 12, wherein, The display driving circuit comprises a third gate driving unit electrically connected with a plurality of the first scan lines, the third gate driving unit being configured to output a plurality of first scan signals to the control terminals of the data transistors of a plurality of the sub-pixels.

14. The display device of claim 12, wherein, The display driving circuit comprises a fourth gate driving unit electrically connected with a plurality of the second scan lines, the fourth gate driving unit being configured to output a plurality of second scan signals to the control terminals of the first initial transistors and the second initial transistors of a plurality of the sub-pixels.

15. The display device of claim 12, wherein, The display driving circuit comprises a fifth gate driving unit electrically connected with a plurality of the light emitting control lines, the fifth gate driving unit being configured to output a plurality of light emitting control signals to the control terminals of the first light emitting control transistors and the second light emitting control transistors of a plurality of the sub-pixels.

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