Display panel and display apparatus

Abstract

Provided in the present application are a display panel and a display apparatus. In the display panel, a first gate insulating layer covers a second doped portion, and the first gate insulating layer does not cover a first doped portion, such that during the formation of the display panel, compared with the second doped region, the first doped portion is more likely to generate electrons when etched or subjected to ion bombardment, thereby differentiating threshold voltages of oxide semiconductor transistors in a pixel driving circuit and a gate driving circuit. Thus, the display panel can perform display normally.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410627329.4, filed on May 20, 2024, with the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] With the development of display technology, the existing display devices have higher and higher requirements for display effect. In order to improve the display effect, the existing display devices will use LTPO (Low Temperature Polysilicon Oxide) pixel circuit, but the LTPO pixel driving circuit needs more GOA (Gate On Array, gate driving circuit arranged on the array substrate) circuit output signal, which will cause the power consumption of the display device to increase, in order to reduce the power consumption of the display device, CMOS (Complementary Metal Oxide Semiconductor) GOA circuit will be used to reduce the number of GOA circuits. In the LTPO pixel driving circuit and the CMOS GOA circuit, the oxide semiconductor transistor in the LTPO pixel driving circuit needs to ensure that the threshold voltage is around 0 volts to achieve better PBTS (Positive Bias Temperature Stress), and the oxide semiconductor transistor in the CMOS GOA circuit needs to ensure that the threshold voltage is positively biased to avoid leakage. However, in the actual production process, the threshold voltages of the oxide semiconductor transistors in the LTPO pixel driving circuit and the CMOS GOA circuit are close to or even equal, which cannot differentiate the oxide semiconductor transistors in the two, resulting in display defects.

[0004] Therefore, the existing display device has the technical problem of display defects caused by the inability to differentiate the threshold voltages of the oxide semiconductor transistors in the LTPO pixel driving circuit and the CMOS GOA circuit. SUMMARY

[0005] The embodiments of the present application provide a display panel and a display device to solve the technical problem of display defects caused by the inability to differentiate the threshold voltages of the oxide semiconductor transistors in the LTPO pixel driving circuit and the CMOS GOA circuit in the existing display device.

[0006] The display panel provided by the embodiment of the present application comprises a display area and a gate drive circuit area arranged at least one side of the display area, and the display panel comprises:

[0007] a substrate;

[0008] a first active layer arranged at one side of the substrate, the first active layer comprising a first active pattern arranged at the display area and a second active pattern arranged at the gate drive circuit area, the first active pattern comprising a first doped part, and the second active pattern comprising a second doped part;

[0009] a first gate insulating layer arranged at a side of the first active layer away from the substrate;

[0010] a first metal layer arranged at a side of the first gate insulating layer away from the first active layer;

[0011] wherein the material of the first active layer comprises an oxide semiconductor, the first gate insulating layer covers the second doped part, and the first gate insulating layer does not cover the first doped part.

[0012] Meanwhile, the embodiment of the present application provides a display device comprising a display panel, the display panel comprising a display area and a gate drive circuit area arranged at least one side of the display area, and the display panel comprises:

[0013] a substrate;

[0014] a first active layer arranged at one side of the substrate, the first active layer comprising a first active pattern arranged at the display area and a second active pattern arranged at the gate drive circuit area, the first active pattern comprising a first doped part, and the second active pattern comprising a second doped part;

[0015] a first gate insulating layer arranged at a side of the first active layer away from the substrate;

[0016] a first metal layer arranged at a side of the first gate insulating layer away from the first active layer;

[0017] wherein the material of the first active layer comprises an oxide semiconductor, the first gate insulating layer covers the second doped part, and the first gate insulating layer does not cover the first doped part. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a schematic diagram of an existing display device provided by the embodiment of the present application.

[0019] FIG. 2 is a schematic diagram of a display panel provided by the embodiment of the present application.

[0020] FIG. 3 is a circuit diagram of a pixel driving circuit according to an embodiment of the present application.

[0021] FIG. 4 is a timing diagram of the pixel driving circuit according to an embodiment of the present application.

[0022] FIG. 5 is a circuit diagram of a gate driving circuit according to an embodiment of the present application.

[0023] FIG. 6 is a schematic diagram of a display panel corresponding to three steps in a method of manufacturing the display panel according to an embodiment of the present application.

[0024] FIG. 7 is a schematic diagram of a display panel corresponding to two other steps in the method of manufacturing the display panel according to an embodiment of the present application.

[0025] FIG. 8 is a schematic diagram of a display panel corresponding to two further steps in the method of manufacturing the display panel according to an embodiment of the present application. Embodiments of the present application

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0027] In the description of the present application, it should be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise” and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms “first” and “second” are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise specifically limited.

[0028] In the description of the application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0029] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0030] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and settings of specific examples are described in the following. Of course, they are only examples, and the purpose is not to limit the application. In addition, the application can repeatedly refer to the same reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not in itself indicate a relationship between the various embodiments and / or settings discussed. In addition, the application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0031] As shown in FIG. 1, the existing display device includes a display area 141 and a GOA area 142, the LTPO pixel driving circuit is arranged in the display area 141, and the CMOS GOA circuit is arranged in the GOA area 142. As shown in FIG. 1, the display device includes a substrate 111, a light shielding metal 112, a first insulating layer 113, a second insulating layer 114, a first semiconductor layer 115, a third insulating layer 116, a first gate layer 117, a fourth insulating layer 118, a second gate layer 119, a fifth insulating layer 120, a second semiconductor layer 121, a sixth insulating layer 122, a third gate layer 123, a seventh insulating layer 124, a first source-drain metal layer 125, an eighth insulating layer 126, a second source-drain metal layer 127, a ninth insulating layer 128, an anode layer 129, a tenth insulating layer 130 and an eleventh insulating layer 131 arranged in sequence. When the display device is formed, the LTPO pixel driving circuit is formed at the same time as the CMOS GOA circuit, therefore, the oxide semiconductor transistor in the LTPO pixel driving circuit and the oxide semiconductor transistor in the CMOS GOA circuit have the same structure and similar or even the same performance, but the oxide semiconductor transistor in the LTPO pixel driving circuit needs to ensure that the threshold voltage is about 0 volt to achieve better PBTS, and the oxide semiconductor transistor in the CMOS GOA circuit needs to ensure that the threshold voltage is positively biased to avoid leakage, therefore, the design of the existing display device cannot meet the needs of the oxide semiconductor transistor in the LTPO pixel driving circuit and the oxide semiconductor transistor in the CMOS GOA circuit, resulting in the problem of display failure of the display device. Therefore, the existing display device has the technical problem that the threshold voltage of the oxide semiconductor transistor in the LTPO pixel driving circuit and the CMOS GOA circuit cannot be differentiated, resulting in display failure.

[0032] Embodiments of the present application aim at the above technical problem, and provide a display panel and a display device to solve the above technical problem.

[0033] As shown in FIG. 2, the present application provides a display panel, the display panel 2 includes a display area 241 and a gate driving circuit area 242 arranged on at least one side of the display area 241, and the display panel 2 includes:

[0034] a substrate 211;

[0035] a first active layer 221 arranged on one side of the substrate 211, the first active layer 221 includes a first active pattern 301 arranged in the display area 241 and a second active pattern 302 arranged in the gate driving circuit area 242, the first active pattern 301 includes a first doped part 301a, and the second active pattern 302 includes a second doped part 302a;

[0036] The first gate insulating layer 222 is arranged on the side of the first active layer 221 away from the substrate 211.

[0037] The first metal layer 223 is arranged on the side of the first gate insulating layer 222 away from the first active layer 221.

[0038] The material of the first active layer 221 includes an oxide semiconductor, the first gate insulating layer 222 covers the second doped part 302a, and the first gate insulating layer 222 does not cover the first doped part 301a.

[0039] The display panel provided by the embodiment of the present application makes the first gate insulating layer cover the second doped part and the first gate insulating layer not cover the first doped part, so that in the process of forming the display panel, the first doped part is more easily etched or ion-bombed to generate electrons than the second doped part, the diffusion of the electrons to the first channel part causes the effective channel length of the first active pattern to decrease, the threshold voltage of the oxide semiconductor transistor of the display area is negatively biased, the hydrogen element in other film layers easily diffuses to the first doped part to make the oxide semiconductor transistor of the display area negatively biased, the threshold voltages of the oxide semiconductor transistors in the pixel driving circuit and the gate driving circuit are differentiated, and the display panel can normally display.

[0040] Specifically, the pixel driving circuit can be arranged in the display area, and the gate driving circuit can be arranged in the gate driving circuit area.

[0041] Specifically, the gate driving circuit area is arranged on one side of the display area in FIG. 2, but the embodiment of the present application is not limited thereto, and the gate driving circuit area can be arranged on multiple sides of the display panel, for example, the gate driving circuit area is arranged on two sides of the display panel.

[0042] Specifically, the gate driving circuit in the embodiment of the present application can be a CMOS GOA circuit.

[0043] Specifically, it can be understood that the negative bias in the embodiments of the present application does not specifically refer to negative bias, but refers to the shift of the threshold voltage to the negative potential, and the threshold voltage can be positive, 0 or negative. Similarly, the positive bias in the embodiments of the present application does not specifically refer to positive bias, but refers to the shift of the threshold voltage to the positive potential, and the threshold voltage can be positive, 0 or negative. For example, in the existing display device, the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area and the display area is 0.5 volts. In the embodiments of the present application, the first gate insulating layer in the display area and the gate drive circuit area is designed differently. For example, the threshold voltage of the oxide semiconductor transistor in the display area is 0, and the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area is 0.5 volts. At this time, it can be said that the threshold voltage of the oxide semiconductor transistor in the display area is negatively biased, but it can be seen that the threshold voltage of the oxide semiconductor transistor in the display area is not negative.

[0044] Specifically, since the first gate insulating layer does not cover the first doped part, the first gate insulating layer covers the second doped part, so that the threshold voltage of the oxide semiconductor transistor in the display area is negatively biased, meeting the demand that the oxide semiconductor transistor in the display area has better positive bias temperature stress, and the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area is positively biased, meeting the demand that the oxide semiconductor transistor in the gate drive circuit area can be completely closed without leakage, thereby taking into account the different needs of the oxide semiconductor transistors in the display area and the gate drive circuit area, and making the display panel display normally.

[0045] Specifically, the first doped part includes a first source doped part and a first drain doped part, and the second doped part includes a second source doped part and a second drain doped part.

[0046] Specifically, by not providing the first gate insulating layer on the first doped part, the chemical bond between the metal in the first doped part and oxygen is more easily broken to produce electrons during the etching process of the first metal layer, the electrons diffuse into the channel to reduce the effective channel length, making the threshold voltage more negatively biased than the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area. Moreover, the first doped part is not protected by the first gate insulating layer during the doping process, and is more damaged by the bombardment of doped ions, producing more electrons, making the threshold voltage more negatively biased than the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area. Moreover, the diffusion of hydrogen elements in other film layers to the first doped part causes the threshold voltage to be more negatively biased than the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area, thereby differentiating the threshold voltages of the oxide semiconductor transistors in the display area and the gate drive circuit area, and making the display panel display normally.

[0047] Specifically, taking the display panel shown in FIG. 2 as an example, it can be seen that the first doped part is free of the first gate insulating layer, and the second doped part is provided with the first gate insulating layer. During etching of the first metal layer 223, the first doped part is etched by plasma in the dry etching process, so that the chemical bond between the metal and oxygen in the first doped part is broken, electrons are generated, the electrons easily diffuse into the channel to reduce the effective channel length, and the threshold voltage is negatively biased. In the doping process, the first doped part in the display area is directly bombarded by doping ions, and compared with the second doped part in the gate drive circuit area which is protected by the first gate insulating layer, the first doped part in the display area is more damaged and generates more electrons, and the threshold voltage is more negatively biased. Hydrogen in the first interlayer insulating layer 224 will diffuse to the doped part of the oxide semiconductor transistor, and the first doped part in the display area is not shielded by the first gate insulating layer, so it is more affected by hydrogen, and the threshold voltage is more negatively biased, so that the threshold voltage of the oxide semiconductor transistor in the display area is more negatively biased than that of the oxide semiconductor transistor in the gate drive circuit area.

[0048] In some embodiments, as shown in FIG. 2, the first active pattern 301 further includes a first channel part 301b, the first gate insulating layer 222 in the display area 241 covers the first channel part 301b, and the projection of the first gate insulating layer 222 of the display area 241 on the substrate 211 is located within the projection range of the first channel part 301b on the substrate 211. By covering the first channel part with the first gate insulating layer in the display area, the first gate insulating layer protects the first channel part, and the projection of the first gate insulating layer on the substrate is located within the projection range of the first channel part on the substrate, so that the first gate insulating layer on the first channel part in the display area can be removed, so that other insulating layers can be arranged on the side surface and top surface of the first doped part, and thus hydrogen can diffuse to the first doped part, further negatively biasing the threshold voltage in the display area.

[0049] In some embodiments, as shown in FIG. 2, the thickness of the first gate insulating layer 222 corresponding to the first channel part 301b is equal to the thickness of the first gate insulating layer 222 corresponding to the second doped part 302a. By making the thickness of the part of the first gate insulating layer corresponding to the first channel part equal to the thickness of the part of the first gate insulating layer corresponding to the second doped part, only one process is needed to remove the part of the first gate insulating layer corresponding to the first channel part outside the display area during etching of the first gate insulating layer, so that the process is relatively simple, and the threshold voltage of the oxide semiconductor transistor in the gate drive circuit area can be positively biased, thereby differentiating the threshold voltages of the oxide semiconductor transistors in the gate drive circuit area and the display area, so that the display panel can display normally.

[0050] In some embodiments, as shown in FIG. 2, the second active pattern 302 further comprises a second channel portion 302b, and the first gate insulating layer 222 in the gate driving circuit region 242 covers the second channel portion 302b. By covering the second channel portion with the first gate insulating layer, the second channel portion can be protected.

[0051] In some embodiments, as shown in FIG. 2, the second active pattern 302 further comprises a second channel portion 302b, and the thickness of the first gate insulating layer 222 corresponding to the second channel portion 302b is equal to the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a. By making the thickness of the portion of the first gate insulating layer corresponding to the second channel portion equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion, the first gate insulating layer can protect the second doped portion and the second channel portion, and the threshold voltage of the oxide semiconductor transistor in the gate driving circuit region can be positively shifted compared to the oxide semiconductor transistor in the display region, thereby avoiding the leakage current of the oxide semiconductor transistor in the gate driving circuit region.

[0052] In some embodiments, as shown in FIG. 2, in the gate driving circuit region 242, the projection of the first gate insulating layer 222 on the substrate 211 coincides with the substrate. By making the projection of the first gate insulating layer on the substrate in the gate driving circuit region coincide with the substrate, the portion of the first gate insulating layer in the gate driving circuit region protects the second doped portion and the second channel portion, and the threshold voltage of the oxide semiconductor transistor in the gate driving circuit region is positively shifted, thereby avoiding the leakage current of the oxide semiconductor transistor in the gate driving circuit region.

[0053] In some embodiments, as shown in FIG. 2 and FIG. 3, the display region 241 is provided with a pixel driving circuit 31, and the pixel driving circuit 31 comprises:

[0054] a first initialization transistor T24 connected to a first initialization signal line VI-G, for inputting a first initialization signal to a first node Q under the control of a first scan signal;

[0055] a switch transistor T22, for inputting a data signal to a second node A under the control of a second scan signal;

[0056] a driving transistor T21 connected to the first initialization transistor T24 at the first node Q and connected to the switch transistor T22 at the second node A, for driving a light emitting device LED to emit light under the control of the potentials of the first node Q and the second node A;

[0057] A compensation transistor T23 is connected with the driving transistor T21 through the first node Q and the third node B, and is used for compensating the threshold voltage of the driving transistor T21 under the control of a third scan signal;

[0058] The first gate insulating layer 222 does not cover the doped part of at least one of the first initialization transistor T24 and the compensation transistor T23. By making the first gate insulating layer not cover the doped part of at least one of the first initialization transistor and the compensation transistor, the threshold voltage of at least one of the first initialization transistor and the compensation transistor can be adjusted, so that at least one of the first initialization transistor and the compensation transistor has better PBTS, thereby improving the performance of the display panel.

[0059] Specifically, when the first gate insulating layer does not cover the first initialization transistor, it means that the active pattern of the first initialization transistor is designed to be the same as the first active pattern. Similarly, when the first gate insulating layer does not cover the compensation transistor, it means that the active pattern of the compensation transistor is designed to be the same as the first active pattern; that is, the first active pattern 301 includes the active pattern of at least one of the first initialization transistor T24 and the compensation transistor T23.

[0060] Specifically, in the embodiment of the present application, when the threshold voltages of the oxide semiconductor transistors in the display area and the oxide semiconductor transistors in the gate driving circuit area are differentiated, the threshold voltages of one oxide semiconductor transistor in the display area and the oxide semiconductor transistors in the gate driving circuit area can be differentiated, the threshold voltages of one type of oxide semiconductor transistor (for example, all compensation transistors) in the display area and the oxide semiconductor transistors in the gate driving circuit area can be differentiated, or the threshold voltages of all oxide semiconductor transistors in the display area and the oxide semiconductor transistors in the gate driving circuit area can be differentiated.

[0061] Specifically, the first initialization transistor T24 and the compensation transistor T23 in FIG. 3 are taken as single-gate transistors for illustration, but the embodiment of the present application is not limited thereto, and the first initialization transistor T24 and the compensation transistor T23 can be double-gate transistors.

[0062] In some embodiments, the thickness of the first gate insulating layer 222 corresponding to the doped portion of one of the first initialization transistor T24 and the compensation transistor T23 is less than the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a; the thickness of the first gate insulating layer 222 corresponding to the doped portion of the other one of the first initialization transistor T24 and the compensation transistor T23 is equal to the thickness of the first gate insulating layer 222 corresponding to the second doped portion 302a. By adjusting the threshold voltage of one of the first initialization transistor and the compensation transistor when the first gate insulating layer is arranged, the one of the first initialization transistor and the compensation transistor has better PBTS, and the performance of the display panel is improved.

[0063] In some embodiments, the thickness of the first gate insulating layer 222 corresponding to the doped portion of the first initialization transistor T24 is equal to the thickness of the first gate insulating layer 222 corresponding to the doped portion of the compensation transistor T23. By making the thickness of the portion of the first gate insulating layer corresponding to the doped portion of the first initialization transistor equal to the thickness of the portion of the first gate insulating layer corresponding to the doped portion of the compensation transistor, the threshold voltages of the first initialization transistor and the compensation transistor are both biased to be negative, so that the first initialization transistor and the compensation transistor both have better PBTS, and the performance of the display panel is improved.

[0064] Specifically, as shown in FIG. 3, the pixel driving circuit 31 further includes a first light-emitting transistor T25, a second light-emitting transistor T26, and a second initialization transistor T27.

[0065] The first light-emitting transistor T25 is connected to the second node A with the driving transistor T21, and is used to conduct the current of the first power signal line VDD to the driving transistor T21 under the control of a light-emitting control signal.

[0066] The second light-emitting transistor T26 is connected to the third node B with the driving transistor T21, and is used to conduct the current of the driving transistor T21 to the light-emitting device LED under the control of the light-emitting control signal.

[0067] One electrode of the second initialization transistor T27 is connected to the fourth node C with the light-emitting device LED, and the other electrode of the second initialization transistor T27 is connected to a second initialization signal line VI-ANO. The second initialization transistor T27 is used to input a second initialization signal to the anode of the light-emitting device LED under the control of a fourth scanning signal.

[0068] Specifically, the driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor and the second initialization transistor are low-temperature polysilicon semiconductor transistors, and the compensation transistor and the first initialization transistor are oxide semiconductor transistors, which can be metal oxide semiconductor transistors.

[0069] Specifically, the driving transistor, the switching transistor, the first light-emitting transistor, the second light-emitting transistor and the second initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0070] Specifically, it can be understood that the first scan signal line Nscan(n-5) outputs a first scan signal, the second scan signal line Pscan(n) outputs a second scan signal, the third scan signal line Nscan(n) outputs a third scan signal, the fourth scan signal line Pscan(n-1) outputs a fourth scan signal, the first initialization signal line outputs a first initialization signal, the second initialization signal line outputs a second initialization signal, the data line outputs a data signal, and the light-emitting control signal line outputs a light-emitting control signal.

[0071] In some embodiments, as shown in FIG. 3, the pixel driving circuit 31 further includes a storage capacitor Cst, one plate of the storage capacitor Cst being connected with the first power signal line VDD, and the other plate of the storage capacitor Cst being connected with the gate of the driving transistor T21.

[0072] In some embodiments, the pixel driving circuit can further include a boosting capacitor, one plate of the boosting capacitor being connected with the first scan signal line, and the other plate of the boosting capacitor being connected with the gate of the driving transistor.

[0073] Specifically, taking the pixel driving circuit shown in FIG. 3 as an example, the working principle of the pixel driving circuit is explained as follows: as shown in FIG. 4, in a first stage S1, the first scan signal line Nscan(n-5) outputs a high potential, the first initialization transistor T24 is turned on, and the first initialization signal line VI-G outputs a first initialization signal to reset the first node Q; in a second stage S2, the second scan signal line Pscan(n) inputs a low potential, the third scan signal line Nscan(n) inputs a high potential, the switching transistor T22 and the compensation transistor T23 are turned on, the data line Data outputs a data signal to the first node Q, and at the same time, the fourth scan signal line Pscan(n-1) inputs a low potential, the second initialization transistor T27 is turned on, and the second initialization signal line VI-ANO outputs a second initialization signal to reset the fourth node C; in a third stage, the light-emitting control signal line EM outputs a low potential, the first light-emitting transistor T25 and the second light-emitting transistor T26 are turned on, and the first power signal line VDD writes a signal to the second node A, the third node B and the fourth node C, so that the light-emitting device LED emits light.

[0074] In some embodiments, as shown in FIGS. 2-5, the gate driving circuit region 242 is provided with an oxide semiconductor transistor (e.g., the first-stage pass transistor T13), the first gate insulating layer 222 does not cover the doped portion of the first initialization transistor T24, the first gate insulating layer 222 does not cover the doped portion of the compensation transistor T23, the first gate insulating layer 222 covers the doped portion of the oxide semiconductor transistor (e.g., the first-stage pass transistor T13), and the pattern height H1 of the source and drain of the oxide semiconductor transistor is greater than the pattern height H2 of the source and drain of the first initialization transistor T24. By having the first gate insulating layer not cover the doped portions of the first initialization transistor and the compensation transistor, and having the first gate insulating layer cover the doped portion of the oxide semiconductor transistor of the gate driving circuit region, the height difference between the source and drain of the first initialization transistor and the doped portion of the first initialization transistor is less than the height difference between the source and drain of the oxide semiconductor transistor of the gate driving circuit region and the doped portion of the oxide semiconductor transistor, so that the pattern height of the source and drain of the oxide semiconductor transistor is greater than the pattern height of the source and drain of the first initialization transistor.

[0075] Specifically, it can be understood that when the first gate insulating layer does not cover the doped portion of the compensation transistor and the doped portion of the first initialization transistor, the pattern height of the source and drain of the first initialization transistor is the same as the pattern height of the source and drain of the compensation transistor, when the first gate insulating layer covers one of the doped portion of the compensation transistor and the doped portion of the first initialization transistor, and the first gate insulating layer does not cover the other of the doped portion of the compensation transistor and the doped portion of the first initialization transistor, the pattern height of the source and drain of the transistor covered by the first gate insulating layer is greater than the pattern height of the source and drain of the transistor not covered by the first gate insulating layer. Similarly, for the pattern height of the source and drain of the transistors in other gate driving circuits and pixel driving circuits, reference can be made to the above description.

[0076] In some embodiments, the material of the first gate insulating layer includes silicon oxide. By having the material of the first gate insulating layer include silicon oxide, the first gate insulating layer can protect the second doped portion from the diffusion of hydrogen elements to the second doped portion, which causes changes in the performance of the oxide semiconductor transistor.

[0077] In some embodiments, as shown in FIG. 2, the display panel 2 further comprises a first interlayer insulating layer 224 disposed on the side of the first metal layer 223 away from the first active layer 221, and the material of the first interlayer insulating layer 224 comprises silicon nitride. By making the material of the first interlayer insulating layer comprise silicon nitride, the hydrogen element in the first interlayer insulating layer can diffuse to the first doped portion, so that the threshold voltage of the oxide semiconductor transistor of the display area is more negative.

[0078] In some embodiments, the thickness range H3 of the first gate insulating layer is 20-600 nm, so that the first gate insulating layer can protect the covered part of the first active layer, and the thickness of the first gate insulating layer will not be too large to cause the thickness of the display panel to be too large.

[0079] In some embodiments, as shown in FIG. 2 and FIG. 5, the gate drive circuit area 242 is provided with a gate drive circuit 32, which comprises:

[0080] a stage transfer signal selection module 321 comprising a first stage transfer transistor T13 and a second stage transfer transistor T12, the gate of the first stage transfer transistor T13 and the gate of the second stage transfer transistor T12 are connected to a stage transfer signal line STV, the first electrode of the first stage transfer transistor T13 is connected to a first low potential signal line PVGL, the second electrode of the first stage transfer transistor T13 and the second electrode of the second stage transfer transistor T12 are connected to a fifth node O, and the first electrode of the second stage transfer transistor T12 is connected to a first high potential signal line PVGH;

[0081] a pull-up control module 322 comprising a pull-up transistor T2, the gate of the pull-up transistor T2 is connected to a second clock signal line XCK, the first electrode of the pull-up transistor T2 is connected to the fifth node O, and the second electrode of the pull-up transistor T2 is connected to a sixth node K;

[0082] a first filter module 323 comprising a first filter transistor T11 and a second storage capacitor C2, the gate of the first filter transistor T11 and one plate of the second storage capacitor C2 are connected to a reset signal line RST, the first electrode of the first filter transistor T11 is connected to the sixth node K, and the second electrode of the first filter transistor T11 and the other plate of the second storage capacitor C2 are connected to a seventh node W;

[0083] a second filter module 324 comprising a second filter transistor T8, the gate of the second filter transistor T8 is connected to the first output end Nout[n-2] of the gate drive circuit of the upper two stages, the first electrode of the second filter transistor T8 is connected to the seventh node W, and the second electrode of the second filter transistor is connected to an eighth node U;

[0084] The first inverting module 325 includes a first inverting transistor T3 and a second inverting transistor T1, the gate of the first inverting transistor T3 and the gate of the second inverting transistor T1 are connected to the sixth node K, the first electrode of the first inverting transistor T3 is connected to the first high potential signal line PVGH, the second electrode of the first inverting transistor T3 and the second electrode of the second inverting transistor T1 are connected to the internal node P, and the first electrode of the second inverting transistor T1 is connected to the first low potential signal line PVGL.

[0085] The feedback module 326 includes a first feedback transistor T4 and a second feedback transistor T5, the gate of the first feedback transistor T4 is connected to the first clock signal line CK, the first electrode of the first feedback transistor T4 is connected to the sixth node K, the second electrode of the first feedback transistor T4 and the second electrode of the second feedback transistor T5 are connected, the gate of the second feedback transistor T5 is connected to the internal node P, and the first electrode of the second feedback transistor T5 is connected to the first high potential signal line PVGH.

[0086] The voltage adjusting module 327 includes an adjusting transistor T14, the gate of the adjusting transistor T14 is connected to the internal node P, the first electrode of the adjusting transistor T14 is connected to the second low potential signal line NVGL, and the second electrode of the adjusting transistor T14 is connected to the sixth node K.

[0087] The first output module 328 includes a first output transistor T10 and a second output transistor T9, the gate of the first output transistor T10 and the gate of the second output transistor T9 are connected to the sixth node K, the first electrode of the first output transistor T10 is connected to the second low potential signal line NVGL, the second electrode of the first output transistor T10 and the second electrode of the second output transistor T9 are connected to the first output end Nout[n], and the second electrode of the second output transistor is connected to the second high potential signal line NVGH.

[0088] The second output module 329 includes a third output transistor T6 and a fourth output transistor T7, the gate of the third output transistor T6 is connected to the eighth node U, the first electrode of the third output transistor T6 is connected to the first clock signal line CK, the second electrode of the third output transistor T6 and the second electrode of the fourth output transistor T7 are connected to the second output end Pout[n], the gate of the fourth output transistor T7 is connected to the internal node P, and the first electrode of the fourth output transistor T7 is connected to the first high potential signal line PVGH.

[0089] Specifically, the gate drive circuit 32 further includes a first storage capacitor C1, one plate of the first storage capacitor C1 is connected to the eighth node U, and the other plate of the first storage capacitor C1 is connected to the second output end Pout[n].

[0090] Specifically, the first output terminal Nout[n] is connected to the third scan signal line Nscan(n), and the second output terminal Pout[n] is connected to the second scan signal line Psca(n).

[0091] Specifically, the first-stage transfer transistor T13, the second inverter transistor T1, the first output transistor T10, and the adjustment transistor T14 are oxide semiconductor transistors, and the second-stage transfer transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverter transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are low-temperature polysilicon semiconductor transistors.

[0092] Specifically, the first-stage transfer transistor T13, the second inverter transistor T1, the first output transistor T10, and the adjustment transistor T14 are N-type transistors, and the second-stage transfer transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverter transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.

[0093] Specifically, the first-stage transfer transistor T13, the second inverter transistor T1, the first output transistor T10, and the adjustment transistor T14 are double-gate transistors.

[0094] In some embodiments, as shown in FIG. 2, the display panel 2 further includes a light-blocking layer 212, a barrier layer 213, a buffer layer 214, a second active layer 215, a second gate insulating layer 216, a second metal layer 217, a third gate insulating layer 218, a third metal layer 219, a second interlayer insulating layer 220, a first interlayer insulating layer 224, a first source-drain layer 225, a first planarization layer 226, a second source-drain layer 227, a second planarization layer 228, a pixel electrode layer 229, a pixel definition layer 230, a light-emitting material layer, a common electrode layer, and a support column 231.

[0095] In some embodiments, the first electrode of the transistor in the above embodiments is a source electrode, and the second electrode is a drain electrode; or the first electrode of the transistor in the above embodiments is a drain electrode, and the second electrode is a source electrode.

[0096] In some embodiments, the material of the first active layer includes metal oxide, and the material of the second active layer includes low-temperature polysilicon.

[0097] Specifically, the above embodiments are described in detail from the structure of each film layer of the display panel, the transistor, and the connection relationship of each film layer and the transistor. It can be understood that the embodiments can be combined when there is no conflict between the embodiments. For example, the thickness of the portion of the first gate insulating layer corresponding to the first channel portion is equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion, and the second active pattern further includes a second channel portion, and the thickness of the portion of the first gate insulating layer corresponding to the second channel portion is equal to the thickness of the portion of the first gate insulating layer corresponding to the second doped portion.

[0098] Meanwhile, the embodiment of the present application provides a preparation method of a display panel, the preparation method of the display panel comprising:

[0099] A substrate is provided, and an optical shielding layer, a barrier layer, a buffer layer, a second active layer, a second gate insulating layer, a second metal layer, a third gate insulating layer, a third metal layer, a second interlayer insulating layer, a first active layer, a first gate insulating layer, and a first metal layer are sequentially formed on the substrate. The structure of the display panel corresponding to this step is shown in (a) of FIG. 6.

[0100] Specifically, the substrate 211 can include a plurality of flexible layers and inorganic layers arranged in an overlapping manner. The flexible layer can be polyimide, and the inorganic layer can be at least one of silicon nitride and silicon oxide.

[0101] Specifically, after the substrate 211 is provided, a metal layer can be formed on the substrate 211, and the metal layer is etched to form the optical shielding layer 212. The material of the optical shielding layer 212 includes aluminum, titanium, molybdenum, copper, nickel, or an alloy or a stack thereof.

[0102] Specifically, after the optical shielding layer is formed, the barrier layer 213 and the buffer layer 214 can be formed on the optical shielding layer. The material of the barrier layer 213 includes at least one of silicon nitride and silicon oxide, and the material of the buffer layer 214 includes at least one of silicon nitride and silicon oxide.

[0103] Specifically, after the buffer layer is formed, the second active layer 215 can be formed on the buffer layer 214, and the second active layer 215 is etched to form a pattern. The material of the second active layer includes a silicon semiconductor, and specifically can be low-temperature polysilicon.

[0104] Specifically, after the second active layer 215 is formed, the second gate insulating layer 216 can be formed on the second active layer 215. The material of the second gate insulating layer 216 includes at least one of silicon nitride and silicon oxide.

[0105] Specifically, after the second gate insulating layer 216 is formed, a second metal layer 217 can be formed on the second gate insulating layer 216, and the second metal layer 217 is etched to form a pattern. The material of the second metal layer 217 includes aluminum, titanium, molybdenum, copper, nickel, or an alloy or a stack thereof.

[0106] Specifically, after the second metal layer 217 is formed, a third gate insulating layer 218 can be formed. The material of the third gate insulating layer 218 includes at least one of silicon nitride and silicon oxide.

[0107] Specifically, after the third gate insulating layer 218 is formed, a third metal layer 219 can be formed, and the third metal layer 219 is etched to form a pattern. The material of the third metal layer 219 includes aluminum, titanium, molybdenum, copper, nickel, or an alloy or a stack thereof.

[0108] Specifically, after the third metal layer 219 is formed, a second interlayer insulating layer 220 can be formed. The material of the second interlayer insulating layer 220 includes at least one of silicon nitride and silicon oxide.

[0109] Specifically, after the second interlayer insulating layer 220 is formed, a first active layer 221 can be formed, and the first active layer 221 is etched to form a pattern.

[0110] Specifically, after the first active layer 221 is formed, a first gate insulating layer 222 and a first metal layer 223 can be formed.

[0111] A photoresist 41 is formed on the first metal layer, and the photoresist is etched for the first time. The structure of the display panel corresponding to this step is shown in (b) of FIG. 6.

[0112] Specifically, the photoresist can be formed on the first metal layer in an integral manner, and then the photoresist is etched by using a semi-transparent photomask, so that the thickness of the photoresist in different regions is different, and part of the photoresist is completely etched away.

[0113] The first metal layer and the first gate insulating layer are etched. The structure of the display panel corresponding to this step is shown in (c) of FIG. 6.

[0114] Specifically, it can be seen that part of the first metal layer and the first gate insulating layer in the region not covered by the photoresist is etched away, and the region of the first metal layer and the first gate insulating layer covered by the photoresist is reserved.

[0115] The photoresist is etched for the second time. The structure of the display panel corresponding to this step is shown in (a) of FIG. 7.

[0116] Specifically, by etching the photoresist, the photoresist in the region with a smaller thickness is etched away, and the photoresist in the region with a larger thickness is reserved. As can be seen from (a) of FIG. 7, part of the photoresist is etched away, and part of the photoresist is reserved.

[0117] etching the first metal layer; the structure of the display panel corresponding to this step is shown as (b) in FIG. 7;

[0118] Specifically, the first metal layer in the region not covered by the photoresist is etched, while the first metal layer in the region covered by the photoresist is reserved.

[0119] removing the photoresist; the structure of the display panel corresponding to this step is shown as (a) in FIG. 8;

[0120] forming a first interlayer insulating layer on the first metal layer, and etching the insulating layer to form a via; the structure of the display panel corresponding to this step is shown as (b) in FIG. 8;

[0121] Specifically, the via with different depths can be formed by twice etching, for example, the via penetrating the first active layer can be formed by first etching, and the via penetrating the second active layer can be formed by second etching.

[0122] forming a first source-drain layer, a first planarization layer, a second source-drain layer, a second planarization layer, a pixel electrode layer, a pixel definition layer and a support column on the first interlayer insulating layer; the structure of the display panel corresponding to this step is shown as FIG. 2.

[0123] Specifically, the first source-drain layer 225 can be formed on the first interlayer insulating layer, and the first source-drain layer 225 is etched to form a pattern, the material of the first source-drain layer 225 including aluminum, titanium, molybdenum, copper, nickel or alloy or stack thereof.

[0124] Specifically, after the first source-drain layer 225 is formed, the first planarization layer 226 can be formed, and the material of the first planarization layer 226 including organic material.

[0125] Specifically, after the first planarization layer 226 is formed, the second source-drain layer 227 can be formed, and the second source-drain layer 227 is etched to form a pattern, the material of the second source-drain layer 227 including aluminum, titanium, molybdenum, copper, nickel or alloy or stack thereof.

[0126] Specifically, after the second source-drain layer 227 is formed, the second planarization layer 228 can be formed, and the material of the second planarization layer 228 including organic material.

[0127] Specifically, after the second planarization layer 228 is formed, the pixel electrode layer 229 can be formed, and the material of the pixel electrode layer 229 including the stack of indium tin oxide and silver.

[0128] Specifically, after the pixel electrode layer 229 is formed, a pixel definition layer 230 can be formed on the pixel electrode layer 229, and the pixel definition layer 230 is etched to form a via hole. The material of the pixel definition layer includes polyimide.

[0129] Specifically, after the pixel definition layer 230 is formed, a support column 231 can be formed on the pixel definition layer 230.

[0130] Meanwhile, the display device provided by the embodiments of the present application includes the display panel as described in any of the above embodiments.

[0131] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0132] The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principle and implementation of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core idea thereof; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising a display area and a gate drive circuit area arranged at least one side of the display area, the display panel comprising: a substrate; a first active layer arranged at one side of the substrate, the first active layer comprising a first active pattern arranged in the display area and a second active pattern arranged in the gate drive circuit area, the first active pattern comprising a first doped portion, and the second active pattern comprising a second doped portion; a first gate insulating layer arranged at a side of the first active layer away from the substrate; a first metal layer arranged at a side of the first gate insulating layer away from the first active layer; wherein a material of the first active layer comprises an oxide semiconductor, the first gate insulating layer covers the second doped portion, and the first gate insulating layer does not cover the first doped portion. The first active pattern further comprises a first channel portion, the first gate insulating layer in the display area covers the first channel portion, and a projection of the first gate insulating layer on the substrate is located within a projection range of the first channel portion on the substrate. A thickness of the first gate insulating layer arranged corresponding to the first channel portion is equal to a thickness of the first gate insulating layer arranged corresponding to the second doped portion. The second active pattern further comprises a second channel portion, the first gate insulating layer in the gate drive circuit area covers the second channel portion. The display area is provided with a pixel drive circuit, the pixel drive circuit comprising: a first initialization transistor connected with a first initialization signal line, for inputting a first initialization signal to a first node under control of a first scan signal; a switch transistor, for inputting a data signal to a second node under control of a second scan signal; a drive transistor connected with the first initialization transistor at the first node and connected with the switch transistor at the second node, for driving a light emitting device to emit light under control of potentials of the first node and the second node; a compensation transistor connected with the drive transistor through the first node and a third node, for compensating a threshold voltage of the drive transistor under control of a third scan signal; wherein the first gate insulating layer does not cover a doped portion of at least one of the first initialization transistor and the compensation transistor. The gate drive circuit area is provided with an oxide semiconductor transistor, the first gate insulating layer does not cover a doped portion of the first initialization transistor, the first gate insulating layer does not cover a doped portion of the compensation transistor, the first gate insulating layer covers a doped portion of the oxide semiconductor transistor, and a pattern height of a source and a drain of the oxide semiconductor transistor is greater than a pattern height of a source and a drain of the first initialization transistor.

2. The display panel of claim 1, wherein, A material of the first gate insulating layer comprises silicon oxide.

3. The display panel of claim 2, wherein, The display panel further comprises a first interlayer insulating layer, the first interlayer insulating layer is arranged at a side of the first metal layer away from the first active layer, and a material of the first interlayer insulating layer comprises silicon nitride.

4. The display panel of claim 1, wherein, A thickness of the first gate insulating layer ranges from 20 nanometers to 600 nanometers.

5. The display panel of claim 1, wherein, ​ ​ ​ ​ ​ ​ 6. The display panel of claim 5, wherein, ​ 7. The display panel of claim 1, wherein, ​ 8. The display panel of claim 1, wherein, ​ 9. The display panel of claim 1, wherein, ​ 10. The display panel of claim 1, wherein, In the gate driving circuit region, a projection of the first gate insulating layer on the substrate overlaps the substrate.

11. A display device comprising a display panel, the display panel comprising a display region and a gate driving circuit region provided at least at one side of the display region, the display panel comprising: a substrate; a first active layer provided at one side of the substrate, the first active layer comprising a first active pattern provided at the display region and a second active pattern provided at the gate driving circuit region, the first active pattern comprising a first doped portion, and the second active pattern comprising a second doped portion; a first gate insulating layer provided at one side of the first active layer away from the substrate; a first metal layer provided at one side of the first gate insulating layer away from the first active layer; wherein a material of the first active layer comprises an oxide semiconductor, the first gate insulating layer covers the second doped portion, and the first gate insulating layer does not cover the first doped portion.

12. The display device of claim 11, wherein, The first active pattern further comprises a first channel portion, the first gate insulating layer in the display region covers the first channel portion, and a projection of the first gate insulating layer on the substrate in the display region is located within a projection range of the first channel portion on the substrate.

13. The display device of claim 12, wherein, A thickness of the first gate insulating layer provided corresponding to the first channel portion is equal to a thickness of the first gate insulating layer provided corresponding to the second doped portion.

14. The display device of claim 11, wherein, The second active pattern further comprises a second channel portion, the first gate insulating layer in the gate driving circuit region covers the second channel portion.

15. The display device of claim 11, wherein, The display region is provided with a pixel driving circuit, the pixel driving circuit comprising: a first initialization transistor connected to a first initialization signal line, for inputting a first initialization signal to a first node under control of a first scan signal; a switching transistor, for inputting a data signal to a second node under control of a second scan signal; a driving transistor connected to the first initialization transistor at the first node and connected to the switching transistor at the second node, for driving a light emitting device to emit light under control of potentials of the first node and the second node; a compensation transistor connected to the driving transistor through the first node and a third node, for compensating a threshold voltage of the driving transistor under control of a third scan signal; wherein the first gate insulating layer does not cover a doped portion of at least one of the first initialization transistor and the compensation transistor.

16. The display device of claim 15, wherein, The gate driving circuit region is provided with an oxide semiconductor transistor, the first gate insulating layer does not cover a doped portion of the first initialization transistor, the first gate insulating layer does not cover a doped portion of the compensation transistor, the first gate insulating layer covers a doped portion of the oxide semiconductor transistor, and a pattern height of a source and a drain of the oxide semiconductor transistor is greater than a pattern height of a source and a drain of the first initialization transistor.

17. The display device of claim 11, wherein, A material of the first gate insulating layer comprises silicon oxide.

18. The display device of claim 11, wherein, The display panel further comprises a first interlayer insulating layer disposed on a side of the first metal layer away from the first active layer, and a material of the first interlayer insulating layer comprises silicon nitride.

19. The display device of claim 11, wherein, The first gate insulating layer has a thickness ranging from 20 nm to 600 nm.

20. The display device of claim 11, wherein, In the gate driving circuit region, a projection of the first gate insulating layer on the substrate overlaps the substrate.

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