Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device, relating to the technical field of semiconductors. The semiconductor device comprises: a plurality of storage units distributed on different layers and stacked in a direction perpendicular to a substrate (1); and word lines (40) passing through the storage units of different layers and extending in the direction perpendicular to substrate (1). Each storage unit comprises a first transistor and a second transistor distributed in parallel; a first semiconductor layer (23a) of the first transistor forms a recess extending in parallel and having an opening facing the second transistor; a first gate electrode (26a) of the first transistor is arranged in the recess and close to the bottom wall of the recess; a corresponding word line (40) passes through the recess in the direction perpendicular to the substrate (1); a second semiconductor layer (23b) of the second transistor is arranged in the recess and surrounds side walls of the word line (40), and the second semiconductor layer (23b) is connected to the first gate electrode (26a); and the word line (40) fills the recess.

Description

A semiconductor device, a manufacturing method thereof, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410642552.6, filed on May 22, 2024, and entitled "A semiconductor device, a manufacturing method thereof, and an electronic device", the content of which is to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the technical field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising:

[0008] a plurality of memory cells distributed along a vertical substrate direction and stacked in different layers;

[0009] a word line extending along a vertical substrate direction through the memory cells in different layers;

[0010] The memory cell comprises a first transistor and a second transistor distributed along a parallel substrate direction, the first transistor comprises a first semiconductor layer and a first gate electrode, and the second transistor comprises a second semiconductor layer; the first semiconductor layer forms a groove extending along a parallel substrate direction and facing the second transistor, the groove comprises a bottom wall and an annular side wall; the first gate electrode is arranged in the groove close to one side of the bottom wall of the groove, and the word line penetrates the groove along a vertical substrate direction; the second semiconductor layer is arranged in the groove and surrounds the side wall of the word line, and the second semiconductor layer is connected with the first gate electrode, and the word line fills the groove.

[0011] In some embodiments, the first gate electrode is distributed on the bottom wall and the sidewall adjacent to the bottom wall of the recess, and the second semiconductor layer covers a surface of the first gate electrode facing away from the first semiconductor layer and is connected to the surface.

[0012] In some embodiments, a first gate insulating layer is arranged between the first gate electrode and the first semiconductor layer, the first gate insulating layer is arranged in the recess to cover the bottom wall and the sidewall of the recess, and the second semiconductor layer further covers a surface of the first gate insulating layer facing away from the first semiconductor layer and not covered by the first gate electrode.

[0013] In some embodiments, a first sub-hole is arranged on the sidewall of the first semiconductor layer facing away from the substrate, a second sub-hole is arranged on the sidewall of the first semiconductor layer facing toward the substrate, the word line penetrates the recess through the first sub-hole and the second hole, a first isolation sub-layer is arranged between the first semiconductor layer and the word line in the first sub-hole and surrounds the word line, and a second isolation sub-layer is arranged between the first semiconductor layer and the word line in the second sub-hole and surrounds the word line.

[0014] In some embodiments, the word line includes a first part extending in a direction perpendicular to the substrate and a second part distributed in the recess, and the first part and the second part are in a non-integral structure.

[0015] In some embodiments, the first transistor further includes a back gate electrode surrounding the sidewall of the recess, and the back gate electrode and the first gate electrode are arranged on the same side of the word line.

[0016] In some embodiments, a projection of the back gate electrode on the substrate overlaps a projection of the first gate electrode on the substrate.

[0017] In some embodiments, the first semiconductor layer includes a first end surface close to the bottom wall of the recess and a second end surface close to the opening of the recess, and the first transistor further includes a first electrode and a second electrode, the first electrode is connected to the first end surface, and the second electrode is connected to the second end surface.

[0018] In some embodiments, the second electrode is connected to all the second end surfaces.

[0019] In some embodiments, the second transistor includes a fourth electrode connected to a surface of the second semiconductor layer facing away from the bottom wall of the recess.

[0020] In some embodiments, the fourth electrode is connected to the second electrode to form an integral structure.

[0021] In some embodiments, the semiconductor device includes a multi-layer memory cell array, each layer of the memory cell array includes a plurality of memory cells arrayed along a first direction and a second direction, the first transistor and the second transistor are arrayed along the first direction, first electrodes of memory cells of a same column arrayed along the second direction of a same layer are connected to form a one-piece structure extending along the second direction, second electrodes and fourth electrodes of memory cells of the same column arrayed along the second direction of the same layer are connected to form a one-piece structure extending along the second direction.

[0022] In some embodiments, back gate electrodes of memory cells of the same column arrayed along the second direction of the same layer and different layers are connected to form a one-piece structure extending along the second direction and a direction perpendicular to the substrate.

[0023] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, including:

[0024] forming a stack structure including a first insulating layer and a sacrificial layer stacked in sequence on a substrate;

[0025] forming a first trench extending through the stack structure along a direction perpendicular to the substrate and extending along a second direction, and forming a first lateral trench by laterally etching the sacrificial layer based on the first trench; and forming a second trench extending through the stack structure along a direction perpendicular to the substrate and extending along the second direction, and forming a second lateral trench by laterally etching the sacrificial layer based on the second trench; wherein the first trench and the second trench are spaced apart along a first direction, and openings of the first lateral trench and the second lateral trench are opposite to each other;

[0026] forming a plurality of first holes extending through the stack structure along the first direction between the first trench and the second trench, the first holes dividing the sacrificial layer into a plurality of independent portions, and etching to remove the sacrificial layer of each independent portion to form a plurality of first lateral recesses;

[0027] forming a first semiconductor layer covering a bottom wall and side walls of the first lateral recesses in the first lateral recesses, and forming a first gate electrode distributed on the bottom wall and side walls adjacent to the bottom wall of the first lateral recesses;

[0028] forming a second hole extending through the stack structure along a direction perpendicular to the substrate and extending through the first lateral recesses, and the second hole is located within a projection of the first semiconductor layer on the substrate and outside a projection of the first gate electrode on the substrate;

[0029] exposing a surface of the first gate electrode in the first lateral recess away from the first semiconductor layer side, forming a second semiconductor layer and a word line in the second hole and the first lateral recess; the second semiconductor layer is disposed on a sidewall of the first lateral recess surrounding the word line, the second semiconductor layer is connected with the second gate electrode, and the word line extends in a direction perpendicular to the substrate and fills the second hole and the first lateral recess.

[0030] In some embodiments, the method further comprises:

[0031] lateral etching the first semiconductor layer based on the second hole to form a first lateral sub-recess disposed on a sidewall of the first semiconductor layer away from the substrate side, and to form a second lateral sub-recess disposed on a sidewall of the first semiconductor layer toward the substrate side;

[0032] forming a first isolation sub-layer filling the first lateral sub-recess and a second isolation sub-layer filling the second lateral sub-recess, the first isolation sub-layer surrounds the word line, and the second isolation sub-layer surrounds the word line.

[0033] In some embodiments, after forming the first semiconductor layer covering the bottom wall and the sidewall of the first lateral recess in the first lateral recess, the method further comprises: forming a third trench extending through the stack structure in a direction perpendicular to the substrate and extending in a second direction to expose the first semiconductor layer; forming a back gate electrode surrounding the first semiconductor layer in the third trench; the back gate electrode and the first gate electrode are disposed on the same side of the word line.

[0034] In some embodiments, the method further comprises:

[0035] depositing a first conductive thin film filling the first trench and the first lateral trench, etching to remove the first conductive thin film in the first trench, and retaining the first conductive thin film in the first lateral trench to form a first electrode line, the first electrode line being in contact with the first semiconductor layer.

[0036] In some embodiments, the method further comprises:

[0037] depositing a second conductive thin film filling the second trench and the second lateral trench, etching to remove the second conductive thin film in the second trench, and retaining the second conductive thin film in the second lateral trench to form a bit line, the bit line being in contact with the first semiconductor layer and the second semiconductor layer.

[0038] In some embodiments, forming a second semiconductor layer and a word line in the second hole and the first lateral recess comprises:

[0039] depositing a second semiconductor thin film, a gate insulating thin film, and a third conductive thin film in the second hole and the first lateral recess in order to form a second semiconductor layer, a gate insulating layer, and a first sub-electrode, the first sub-electrode filling the second hole and the first lateral recess;

[0040] etching to remove the first sub-electrode in the second hole while retaining the first sub-electrode in the first lateral recess;

[0041] etching to remove the second semiconductor layer and the gate insulating layer distributed on the sidewall of the second hole;

[0042] depositing a fourth conductive thin film to fill the second hole to form a second sub-electrode connected to the first sub-electrode, the first sub-electrode and the second sub-electrode forming the word line.

[0043] The electronic device provided by the embodiments of the present disclosure includes the semiconductor device described above, or the semiconductor device manufactured according to the manufacturing method of any of the semiconductor devices.

[0044] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly described herein.

[0045] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0046] SUMMARY

[0047] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is included to explain the present application, and are not intended to limit the present application.

[0048] FIG. 1A is a schematic perspective view of a semiconductor device according to an example embodiment; FIG. 1B is a schematic perspective view of a memory cell according to an example embodiment; FIG. 1C is a schematic cross-sectional view of the semiconductor device according to an example embodiment, taken along a direction cc’ parallel to the substrate; FIG. 1D is a schematic cross-sectional view of the semiconductor device according to an example embodiment, taken along a direction aa’; and FIG. 1E is a schematic equivalent circuit diagram of the semiconductor device according to an example embodiment;

[0049] FIG. 2 is a schematic front view of the semiconductor device according to an example embodiment after forming a stack structure;

[0050] FIG. 3A is a schematic plan view of the semiconductor device according to an example embodiment after forming a first protective layer 61 and a second insulating layer 12, and FIG. 3B is a schematic front view of the semiconductor device according to an example embodiment after forming the first protective layer 61 and the second insulating layer 12;

[0051] FIG. 4A is a plan view of a substrate after forming a second trench T2 and a second lateral trench T21 according to an exemplary embodiment, and FIG. 4B is a front view of a substrate after forming a second trench T2 and a second lateral trench T21 according to an exemplary embodiment;

[0052] FIG. 5A is a plan view of a substrate after forming a third insulating layer 13 according to an exemplary embodiment, FIG. 5B is a cross-sectional view of a substrate after forming a third insulating layer 13 along the aa' direction perpendicular to the substrate according to an exemplary embodiment, and FIG. 5C is a cross-sectional view of a substrate after forming a third insulating layer 13 along the bb' direction perpendicular to the substrate according to an exemplary embodiment;

[0053] FIG. 6A is a cross-sectional view of a substrate along the cc' direction parallel to the substrate after forming a first lateral recess according to an exemplary embodiment, and FIG. 6B is a cross-sectional view along the aa' direction of FIG. 6A;

[0054] FIG. 7 is a cross-sectional view along the aa' direction of a substrate after forming a first semiconductor layer, a first gate insulating layer, and a first gate electrode according to an exemplary embodiment;

[0055] FIG. 8 is a cross-sectional view along the aa' direction of a substrate after forming a second dummy layer according to an exemplary embodiment;

[0056] FIG. 9 is a cross-sectional view along the aa' direction of a substrate after forming a third dummy layer, a second protective layer, and a fourth insulating layer according to an exemplary embodiment;

[0057] FIG. 10A is a cross-sectional view along the aa' direction of a substrate after forming a third trench according to an exemplary embodiment, and FIG. 10B is a cross-sectional view along the bb' direction of a substrate after forming a third trench according to an exemplary embodiment;

[0058] FIG. 11A is a cross-sectional view along the aa' direction of a substrate after forming a third gate insulating layer and a back gate electrode according to an exemplary embodiment, and FIG. 11B is a cross-sectional view along the bb' direction of a substrate after forming a third gate insulating layer and a back gate electrode according to an exemplary embodiment;

[0059] FIG. 12A is a cross-sectional view along the cc' direction of a substrate after forming a second hole according to an exemplary embodiment, and FIG. 12B is a cross-sectional view along the aa' direction of FIG. 12A;

[0060] FIG. 13 is a cross-sectional view along the aa' direction of a substrate after forming an isolation layer according to an exemplary embodiment;

[0061] FIG. 14 is a cross-sectional view along the aa' direction of a substrate after forming a second semiconductor layer, a second gate insulating layer, and a first sub-electrode according to an exemplary embodiment;

[0062] FIG. 15A is a cross-sectional view along the cc' direction of a substrate after removing a parasitic semiconductor layer according to an exemplary embodiment, and FIG. 15B is a cross-sectional view along the aa' direction of a substrate after removing a parasitic semiconductor layer according to an exemplary embodiment.

[0063] DETAILED DESCRIPTION

[0064] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0065] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0066] The embodiments of the present disclosure are not necessarily limited to the sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings do not reflect actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0067] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of the components, and do not represent any order, number, or importance.

[0068] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0069] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integrally connected connection; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0070] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0071] In the present disclosure, it can be that the first electrode is a drain electrode and the second electrode is a source electrode, or it can be that the first electrode is a source electrode and the second electrode is a drain electrode. In the case of using a transistor of opposite polarity or in the case of a change in the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0072] In the present disclosure, "connection" includes a case where constituent elements are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0073] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0074] In the present disclosure, "A and B are of an integral structure" can mean that there is no clear boundary interface such as a clear fault or gap in the microstructure. Generally, a film layer formed by patterning on one film layer is integral with the connected film layer. For example, A and B are formed as one film layer using the same material and are simultaneously formed in a structure having a connection relationship by the same patterning process.

[0075] In the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0076] FIG. 1A is a schematic perspective view of a semiconductor device according to an example embodiment. As shown in FIG. 1A, the present disclosure provides a semiconductor device including a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate 1, and a plurality of word lines 40 extending in a direction perpendicular to the substrate 1. Each of the memory cell arrays can include a plurality of memory cells and a plurality of bit lines 30, and the plurality of memory cells can be arranged in a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1.

[0077] The memory cells at the same position in different layers share the same word line 40, i.e., are connected to the same word line 40.

[0078] The bit line 30 can be a conductive line extending along the second direction Y, and a plurality of bit lines 30 of the same layer of the memory cell array can be spaced apart from each other, and the plurality of bit lines 30 of the same layer can be distributed along the first direction X. The bit lines 30 of the memory cell arrays of different layers can be stacked on the substrate 1, and the bit lines 30 at the same position of different layers are spaced apart from each other.

[0079] The memory cell can include a first transistor and a second transistor. The first transistor and the second transistor of the same memory cell can be distributed along the first direction X. The first transistor can include a first gate electrode 26a, a first electrode 51, a second electrode 52, and a first semiconductor layer 23a. The second transistor can include a second gate electrode 26b, a third electrode 53, a fourth electrode 54, and a second semiconductor layer 23b. The first electrodes 51 of the first transistors of the same column distributed along the second direction Y of the same layer can be connected together to form a first electrode line 31 extending along the second direction Y; and the second electrodes 52 of the first transistors of the same column distributed along the second direction Y of the same layer can be connected together to form a bit line 30 extending along the second direction Y. The second electrodes 52 of the first transistors of the memory cells of two adjacent columns of the same layer can be connected to different bit lines 30.

[0080] In some embodiments, the first transistor can further include a back gate electrode 26c, and the back gate electrodes 26c of the second transistors of the same column of the same layer and different layers can be connected to form an integrated structure extending along a direction perpendicular to the substrate 1 and parallel to the second direction Y, i.e., form a planar film layer.

[0081] The following describes a semiconductor device including a plurality of vertically stacked memory cells at the same position as an example.

[0082] FIG. 1B is a schematic perspective view of a memory cell according to an example embodiment, FIG. 1C is a cross-sectional view of a semiconductor device according to an example embodiment along a direction cc' parallel to the substrate, and FIG. 1D is a cross-sectional view along an aa' direction in FIG. 1C. As shown in FIGS. 1A, 1B, 1C, and 1D, a semiconductor device according to an example embodiment can include:

[0083] A plurality of memory cells stacked along a direction perpendicular to the substrate 1, the memory cell can include a first transistor and a second transistor distributed along the first direction X, the first transistor can include a first electrode 51, a second electrode 52, a first semiconductor layer 23a, and a first gate electrode 26a; and the second transistor can include a second gate electrode 26b (only for distinguishing from the first gate electrode 26a, and does not mean that the second transistor includes two gate electrodes), a second gate insulating layer 24b, a second semiconductor layer 23b, a third electrode 53, and a fourth electrode 54.

[0084] The first semiconductor layer 23a forms a groove extending along a direction parallel to the substrate 1, the groove has an opening facing the word line 40, and the groove can include a bottom wall and annular side walls. The annular shape is, for example, a square ring. That is, the groove can include a bottom wall and four side walls, two of which are parallel to the substrate 1 and two of which are perpendicular to the substrate 1.

[0085] In some embodiments, the groove extends along the first direction X.

[0086] The first gate electrode 26a can be disposed in the groove to cover the bottom wall and the side walls of the groove that are less than or equal to a first preset length from the bottom wall. That is, the first gate electrode 26a is disposed in the groove close to one side of the bottom wall of the groove, and the first gate electrode 26a covers part of the side walls of the groove.

[0087] In some embodiments, the first transistor can further include a first gate insulating layer 24a disposed between the first gate electrode 26a and the first semiconductor layer 23a, the first gate insulating layer 24a being disposed in the groove to cover the bottom wall and the side walls of the groove. That is, the first gate insulating layer 24a completely covers the bottom wall and the side walls of the first semiconductor layer 23a.

[0088] In some embodiments, the word line 40 extends through the first semiconductor layer 23a along a direction perpendicular to the substrate 1. The side wall of the first semiconductor layer 23a away from the substrate 1 is provided with a first sub-hole, and the side wall of the first semiconductor layer 23a toward the substrate 1 is provided with a second sub-hole. The word line 40 extends from the first sub-hole to the groove through the first sub-hole along a direction perpendicular to the substrate 1, and extends from the groove to the outside of the groove through the second sub-hole.

[0089] In some embodiments, the word line 40 includes a first portion disposed in the groove and a second portion extending along a direction perpendicular to the substrate 1, the first portion is in contact with the second portion, and the first portion and the second portion are not in an integral structure. The word line 40 fills the groove. The scheme provided in this embodiment can control the opening and closing of the first transistor. When the first transistor is a read transistor and the second transistor is a write transistor, during data reading, the first transistor and the second transistor of the non-target memory cell can be turned off by the word line 40 to avoid current sharing. The word line 40 can control data reading and writing, thereby reducing the number of control lines and reducing the device area.

[0090] In some embodiments, the second semiconductor layer 23b can be disposed in the recess, the second semiconductor layer 23b encircles the word line 40; the second semiconductor layer 23b covers the surface of the first gate electrode 26a on the side facing away from the first semiconductor layer 23a, and the second semiconductor layer 23b is in contact with the surface of the first gate electrode 26a on the side facing away from the first semiconductor layer 23a. That is, the first gate electrode 26a is also multiplexed as the third electrode 53 of the second transistor.

[0091] In some embodiments, the second semiconductor layer 23b also covers part of the surface of the first gate insulating layer 24a on the side facing away from the first semiconductor layer 23a. That is, the second semiconductor layer 23b covers the area of the surface of the first gate insulating layer 24a on the side facing away from the first semiconductor layer 23a that is not covered by the first gate electrode 26a. Of the surface of the first gate insulating layer 24a on the side facing away from the first semiconductor layer 23a, part is covered by the first gate electrode 26a, and part is covered by the second semiconductor layer 23b.

[0092] In some embodiments, the memory cell can further include an isolation layer 16 disposed in the first sub-hole and the second sub-hole and encircling the word line 40, the isolation layer 16 including two parts, a first isolation sub-layer 161 disposed in the first sub-hole and encircling the word line 40, and a second isolation sub-layer 162 disposed in the second sub-hole and encircling the word line 40. The first isolation sub-layer 161 is distributed on the sidewall of the first sub-hole, and the second isolation sub-layer 162 is disposed on the sidewall of the second sub-hole. The first semiconductor layer 23a and the word line 40 are isolated by the first isolation sub-layer 161 and the second isolation sub-layer 162. The surface of the first isolation sub-layer 161 on the side facing the substrate 1 is in contact with the first gate insulating layer 24a, and the surface of the second isolation sub-layer 162 on the side facing away from the substrate 1 is in contact with the first gate insulating layer 24a.

[0093] In some embodiments, a second gate insulating layer 24b encircling the word line 40 is further disposed between the second semiconductor layer 23b and the word line 40. The second gate insulating layer 24b is disposed in the recess.

[0094] In some embodiments, the second gate insulating layers 24b of the second transistors at the same position of different layers are disconnected, such as physically disconnected.

[0095] In some embodiments, the second semiconductor layers 23b of the second transistors at the same position of different layers are disconnected, such as physically disconnected.

[0096] In some embodiments, the first transistor can further include a back gate electrode 26c surrounding a sidewall of the first semiconductor layer 23a, i.e. a sidewall of the recess formed by the first semiconductor layer 23a, where the sidewall is a sidewall of an outer surface of the recess, i.e. an outer sidewall of the recess. The back gate electrode 26c is disposed close to the outer sidewall of the recess at a side close to the bottom wall of the recess. The back gate electrode 26c and the first gate electrode 26a are disposed at the same side of the word line 40. The back gate electrode 26c and the first gate electrode 26a overlap in a projection of the substrate 1. The scheme provided in this embodiment can turn off the read transistor during the write operation when the first transistor is a read transistor and the second transistor is a write transistor. In addition, the scheme provided in this embodiment, the back gate electrode 26c surrounds the first semiconductor layer 23a, without occupying additional area, which is conducive to improving the device density.

[0097] In some embodiments, the first transistor can further include a third gate insulating layer 24c disposed between the first semiconductor layer 23a and the back gate electrode 26c, the third gate insulating layer 24c isolating the back gate electrode 26c and the first semiconductor layer 23a. The third gate insulating layers 24c of the first transistors in the same layer and the same column are connected to form an integrated structure. The third gate insulating layer 24c surrounds the sidewall of the first semiconductor layer 23a.

[0098] In some embodiments, the first semiconductor layer 23a includes a first end surface close to the bottom wall of the recess and a second end surface close to the opening of the recess. The first electrode 51 can be connected to the first end surface. The second electrode 52 can be connected to the second end surface of the recess and close the recess. That is, the second electrode 52 is connected to the entire area of the second end surface.

[0099] The fourth electrode 54 is connected to a surface of the second semiconductor layer 23b away from the bottom wall of the recess. The fourth electrode 54 and the second electrode 52 are connected to form an integrated structure, i.e. connected to form a bit line 30 extending in the second direction Y.

[0100] In some embodiments, the semiconductor device can include a hole penetrating through a plurality of the second transistors, and the second semiconductor layer 23b, the second gate insulating layer 24b, and the word line 40 are sequentially arranged from the outside to the inside in the hole. The scheme provided in this embodiment can form the second semiconductor layer 23b, the second gate insulating layer 24b, and the word line 40 of a plurality of second transistors through one process, simplifying the process.

[0101] In some embodiments, the first transistor can be a read transistor, and the second transistor can be a write transistor.

[0102] Figure 1E is an equivalent circuit diagram of the semiconductor device according to an exemplary embodiment. As shown in Figure 1E, the semiconductor device can include a first transistor and a second transistor, the first transistor including a first electrode 51, a second electrode 52, a first gate electrode 26a, and a back gate electrode 26c, the first electrode 51 being connected to a first electrode line 31, i.e., a source line SL, the second electrode 52 being connected to a bit line 30, the second transistor including a third electrode 53, a fourth electrode 54, and a second gate electrode 26b, the third electrode 53 and the first gate electrode 26a being multiplexed to the same electrode, and the electrode can serve as a storage node SN to store data, the fourth electrode 54 being connected to the bit line 30, and the second gate electrode 26b being connected to a word line 40, and the second gate electrode 26b can also serve as a gate electrode to control the first transistor. That is, the second gate electrode 26b can control the first transistor and the second transistor.

[0103] In some embodiments, the first transistor is a read transistor, and the second transistor is a write transistor. The working process of the circuit shown in Figure 1E is described by taking the first transistor and the second transistor as N-type transistors as an example.

[0104] In a write operation, the word line 40 connected to the target storage unit is loaded with a high level to open the second transistor (i.e., the write transistor), the back gate electrode 26c is loaded with a low level signal or a reverse voltage to close the first transistor (i.e., the read transistor) to prevent the first transistor from leaking, and then the bit line 30 is adjusted to a voltage corresponding to the logic data "1" or "0" to change the voltage of the storage node (SN) to write data to the SN, and then the second transistor is closed.

[0105] In a read operation, the word line 40 connected to a non-target storage unit is loaded with a reverse voltage to close the corresponding first transistor and second transistor, and for a target unit, a zero voltage or a small voltage (to ensure that the second transistor cannot be opened, but the first transistor is not closed) is applied to the word line 40 connected to the target unit, and a certain voltage difference is applied between the bit line 30 and the source line SL to detect the stored data by reading the current of the first transistor. For example, when the SN stores logic data "1", the channel of the first transistor is opened, and the current of the bit line 30 is large, and when the SN stores "0", the channel of the first transistor is closed, and the current of the bit line 30 is small.

[0106] The technical solution of the present embodiment is further illustrated by the manufacturing process of the semiconductor device of the present embodiment. The "patterning process" in the present embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which are mature manufacturing processes in the related art. The "lithography process" in the present embodiment includes coating of a film layer, mask exposure and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the present embodiment, it should be understood that "film" refers to a film of a certain material manufactured on a substrate by deposition or coating process. If the "film" does not need to be patterned or lithographed during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" still needs to be patterned or lithographed during the entire manufacturing process, it is referred to as a "film" before patterning, and a "layer" after patterning. The "layer" after patterning or lithography includes at least one "pattern".

[0107] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0108] 1) forming a stack structure;

[0109] A buffer layer film is deposited on the substrate 1 to form a buffer layer 2, and a first insulating film and a sacrificial layer film are sequentially and alternately deposited on the buffer layer 2 to form a stack structure including a plurality of alternately arranged first insulating layers 11 and sacrificial layers 10, as shown in FIG. 2, which is a front view after the stack structure is formed according to an exemplary embodiment.

[0110] As used herein, the term substrate means and includes a base material or construction on which materials such as vertical field effect transistors are formed. The substrate 1 can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate 1 can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0111] In some embodiments, the first insulating film and the sacrificial layer film can be deposited using a chemical vapor deposition method.

[0112] In some embodiments, the buffer layer film can be aluminum oxide (Al2O3) or the like, which can be used as an etching stop layer during subsequent etching.

[0113] In some embodiments, the first insulating film can be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) or the like.

[0114] In some embodiments, the sacrificial layer film can be polysilicon, but is not limited thereto, and can be other film layers.

[0115] 2) forming a first protective layer 61 and a second insulating layer 12;

[0116] Etching the stack structure from top to bottom (stopping etching on the buffer layer 2), a first trench T1 is formed; the first trench T1 extends along the second direction Y;

[0117] Based on the first trench T1, etching (etching along a direction parallel to the substrate 1) the sacrificial layer 10 by a first preset length, a first lateral trench T11 is formed in the sacrificial layer 10; a first electrode 51 can be subsequently formed in the first lateral trench T11;

[0118] Depositing a first protective layer film and a second insulating film in sequence, forming a first protective layer 61 and a second insulating layer 12 filling the first trench T1 and the first lateral trench T11, as shown in FIG. 3A and FIG. 3B, FIG. 3A is a top view provided by an exemplary embodiment after forming the first protective layer 61 and the second insulating layer 12, and FIG. 3B is a front view provided by an exemplary embodiment after forming the first protective layer 61 and the second insulating layer 12. The first protective layer 61 covers the inner walls of the first trench T1 and the first lateral trench T11.

[0119] In some embodiments, the first protective layer film can be a film layer having etching selectivity, such as silicon dioxide and the like. This film layer can serve as a protective layer for the film layer located outside the first trench T1 and the first lateral trench T11 during subsequent etching.

[0120] In some embodiments, the second insulating film can be a material having etching selectivity with the first insulating film, such as SiN and the like.

[0121] In some embodiments, the first protective layer film can not be deposited.

[0122] 3) forming a second trench T2 and a second lateral trench T21;

[0123] Etching the stack structure from top to bottom (stopping etching on the buffer layer 2), a second trench T2 is formed; the second trench T2 extends along the second direction Y;

[0124] etching the second trench T2 a second preset length laterally, a second lateral trench T21 is formed in the sacrificial layer 10; subsequently, a bit line 30 can be formed in the second lateral trench T21; as shown in FIG. 4A and FIG. 4B, FIG. 4A is a top view of the structure after forming the second trench T2 and the second lateral trench T21 according to an exemplary embodiment, and FIG. 4B is a front view of the structure after forming the second trench T2 and the second lateral trench T21 according to an exemplary embodiment.

[0125] 4) forming a third insulating layer 13;

[0126] depositing a first dummy layer film to fill the second trench T2 and the second lateral trench T21, and forming a first dummy layer;

[0127] etching the first insulating layer 11 and the sacrificial layer 10 in a direction perpendicular to the substrate 1 until the buffer layer 2, and forming a plurality of first holes penetrating the stack structure in the direction perpendicular to the substrate 1; at this time, the sacrificial layer 10 between the first trench T1 and the second trench T2 in the same layer is divided into a plurality of independent parts by the first holes, and the plurality of parts are distributed in the second direction Y; the first holes are located between the first lateral trench T11 and the second lateral trench T21, and the sidewalls expose the first lateral trench T11 and the second lateral trench T21.

[0128] depositing a third insulating film to fill the first holes, and forming a third insulating layer 13;

[0129] etching and removing the first dummy layer, and exposing the second trench T2 and the second lateral trench T21, as shown in FIG. 5A, FIG. 5B and FIG. 5C, FIG. 5A is a top view of the structure after forming the third insulating layer 13 according to an exemplary embodiment, FIG. 5B is a cross-sectional view of the structure along the aa' direction perpendicular to the substrate 1 after forming the third insulating layer 13 according to an exemplary embodiment, and FIG. 5C is a cross-sectional view of the structure along the bb' direction perpendicular to the substrate 1 after forming the third insulating layer 13 according to an exemplary embodiment.

[0130] In some embodiments, the first dummy layer film can be polysilicon.

[0131] In some embodiments, the third insulating film can be a low-K dielectric layer, such as SiO2, etc.

[0132] 5) forming a first lateral recess A1;

[0133] Based on the second trench T2 and the second lateral trench T21, the sacrificial layer 10 is removed by lateral etching to form a plurality of first lateral recesses A1; the bottom wall of the first lateral recess A1 is the first protective layer 61, the side walls on the upper and lower sides (i.e. the side walls in the direction parallel to the substrate 1) are the first insulating layer 11, and the two side walls perpendicular to the substrate 1 are the third insulating layer 13, as shown in FIG. 6A and FIG. 6B, wherein FIG. 6A is a cross-sectional view along the cc' direction parallel to the substrate 1 after the first lateral recess A1 is formed according to an exemplary embodiment; and FIG. 6B is a cross-sectional view along the aa' direction in FIG. 6A.

[0134] 6) forming the first semiconductor layer 23a, the first gate insulating layer 24a and the first gate electrode 26a;

[0135] The first semiconductor thin film, the first gate insulating thin film and the first conductive thin film are sequentially deposited, and the first semiconductor thin film, the first gate insulating thin film and the first conductive thin film in the second trench T2 and the second lateral trench T21 are removed by etching to form the first semiconductor layer 23a, the first gate insulating layer 24a and the first gate electrode 26a arranged in the first lateral recess A1; the first semiconductor layer 23a covers the bottom wall and the side walls of the first lateral recess A1, the first gate insulating layer 24a covers the first semiconductor layer 23a, and the first gate electrode 26a covers the first gate insulating layer 24a, as shown in FIG. 7, which is a cross-sectional view along the aa' direction after the first semiconductor layer 23a, the first gate insulating layer 24a and the first gate electrode 26a are formed according to an exemplary embodiment. The first gate electrode 26a does not completely fill the first lateral recess A1.

[0136] In some embodiments, the material of the first semiconductor thin film can be silicon or polycrystalline silicon or the like material with a band gap less than 2eV, or can be a wide band gap material, such as a metal oxide material with a band gap greater than 2eV.

[0137] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, etc.; and can also include other small amounts of doped elements.

[0138] In some embodiments, the material of the metal-oxide semiconductor layer or channel can include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0139] The band gap of these materials is wide, and the leakage current is low. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0140] The material of the metal-oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0141] The second semiconductor thin film is similar to the first semiconductor thin film in material, and will not be described again.

[0142] In some embodiments, the first gate insulating thin film can include one or more layers of high-K dielectric materials, such as dielectric materials with a dielectric constant K≥3.9. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. can be included. For example, at least one of the following high-K materials can be included, but not limited to: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0143] The second gate insulating thin film and the third gate insulating thin film are similar in material, and will not be described again.

[0144] In some embodiments, the first conductive thin film can be one or more of the following different types of materials:

[0145] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt and other metals; can be a metal alloy containing the aforementioned metals;

[0146] Alternatively, it can be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), conductive metal oxide materials such as indium oxide (InO); For example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

[0147] Alternatively, it can be a conductive polycrystalline silicon, silicon, germanium, silicon germanium, etc. after doping.

[0148] The subsequent second conductive film, third conductive film, fourth conductive film, fifth conductive film material is similar and will not be repeated.

[0149] 7) Forming a second dummy layer 9;

[0150] Depositing a second dummy layer film to form a second dummy layer 9, which fills the second trench T2 and the second lateral trench T21;

[0151] Etching to remove the second dummy layer 9 in the second trench T2, etching to remove the second dummy layer 9 in the second lateral trench T21, and etching to remove part of the second dummy layer 9 and part of the first gate electrode 26a in the first lateral recess A1, that is, etching the second dummy layer 9 and the first gate electrode 26a from the opening of the first lateral recess A1 inwardly by a third predetermined length, leaving a fourth predetermined length of the second dummy layer 9 and the first gate electrode 26a, as shown in Figure 8, which is a cross-sectional view along the direction aa' after forming the second dummy layer 9 according to an exemplary embodiment.

[0152] In some embodiments, the second dummy layer film can be an insulating material with etching selectivity with the first insulating layer 11, such as SiN.

[0153] 8) Forming a third dummy layer 8, a second protective layer 62 and a fourth insulating layer 14;

[0154] Depositing a third dummy layer film, which fills the first lateral recess A1, the second lateral trench T21 and the second trench T2, etching to remove the third dummy layer film in the second lateral trench T21 and the second trench T2, forming a third dummy layer 8 filling the first lateral recess A1;

[0155] The second protective layer film and the fourth insulating film are sequentially deposited, the fourth insulating film fills the second lateral trench T21 and the second trench T2, and the second protective layer 62 and the fourth insulating layer 14 are formed, as shown in FIG. 9, which is a cross-sectional view along the direction aa' after the third dummy layer 8, the second protective layer 62 and the fourth insulating layer 14 are formed according to an exemplary embodiment. The second protective layer film covers the inner walls of the second lateral trench T21 and the second trench T2.

[0156] In some embodiments, the second protective layer film can be a film layer having etching selectivity with the fourth insulating film, such as silicon dioxide or the like. The film layer can serve as a protective layer for the film layer outside the second lateral trench T21 and the second trench T2 during subsequent etching. The fourth insulating film can be a film layer having etching selectivity with the first insulating film, such as SiN or the like.

[0157] In some embodiments, the second protective layer film can not be deposited.

[0158] 9) Forming a third trench T3;

[0159] The first insulating layer 11 and the third insulating layer 13 in the preset back gate region are etched to form the third trench T3; the third insulating layer 13 can be etched in a direction perpendicular to the substrate 1 by dry etching to form a plurality of through holes penetrating the third insulating layer 13, and the first insulating layer 11 can be etched in the second direction Y through the through holes to form the third trench T3, which exposes part of the sidewalls of the plurality of first semiconductor layers 23a, as shown in FIGS. 10A and 10B, which are schematic views along the direction aa' and the direction bb' after the third trench T3 is formed according to an exemplary embodiment.

[0160] 10) Forming a third gate insulating layer 24c and a back gate electrode 26c;

[0161] The second gate insulating film and the second conductive film are sequentially deposited to form the third gate insulating layer 24c and the back gate electrode 26c, and the second conductive film fills the third trench T3; the back gate electrode 26c surrounds the first semiconductor layer 23a, the third gate insulating layer 24c is arranged between the first semiconductor layer 23a and the back gate electrode 26c, and the back gate electrodes 26c of the first transistors in the same column are connected to form an integrated structure, which can be a planar film layer extending in a direction perpendicular to the substrate 1.

[0162] etching the first protective layer 61 and the second insulating layer 12 in the first trench T1 and the first lateral trench T11, and etching the second protective layer 62 and the fourth insulating layer 14 in the second trench T2 and the second lateral trench T21;

[0163] depositing a third conductive thin film, which fills the first trench T1 and the first lateral trench T11, and fills the second trench T2 and the second lateral trench T21, etching the third conductive thin film in the first trench T1 and the second trench T2 to form a first electrode line 31 filled in the first lateral trench T11, the first electrode line 31 including the first electrodes 51 of the plurality of transistors, and to form a bit line 30 filled in the second lateral trench T21, the bit line 30 including the second electrodes 52 of the plurality of transistors;

[0164] depositing a fifth insulating thin film to form a fifth insulating layer 15 filled in the first trench T1 and the second trench T2; as shown in FIG. 11A and FIG. 11B, FIG. 11A is a schematic view of a cross section along the direction aa’ after forming the third gate insulating layer 24c and the back gate electrode 26c according to an exemplary embodiment, and FIG. 11B is a schematic view of a cross section along the direction bb’ after forming the third gate insulating layer 24c and the back gate electrode 26c according to an exemplary embodiment.

[0165] In some embodiments, the fifth insulating thin film can be a material having etching selectivity with the first insulating thin film, such as SiN.

[0166] 11) forming a second hole K2;

[0167] etching the stack structure from the top layer to the bottom layer (etching stops at the buffer layer 2) to form a plurality of second holes K2, the second holes K2 being located in the third dummy layer 8 in the orthographic projection of the substrate 1 (the second holes K2 being located in the sub-holes of the third dummy layer 8 to expose the third dummy layer 8), as shown in FIG. 12A and FIG. 12B, FIG. 12A is a cross-sectional view along the direction cc’ after forming the second holes K2 according to an exemplary embodiment, and FIG. 12B is a cross-sectional view along the direction aa’ in FIG. 12A. Subsequently, the second semiconductor layer 23b, the second gate insulating layer 24b and the second gate electrode 26b can be formed in the second holes K2.

[0168] In some embodiments, in a direction parallel to the substrate 1, the cross section of the second hole K2 can be square, circular, elliptical, etc.

[0169] 12) forming an isolation layer 16;

[0170] etching the first semiconductor layer 23a based on the second hole K2 to form a second lateral recess around the second hole K2; two second lateral recesses are formed on the same first semiconductor layer 23a; one is arranged on the sidewall of the first semiconductor layer 23a away from the substrate 1 (the sidewall of the two sidewalls of the substrate 1 which is farther away from the substrate 1), and the other is arranged on the sidewall of the first semiconductor layer 23a towards the substrate 1 (the sidewall of the two sidewalls of the substrate 1 which is closer to the substrate 1);

[0171] depositing a sixth insulating film, which fills the second hole K2 and the second lateral recess, etching to remove the sixth insulating film in the second hole K2, and retaining the sixth insulating film in the second lateral recess to form an isolation layer 16; the isolation layer 16 surrounds the second hole K2; the subsequent isolation layer 16 can isolate the second gate electrode 26b and the first semiconductor layer 23a; as shown in FIG. 13, which is a cross-sectional view along the direction of aa’ after the formation of the isolation layer 16 according to an exemplary embodiment. The second lateral recess is not shown in FIG. 13, and the area filled by the isolation layer 16 is the second lateral recess. The sixth insulating film filling the second lateral recess arranged on the sidewall of the first semiconductor layer 23a away from the substrate 1 forms a first isolation sub-layer 161, and the sixth insulating film filling the second lateral recess arranged on the sidewall of the first semiconductor layer 23a towards the substrate 1 forms a second isolation sub-layer 162.

[0172] In some embodiments, the isolation layer 16 can be a Low-k dielectric layer, such as SiO2, etc.

[0173] 13) forming a second semiconductor layer 23b, a second gate insulating layer 24b and a first sub-electrode 26b_1;

[0174] etching and removing the third dummy layer 8 and the second dummy layer 9 based on the second hole K2 to expose the first lateral recess A1 and expose the first gate electrode 26a in the first lateral recess A1 away from the first semiconductor layer 23a;

[0175] depositing a second semiconductor film, a third gate insulating film and a fourth conductive film in the second hole K2 and the first lateral recess A1 in sequence to form a second semiconductor layer 23b, a second gate insulating layer 24b and a first sub-electrode 26b_1, as shown in FIG. 14, which is a schematic diagram along the direction of aa’ after the formation of the second semiconductor layer 23b, the second gate insulating layer 24b and the first sub-electrode 26b_1 according to an exemplary embodiment.

[0176] 14) removing the parasitic semiconductor layer;

[0177] The dry etching removes the first sub-electrode 26b_1 in the second hole K2 along a direction perpendicular to the substrate 1, and retains the first sub-electrode 26b_1 in the first lateral recess A1; the retained first sub-electrode 26b_1 is a first part of the word line 40;

[0178] The wet etching removes the second semiconductor layer 23b and the second gate insulating layer 24b distributed on the sidewall of the second hole K2; thereby removing the second semiconductor layer 23b between layers, and disconnecting the second semiconductor layer 23b of the storage unit in different layers;

[0179] The fifth conductive thin film is deposited, which fills the second hole K2 and forms a second sub-electrode 26b_2 connected with the first sub-electrode 26b_1; the first sub-electrode 26b_1 and the second sub-electrode 26b_2 form the word line 40, as shown in FIG. 15A and FIG. 15B; FIG. 15A is a cross-sectional view along the direction cc' of FIG. 15A after removing the parasitic semiconductor layer according to an exemplary embodiment, and FIG. 15B is a schematic view along the direction aa' of FIG. 15B after removing the parasitic semiconductor layer according to an exemplary embodiment. The second sub-electrode 26b_2 is a second part of the word line 40 extending along a direction perpendicular to the substrate 1.

[0180] The semiconductor device according to any one of the preceding embodiments, or the semiconductor device manufactured by the manufacturing method according to any one of the preceding embodiments, can be used in an electronic device. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like.

[0181] Although the embodiments of the present application are disclosed as above, the above description is only used to facilitate understanding of the present application, and is not intended to limit the present application. Any modification and change in the form and details of the embodiments of the present application can be made by those skilled in the art without departing from the spirit and scope of the present application. The patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of memory cells distributed in different tiers stacked along a vertical substrate direction; a word line extending along a vertical direction of the substrate through the memory cells in the different tiers; the memory cell comprising a first transistor and a second transistor distributed along a parallel direction of the substrate, the first transistor comprising a first semiconductor layer and a first gate electrode, the second transistor comprising a second semiconductor layer; the first semiconductor layer forming a recess toward the second transistor along an opening extending in a parallel direction of the substrate, the recess comprising a bottom wall and a ring-shaped sidewall; the first gate electrode disposed in the recess close to a side of the bottom wall of the recess, the word line penetrating the recess along a vertical direction of the substrate; the second semiconductor layer disposed in the recess and surrounding the sidewall of the word line, and the second semiconductor layer connected with the first gate electrode, the word line filling the recess. the first gate electrode distributed on the bottom wall of the recess and the sidewall adjacent to the bottom wall, the second semiconductor layer covering a surface of the first gate electrode away from the first semiconductor layer and connected with the surface. a first gate insulating layer disposed between the first gate electrode and the first semiconductor layer, the first gate insulating layer disposed in the recess covering the bottom wall and the sidewall of the recess, the second semiconductor layer further covering a surface of the first gate insulating layer away from the first semiconductor layer and not covered by the first gate electrode. a first sub-hole provided on a sidewall of the first semiconductor layer away from the substrate, and a second sub-hole provided on a sidewall of the first semiconductor layer toward the substrate, the word line penetrating the recess through the first sub-hole and the second sub-hole, a first isolation sub-layer surrounding the word line provided between the first semiconductor layer and the word line in the first sub-hole, and a second isolation sub-layer surrounding the word line provided between the first semiconductor layer and the word line in the second sub-hole.

2. The semiconductor device of claim 1, wherein, the word line comprising a first portion extending along a vertical direction of the substrate and a second portion distributed in the recess, the first portion and the second portion being non-integrated structures.

3. The semiconductor device of claim 1, wherein, the first transistor further comprising a back gate electrode surrounding the sidewall of the recess, the back gate electrode and the first gate electrode disposed on the same side of the word line.

4. The semiconductor device of claim 1, wherein, a projection of the back gate electrode on the substrate overlaps a projection of the first gate electrode on the substrate.

5. The semiconductor device of claim 1, wherein, the first semiconductor layer comprising a first end surface close to the bottom wall of the recess and a second end surface close to the opening of the recess, the first transistor further comprising a first electrode and a second electrode, the first electrode connected with the first end surface, and the second electrode connected with the second end surface.

6. The semiconductor device of claim 1, wherein, the second electrode connected with all the second end surfaces.

7. The semiconductor device of claim 6, wherein, the second transistor comprising a fourth electrode connected with a surface of the second semiconductor layer away from the bottom wall of the recess.

8. The semiconductor device of claim 6, wherein, the fourth electrode connected with the second electrode to form an integrated structure.

9. The semiconductor device of claim 8, wherein, ​ 10. The semiconductor device of claim 9, wherein, ​ 11. The semiconductor device of claim 10, wherein, ​ 12. The semiconductor device of claim 10, wherein, The semiconductor device includes a multi-layered memory cell array, each layer of the memory cell array includes a plurality of memory cells arrayed along a first direction and a second direction, the first and second transistors are arrayed along the first direction, the first electrodes of the memory cells of the same column along the second direction of the same layer are connected to form an integrated structure extending along the second direction, the second electrodes and the fourth electrodes of the memory cells of the same column along the second direction of the same layer are connected to form an integrated structure extending along the second direction.

13. The semiconductor device of claim 12, wherein, The back gate electrodes of the memory cells of the same column along the second direction of the same layer and different layers are connected to form an integrated structure extending along the second direction and perpendicular to the substrate direction.

14. A method for manufacturing a semiconductor device, comprising: forming a stack structure including a first insulating layer and a sacrificial layer stacked in sequence on a substrate; forming a first trench extending along a second direction and penetrating the stack structure in a direction perpendicular to the substrate, and forming a first lateral trench by laterally etching the sacrificial layer based on the first trench; forming a second trench extending along the second direction and penetrating the stack structure in the direction perpendicular to the substrate, and forming a second lateral trench by laterally etching the sacrificial layer based on the second trench; wherein the first trench and the second trench are spaced apart along a first direction, and the openings of the first lateral trench and the second lateral trench are opposite to each other; forming a plurality of first holes extending along the first direction and penetrating the stack structure between the first trench and the second trench, the first holes dividing the sacrificial layer into a plurality of independent portions, and etching the sacrificial layer of each independent portion to form a plurality of first lateral recesses; forming a first semiconductor layer covering the bottom wall and the sidewalls of the first lateral recesses in the first lateral recesses, and forming a first gate electrode distributed on the bottom wall and the sidewalls adjacent to the bottom wall of the first lateral recesses; forming a second hole penetrating the first lateral recesses and the stack structure in the direction perpendicular to the substrate, and the second hole is located within the first semiconductor layer in the projection of the substrate and is located outside the first gate electrode in the projection of the substrate; exposing the surface of the first gate electrode in the first lateral recesses away from the first semiconductor layer, and forming a second semiconductor layer and a word line in the second hole and the first lateral recesses; the second semiconductor layer is arranged on the sidewalls of the word line within the first lateral recesses, the second semiconductor layer is connected to the first gate electrode, and the word line extends in the direction perpendicular to the substrate and fills the second hole and the first lateral recesses.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising: laterally etching the first semiconductor layer based on the second hole to form a first lateral sub-recess arranged on the sidewalls of the first semiconductor layer away from the substrate, and to form a second lateral sub-recess arranged on the sidewalls of the first semiconductor layer toward the substrate. forming a first isolation sub-layer filling the first lateral sub-trench and a second isolation sub-layer filling the second lateral sub-trench, the first isolation sub-layer surrounding the word line, the second isolation sub-layer surrounding the word line.

16. The method of manufacturing a semiconductor device according to claim 14 or 15, wherein After forming the first semiconductor layer covering the bottom wall and the sidewall of the first lateral trench, the method further comprises: forming a third trench extending through the stack structure in a direction perpendicular to the substrate and extending in a second direction to expose the first semiconductor layer; forming a back gate electrode surrounding the first semiconductor layer in the third trench; the back gate electrode and the first gate electrode are disposed on the same side of the word line.

17. The method of manufacturing a semiconductor device according to claim 14 or 15, further comprising: depositing a first conductive thin film filling the first trench and the first lateral trench, etching to remove the first conductive thin film in the first trench, leaving the first conductive thin film in the first lateral trench, forming a first electrode line, the first electrode line being in contact with the first semiconductor layer.

18. The method of manufacturing a semiconductor device according to claim 14 or 15, further comprising: depositing a second conductive thin film filling the second trench and the second lateral trench, etching to remove the second conductive thin film in the second trench, leaving the second conductive thin film in the second lateral trench, forming a bit line, the bit line being in contact with the first semiconductor layer, the second semiconductor layer.

19. The method of manufacturing a semiconductor device according to Claim 14 or 15, wherein, forming a second semiconductor layer and a word line in the second hole and the first lateral trench comprises: sequentially depositing a second semiconductor thin film, a gate insulating thin film, a third conductive thin film in the second hole and the first lateral trench, forming a second semiconductor layer, a gate insulating layer and a first sub-electrode, the first sub-electrode filling the second hole and the first lateral trench; etching to remove the first sub-electrode in the second hole, leaving the first sub-electrode in the first lateral trench; etching to remove the second semiconductor layer and the gate insulating layer distributed on the sidewall of the second hole; depositing a fourth conductive thin film filling the second hole, forming a second sub-electrode connected with the first sub-electrode, the first sub-electrode and the second sub-electrode forming the word line.

20. An electronic device comprising the semiconductor device according to any one of claims 1 to 13, or a semiconductor device formed according to the method of manufacturing a semiconductor device according to any one of claims 14 to 19.

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