Semiconductor structure and preparation method therefor, and electronic device

Abstract

The present disclosure relates to the field of semiconductors, and relates to a semiconductor structure and a preparation method therefor, which are used for increasing storage density. The semiconductor structure comprises a shared bit line (300), a read source line (400) and memory cells. The shared bit line (300) and the read source line (400) are arranged in a first direction, and both extend in a second direction. Each memory cell is located between the shared bit line (300) and the read source line (400), and comprises a write transistor (500) and a read transistor (200). A write channel layer (510) of the write transistor (500) surrounds a write gate dielectric layer (520), and is connected to the shared bit line (300) in the first direction. The read transistor (200) comprises a read transistor base structure (210) and a back gate structure (220). The read transistor base structure (210) comprises a storage gate (211), a first read gate dielectric layer (212) and a read channel layer (213). The back gate structure (220) comprises a second read gate dielectric layer (221) and a control gate (222). The storage gate (211) is located on the side of the write transistor (500) away from the shared bit line (300) in the first direction, and the storage gate (211) forms a U shape around the write channel layer (510). The control gate (222) is located on at least one side of the storage gate (211) in the second direction. The read channel layer (213) is located between the control gate (222) and the storage gate (211), and connects the shared bit line (300) to the read source line (400).

Description

Semiconductor structure, method of manufacturing the same, and electronic device

[0001] Cross-reference to Related Applications

[0002] The present disclosure claims priority to a Chinese patent application No. 2024106411307, filed on May 22, 2024, and entitled “Semiconductor structure, method of manufacturing the same, and electronic device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor structure, a method of manufacturing the same, and an electronic device. BACKGROUND

[0004] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0005] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0006] SUMMARY

[0007] According to various embodiments of the present disclosure, a semiconductor structure and a method of manufacturing the same are provided.

[0008] According to various embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising:

[0009] a shared bit line and a read source line, the shared bit line and the read source line being arranged along a first direction and both extending along a second direction, the second direction intersecting the first direction;

[0010] a storage unit between the shared bit line and the read source line in the first direction, the storage unit comprising:

[0011] a write transistor comprising a write gate, a write gate dielectric layer surrounding the write gate, and a write channel layer surrounding the write gate dielectric layer and connected to the shared bit line in the first direction;

[0012] The read transistor comprises a read tube base structure and a back gate structure, the read tube base structure comprises a storage gate, a first read gate dielectric layer and a read channel layer, the back gate structure comprises a second read gate dielectric layer and a control gate, the storage gate is located on a side of the write transistor away from the shared bit line in the first direction, and the storage gate is in a U shape around the write channel layer, the control gate is located on at least one side of the storage gate in the second direction, the read channel layer is located between the control gate and the storage gate, and connects the shared bit line and the read source line, the first read gate dielectric layer is located between the read channel layer and the storage gate, and the second read gate dielectric layer is located between the read channel layer and the control gate.

[0013] In some embodiments, in a plane determined by the first direction and the second direction, the first read gate dielectric layer is in a U shape around the storage gate, and the read channel layer is in a U shape around the first read gate dielectric layer; the read source line connects the read channel layer in the first direction.

[0014] In some embodiments, both ends of the read channel layer extend from both ends of the first read gate dielectric layer towards the side of the shared bit line;

[0015] The shared bit line comprises a connecting part and an extension part, the connecting part is located between both ends of the read channel layer in the second direction, and the extension part connects the connecting part and extends along the second direction.

[0016] In some embodiments, the second read gate dielectric layer surrounds the control gate.

[0017] In some embodiments, the same read source line is symmetrically provided with the storage unit connected thereto on opposite sides in the first direction.

[0018] In some embodiments, the semiconductor structure further comprises:

[0019] A substrate, a plurality of the storage units are stacked on the substrate;

[0020] A write word line extends from above the top layer of the storage units towards the substrate and comprises a plurality of the write gates of the write transistors arranged in a direction perpendicular to the substrate;

[0021] A read word line extends from above the top layer of the storage units towards the substrate and comprises a plurality of the control gates of the read transistors arranged in a direction perpendicular to the substrate;

[0022] The read source line extends from above the memory cell to the substrate and in the second direction, connecting the read channel layer of the plurality of read transistors arranged in a direction perpendicular to the substrate and in the second direction.

[0023] In some embodiments, the semiconductor structure further comprises:

[0024] The plurality of first dielectric layers are stacked with intervals, the memory cell and the shared bit line are located between adjacent layers of the first dielectric layers, and the first read gate dielectric layer and the read channel layer extend to the surface of the first dielectric layer on both sides thereof between adjacent layers of the first dielectric layers;

[0025] A first isolation layer is located between the memory gate and the first dielectric layer, insulating and separating the read channel layer and the write channel layer;

[0026] A second isolation layer is located between adjacent layers of the first dielectric layers and between the shared bit line and the memory gate;

[0027] A first filling layer is located on a side of the shared bit line away from the memory cell in the first direction and extends from above the memory cell to the substrate;

[0028] A second filling layer is located on a side of the read channel layer away from the memory gate in the second direction and extends from above the memory cell to the substrate, and the back gate structure penetrates the second filling layer.

[0029] According to various embodiments of the present disclosure, a method for manufacturing a semiconductor structure is also provided, the method comprising:

[0030] providing a substrate,

[0031] forming a read tube base structure on the substrate, the read tube base structure comprising a memory gate, a first read gate dielectric layer, and a read channel layer, the memory gate being U-shaped and having an opening in a first direction, the first read gate dielectric layer and the read channel layer being located on at least one side of the memory gate in a second direction, the first read gate dielectric layer being located between the read channel layer and the memory gate in the second direction, the second direction intersecting the first direction;

[0032] forming a shared bit line on a side of the memory gate having the opening in the first direction and forming a read source line on the other side of the memory gate in the first direction, the shared bit line and the read source line both connecting the read channel layer and extending in the second direction;

[0033] a back gate structure is formed on at least one side of the storage gate in the second direction, the back gate structure and the read tube base structure form a read transistor, and the back gate structure includes a second read gate dielectric layer and a control gate, the read channel layer is located between the control gate and the storage gate, and the second read gate dielectric layer is located between the read channel layer and the control gate;

[0034] a write transistor is formed on one side of the storage gate close to the shared bit line in the first direction, the write transistor includes a write gate, a write gate dielectric layer, and a write channel layer, the write gate dielectric layer surrounds the write gate, the write channel layer surrounds the write gate dielectric layer, and the write channel layer is connected to the shared bit line and the storage gate on both sides in the first direction and is surrounded by the storage gate.

[0035] In some embodiments, before the read tube base structure is formed on the substrate, the method comprises:

[0036] a stack material layer is formed on the substrate, the stack material layer includes alternately stacked first dielectric material layers and second dielectric material layers;

[0037] an initial filling layer is formed in the stack material layer, the initial filling layer penetrates the stack material layer;

[0038] on both sides of the initial filling layer in the first direction, a first slot extending in the second direction and a second slot extending in the second direction are respectively etched from the stack material layer, a dummy bit line layer is formed in the first slot, and a dummy source line layer is formed in the second slot, the first slot includes a first trench and a first lateral slot, the first trench penetrates the stack material layer, and the first lateral slot is formed by laterally etching the second dielectric material layer to the initial filling layer, and the second slot penetrates the stack material layer.

[0039] In some embodiments, the read tube base structure is formed on the substrate, comprising:

[0040] the stack material layer is etched between the dummy bit line layer and the dummy source line layer to form an opening, the remaining first dielectric material layer forms a first dielectric layer, the opening is located on one side of the initial filling layer in the second direction, and the opening includes a through hole and a lateral hole, the through hole penetrates the stack material layer, and the lateral hole is connected to the through hole and is formed by etching the second dielectric material layer;

[0041] forming a read trench initial layer, a first read gate dielectric initial layer and a storage gate initial layer in the lateral hole, the read trench initial layer is located on the hole wall of the lateral hole, the first read gate dielectric initial layer is located on the surface of the read trench initial layer, and the storage gate initial layer is located on the surface of the first read gate dielectric initial layer and protrudes in the direction towards the through hole;

[0042] forming a first isolation layer between the storage gate initial layer and the first dielectric layer, and forming a dummy write tube layer in the remaining space of the opening hole;

[0043] removing the dummy bit line layer to open the first slot again, and etching the read trench initial layer, the first read gate dielectric initial layer and the storage gate initial layer in sequence from the first lateral slot to form the read trench layer, the first read gate dielectric intermediate layer and the storage gate respectively, and a lateral extension hole is formed between the storage gate and the first lateral slot;

[0044] forming a second isolation layer covering the storage gate, and etching to remove the first read gate dielectric intermediate layer between the second isolation layer and the first lateral slot to form a first read gate dielectric layer.

[0045] In some embodiments, the storage gate is provided with an opening on one side in the first direction to form a shared bit line, and a read source line is formed on the other side of the storage gate in the first direction, comprising:

[0046] forming a shared bit line in the remaining space of the lateral extension hole and the first lateral slot after forming the first read gate dielectric layer;

[0047] forming a first filling layer in the first groove;

[0048] replacing the dummy source line layer with a read source line.

[0049] In some embodiments, before forming the dummy bit line layer in the first slot, comprising:

[0050] forming a third dielectric layer on at least the surface of the second dielectric material layer exposed by the first slot;

[0051] And, when forming the lateral hole of the opening hole, the second dielectric material layer is etched with the third dielectric layer as the etching stop layer, so that the hole depth of the lateral hole formed on the side close to the dummy bit line layer is smaller than the hole depth of the lateral hole on the side close to the dummy source line layer.

[0052] In some embodiments, the write transistor is formed on the side of the storage gate close to the shared bit line in the first direction, comprising:

[0053] removing the dummy write tube layer;

[0054] forming a write channel layer in the lateral hole, the write channel layer being formed on a hole wall surface of the lateral hole opposite to the through hole, and forming a write gate dielectric layer on a surface of the write channel layer;

[0055] forming a write word line in a remaining space of the opening, the write word line comprising a plurality of the write gates of the write transistors arranged in a direction perpendicular to the substrate.

[0056] In some embodiments, the back gate structure formed by the read channel layer on at least one side of the memory gate in the second direction comprises:

[0057] etching a region of the initial filling layer close to the read channel layer to form a back gate hole, and the remaining initial filling layer forming a second filling layer;

[0058] forming the second read gate dielectric layer and a read word line in the back gate hole, the read word line comprising a plurality of the control gates of the read transistors arranged in a direction perpendicular to the substrate.

[0059] According to various embodiments of the present disclosure, an electronic device is also provided, which comprises the semiconductor structure described in the above embodiments, or a semiconductor structure prepared according to the preparation method of the semiconductor structure described in the above embodiments.

[0060] The details of one or more embodiments of the present disclosure are presented in the accompanying drawings and description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings needed to be used in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description only illustrate some of the embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0062] FIG. 1 is a flowchart of a preparation method of a semiconductor structure provided in an embodiment;

[0063] FIGS. 2 to 23 are structural schematic diagrams of structures obtained in a preparation process of a semiconductor structure provided in an embodiment; in FIGS. 2 to 8 and 12 to 23, (a) is a perspective schematic diagram, and the rest of the diagrams are related cross-sectional schematic diagrams of longitudinal sections along the cross-sectional lines marked in (a); FIGS. 9 to 11 are cross-sectional schematic diagrams;

[0064] FIG. 24 is a perspective structural schematic view of a semiconductor structure provided in an embodiment.

[0065] It can be understood that in FIGS. 2 to 23, when different film layers adopt the same material, some of the drawings connect the different film layers of the same material, so that the drawings are closer to the actual structural topography.

[0066] For a better description and illustration of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions. DETAILED DESCRIPTION

[0067] For the purpose of understanding the present disclosure, a more complete description of the present disclosure will be provided in reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided for the purpose of making the disclosure of the present disclosure more thorough and comprehensive.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0069] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0070] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0071] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0072] In one embodiment, referring to FIG. 1, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0073] In step S1, a substrate 100 is provided.

[0074] Referring to FIG. 2, the substrate 100 can comprise a semiconductor substrate 110. The semiconductor substrate 110 can include, but is not limited to, a silicon substrate. In addition, the substrate 100 can further comprise an insulating isolation layer 120, which is used to insulate and isolate the subsequently formed memory cell from the semiconductor substrate 110, so as to prevent leakage between the semiconductor substrate 110.

[0075] In step S3, referring to FIG. 16, a read pipe base structure 210 is formed on the substrate 100, the read pipe base structure 210 comprising a memory gate 211, a first read gate dielectric layer 212 and a read channel layer 213, the memory gate 211 being in a U shape and having an opening in a first direction D1, the first read gate dielectric layer 212 and the read channel layer 213 being located on at least one side of the memory gate 211 in a second direction D2, the first read gate dielectric layer 212 being located between the read channel layer 213 and the memory gate 211 in the second direction D2, the second direction D2 intersecting the first direction D1.

[0076] The read pipe base structure 210 can be a base transistor structure of the read transistor 200 in the memory cell.

[0077] The storage gate 211 contacts with the write channel layer of the write transistor, which can be a storage node of the memory cell. The material of the storage gate 211 can include but is not limited to a conductive material such as TiN.

[0078] The first read gate dielectric layer 212 is located between the storage gate 211 and the read channel layer 213, and the material thereof can include but is not limited to HfOx, HfSiOx, HfOx / SiO2stacked material, or Al2O3, STO, and the like.

[0079] The read channel layer 213 can be a doped semiconductor layer, so that a junctionless read transistor 200 can be formed. The material of the read channel layer 213 can include but is not limited to polysilicon.

[0080] The first read gate dielectric layer 212 and the read channel layer 213 can be formed on both sides of the storage gate 211 in the second direction D2, so that the read transistor 200 can form a conductive channel on both sides of the storage gate 211. Of course, the first read gate dielectric layer 212 and the read channel layer 213 can be formed on one side of the storage gate 211 in the second direction D2, which is not limited here.

[0081] At step S4, referring to FIG. 19, the shared bit line 300 is formed on the side of the storage gate 211 where the opening in the first direction D1 is provided, and the read source line 400 is formed on the other side of the storage gate 211 in the first direction D1. Both the shared bit line 300 and the read source line 400 are connected to the read channel layer 213 and extend in the second direction D2.

[0082] The shared bit line 300 and the read source line 400 are respectively connected to both ends of the read channel layer 213, so as to respectively connect the source region and the drain region of the read transistor. At this time, the shared bit line 300 and the read source line 400 can respectively provide the read bit line signal and the source signal for the read transistor, wherein the source signal can be, for example, a ground signal.

[0083] Meanwhile, the shared bit line 300 and the read source line 400 both extend in the second direction D2, so as to provide signals for a plurality of read transistors arranged in the second direction D2.

[0084] The materials of the shared bit line 300 and the shared bit line 300 can be the same or different. As an example, the shared bit line 300 can include but is not limited to a conductive material such as TiN. The shared bit line 300 can include but is not limited to a conductive metal material or a heavily doped polysilicon, and the like.

[0085] Step S5, please refer to FIG. 21, a back gate structure 220 is formed on at least one side of the storage gate 211 in the second direction D2, the back gate structure 220 and the read tube base structure 210 form a read transistor 200, and the back gate structure 220 includes a second read gate dielectric layer 221 and a control gate 222, the read channel layer 213 is located between the control gate 222 and the storage gate 211, and the second read gate dielectric layer 221 is located between the read channel layer 213 and the control gate 222.

[0086] The control gate 222 and the storage gate 211 of the back gate structure 220 are located on both sides of the read channel layer 213, which can be used to control the switching of the read transistor 200.

[0087] When the first read gate dielectric layer 212 and the read channel layer 213 are formed on both sides of the storage gate 211 in the second direction D2, two back gate structures 220 can be formed corresponding to the same read transistor 200. Thus, the control ability of the control gate 222 can be effectively improved. When the first read gate dielectric layer 212 and the read channel layer 213 are formed on one side of the storage gate 211 in the second direction D2, one back gate structure 220 can also be formed corresponding to the same read transistor 200.

[0088] The materials of the control gate 222 and the storage gate 211 can be different or the same. For example, the material of the control gate 222 can include but is not limited to conductive material W.

[0089] The material of the second read gate dielectric layer 221 can include but is not limited to HfOx, HfSiOx, HfOx / SiO2 laminated material, or Al2O3, STO and other materials. The materials of the second read gate dielectric layer 221 and the first read gate dielectric layer 212 can be different or the same.

[0090] Step S6, please refer to FIG. 23, a write transistor 500 is formed on one side of the storage gate 211 in the first direction D1 close to the shared bit line 300, the write transistor 500 includes a write gate 530, a write gate dielectric layer 520 and a write channel layer 510, the write gate dielectric layer 520 surrounds the write gate 530, the write channel layer 510 surrounds the write gate dielectric layer 520, and the write channel layer 510 is connected to the shared bit line 300 and the storage gate 211 on both sides in the first direction D1 respectively, and is surrounded by the storage gate 211.

[0091] The write transistor 500 and the read transistor 200 can form a 2T0C architecture storage unit.

[0092] The material of the write channel layer 510 can be IGZO, so that the write transistor 500 has a lower off-state current. Of course, the material of the write channel layer 510 is not limited to this, for example, it can also be other metal oxide materials. The material of the write gate 530 can include but is not limited to conductive material ITO. The material of the write gate dielectric layer 520 can include but is not limited to high-k material.

[0093] The two sides of the write channel layer 510 in the first direction D1 are connected with the shared bit line 300 and the storage gate 211 respectively, so that the shared bit line 300 and the storage gate 211 can be connected with the source region and the drain region of the write transistor 500 respectively. At this time, the write transistor 500 can obtain the write bit line signal from the shared bit line 300, and store data to the storage node when the write transistor 500 is turned on under the control of the write gate 530.

[0094] In this embodiment, in the forming process of the read transistor 200, the storage gate 211 in the shape of U is formed, and the shared bit line 300 is formed on the side of the storage gate 211 which is provided with an opening in the first direction D1, and the write transistor 500 is formed between the shared bit line 300 and the storage gate 211, so that the U-shaped storage gate 211 can be arranged around the write channel layer 510. At this time, the coupling between the write transistor 500 and the storage gate 211 can be enhanced, and the write transistor 500 can better regulate the potential of the storage gate 211 as the storage node, thereby widening the selectivity of the device operation; at the same time, the contact area between the storage gate 211 and the write channel layer 510 is increased, thereby reducing the contact resistance therebetween. At the same time, the storage gate 211 and the write transistor 500 can partially overlap at this time, so that the size of the storage unit in the first direction D1 can be effectively reduced, thereby reducing the area of the storage unit. Therefore, the storage density and integration can also be improved at this time.

[0095] At the same time, the shared bit line 300 and the read source line 400 are formed on the two sides of the storage gate 211 in the first direction D1, and the first read gate dielectric layer 212 and the read channel layer 213 are formed on at least one side of the storage gate 211 in the second direction D2, so that the two ends of the read channel layer 213 in the first direction D1 can be connected with the shared bit line 300 and the read source line 400 respectively. At the same time, the write transistor 500 is formed between the storage gate 211 and the shared bit line 300, so that the write transistor 500 and the read transistor 200 can share the shared bit line 300, thereby effectively reducing the number of bit lines, and thereby the subsequent step process of connecting the bit lines can be reduced by half. Moreover, the write transistor 500 and the read transistor 200 share the shared bit line 300, which can effectively make the storage unit density in a unit area higher.

[0096] In one embodiment, before step S3 of forming the read tube structure 210, it further includes:

[0097] At step S21, referring to FIG. 2, a stack material layer 6001 is formed on the substrate 100, the stack material layer 6001 comprising first dielectric material layers 6101 and second dielectric material layers 6201 alternately stacked.

[0098] The first dielectric material layers 6101 and the second dielectric material layers 6201 can be alternately stacked on the substrate 100 by a deposition process. The deposition process can include, but is not limited to, chemical vapor deposition, etc. As an example, the material of the first dielectric material layers 6101 can be the same as that of the insulating isolation layer 120. In this case, the insulating isolation layer 120 can be formed on the semiconductor substrate 110 first, and then the second dielectric material layers 6201 and the first dielectric material layers 6101 can be periodically stacked on the insulating isolation layer.

[0099] As an example, the material of the first dielectric material layers 6101 can be silicon oxide, and the material of the second dielectric material layers 6201 can be silicon nitride. The first dielectric material layers 6101 can be prepared by a TEOS sol-gel process, etc., and the second dielectric material layers 6201 can be prepared by a plasma-enhanced chemical vapor deposition (PECVD) process, etc.

[0100] At step S22, referring to FIG. 3, an initial filling layer 7201 is formed in the stack material layer 6001, the initial filling layer 7201 penetrating the stack material layer 6001.

[0101] As an example, referring to FIG. 2, dry etching can be performed on the stack material layer 6001 first, so as to form a filling hole 10. Then, referring to FIG. 3, insulating dielectric material is filled in the filling hole 10, so as to form the initial filling layer 7201. In subsequent processes, the back gate structure 220 can be formed in the initial filling layer 7201.

[0102] At step S23, referring to FIGS. 4-7, the stack material layer 6001 is etched on both sides of the initial filling layer 7201 in a first direction D1, so as to form a first slot 20 and a second slot 30 extending in a second direction D2, and a dummy bit line layer 300a is formed in the first slot 20, and a dummy source line layer 400a is formed in the second slot 30. The first slot 20 comprises a first trench 21 and a first lateral trench 22, the first trench 21 penetrating the stack material layer 6001, and the first lateral trench 22 is communicated with the first trench 21 and is formed by laterally etching the second dielectric material layers 6201 to the initial filling layer 7201, and the second slot 30 penetrates the stack material layer 6001.

[0103] As an example, referring to FIG. 4, the stack material layer 6001 can be etched towards the substrate 100 at one side of the fill initial layer 7201 in the first direction D1 to form a first trench 21 extending along the second direction D2. Then, the second dielectric material layer 6201 is etched laterally from the first trench 21 to the fill initial layer 7201 to form a first lateral slot 22. Then, referring to FIG. 5, the dummy bit line layer 300a is formed in the first trench 21 and the first lateral slot 22, i.e., the dummy bit line layer 300a is formed in the first slot 20.

[0104] The dummy bit line layer 300a is a dummy film layer preset to locate the position of the bit line 300. The dummy bit line layer 300a can be formed by a process such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). The material of the dummy bit line layer 300a can include, but is not limited to, Si3N4.

[0105] Then, referring to FIG. 6, the stack material layer 6001 can be etched towards the substrate 100 at the other side of the fill initial layer 7201 in the first direction D1 to form a second slot 30 extending along the second direction D2. Then, referring to FIG. 7, the dummy source line layer 400a is formed by backfilling the insulating dielectric material in the second slot 30.

[0106] The dummy source line layer 400a is a dummy film layer preset to locate the position of the read source line 400. The dummy source line layer 400a can be formed by a process such as spin-on dielectric (SOD), for example. The material of the dummy source line layer 400a can include, but is not limited to, silicon oxide.

[0107] As another example, the second slot 30 can be formed first, and the dummy source line layer 400a is formed in the second slot 30. Then, the first slot 20 is formed, and the dummy source line layer 400a is formed in the first slot 20.

[0108] In the present embodiment, the frame positions of the memory cells can be preset by the fill initial layer 7201 and the dummy bit line layer 300a and the dummy source line layer 400a located at two sides thereof, respectively.

[0109] In one embodiment, based on the steps S21 to S24, the step S3 of forming the read pipe base structure 210 on the substrate 100 includes:

[0110] Step S31, referring to FIG. 9, etching the stack material layer 6001 between the dummy bit line layer 300a and the dummy source line layer 400a to form the opening 40, the remaining first dielectric material layer 6101 forms the first dielectric layer 610, the opening 40 is located on one side of the filling initial layer 7201 in the second direction D2, and the opening 40 includes the via hole 41 and the lateral hole 42, the via hole 41 penetrates the stack material layer 6001, and the lateral hole 42 is communicated with the via hole 41 and is formed by etching the second dielectric material layer 6201.

[0111] Referring to FIG. 8, the via hole 41 can be formed by etching the stack material layer 6001 towards the substrate 100 first. Then, referring to FIG. 9, the second dielectric material layer 6201 is etched from the via hole 41, thereby forming the lateral hole 42.

[0112] Step S32, referring to FIG. 12, forming the read channel initial layer 2132, the first read gate dielectric initial layer 2122 and the storage gate initial layer 2112 in the lateral hole 42, the read channel initial layer 2132 is located on the hole wall of the lateral hole 42, the first read gate dielectric initial layer 2122 is located on the surface of the read channel initial layer 2132, and the storage gate initial layer 2112 is located on the surface of the first read gate dielectric initial layer 2122 and protrudes in the direction towards the via hole 41.

[0113] Referring to FIG. 10, the read channel material layer 2131, the first read gate dielectric material layer 2121 and the storage gate material layer 2111 can be sequentially formed on the surface of the structure after the opening 40 is formed.

[0114] Then, referring to FIG. 11, the storage gate material layer 2111 is etched back. The etching depth in the lateral hole 42 can be 25-30 nm. After etching, the storage gate material layer 2111 remaining in the lateral hole 42 forms the storage gate initial layer 2112.

[0115] Then, referring to FIG. 12, the first read gate dielectric material layer 2121 and the read channel material layer 2131 are etched with the storage gate initial layer 2112 as an etching stop layer, thereby forming the first read gate dielectric initial layer 2122 and the read channel initial layer 2132. At this time, part of the first read gate dielectric material layer 2121 and the read channel material layer 2131 between the storage gate initial layer 2112 and the first dielectric layer 610 are etched and removed, so that the storage gate initial layer 2112 protrudes in the direction towards the via hole 41. Therefore, there will be a gap between the storage gate initial layer 2112 and the first dielectric layer 610 at this time.

[0116] Step S33, referring to FIG. 12, forming the first isolation layer 810 between the storage gate initial layer 2112 and the first dielectric layer 610, and forming the dummy write tube layer 500a in the remaining space of the opening 40.

[0117] The first isolation layer 810 can fill the gap between the storage gate initial layer 2112 and the first dielectric layer 610. As an example, the material of the first isolation layer 810 can also include, but is not limited to, a high-k material (such as HfOx).

[0118] The dummy write tube layer 500a is a dummy film layer for presetting the position of the write transistor 500. The material of the dummy write tube layer 500a can include, but is not limited to, polysilicon. For example, the material of the dummy write tube layer 500a can also be SiN, carbon, AlN, SiFO, etc. An oxide and polysilicon combination formed by an ALD deposition process, etc. can also be selected as the material of the dummy write tube layer 500a.

[0119] At this time, the first isolation layer 810 can effectively isolate the read channel initial layer 2132 and the dummy write tube layer 500a.

[0120] Step S34, please refer to FIG. 14 and FIG. 15, the dummy bit line layer 300a is removed to open the first slot 20 again, and the read channel initial layer 2132, the first read gate dielectric initial layer 2122 and the storage gate initial layer 2112 are etched in turn from the first lateral slot 22 to form the read channel layer 213, the first read gate dielectric intermediate layer 2123 and the storage gate 211 respectively, and the lateral extension hole is formed between the storage gate 211 and the first lateral slot 22.

[0121] As an example, please refer to FIG. 13, before removing the dummy bit line layer 300a, a protection dielectric layer 920 can also be formed on the structure surface after forming the dummy write tube layer 500a. At this time, the protection dielectric layer 920 covers the dummy write tube layer 500a. The material of the protection dielectric layer 920 can include, but is not limited to, silicon oxide.

[0122] Then, please refer to FIG. 14, the dummy bit line layer 300a can be removed by a wet etching method. When the dummy bit line layer 300a is removed, the protection dielectric layer 920 can isolate and protect the dummy write tube layer 500a.

[0123] After removing the dummy bit line layer 300a, please refer to FIG. 15, the read channel initial layer 2132 and the first read gate dielectric initial layer 2122 between the storage gate initial layer 2112 and the first lateral slot 22 can be etched to open a window towards the first lateral slot 22. The remaining read channel initial layer 2132 forms the read channel layer 213, and the remaining first read gate dielectric initial layer 2122 forms the first read gate dielectric intermediate layer 2123.

[0124] Then, based on the opened window, the storage gate initial layer 2112 is continuously etched to form the lateral extension hole. The remaining storage gate initial layer 2112 forms the storage gate 211.

[0125] At step S35, referring to FIG. 16, a second isolation layer 820 is formed to cover the storage gate 211, and the first read gate dielectric intermediate layer 2123 between the second isolation layer 820 and the first lateral slot 22 is etched to form a first read gate dielectric layer 212.

[0126] The second isolation material layer can be formed first to fill the laterally extending hole. Then the second isolation material layer is etched back to form the second isolation layer 820. The first read gate dielectric intermediate layer 2123 can be etched at the same time as the second isolation material layer is etched back, thereby forming the first read gate dielectric layer 212 that exposes the read channel layer 213. At this time, the two end portions of the read channel layer 213 extend from the two end portions of the first read gate dielectric layer 212 toward the dummy bit line layer 300a side.

[0127] The material of the second isolation layer 820 can include, but is not limited to, a high-k material.

[0128] After that, as an example, the read channel layer 213 exposed at this time can also be heavily doped to form a source region (or a drain region) of the read transistor 200. After the heavy doping, a metal silicide can also be formed on the surface of the source region (or the drain region) to further reduce the contact resistance between the read channel layer 213 and the subsequently formed shared bit line 300.

[0129] In one embodiment, after step S35, step S4 includes:

[0130] At step S41, referring to FIG. 17, the shared bit line 300 is formed in the remaining space of the laterally extending hole and the first lateral slot 22 after the first read gate dielectric layer 212 is formed.

[0131] The first read gate dielectric layer 212 is formed, and the read channel layer 213 is exposed. At this time, after the shared bit line 300 is formed in the remaining space of the laterally extending hole and the first lateral slot 22, the shared bit line 300 is effectively connected to the exposed read channel layer 213.

[0132] At this time, the shared bit line 300 includes a connection portion 310 and an extension portion 320. The connection portion 310 is located in the remaining space of the laterally extending hole, and the connection portion 310 is located between the two end portions of the read channel layer 213 in the second direction D2. The extension portion 320 is located in the first lateral slot 22 to connect the connection portion 310 and extends along the second direction D2.

[0133] At step S42, referring to FIG. 17, the first filling layer 710 is formed in the first trench 21.

[0134] The first filling layer 710 can be formed by a deposition process, etc. The material of the first filling layer 710 can include, but is not limited to, silicon oxide.

[0135] Step S43, referring to FIG. 19, the dummy source line layer 400a is replaced by the read source line 400.

[0136] Referring to FIG. 18, the dummy source line layer 400a can be etched away first, so that the second slot 30 is opened again. Referring to FIG. 19, the read source line 400 is then formed in the second slot 30.

[0137] As an example, before the read source line 400 is formed in the second slot 30, the read channel layer 213 exposed by the second slot 30 can also be heavily doped, so as to form the drain region (or source region) of the read transistor 200. After the heavy doping, a metal silicide can also be formed on the surface of the drain region (or source region), so as to further reduce the contact resistance between the read channel layer 213 and the read source line 400.

[0138] In one embodiment, referring to FIG. 5, before the dummy bit line layer 300a is formed in the first slot 20 in step S23, it can also include:

[0139] A third dielectric layer 910 is formed on the surface of at least the second dielectric material layer 6201 exposed by the first slot 20.

[0140] The third dielectric layer 910 can be formed by atomic layer deposition (ALD) or the like. The material of the third dielectric layer 910 can include, but is not limited to, silicon oxide.

[0141] At this time, the third dielectric layer 910 is between the dummy bit line layer 300a and the second dielectric material layer 6201.

[0142] Therefore, in step S31, referring to FIG. 9, when the lateral hole 42 of the opening 40 is formed, the third dielectric layer 910 can be used as an etching stop layer to etch the second dielectric material layer 6201.

[0143] At this time, when the second dielectric material layer 6201 is etched, the etching depth towards the side of the dummy bit line layer 300a can not be affected by the etching depth towards the side of the dummy source line layer 400a, so that the hole depth of the lateral hole 42 formed near the side of the dummy bit line layer 300a is smaller than the hole depth of the lateral hole 42 near the side of the dummy source line layer 400a.

[0144] In this embodiment, it can not only ensure that the storage gate 211 formed in the lateral hole 42 in the subsequent process has sufficient width in the first direction D1, but also effectively shorten the size of the storage unit in the first direction D1, so as to utilize the miniaturization of the device size.

[0145] In one embodiment, based on steps S21 to S24, the back gate structure 220 is formed in step S5, which includes:

[0146] Step S51, referring to FIG. 20, etch the filling initial layer 7201 near the reading channel layer to form the back gate hole 50, and the remaining filling initial layer 7201 forms the second filling layer 720.

[0147] The filling initial layer 7201 can be etched towards the substrate 100 by dry etching or the like to form the back gate hole 50.

[0148] As an example, the back gate structure 220 can be formed after the reading tube base structure 210 is formed. At this time, when the back gate hole 50 is formed, it can expose the reading channel layer 213 formed in the front. Of course, the back gate structure 220 can also be formed before the reading tube base structure 210 is formed.

[0149] Step S52, referring to FIG. 21, form the second reading gate dielectric layer 221 and the reading word line 222a in the back gate hole 50, and the reading word line 222a includes the control gate 222 of the plurality of reading transistors 200 arranged in the direction perpendicular to the substrate.

[0150] The second reading gate dielectric material layer and the reading word line material layer can be sequentially formed on the surface of the structure after the back gate hole 50 is formed to fill the back gate hole 50. Then the second reading gate dielectric material layer and the reading word line material layer outside the back gate hole 50 can be removed by chemical mechanical polishing (CMP) or the like to form the second reading gate dielectric layer 221 and the reading word line 222a. The reading word line 222a includes the control gate 222 of the plurality of reading transistors 200 arranged in the direction perpendicular to the substrate.

[0151] In one embodiment, the process of step S6 for forming the writing transistor 500 includes:

[0152] Step S61, remove the pseudo writing tube layer 500a.

[0153] Referring to FIG. 22, the pseudo writing tube layer 500a can be removed by wet etching or the like. After the pseudo writing tube layer 500a is removed, the through hole 41 and the part of the lateral hole 42 in communication with it are opened again, thereby exposing the storage gate 211.

[0154] Step S62, referring to FIG. 23, form the writing channel layer 510 and the writing gate dielectric layer 520 in the lateral hole 42, the writing channel layer 510 is formed on the hole wall surface of the lateral hole 42 opposite to the through hole 41, and the writing gate dielectric layer 520 is formed on the surface of the writing channel layer 510.

[0155] As an example, the writing channel material layer, the writing gate dielectric material layer and the conductive protection material layer can be sequentially formed on the surface of the structure after the pseudo writing tube layer 500a is removed. For example, the material of the writing channel material layer can be IGZO, and the material of the writing gate dielectric material layer can be HfOx.

[0156] Afterwards, the write channel material layer, the write gate dielectric material layer and the conductive protection material layer outside the lateral hole 42 are etched away, and part of the write gate dielectric material layer and the write channel material layer inside the lateral hole 42 are removed, thereby forming a write channel layer 510 and a write gate dielectric layer 520. A third isolation layer 830 covering the write channel layer 510 or covering the write channel layer 510 and the write gate dielectric layer 520 can be formed in the lateral hole 42 to insulate the write channel layer 510 from the write word line 530a to be formed later.

[0157] At step S63, referring to FIG. 23, the write word line 530a is formed in the remaining space of the opening 40 and is insulated from the write channel layer 510. The write word line 530a includes a plurality of write gates 530 of the write transistors 500 arranged along a direction perpendicular to the base.

[0158] The material of the write word line 530a can be the same as that of the conductive protection material layer, for example, both are W. Of course, the materials of the two can also be different, which can be set according to actual needs.

[0159] In the embodiment, the formation process of the write transistor 500 can be completed by the hole etching process, which has an advantage in size and process flow.

[0160] It should be understood that although the steps in the flowchart of FIG. 1 are shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in FIG. 1 can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0161] In one embodiment, a semiconductor structure is also provided, referring to FIG. 23 or FIG. 24, including a shared bit line 300, a read source line 400 and a memory cell.

[0162] The shared bit line 300 and the read source line 400 are arranged along a first direction D1, and both extend along a second direction D2. The second direction D2 intersects the first direction D1.

[0163] The memory cell is located between the shared bit line 300 and the read source line 400 in the first direction D1. At the same time, the memory cell includes a write transistor 500 and a read transistor 200.

[0164] The write transistor 500 includes a write gate 530, a write gate dielectric layer 520, and a write channel layer 510. The write gate dielectric layer 520 surrounds the write gate 530. The write channel layer 510 surrounds the write gate dielectric layer 520 and connects the shared bit line 300 in the first direction Dl.

[0165] The read transistor 200 includes a read tube base structure 210 and a back gate structure 220. The read tube base structure 210 includes a storage gate 211, a first read gate dielectric layer 212, and a read channel layer 213. The back gate structure 220 includes a second read gate dielectric layer 221 and a control gate 222.

[0166] The storage gate 211 is located on a side of the write transistor 500 away from the shared bit line 300 in the first direction Dl, and the storage gate 211 surrounds the write channel layer 510 in a U shape.

[0167] Therefore, the write channel layer 510 connects the storage gate 211 and the shared bit line 300 on two sides thereof in the first direction Dl, respectively, so that the shared bit line 300 and the storage gate 211 can connect the source region and the drain region of the write transistor 500, respectively. At this time, the write transistor 500 can obtain a write bit line signal from the shared bit line 300, and store data to the storage gate 211 when the write transistor 500 is controlled to be turned on by the write gate 530.

[0168] The control gate 222 is located on at least one side of the storage gate 211 in the second direction D2. The read channel layer 213 is located between the control gate 222 and the storage gate 211. The first read gate dielectric layer 212 is located between the read channel layer 213 and the storage gate 211, and the second read gate dielectric layer 221 is located between the read channel layer 213 and the control gate 222. Therefore, the formation of the conductive channel of the read transistor 200 is simultaneously affected by the control gate 222 and the storage gate 211. Therefore, the read transistor 200 can be controlled to be turned on and off by the control gate 222.

[0169] The read channel layer 213 connects the shared bit line 300 and the read source line 400, so that the shared bit line 300 and the read source line 400 can connect the source region and the drain region of the read transistor 200, respectively. At this time, the read transistor 200 can obtain a read bit line signal from the shared bit line 300, and obtain a source signal (such as a ground signal) from the read source line 400.

[0170] The materials of the shared bit line 300, the read source line 400, the write gate 530, the control gate 222, and the storage gate 211 can be selected from conductive materials W, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides such as titanium nitride TiN, conductive metal silicides, conductive metal carbides, conductive doped semiconductors such as doped polysilicon, conductive metal oxide semiconductors such as indium tin oxide, and the like.

[0171] The materials of the first read gate dielectric layer 212, the second read gate dielectric layer 221, and the write gate dielectric layer 520 can include, but are not limited to, high-k materials. The high-k materials can include, but are not limited to, HfOx, and can also be HfSiOx, a stacked material of HfOx / SiO2, or other oxide materials (e.g., Al2O3, STO, and the like).

[0172] The material of the write channel layer 510 can include, but is not limited to, IGZO. The material of the read channel layer 213 can include, but is not limited to, amorphous silicon.

[0173] In the present embodiment, the storage gate 211 is in a U shape and surrounds the write channel layer 510. At this time, the coupling between the write transistor 500 and the storage gate 211 can be enhanced, the write transistor 500 can better regulate the potential of the storage gate 211 as a storage node, thereby widening the selectivity of the device operation; at the same time, the contact area between the storage gate 211 and the write channel layer 510 is increased, thereby reducing the contact resistance therebetween. At the same time, the storage gate 211 and the write transistor 500 can partially overlap at this time, thereby effectively reducing the size of the storage unit in the first direction D1, and further reducing the storage unit area. Therefore, the storage density and integration can also be improved at this time.

[0174] Meanwhile, the shared bit line 300 and the read source line 400 are respectively located on two sides of the storage gate 211 in the first direction D1, while the first read gate dielectric layer 212 and the read channel layer 213 are located on at least one side of the storage gate 211 in the second direction D2, so that two ends of the read channel layer 213 in the first direction D1 can be connected to the shared bit line 300 and the read source line 400 respectively. Meanwhile, the write transistor 500 is formed between the storage gate 211 and the shared bit line 300, so that the write transistor 500 and the read transistor 200 can share the shared bit line 300, thereby effectively reducing the number of bit lines, and further reducing the step process of connecting the bit lines by half. In addition, the write transistor 500 and the read transistor 200 share the shared bit line 300, which can effectively increase the storage unit density per unit area.

[0175] In one embodiment, the first read gate dielectric layer 212 surrounds the storage gate 211 in a U shape in the plane determined by the first direction D1 and the second direction D2, and the read channel layer 213 surrounds the first read gate dielectric layer 212 in a U shape.

[0176] Meanwhile, the read source line 400 is connected to the read channel layer 213 in the first direction D1, thereby effectively increasing the contact area between the read channel layer 213 and the read source line 400 and reducing the contact resistance therebetween.

[0177] In one embodiment, two end portions of the read channel layer 213 extend from two end portions of the first read gate dielectric layer 212 toward the side of the shared bit line 300. The shared bit line 300 includes a connecting portion 310 and an extending portion 320. The connecting portion 310 is located between the two end portions of the read channel layer 213 in the second direction D2, and the extending portion 320 is connected to the connecting portion 310 and extends along the second direction D2.

[0178] At this time, the shared bit line 300 can be effectively connected to the read channel layer 213 through the connecting portion 310.

[0179] In one embodiment, the second read gate dielectric layer 221 surrounds the control gate 222. The preparation difficulty of the control gate 222 can be effectively reduced.

[0180] In one embodiment, the same read source line 400 is symmetrically provided with storage units connected thereto on opposite sides in the first direction D1.

[0181] At this time, the symmetrically arranged storage units share the read source line 400, thereby improving the storage density.

[0182] In one embodiment, the semiconductor structure further includes a substrate 100, a write word line 530a, and a read word line 222a.

[0183] The plurality of memory cells are stacked on the substrate 100. The write word line 530a extends from above the top memory cell toward the substrate 100 and includes the write gate 530 of the plurality of write transistors 500.

[0184] The read word line 222a extends from above the top memory cell toward the substrate 100 and includes the control gate 222 of the plurality of read transistors arranged along a direction perpendicular to the substrate. In this case, the second read gate dielectric layer 221 can be located on the sidewall of the read word line 222a, thereby also extending from above the top memory cell toward the substrate 100. The read source line 400 extends from above the top memory cell toward the substrate 100 and along the second direction, and connects the read channel layer 213 of the plurality of read transistors arranged along a direction perpendicular to the substrate and along the second direction.

[0185] In one embodiment, the semiconductor structure further includes a plurality of first dielectric layers 610 spacedly stacked, and includes a first isolation layer 810, a second isolation layer 820, a first fill layer 710, and a second fill layer 720.

[0186] The memory cells and the shared bit line 300 are located between adjacent first dielectric layers 610.

[0187] The first isolation layer 810 is located between the memory gate 211 and the first dielectric layer 610, and insulates the read channel layer 213 and the write channel layer 510.

[0188] The second isolation layer 820 is located between adjacent first dielectric layers 610, and is located between the shared bit line 300 and the memory gate 211.

[0189] The first fill layer 710 is located on a side of the shared bit line 300 away from the memory cells in the first direction Dl, and extends from above the top memory cell toward the substrate 100.

[0190] The second fill layer 720 is located on a side of the read channel layer 213 away from the memory gate 211 in the second direction D2, and extends from above the top memory cell toward the substrate 100. The back gate structure 220 penetrates the second fill layer 720.

[0191] The material of the first fill layer 710 and the second fill layer 720 can be selected from SiO2, other low-k materials, or other oxides or nitrides, etc. The material of the first isolation layer 810 and the second isolation layer 820 can be selected from HfOx or other high-k materials, etc.

[0192] In one embodiment, an electronic device is also provided, which includes the semiconductor structure provided by any of the above embodiments, or the semiconductor structure prepared according to the preparation method of the semiconductor structure provided by the above embodiments. The electronic device can be any electronic product with storage function, such as a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0193] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described, but it should be understood that any combination of the technical features is within the scope of the present disclosure as long as the combination does not result in contradictions.

[0194] The above embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these are within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A semiconductor structure, comprising: a shared bit line and a read source line, the shared bit line and the read source line being arranged along a first direction and both extending along a second direction intersecting the first direction; a memory cell located between the shared bit line and the read source line in the first direction, the memory cell comprising: a write transistor comprising a write gate, a write gate dielectric layer surrounding the write gate, and a write channel layer surrounding the write gate dielectric layer and connected to the shared bit line in the first direction; a read transistor comprising a read tube base structure and a back gate structure, the read tube base structure comprising a storage gate, a first read gate dielectric layer, and a read channel layer, the back gate structure comprising a second read gate dielectric layer and a control gate, the storage gate being located on a side of the write transistor away from the shared bit line in the first direction and the storage gate being U-shaped around the write channel layer, the control gate being located on at least one side of the storage gate in the second direction, the read channel layer being located between the control gate and the storage gate and connected to the shared bit line and the read source line, the first read gate dielectric layer being located between the read channel layer and the storage gate, and the second read gate dielectric layer being located between the read channel layer and the control gate.

2. The semiconductor structure of claim 1, wherein, In a plane determined by the first direction and the second direction, the first read gate dielectric layer is U-shaped around the storage gate, and the read channel layer is U-shaped around the first read gate dielectric layer; and the read source line is connected to the read channel layer in the first direction.

3. The semiconductor structure of claim 2, wherein, Two end portions of the read channel layer extend toward the side of the shared bit line from two end portions of the first read gate dielectric layer; The shared bit line comprises a connecting portion located between the two end portions of the read channel layer in the second direction and an extending portion connected to the connecting portion and extending along the second direction.

4. The semiconductor structure of claim 1, wherein, The second read gate dielectric layer surrounds the control gate.

5. The semiconductor structure of claim 1, wherein, The memory cell connected to the read source line is symmetrically arranged on opposite sides of the read source line in the first direction.

6. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a substrate on which a plurality of the memory cells are stacked; a write word line extending from above a topmost one of the memory cells toward the substrate and comprising a plurality of the write gates of the write transistors arranged in a direction perpendicular to the substrate; a read word line extending from above the topmost one of the memory cells toward the substrate and comprising a plurality of the control gates of the read transistors arranged in the direction perpendicular to the substrate; and the read source line extending from above the topmost one of the memory cells toward the substrate and along the second direction and connected to the read channel layers of a plurality of the read transistors arranged in the direction perpendicular to the substrate and along the second direction.

7. The semiconductor structure of claim 6, wherein, The semiconductor structure further comprises: a plurality of first dielectric layers stacked with spaces, the memory cell and the shared bit line are located between adjacent layers of the first dielectric layers, the first read gate dielectric layer and the read channel layer are extended to the surface of the first dielectric layers between adjacent layers of the first dielectric layers; a first isolation layer located between the memory gate and the first dielectric layer, insulating and isolating the read channel layer and the write channel layer; a second isolation layer located between adjacent layers of the first dielectric layers, and located between the shared bit line and the memory gate; a first filling layer located on a side of the shared bit line away from the memory cell in the first direction, and extending from above the top memory cell towards the substrate; a second filling layer located on a side of the read channel layer away from the memory gate in the second direction, and extending from above the top memory cell towards the substrate, and the back gate structure penetrates the second filling layer.

8. A method for manufacturing a semiconductor structure, comprising: providing a substrate, forming a read tube base structure on the substrate, the read tube base structure comprising a memory gate, a first read gate dielectric layer, and a read channel layer, the memory gate having an opening in a first direction, the first read gate dielectric layer and the read channel layer being located on at least one side of the memory gate in a second direction, the second direction intersecting the first direction, the first read gate dielectric layer being located between the read channel layer and the memory gate in the second direction; forming a shared bit line on a side of the memory gate having the opening in the first direction, and forming a read source line on another side of the memory gate in the first direction, the shared bit line and the read source line both connecting the read channel layer and extending in the second direction; forming a back gate structure on at least one side of the memory gate having the read channel layer in the second direction, the back gate structure and the read tube base structure forming a read transistor, and the back gate structure comprising a second read gate dielectric layer and a control gate, the read channel layer being located between the control gate and the memory gate, the second read gate dielectric layer being located between the read channel layer and the control gate; forming a write transistor on a side of the memory gate close to the shared bit line in the first direction, the write transistor comprising a write gate, a write gate dielectric layer, and a write channel layer, the write gate dielectric layer surrounding the write gate, the write channel layer surrounding the write gate dielectric layer, and the write channel layer connecting the shared bit line and the memory gate in the first direction on two sides of the write channel layer respectively, and being surrounded by the memory gate.

9. The method of producing a semiconductor structure according to claim 8, wherein, Before the forming the read tube base structure on the substrate, comprising: forming a stacked material layer on the substrate, the stacked material layer comprising first dielectric material layers and second dielectric material layers stacked alternately; forming a filling initial layer penetrating the stacked material layer in the stacked material layer. The stack material layer is etched to form a first slot and a second slot extending along a second direction on both sides of the initial filling layer in the first direction, a dummy bit line layer is formed in the first slot, and a dummy source line layer is formed in the second slot, the first slot includes a first trench and a first lateral slot, the first trench penetrates the stack material layer, the first lateral slot is connected to the first trench and is formed by laterally etching the second dielectric material layer to the initial filling layer, and the second slot penetrates the stack material layer.

10. The method of producing a semiconductor structure according to claim 9, wherein, The formation of the read pipe base structure on the substrate includes: The stack material layer is etched between the dummy bit line layer and the dummy source line layer to form an opening, the remaining first dielectric material layer forms a first dielectric layer, the opening is located on one side of the initial filling layer in the second direction, and the opening includes a through hole and a lateral hole, the through hole penetrates the stack material layer, and the lateral hole is connected to the through hole and is formed by etching the second dielectric material layer; A read channel initial layer, a first read gate dielectric initial layer, and a storage gate initial layer are formed in the lateral hole, the read channel initial layer is located on the hole wall of the lateral hole, the first read gate dielectric initial layer is located on the surface of the read channel initial layer, and the storage gate initial layer is located on the surface of the first read gate dielectric initial layer and protrudes in the direction towards the through hole; A first isolation layer is formed between the storage gate initial layer and the first dielectric layer, and a dummy write pipe layer is formed in the remaining space of the opening; The dummy bit line layer is removed to reopen the first slot, and the read channel initial layer, the first read gate dielectric initial layer, and the storage gate initial layer are sequentially etched from the first lateral slot to form the read channel layer, the first read gate dielectric intermediate layer, and the storage gate, respectively, and a lateral extension hole is formed between the storage gate and the first lateral slot; A second isolation layer covering the storage gate is formed, and the first read gate dielectric intermediate layer between the second isolation layer and the first lateral slot is etched and removed to form a first read gate dielectric layer.

11. The method of producing a semiconductor structure according to claim 10, wherein, The formation of the shared bit line on one side of the storage gate in the first direction and the formation of the read source line on the other side of the storage gate in the first direction includes: A shared bit line is formed in the remaining space of the lateral extension hole and the first lateral slot after the formation of the first read gate dielectric layer; A first filling layer is formed in the first trench; The dummy source line layer is replaced by a read source line.

12. The method of fabricating a semiconductor structure of claim 10, wherein, Before the formation of the dummy bit line layer in the first slot, it includes: A third dielectric layer is formed on at least the surface of the second dielectric material layer exposed by the first slot; When the lateral hole of the opening is formed, the second dielectric material layer is etched with the third dielectric layer as an etching stop layer, so that the hole depth of the lateral hole formed on the side close to the dummy bit line layer is smaller than the hole depth of the lateral hole on the side close to the dummy source line layer.

13. The method of fabricating a semiconductor structure of claim 10, wherein, The formation of the write transistor on the side of the storage gate close to the shared bit line in the first direction includes: The dummy write pipe layer is removed; forming a write channel layer in the lateral hole, the write channel layer being formed on a hole wall surface of the lateral hole opposite to the through hole; forming a write word line in a remaining space of the opening, the write word line being formed of the write gate electrode of the write transistor and being insulated from the write channel layer.

14. The method of producing a semiconductor structure according to claim 9 or 10, wherein, forming a back gate structure on at least one side of the read channel layer in the second direction, the back gate structure including: forming a back gate hole by etching the remaining filling initial layer near the read channel layer, the remaining filling initial layer forming a second filling layer; forming the second read gate dielectric layer and a read word line in the back gate hole, the read word line including the control gate electrode of the read transistor and being arranged in a direction perpendicular to the substrate.

15. An electronic device comprising the semiconductor structure according to any one of claims 1-7, or a semiconductor structure prepared according to the method of any one of claims 8-14.

Images