Micro light-emitting diode chip and forming method therefor

Abstract

A micro light-emitting diode chip and a forming method therefor. The micro light-emitting diode chip comprises: a first epitaxial layer, wherein first doped ions are provided in the first epitaxial layer, and the first epitaxial layer has a first side and a second side that are opposite to each other; a multi-quantum well layer located on the first side, wherein the multi-quantum well layer is in contact with the first epitaxial layer; a second epitaxial layer located on the first side, wherein second doped ions are provided in the second epitaxial layer, the electrical type of the second doped ions is different from the electrical type of the first doped ions, and the multi-quantum well layer is located between the first epitaxial layer and the second epitaxial layer; and multiple layers of reflection rings located on the first side and sequentially arranged in a surrounding mode, wherein the reflection rings on the innermost side surround the multi-quantum well layer. By additionally arranging multiple layers of reflection rings on the periphery of the multi-quantum well layer, the light emitted by the multi-quantum well layer can be reflected multiple times, so that the sidewall effect generated due to the small size of a device can be effectively reduced, and the light-emitting efficiency and use stability of the micro light-emitting diode chip can be effectively improved.

Description

Micro light emitting diode chip and forming method thereof

[0001] The present application claims priority to the Chinese patent application No. 202410650772.3, filed on May 23, 2024, and entitled "Micro light emitting diode chip and forming method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of micro display, and in particular to a micro light emitting diode chip and a forming method thereof. BACKGROUND

[0003] Inorganic micro-pixel light emitting diode, also known as micro light emitting diode (Micro LED or μ-LED), micro light emitting diode technology is a high-pixel-density LED planar display technology that uses micron-level LEDs as pixel elements and assembles them on a CMOS backplane in micron-level cycles. The display principle is to design the LED structure to be thin, small and arrayed, with a size of only a few microns to tens of microns. Then, the micro light emitting diode chips are massively transferred to the TFT or CMOS backplane. Micro light emitting diode display has excellent characteristics such as high luminous efficiency, high brightness, short response time and good reliability, and is known as the next generation of display technology and the ultimate form of display.

[0004] However, the micro light emitting diode chip in the prior art still has many problems. SUMMARY

[0005] The technical problem solved by the present application is to provide a micro light emitting diode chip and a forming method thereof, which improves the luminous efficiency of the micro light emitting diode chip.

[0006] To solve the above problems, the technical scheme of the present application provides a micro light emitting diode chip, comprising: a first epitaxial layer, the first epitaxial layer has a first doping ion therein, the first epitaxial layer has opposite first and second sides; a multi-quantum well layer located on the first side, the multi-quantum well layer is in contact with the first epitaxial layer; a second epitaxial layer located on the first side, the second epitaxial layer has a second doping ion therein, the second doping ion and the first doping ion are different in electrical type, the multi-quantum well layer is located between the first epitaxial layer and the second epitaxial layer; a plurality of reflection rings arranged in a multi-layered manner, wherein the innermost reflection ring surrounds the multi-quantum well layer.

[0007] Optionally, the plurality of reflection rings comprises: a first reflection ring surrounding the multi-quantum well layer; a second reflection ring surrounding the first reflection ring, the second reflection ring being in contact with the first epitaxial layer.

[0008] Optionally, the first through hole and the second through hole are located in the first epitaxial layer; a conductive layer is located on the first side, and the conductive layer is electrically connected with the second epitaxial layer and the first reflective ring respectively; a first lead wire is located in the first through hole, and the first lead wire is electrically connected with the first reflective ring; and a second lead wire is located in the second through hole, and the second lead wire is electrically connected with the second reflective ring.

[0009] Optionally, a bottom reflective layer is located on the second side, and the first through hole and the second through hole pass through the bottom reflective layer.

[0010] Optionally, an insulating layer is located on the second side, and the insulating layer is located between the first epitaxial layer and the bottom reflective layer, and the first through hole and the second through hole pass through the insulating layer.

[0011] Optionally, a protective layer is located on the second side, and the protective layer covers the bottom reflective layer, and the bottom reflective layer is located between the first epitaxial layer and the protective layer, and the first through hole and the second through hole pass through the protective layer.

[0012] Optionally, a side wall of the multi-quantum well layer is an inclined surface, and a projection area of a surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer.

[0013] Optionally, an inclination angle of the side wall of the multi-quantum well layer ranges from 70° to 80°.

[0014] Optionally, a side wall of the first reflective ring is an inclined surface, and a projection area of a surface of the first reflective ring away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the first reflective ring close to the first epitaxial layer towards the first epitaxial layer.

[0015] Optionally, an inclination angle of the side wall of the first reflective ring ranges from 73° to 85°.

[0016] Optionally, a side wall of the second reflective ring is an inclined surface, and a projection area of a surface of the second reflective ring away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the second reflective ring close to the first epitaxial layer towards the first epitaxial layer.

[0017] Optionally, an inclination angle of the side wall of the second reflective ring ranges from 73° to 85°.

[0018] Optionally, the first reflective ring has a first spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, and the multi-quantum well layer has a second spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, the first spacing dimension being greater than the second spacing dimension.

[0019] Optionally, the second reflective ring has a third spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

[0020] Optionally, further comprising: a first passivation layer on the first side, the first via sidewall and the second via sidewall; the first passivation layer on the first side covering a portion of a surface of the first epitaxial layer on the first side, the second reflective ring being electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer on the first side further covering a sidewall of the multi-quantum well layer and the second epitaxial layer, and a portion of a surface of the second epitaxial layer away from the first epitaxial layer, the conductive layer being electrically connected to the second epitaxial layer exposed by the first passivation layer.

[0021] Optionally, further comprising: a second passivation layer on the first side, the second passivation layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer.

[0022] Optionally, further comprising: a microlens on the first side, a projection area of the multi-quantum well layer towards the first epitaxial layer being within a projection area range of the microlens towards the first epitaxial layer.

[0023] Optionally, further comprising: a first pad on the second side, the first pad being electrically connected to the first lead; a second pad on the second side, the second pad being electrically connected to the second lead.

[0024] Optionally, further comprising: an electron blocking layer on the first side, the electron blocking layer being between the multi-quantum well layer and the second epitaxial layer.

[0025] Optionally, materials of the first epitaxial layer and the second epitaxial layer comprise gallium nitride.

[0026] Correspondingly, the application also provides a method for forming a micro LED chip, comprising: forming a first epitaxial layer, the first epitaxial layer having first doped ions, the first epitaxial layer having opposite first and second sides; forming a multi-quantum well layer and a second epitaxial layer on the first side, the multi-quantum well layer being in contact with the first epitaxial layer, and the multi-quantum well layer being between the first epitaxial layer and the second epitaxial layer, the second epitaxial layer having second doped ions, the second doped ions and the first doped ions being of different electrical types; and forming a plurality of reflective rings arranged in a multilayer and surrounding each other on the first side, wherein the innermost reflective ring surrounds the multi-quantum well layer.

[0027] Optionally, the plurality of reflective rings comprises: a first reflective ring surrounding the multi-quantum well layer; and a second reflective ring surrounding the first reflective ring, the second reflective ring being in contact with the first epitaxial layer.

[0028] Optionally, before forming the first epitaxial layer, the method further comprises: providing a first temporary substrate; and forming the first epitaxial layer on the first temporary substrate, the first temporary substrate being on the second side.

[0029] Optionally, before forming the plurality of reflective rings, the method further comprises: etching the first epitaxial layer from the first side to the second side to form a first via and a second via in the first epitaxial layer; forming a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflective ring, respectively; and after forming the plurality of reflective rings, the method further comprises: forming a first lead wire in the first via, the first lead wire being electrically connected to the first reflective ring; and forming a second lead wire in the second via, the second lead wire being electrically connected to the second reflective ring.

[0030] Optionally, after forming the first lead wire and the second lead wire, the method further comprises: forming a microlens on the first side, a projection area of the multi-quantum well layer towards the first epitaxial layer being within a projection area of the microlens towards the first epitaxial layer; providing a second temporary substrate; bonding the second temporary substrate to the microlens from the first side; and removing the first temporary substrate after the bonding.

[0031] Optionally, after removing the first temporary substrate, the method further comprises: forming a first pad and a second pad on the second side, the first pad being electrically connected to the first lead wire, and the second pad being electrically connected to the second lead wire; and removing the second temporary substrate after forming the first pad and the second pad.

[0032] Optionally, before forming the first epitaxial layer, the method further comprises: forming a buffer layer on the first temporary substrate; the buffer layer is located on the second side, and the buffer layer is located between the first epitaxial layer and the first temporary substrate.

[0033] Optionally, after etching the first epitaxial layer, the method further comprises: etching the buffer layer from the first side to the second side; the first via and the second via are also located in the buffer layer.

[0034] Optionally, after removing the first temporary substrate, the method further comprises: removing the buffer layer.

[0035] Optionally, before forming the first pad and the second pad, the method further comprises: forming a bottom reflection layer on the second side; the first via and the second via pass through the bottom reflection layer.

[0036] Optionally, before forming the bottom reflection layer, the method further comprises: forming an insulating layer on the second side; the insulating layer is located between the first epitaxial layer and the bottom reflection layer, and the first via and the second via pass through the insulating layer.

[0037] Optionally, after forming the bottom reflection layer, the method further comprises: forming a protective layer on the second side; the protective layer covers the bottom reflection layer, and the bottom reflection layer is located between the first epitaxial layer and the protective layer, and the first via and the second via pass through the protective layer.

[0038] Optionally, a side wall of the first reflective ring is an inclined surface, and a projection area of a surface of the first reflective ring away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the first reflective ring close to the first epitaxial layer towards the first epitaxial layer.

[0039] Optionally, an inclination angle of the side wall of the first reflective ring ranges from 73° to 85°.

[0040] Optionally, a side wall of the second reflective ring is an inclined surface, and a projection area of a surface of the second reflective ring away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the second reflective ring close to the first epitaxial layer towards the first epitaxial layer.

[0041] Optionally, an inclination angle of the side wall of the second reflective ring ranges from 73° to 85°.

[0042] Optionally, a side wall of the second reflective ring is an inclined surface, and a projection area of a surface of the second reflective ring away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the second reflective ring close to the first epitaxial layer towards the first epitaxial layer.

[0043] Optionally, the second reflective ring has a side wall with an inclination angle ranging from 73° to 85°.

[0044] Optionally, the first reflective ring has a first spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, and the multi-quantum well layer has a second spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, wherein the first spacing dimension is greater than the second spacing dimension.

[0045] Optionally, the second reflective ring has a third spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, wherein the third spacing dimension is greater than or equal to the first spacing dimension.

[0046] Optionally, before forming the conductive layer, the method further comprises: forming a first passivation layer on the first side, the first via side wall and the second via side wall; the first passivation layer on the first side covers a portion of the surface of the first epitaxial layer on the first side, and the second reflective ring is electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer on the first side also covers the side wall of the multi-quantum well layer and the second epitaxial layer, and a portion of the surface of the second epitaxial layer away from the first epitaxial layer, and the conductive layer is electrically connected to the second epitaxial layer exposed by the first passivation layer.

[0047] Optionally, in the process of forming the microlens, the method further comprises: forming a second passivation layer on the first side, wherein the second passivation layer covers the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer.

[0048] Optionally, the microlens and the second passivation layer are made of the same material.

[0049] Optionally, the method for forming the microlens and the second passivation layer comprises: forming a passivation material layer on the first side, wherein the passivation material layer covers the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer; and performing a patterned etching process on the passivation material layer to form the microlens and the second passivation layer.

[0050] Optionally, the microlens and the second passivation layer are made of different materials.

[0051] Optionally, the method for forming the microlens and the second passivation layer comprises: forming a passivation material layer on the first side, the passivation material layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer, and the conductive layer; forming a microlens material layer on the passivation material layer; and performing a patterned etching treatment on the passivation material layer and the microlens material layer to form the microlens and the second passivation layer.

[0052] Optionally, after the multi-quantum well layer is formed and before the second epitaxial layer is formed, the method further comprises: forming an electron blocking layer on the first side, the electron blocking layer being located between the multi-quantum well layer and the second epitaxial layer.

[0053] Optionally, the material of the first epitaxial layer and the second epitaxial layer comprises gallium nitride.

[0054] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0055] In the micro light-emitting diode chip of the technical scheme of the present application, the multi-layer reflective ring is additionally arranged on the periphery of the multi-quantum well layer, the light emitted by the multi-quantum well layer can be subjected to multiple reflection processing, the sidewall effect caused by the small size of the device can be effectively reduced, and the light-emitting efficiency and the use stability of the micro light-emitting diode chip can be effectively improved.

[0056] Further, the first through hole and the second through hole are located in the first epitaxial layer, the conductive layer is located on the first side and is electrically connected with the second epitaxial layer and the first reflective ring respectively, the first lead wire is located in the first through hole and is electrically connected with the first reflective ring, and the second lead wire is located in the second through hole and is electrically connected with the second reflective ring. The first reflective ring is electrically connected with the first epitaxial layer to serve as a transition component for leading out the connection line of the first epitaxial layer, and the second reflective ring is electrically connected with the second epitaxial layer to serve as a transition component for leading out the connection line of the second epitaxial layer. Therefore, the transition components for leading out the connection lines of the first epitaxial layer and the second epitaxial layer are omitted, the device structure is simplified, and the manufacturing process and the manufacturing cost are reduced.

[0057] Further, the bottom reflective layer is located on the second side, and the first through hole and the second through hole penetrate through the bottom reflective layer. The bottom reflective layer can reflect the light emitted by the multi-quantum well layer towards the second side, and the light-emitting efficiency of the micro light-emitting diode chip is further improved.

[0058] Further, the protective layer is located on the second side, the protective layer covers the bottom reflective layer, the bottom reflective layer is located between the first epitaxial layer and the protective layer, and the first through hole and the second through hole penetrate through the protective layer. The stability of the bottom reflective layer is improved by covering the bottom reflective layer with the protective layer.

[0059] Further, the sidewall of the multi-quantum well layer is an inclined surface, and the projection area of the surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is within the projection area of the surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer. By making the sidewall of the multi-quantum well layer an inclined surface, the light emitting angle and the light emitting area of the multi-quantum well layer can be effectively increased. Moreover, the inclined sidewall is also conducive to forming a V-shaped angle between the sidewall opposite to the first reflective ring and the second reflective ring, which is beneficial to the reflection of the light by the first reflective ring and the second reflective ring.

[0060] Further, the sidewall of the first reflective ring is an inclined surface, and the projection area of the surface of the first reflective ring away from the first epitaxial layer towards the first epitaxial layer is within the projection area of the surface of the first reflective ring close to the first epitaxial layer towards the first epitaxial layer. The inclined sidewall of the first reflective ring and the inclined sidewall of the multi-quantum well layer can form a V-shaped angle, which is beneficial to the reflection of the light by the first reflective ring.

[0061] Further, the sidewall of the second reflective ring is an inclined surface, and the projection area of the surface of the second reflective ring away from the first epitaxial layer towards the first epitaxial layer is within the projection area of the surface of the second reflective ring close to the first epitaxial layer towards the first epitaxial layer. The inclined sidewall of the second reflective ring and the inclined sidewall of the multi-quantum well layer can form a V-shaped angle, which is beneficial to the reflection of the light by the second reflective ring.

[0062] Further, the first reflective ring has a first spacing dimension between the surface away from the first epitaxial layer and the first epitaxial layer, the multi-quantum well layer has a second spacing dimension between the surface away from the first epitaxial layer and the first epitaxial layer, and the first spacing dimension is greater than the second spacing dimension. By setting the height of the first reflective ring to be higher than the height of the multi-quantum well layer, the first reflective ring can reflect as much light as possible emitted by the multi-quantum well layer, thereby improving the light emitting efficiency of the micro light emitting diode chip.

[0063] Further, the second reflective ring has a third spacing dimension between the surface away from the first epitaxial layer and the first epitaxial layer, and the third spacing dimension is greater than or equal to the first spacing dimension. When the third spacing dimension is greater than the first spacing dimension, the second reflective ring can reflect the light that is not reflected by the first reflective ring, thereby further improving the light emitting efficiency of the micro light emitting diode chip.

[0064] In the method for forming the micro light emitting diode chip, the multi-layer reflective ring is formed around the multi-quantum well layer, the light emitted by the multi-quantum well layer can be subjected to multiple reflection processing, the sidewall effect caused by the small size of the device can be effectively reduced, and the light emitting efficiency and the use stability of the micro light emitting diode chip can be effectively improved.

[0065] Further, before forming the multi-layered reflecting ring, the method further comprises: etching the first epitaxial layer from the first side to the second side to form a first through hole and a second through hole in the first epitaxial layer; and forming a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflecting ring respectively; and after forming the multi-layered reflecting ring, the method further comprises: forming a first lead wire in the first through hole, the first lead wire being electrically connected to the first reflecting ring; and forming a second lead wire in the second through hole, the second lead wire being electrically connected to the second reflecting ring. The first reflecting ring is electrically connected to the first epitaxial layer as a transition component for leading out the first epitaxial layer, and the second reflecting ring is electrically connected to the second epitaxial layer as a transition component for leading out the second epitaxial layer, thereby eliminating the need for additional transition components for leading out the first epitaxial layer and the second epitaxial layer, simplifying the structure of the device and reducing the manufacturing process and cost.

[0066] Further, before forming the first pad and the second pad, the method further comprises: forming a bottom reflecting layer on the second side, the first through hole and the second through hole penetrating the bottom reflecting layer. The bottom reflecting layer can reflect light emitted by the multi-quantum well layer towards the second side, thereby further improving the light emitting efficiency of the micro light emitting diode chip.

[0067] Further, after forming the bottom reflecting layer, the method further comprises: forming a protective layer on the second side, the bottom reflecting layer being covered by the protective layer, the bottom reflecting layer being located between the first epitaxial layer and the protective layer, and the first through hole and the second through hole penetrating the protective layer. The protective layer covering the bottom reflecting layer can improve the stability of the bottom reflecting layer.

[0068] Further, the sidewall of the multi-quantum well layer is an inclined surface, and a projection area of a surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is located within a projection area of a surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer. The inclined sidewall of the multi-quantum well layer can effectively increase the light emitting angle and the light emitting area of the multi-quantum well layer. Moreover, the inclined sidewall facilitates the formation of a V-shaped angle between the sidewall opposite to the first reflecting ring and the sidewall opposite to the second reflecting ring, which is conducive to the reflection of light by the first reflecting ring and the second reflecting ring.

[0069] Further, the sidewall of the first reflecting ring is an inclined surface, and a projection area of a surface of the first reflecting ring away from the first epitaxial layer towards the first epitaxial layer is located within a projection area of a surface of the first reflecting ring close to the first epitaxial layer towards the first epitaxial layer. The inclined sidewall of the first reflecting ring can form a V-shaped angle with the inclined sidewall of the multi-quantum well layer, which is conducive to the reflection of light by the first reflecting ring.

[0070] Further, the side wall of the second reflective ring is an inclined surface, and the projection area of the surface of the second reflective ring away from the first epitaxial layer towards the first epitaxial layer is within the projection area of the surface of the second reflective ring close to the first epitaxial layer towards the first epitaxial layer. The V-shaped angle between the inclined side wall of the second reflective ring and the inclined side wall of the multi-quantum well layer can be formed, which is beneficial to the reflection of the second reflective ring to the light.

[0071] Further, the first reflective ring has a first spacing size between the surface of the first reflective ring away from the first epitaxial layer and the first epitaxial layer, the multi-quantum well layer has a second spacing size between the surface of the multi-quantum well layer away from the first epitaxial layer and the first epitaxial layer, and the first spacing size is greater than the second spacing size. By setting the height of the first reflective ring to be higher than the height of the multi-quantum well layer, the first reflective ring can reflect as much light as possible emitted by the multi-quantum well layer, thereby improving the light-emitting efficiency of the micro light-emitting diode chip.

[0072] Further, the second reflective ring has a third spacing size between the surface of the second reflective ring away from the first epitaxial layer and the first epitaxial layer, and the third spacing size is greater than or equal to the first spacing size. When the third spacing size is greater than the first spacing size, the second reflective ring can reflect the light that is not reflected by the first reflective ring, thereby further improving the light-emitting efficiency of the micro light-emitting diode chip. BRIEF DESCRIPTION OF DRAWINGS

[0073] FIGS. 1-15 are structural schematic diagrams of each step of the forming method of the micro light-emitting diode chip according to the embodiments of the present application. DETAILED DESCRIPTION

[0074] As described in the background, the micro light-emitting diode chip in the prior art still has many problems. The following will be specifically described.

[0075] Although the micro light-emitting diode chip has many advantages, there are also technical challenges at the present stage. The EQE (the ratio of the number of photons emitted to the outside to the number of carriers flowing through the junction) of the micro light-emitting diode chip is significantly low. Solving the light-emitting efficiency problem of the micro light-emitting diode chip is the basis for the large-scale production of the micro light-emitting diode chip.

[0076] On this basis, the present application provides a micro light-emitting diode chip and a forming method thereof. By additionally arranging a plurality of reflective rings around the multi-quantum well layer, the light emitted by the multi-quantum well layer can be subjected to multiple reflection processing, the side wall effect caused by the small size of the device can be effectively reduced, and the light-emitting efficiency and use stability of the micro light-emitting diode chip can be effectively improved.

[0077] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0078] In the description of the present application, it should be understood that the terms "upper", "lower", "top surface", "bottom surface" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated position or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are only used to distinguish entities or operations from each other, and do not require or imply any actual relationship, order or relative importance between the entities or operations.

[0079] FIGS. 1 to 15 are schematic structural views of each step of the method for forming a micro light emitting diode chip according to an embodiment of the present application.

[0080] Referring to FIG. 1, a first temporary substrate 100 is provided.

[0081] In the present embodiment, the first temporary substrate 100 is an epitaxial substrate layer, which is used as a temporary supporting structure in the flip-chip fabrication process of the micro light emitting diode chip. After the actual device structure of the micro light emitting diode chip is completed, the first temporary substrate 100 needs to be removed.

[0082] Continuing to refer to FIG. 1, in the present embodiment, after the first temporary substrate 100 is provided, a buffer layer 101 is formed on the first temporary substrate 100. Since a bottom reflection layer needs to be fabricated on the back surface of the micro light emitting diode chip in the subsequent fabrication process to further improve the light emitting efficiency of the micro light emitting diode chip, the buffer layer 101 needs to be formed first to serve as a placeholder for the subsequently formed bottom reflection layer.

[0083] In the present embodiment, the buffer layer 101 is an epitaxial buffer layer of aluminum nitride (ALN).

[0084] Referring to FIG. 2, a first epitaxial layer 102 is formed on the first temporary substrate 100, the first epitaxial layer 102 has first and second sides 102a and 102b opposite to each other, and the first temporary substrate 100 is located at the second side 102b. The first epitaxial layer 102 has a first doping ion.

[0085] In the embodiment, the buffer layer 101 is located at the second side 102b, and the buffer layer 101 is located between the first epitaxial layer 102 and the first temporary substrate 100.

[0086] In the embodiment, the first doping ions are of N type.

[0087] It should be noted that, in the embodiment, the first side 102a is the front surface of the micro LED chip, and the second side 102b is the back surface of the micro LED chip.

[0088] In the embodiment, the material of the first epitaxial layer is gallium nitride.

[0089] Referring to FIG. 3, the multi-quantum well layer 103 and the second epitaxial layer 105 are sequentially stacked at the first side 102a, the multi-quantum well layer 103 is in contact with the first epitaxial layer 102, the second epitaxial layer 105 has second doping ions therein, and the second doping ions and the first doping ions are of different electrical types.

[0090] In the embodiment, after the multi-quantum well layer 103 is formed and before the second epitaxial layer 105 is formed, the method further includes: forming an electron blocking layer 104 at the first side 102a, the electron blocking layer 104 being located between the multi-quantum well layer 103 and the second epitaxial layer 105.

[0091] In the embodiment, the method for forming the multi-quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105 includes: sequentially stacking a multi-quantum well material layer, an electron blocking material layer, and a second gallium nitride material layer (not shown) at the first side 102a; and sequentially performing etching treatment on the second gallium nitride material layer, the electron blocking material layer, and the multi-quantum well material layer to form the multi-quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105.

[0092] It should be noted that, in the embodiment, after the multi-quantum well material layer is etched, a certain amount of etching treatment is performed on the first epitaxial layer 102, so that the first epitaxial layer 102 has a raised portion (not shown) for supporting the multi-quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105.

[0093] In the embodiment, the second doping ions are of P type. The first epitaxial layer 102 and the second epitaxial layer 105 serve as an anode and a cathode of the micro LED chip, respectively.

[0094] In the embodiment, the material of the second epitaxial layer is gallium nitride.

[0095] In the embodiment, the sidewall of the multi-quantum well layer 103 is an inclined surface, and the projection area of the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 towards the first epitaxial layer 102 is located in the projection area of the surface of the multi-quantum well layer 103 close to the first epitaxial layer 102 towards the first epitaxial layer 102. By making the sidewall of the multi-quantum well layer 103 an inclined surface, the light emitting angle and the light emitting area of the multi-quantum well layer 103 can be effectively increased. Moreover, the inclined sidewall is also conducive to forming a V-shaped angle between the sidewalls opposite to the first reflective ring and the second reflective ring formed subsequently, which is beneficial to the reflection of light by the first reflective ring and the second reflective ring.

[0096] In the embodiment, by adjusting the photoresist profile chamfer, and then etching the multi-quantum well material layer with the photoresist as a mask, the sidewall of the multi-quantum well layer 103 can present an inclined profile.

[0097] In the embodiment, the inclination angle of the sidewall of the multi-quantum well layer 103 ranges from 70° to 80°.

[0098] Please refer to FIG. 4. The first epitaxial layer 102 is etched from the first side 102a to the second side 102b to form the first via hole 117 and the second via hole 118 in the first epitaxial layer 102.

[0099] It should be noted that, in the embodiment, the deep hole lithography is performed by lithography at the horizontal position of the first epitaxial layer 102. It should be noted that, due to the small hole, the lithography offset is less than 0.2 microns. The deep via hole is formed by ion etching, and the etching depth needs to reach the first temporary substrate 100, which is convenient for the backside epitaxial thinning process after the first temporary substrate 100 is removed. Due to the characteristics of the photoresist, the etching profile of the first via hole 117 and the second via hole 118 generally presents an inverted trapezoidal structure with the upper part being large and the lower part being small.

[0100] In the embodiment, since the first via hole 117 and the second via hole 118 need to extend to the first temporary substrate 100, after etching the first epitaxial layer 102, the buffer layer 101 is etched from the first side 102a to the second side 102b, and the first via hole 117 and the second via hole 118 are also located in the buffer layer 101.

[0101] Please refer to FIG. 5. The first passivation layer 106 is formed at the first side 102a, the sidewall of the first via hole 117, and the sidewall of the second via hole 118.

[0102] In the embodiment, the first passivation layer 106 located at the first side 102a covers part of the surface of the first epitaxial layer 102 located at the first side 102a; the first passivation layer 106 located at the first side 102a also covers the sidewalls of the multi-quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105, and part of the surface of the second epitaxial layer 105 away from the first epitaxial layer 102.

[0103] In the embodiment, the forming method of the first passivation layer 106 includes: forming a first passivation material layer (not shown) on the first side 102a, the first via hole 117 sidewall and the second via hole 118 sidewall, the first passivation material layer on the first side 102a covers the surface of the first epitaxial layer 102 on the first side 102a, the sidewall of the multi-quantum well layer 103, the electron blocking layer 104 and the second epitaxial layer 105, and the surface of the second epitaxial layer 105 away from the first epitaxial layer 102; and performing etching treatment on the first passivation material layer to expose part of the surface of the first epitaxial layer 102 and part of the surface of the second epitaxial layer 105, thereby forming the first passivation layer 106.

[0104] In the embodiment, the first passivation layer 106 mainly plays an electrical isolation role, and the first passivation material layer can be an aluminum oxide (AL2O3) film layer formed by an atomic layer deposition process with good step coverage.

[0105] Please refer to FIG. 6, the conductive layer 107 is formed on the first side 102a, and the conductive layer 107 is electrically connected with the second epitaxial layer 105.

[0106] In the embodiment, the first passivation layer 106 is used for electrical isolation of the conductive layer 107 and the first epitaxial layer 102, the multi-quantum well layer 103 and the electron blocking layer 104.

[0107] In the embodiment, the conductive layer 107 adopts indium tin oxide material, which can ensure good ohmic contact with the second epitaxial layer 105 and ensure the transmittance of light emitted from the front surface and the side surface of the multi-quantum well layer 103.

[0108] In the embodiment, the conductive layer 107 is electrically connected with the second epitaxial layer 105 exposed by the first passivation layer 106.

[0109] In the embodiment, after the conductive layer 107 is formed, a plurality of reflective rings are formed on the first side 102a in a multilayer arrangement, wherein the innermost reflective ring surrounds the multi-quantum well layer 103.

[0110] In the embodiment, the number of layers of the reflective ring is taken as an example of 2 layers, i.e., a first reflective ring surrounding the multi-quantum well layer 103, and a second reflective ring surrounding the first reflective ring and in contact with the first epitaxial layer 102. For details, please refer to FIG. 7 and FIG. 8.

[0111] Please refer to FIG. 7, the first reflective ring 108 is formed on the first side 102a, the first reflective ring 108 surrounds the multi-quantum well layer 103, and the first reflective ring 108 is electrically connected with the conductive layer 107.

[0112] In the embodiment, the first reflective ring 108 is formed by one or both of a magnetron sputtering coating process and an evaporation process, and the material of the first reflective ring 108 can be chromium, aluminum, titanium, nickel, platinum or gold.

[0113] It should be noted that, in the embodiment, the first lead 109 is also formed in the first through hole 117 in the process of forming the first reflective ring 108, and the first lead 109 is electrically connected with the first reflective ring 108, that is, the first reflective ring 108 and the first lead 109 are formed synchronously.

[0114] In the embodiment, the side wall of the first reflective ring 108 is an inclined surface, and the projection area of the surface of the first reflective ring 108 away from the first epitaxial layer 102 towards the first epitaxial layer 102 is located in the projection area of the surface of the first reflective ring 108 close to the first epitaxial layer 102 towards the first epitaxial layer 102. The inclined side wall of the first reflective ring 108 and the inclined side wall of the multi-quantum well layer 103 form a V-shaped angle, which is beneficial to the reflection of the first reflective ring 108 to the light.

[0115] In the embodiment, the inclination angle of the side wall of the first reflective ring 108 ranges from 73° to 85°.

[0116] In the embodiment, the first reflective ring 108 has a first spacing size d1 between the surface of the first reflective ring 108 away from the first epitaxial layer 102 and the first epitaxial layer 102, and the multi-quantum well layer 103 has a second spacing size d2 between the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 and the first epitaxial layer 102, and the first spacing size d1 is greater than the second spacing size d2. The height of the first reflective ring 108 is set to be higher than the height of the multi-quantum well layer 103, so as to ensure that the first reflective ring 108 can reflect as much light as possible emitted by the multi-quantum well layer 103, thereby improving the light emitting efficiency of the micro light emitting diode chip.

[0117] Please refer to FIG. 8 and FIG. 9, FIG. 8 is a top view of the position relationship of part of the structure, and FIG. 9 is a schematic view of the section along the line A-A of FIG. 8. The second reflective ring 110 is formed on the first side 102a, the second reflective ring 110 surrounds the first reflective ring 108, and the second reflective ring 110 is electrically connected with the first epitaxial layer 102.

[0118] In the embodiment, the second reflective ring 110 is formed by one or both of a magnetron sputtering coating process and an evaporation process, and the material of the second reflective ring 110 can be chromium, aluminum, titanium, nickel, platinum or gold.

[0119] It should be noted that, in the embodiment, the second lead 111 is also formed in the second through hole 118 in the process of forming the second reflective ring 110, and the second lead 111 is electrically connected with the second reflective ring 110, that is, the second reflective ring 110 and the second lead 111 are formed synchronously.

[0120] In other embodiments, the first and second leads can also be formed in separate fabrication steps.

[0121] In the embodiment, the sidewall of the second reflective ring 110 is an inclined surface, and the projection area of the second reflective ring 110 away from the surface of the first epitaxial layer 102 towards the first epitaxial layer 102 is within the projection area of the second reflective ring 110 close to the surface of the first epitaxial layer 102 towards the first epitaxial layer 102. The inclined sidewall of the second reflective ring 110 and the inclined sidewall of the multi-quantum well layer 103 form a V-shaped angle, which is beneficial to the reflection of the light by the first reflective ring 108.

[0122] In the embodiment, the inclined angle of the sidewall of the second reflective ring 110 ranges from 73° to 85°.

[0123] In the embodiment, the second reflective ring 110 has a third spacing dimension d3 between the surface away from the first epitaxial layer 102 and the first epitaxial layer 102, and the third spacing dimension d3 is greater than the first spacing dimension d1. When the third spacing dimension d3 is greater than the first spacing dimension d1, the second reflective ring 110 can reflect the light that is not reflected by the first reflective ring 108, further improving the light emitting efficiency of the micro LED chip.

[0124] It should be noted that, in the embodiment, the first reflective ring 108 and the second reflective ring 110 need to be fabricated separately because the height of the first reflective ring 108 and the height of the second reflective ring 110 are different.

[0125] In other embodiments, the third spacing dimension can also be equal to the first spacing dimension. When the third spacing dimension is equal to the first spacing dimension, i.e., the height of the first reflective ring and the height of the second reflective ring are the same, the first reflective ring and the second reflective ring can be fabricated simultaneously.

[0126] In the embodiment, the second reflective ring 110 is electrically connected to the first epitaxial layer 102 exposed by the first passivation layer 106.

[0127] Referring to FIG. 10, after the second reflective ring 110 is formed, a microlens 113 is formed on the first side 102a, the microlens 113 is in contact with the conductive layer 107, and the projection area of the multi-quantum well layer 103 towards the first epitaxial layer 102 is within the projection area of the microlens 113 towards the first epitaxial layer 102.

[0128] In the present embodiment, in the process of forming the microlens 113, the second passivation layer 112 is formed on the first side 102a, and the second passivation layer 112 covers the multi-quantum well layer 103, the electron blocking layer 104, the second epitaxial layer 105, the first reflective ring 108, the second reflective ring 110, the second passivation layer 112, and the conductive layer 107.

[0129] In the present embodiment, the microlens 113 and the second passivation layer 112 are made of the same material, and the material of the second passivation layer 112 and the microlens 113 is silicon dioxide (SiO2).

[0130] In the present embodiment, the forming method of the microlens 113 and the second passivation layer 112 includes: forming a passivation material layer (not shown) on the first side 102a, the passivation material layer covering the multi-quantum well layer 103, the electron blocking layer 104, the second epitaxial layer 105, the first reflective ring 108, the second reflective ring 110, the second passivation layer 112, and the conductive layer 107; and performing a patterned etching process on the passivation material layer to form the microlens 113 and the second passivation layer 112.

[0131] In other embodiments, the microlens and the second passivation layer can also be made of different materials, and the material of the second passivation layer can be silicon oxide, and the material of the second passivation layer can be silicon nitride.

[0132] Correspondingly, the forming method of the microlens and the second passivation layer includes: forming a passivation material layer on the first side, the passivation material layer covering the multi-quantum well layer, the electron blocking layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer, and the conductive layer; forming a microlens material layer on the passivation material layer; and performing a patterned etching process on the passivation material layer and the microlens material layer to form the microlens and the second passivation layer.

[0133] In the present embodiment, the microlens 113 has a hemispherical shape, and the hemispherical structure can further improve the light extraction efficiency of the micro light emitting diode chip.

[0134] Please refer to FIG. 11, the second temporary substrate 200 is provided.

[0135] In the present embodiment, the second temporary substrate 200 is made of a silicon wafer, and the second temporary substrate 200 is also used as a temporary support structure in the flip-chip fabrication process of the micro light emitting diode chip. After the actual device structure of the micro light emitting diode chip is completed, the second temporary substrate 200 needs to be removed.

[0136] Please refer to FIG. 12, the second temporary substrate 200 is bonded to the microlens 113 from the first side 102a.

[0137] In the embodiment, the second temporary substrate 200 is adhered to the surface of the microlens 113 by the temporary bonding glue layer 201, and temporary bonding is achieved.

[0138] In the embodiment, the temporary bonding glue layer 201 needs to have high-temperature resistance (200-220°C) to cope with the heat treatment in the subsequent process.

[0139] Please refer to FIG. 13, the first temporary substrate 100 is removed after bonding.

[0140] In the embodiment, the process of removing the first temporary substrate 100 adopts a laser stripping process.

[0141] Please continue to refer to FIG. 13, in the embodiment, the buffer layer 101 is also removed after the first temporary substrate 100 is removed. The process of removing the buffer layer 101 adopts an ion etching process.

[0142] It should be noted that in the embodiment, the additional sacrificial layer is formed to protect the first lead 109 and the second lead 111 during the removal of the buffer layer 101, so that the first lead 109 and the second lead 111 still protrude from the surface of the first epitaxial layer 102 after the buffer layer 101 is removed by the dry etching process.

[0143] In other embodiments, the first lead and the second lead can also not be protected during the removal of the buffer layer, so that the first lead and the second lead are flush with the surface of the first epitaxial layer after the buffer layer is removed by the dry etching process.

[0144] Please refer to FIG. 14, the bottom reflection layer 114 is formed on the second side 102b, and the first through hole 117 and the second through hole 118 penetrate the bottom reflection layer 114.

[0145] The light emitted by the multi-quantum well layer 103 towards the second side 102b can be reflected by the bottom reflection layer 114, further improving the light emitting efficiency of the micro light emitting diode chip.

[0146] In the embodiment, the material of the bottom reflection layer 114 can be aluminum or silver.

[0147] Please continue to refer to FIG. 14, in the embodiment, before the bottom reflection layer 114 is formed, the insulating layer 115 is formed on the second side 102b; the insulating layer 115 is located between the first epitaxial layer 102 and the bottom reflection layer 114, and the first through hole 117 and the second through hole 118 penetrate the insulating layer 115.

[0148] In the embodiment, the insulating layer 115 is used for electrical isolation between the bottom reflection layer 114 and the first epitaxial layer 102, and the material of the insulating layer 115 can be silicon dioxide or aluminum oxide.

[0149] Please continue to refer to Figure 14, in this embodiment, after the bottom reflection layer 114 is formed, the protective layer 116 is formed on the second side 102b; the protective layer 116 covers the bottom reflection layer 114, and the bottom reflection layer 114 is located between the first epitaxial layer 102 and the protective layer 116, and the first through hole 117 and the second through hole 118 penetrate the protective layer 116. By covering the bottom reflection layer 114 with the protective layer 116, the stability of the bottom reflection layer 114 can be improved.

[0150] In this embodiment, the material of the protective layer 116 can be silicon dioxide or silicon nitride (SiN).

[0151] In other embodiments, if the first lead and the second lead are flush with the surface of the first epitaxial layer, after the insulating layer, the bottom reflection layer and the protective layer are formed, the insulating layer, the bottom reflection layer and the protective layer covering the first lead and the second lead need to be removed, and the first connecting hole and the second connecting hole are formed in the insulating layer, the bottom reflection layer and the protective layer, the first connecting hole exposes the first lead, and the second connecting hole exposes the second lead.

[0152] Please refer to Figure 15, the first pad 119 and the second pad 120 are formed on the second side 102b, the first pad 119 is electrically connected with the first lead 109, and the second pad 120 is electrically connected with the second lead 111.

[0153] By adding the first reflection ring 108 and the second reflection ring 110 on the periphery of the multi-quantum well layer 103, the light emitted by the multi-quantum well layer 103 can be subjected to multiple reflection processing, which can effectively reduce the sidewall effect caused by the small size of the device, and further improve the light-emitting efficiency and the use stability of the micro light-emitting diode chip.

[0154] In addition, the first reflection ring 108 is electrically connected with the first epitaxial layer 102 as a transition component for leading out the connection of the first epitaxial layer 102, and the second reflection ring 110 is electrically connected with the second epitaxial layer 105 as a transition component for leading out the connection of the second epitaxial layer 105, which saves the additional transition components for leading out the connection of the first epitaxial layer 102 and the second epitaxial layer 105, thereby simplifying the device structure and reducing the manufacturing process and cost.

[0155] In this embodiment, the material of the first pad 119 and the second pad 120 can be one or a combination of chromium, aluminum, titanium, nickel, platinum, gold and tin.

[0156] In other embodiments, if the first connecting hole and the second connecting hole are formed in the insulating layer, the bottom reflection layer and the protective layer, metal is also filled in the first connecting hole and the second connecting hole respectively during the formation of the first pad and the second pad, so that the first lead and the first pad are electrically connected, and the second lead and the second pad are electrically connected.

[0157] Please continue to refer to Figure 15, in this embodiment, after the formation of the first pad 119 and the second pad 120, the second temporary substrate 200 is removed.

[0158] Correspondingly, the embodiment of the present application also provides a micro light emitting diode chip, please continue to refer to Figure 15, comprising: a first epitaxial layer 102, the first epitaxial layer 102 has a first doping ion, the first epitaxial layer 102 has a first side 102a and a second side 102b opposite to each other; a multi quantum well layer 103 located on the first side 102a, the multi quantum well layer 103 is in contact with the first epitaxial layer 102; a second epitaxial layer 105 located on the first side 102a, the second epitaxial layer 105 has a second doping ion, the second doping ion and the first doping ion are different in electrical type, the multi quantum well layer 103 is located between the first epitaxial layer 102 and the second epitaxial layer 105; a plurality of reflection rings arranged in turn and surrounded by each other, wherein the innermost reflection ring surrounds the multi quantum well layer 103.

[0159] By adding the first reflection ring 108 and the second reflection ring 110 on the periphery of the multi quantum well layer 103, the light emitted by the multi quantum well layer 103 can be subjected to multiple reflection processing, which can effectively reduce the side wall effect caused by the small size of the device, and further improve the light emitting efficiency and the use stability of the micro light emitting diode chip.

[0160] In this embodiment, the plurality of reflection rings comprises: a first reflection ring 108, the first reflection ring 108 surrounds the multi quantum well layer 103; a second reflection ring 110, the second reflection ring 110 surrounds the first reflection ring 108, and the second reflection ring 110 is in contact with the first epitaxial layer 102.

[0161] In this embodiment, the micro light emitting diode chip further comprises: a first via hole 117 and a second via hole 118 located in the first epitaxial layer 102; a conductive layer 107 located on the first side 102a, the conductive layer 107 is electrically connected with the second epitaxial layer 105 and the first reflection ring 108 respectively; a first lead wire 109 located in the first via hole 117, the first lead wire 109 is electrically connected with the first reflection ring 108; a second lead wire 111 located in the second via hole 118, the second lead wire 111 is electrically connected with the second reflection ring 110.

[0162] The first reflection ring 108 is electrically connected with the first epitaxial layer 102 to serve as a transition component for leading out the connection of the first epitaxial layer 102, and the second reflection ring 110 is electrically connected with the second epitaxial layer 105 to serve as a transition component for leading out the connection of the second epitaxial layer 105, which eliminates the need for additional manufacturing of transition components for leading out the connection of the first epitaxial layer 102 and the second epitaxial layer 105, thereby simplifying the device structure and reducing the manufacturing process and cost.

[0163] In the embodiment, the micro light emitting diode chip further comprises a bottom reflection layer 114 located at the second side 102b, and the first through hole 117 and the second through hole 118 penetrate the bottom reflection layer 114. The light emitted by the multi-quantum well layer 103 towards the second side 102b can be reflected by the bottom reflection layer 114, further improving the light emitting efficiency of the micro light emitting diode chip.

[0164] In the embodiment, the micro light emitting diode chip further comprises an insulating layer 115 located at the second side 102b, the insulating layer 115 is located between the first epitaxial layer 102 and the bottom reflection layer 114, and the first through hole 117 and the second through hole 118 penetrate the insulating layer 115.

[0165] In the embodiment, the micro light emitting diode chip further comprises a protective layer 116 located at the second side 102b, the protective layer 116 covers the bottom reflection layer 114, and the bottom reflection layer 114 is located between the first epitaxial layer 102 and the protective layer 116, and the first through hole 117 and the second through hole 118 penetrate the protective layer 116. By covering the bottom reflection layer 114 with the protective layer 116, the stability of the bottom reflection layer 114 can be improved.

[0166] In the embodiment, the side wall of the multi-quantum well layer 103 is an inclined surface, and the projection area of the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 towards the first epitaxial layer 102 is located within the projection area of the surface of the multi-quantum well layer 103 close to the first epitaxial layer 102 towards the first epitaxial layer 102. By making the side wall of the multi-quantum well layer 103 an inclined surface, the light emitting angle and light emitting area of the multi-quantum well layer 103 can be effectively increased. Moreover, the inclined side wall is also conducive to forming a V-shaped angle between the side wall opposite to the first reflection ring 108 and the second reflection ring 110, which is beneficial to the reflection of light by the first reflection ring 108 and the second reflection ring 110.

[0167] In the embodiment, the inclination angle of the side wall of the multi-quantum well layer 103 ranges from 70° to 80°.

[0168] In the embodiment, the side wall of the first reflection ring 108 is an inclined surface, and the projection area of the surface of the first reflection ring 108 away from the first epitaxial layer 102 towards the first epitaxial layer 102 is located within the projection area of the surface of the first reflection ring 108 close to the first epitaxial layer 102 towards the first epitaxial layer 102. The inclined side wall of the first reflection ring 108 and the inclined side wall of the multi-quantum well layer 103 can form a V-shaped angle, which is beneficial to the reflection of light by the first reflection ring 108.

[0169] In the embodiment, the inclination angle of the side wall of the first reflection ring 108 ranges from 73° to 85°.

[0170] In the embodiment, the sidewall of the second reflective ring 110 is an inclined surface, and the projection area of the second reflective ring 110 away from the surface of the first epitaxial layer 102 towards the first epitaxial layer 102 is within the projection area of the second reflective ring 110 close to the surface of the first epitaxial layer 102 towards the first epitaxial layer 102. The inclined sidewall of the second reflective ring 110 and the inclined sidewall of the multi-quantum well layer 103 form a V-shaped angle, which is beneficial to the reflection of the second reflective ring 110 to the light.

[0171] In the embodiment, the inclined angle of the sidewall of the second reflective ring 110 ranges from 73° to 85°.

[0172] In the embodiment, the first reflective ring 108 has a first spacing size d1 between the surface away from the first epitaxial layer 102 and the first epitaxial layer 102, and the multi-quantum well layer 103 has a second spacing size d2 between the surface away from the first epitaxial layer 102 and the first epitaxial layer 102, and the first spacing size d1 is greater than the second spacing size d2. The height of the first reflective ring 108 is set to be higher than the height of the multi-quantum well layer 103, so as to ensure that the first reflective ring 108 can reflect as much light as possible emitted by the multi-quantum well layer 103, thereby improving the light-emitting efficiency of the micro light-emitting diode chip.

[0173] In the embodiment, the second reflective ring 110 has a third spacing size d3 between the surface away from the first epitaxial layer 102 and the first epitaxial layer 102, and the third spacing size d3 is greater than the first spacing size d1. When the third spacing size d3 is greater than the first spacing size d1, the second reflective ring 110 can reflect the light that is not reflected by the first reflective ring 108, thereby further improving the light-emitting efficiency of the micro light-emitting diode chip.

[0174] In other embodiments, the third spacing size can also be equal to the first spacing size.

[0175] In the embodiment, the micro light-emitting diode chip further comprises a first passivation layer 106 located on the first side 102a, the sidewall of the first via hole 117, and the sidewall of the second via hole 118; the first passivation layer 106 located on the first side 102a covers part of the surface of the first epitaxial layer 102 located on the first side 102a, and the second reflective ring 110 is electrically connected to the first epitaxial layer 102 exposed by the first passivation layer 106; the first passivation layer 106 located on the first side 102a also covers the sidewall of the multi-quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105, and part of the surface of the second epitaxial layer 105 away from the first epitaxial layer 102, and the conductive layer 107 is electrically connected to the second epitaxial layer 105 exposed by the first passivation layer 106.

[0176] In the embodiment, the micro light emitting diode chip further comprises a second passivation layer 112 on the first side 102a, the second passivation layer 112 covers the multi-quantum well layer 103, the electron blocking layer 104, the second epitaxial layer 105, the first reflective ring 108, the second reflective ring 110, the second passivation layer 112 and the conductive layer 107.

[0177] In the embodiment, the micro light emitting diode chip further comprises a microlens 113 on the first side 102a, a projection area of the multi-quantum well layer 103 towards the first epitaxial layer 102 is within a projection area range of the microlens 113 towards the first epitaxial layer 102.

[0178] In the embodiment, the micro light emitting diode chip further comprises a first pad 119 on the second side 102b, the first pad 119 is electrically connected with the first lead wire 109; a second pad 120 on the second side 102b, the second pad 120 is electrically connected with the second lead wire 111.

[0179] In the embodiment, the micro light emitting diode chip further comprises an electron blocking layer 104 on the first side 102a, the electron blocking layer 104 is between the multi-quantum well layer 103 and the second epitaxial layer 105.

[0180] In the embodiment, the material of the first epitaxial layer 102 and the second epitaxial layer 105 is gallium nitride.

[0181] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A micro light emitting diode chip, characterized by, Comprising: a first epitaxial layer having first doping ions therein, the first epitaxial layer having opposite first and second sides; a multi-quantum well layer on the first side, the multi-quantum well layer being in contact with the first epitaxial layer; a second epitaxial layer on the first side, the second epitaxial layer having second doping ions therein, the second doping ions and the first doping ions being of different electrical types, the multi-quantum well layer being between the first epitaxial layer and the second epitaxial layer; a plurality of reflector rings arranged in a nested manner on the first side, wherein an innermost one of the reflector rings surrounds the multi-quantum well layer.

2. The micro light emitting diode chip of claim 1, wherein, The plurality of reflector rings comprises: a first reflector ring surrounding the multi-quantum well layer; and a second reflector ring surrounding the first reflector ring, the second reflector ring being in contact with the first epitaxial layer.

3. The micro light emitting diode chip of claim 2, wherein, Further comprising: a first via and a second via in the first epitaxial layer; a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflector ring, respectively; a first lead wire on the first via, the first lead wire being electrically connected to the first reflector ring; and a second lead wire on the second via, the second lead wire being electrically connected to the second reflector ring.

4. The micro light emitting diode chip of claim 3, wherein, Further comprising: a bottom reflector layer on the second side, the first via and the second via penetrating the bottom reflector layer.

5. The micro light emitting diode chip of claim 4, wherein, Further comprising: an insulating layer on the second side, the insulating layer being between the first epitaxial layer and the bottom reflector layer, the first via and the second via penetrating the insulating layer.

6. The micro light emitting diode chip of claim 4, wherein, Further comprising: a protective layer on the second side, the protective layer covering the bottom reflector layer, and the bottom reflector layer being between the first epitaxial layer and the protective layer, the first via and the second via penetrating the protective layer.

7. The micro light emitting diode chip of claim 1, wherein, A sidewall of the multi-quantum well layer is an inclined surface, and a projection area of a surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is within a projection area of a surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer.

8. The micro light emitting diode chip of claim 7, wherein, An inclination angle of the sidewall of the multi-quantum well layer ranges from 70° to 80°.

9. The micro light emitting diode chip of claim 2, wherein, A sidewall of the first reflector ring is an inclined surface, and a projection area of a surface of the first reflector ring away from the first epitaxial layer towards the first epitaxial layer is within a projection area of a surface of the first reflector ring close to the first epitaxial layer towards the first epitaxial layer.

10. The micro light emitting diode chip of claim 9, wherein, An inclination angle of the sidewall of the first reflector ring ranges from 73° to 85°.

11. The micro light emitting diode chip of claim 2, wherein, A sidewall of the second reflector ring is an inclined surface, and a projection area of a surface of the second reflector ring away from the first epitaxial layer towards the first epitaxial layer is within a projection area of a surface of the second reflector ring close to the first epitaxial layer towards the first epitaxial layer.

12. The micro light emitting diode chip of claim 11, wherein, An inclination angle of the sidewall of the second reflector ring ranges from 73° to 85°.

13. The micro light emitting diode chip of claim 2, wherein, The first reflective ring has a first spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, and the multi-quantum well layer has a second spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, the first spacing dimension being greater than the second spacing dimension.

14. The micro light emitting diode chip of claim 13, wherein, The second reflective ring has a third spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

15. The micro light emitting diode chip of claim 3, wherein, Further comprising: a first passivation layer on the first side, the first via sidewall and the second via sidewall; the first passivation layer on the first side covering a portion of a surface of the first epitaxial layer on the first side, the second reflective ring being electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer on the first side further covering a sidewall of the multi-quantum well layer and the second epitaxial layer, and a portion of a surface of the second epitaxial layer away from the first epitaxial layer, the conductive layer being electrically connected to the second epitaxial layer exposed by the first passivation layer.

16. The micro light emitting diode chip of claim 15, wherein, Further comprising: A second passivation layer on the first side, the second passivation layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer.

17. The micro light emitting diode chip of claim 1, wherein, Further comprising: A microlens on the first side, a projection area of the multi-quantum well layer towards the first epitaxial layer being within a projection area range of the microlens towards the first epitaxial layer.

18. The micro light emitting diode chip of claim 3, wherein, Further comprising: a first pad on the second side, the first pad being electrically connected to the first lead; a second pad on the second side, the second pad being electrically connected to the second lead.

19. The micro light emitting diode chip of claim 1, wherein, Further comprising: An electron blocking layer on the first side, the electron blocking layer being between the multi-quantum well layer and the second epitaxial layer.

20. The micro light emitting diode chip of claim 1, wherein, Materials of the first epitaxial layer and the second epitaxial layer include gallium nitride.

21. A method of forming a micro light emitting diode chip, characterized by, Comprising: forming a first epitaxial layer having first dopant ions therein, the first epitaxial layer having opposite first and second sides; stacking a multi-quantum well layer and a second epitaxial layer on the first side, the multi-quantum well layer being in contact with the first epitaxial layer and being between the first epitaxial layer and the second epitaxial layer, the second epitaxial layer having second dopant ions therein, the second dopant ions and the first dopant ions being of different electrical types; forming a plurality of reflective rings on the first side in a stacked arrangement, wherein an innermost one of the reflective rings surrounds the multi-quantum well layer.

22. The method of claim 21, wherein the micro-LED chip is formed by: The plurality of reflective rings includes: a first reflective ring surrounding the multi-quantum well layer; and a second reflective ring surrounding the first reflective ring, the second reflective ring being in contact with the first epitaxial layer.

23. The method of claim 22, wherein the micro-LED chip is formed by: Before forming the first epitaxial layer, further comprising: providing a first temporary substrate; and forming the first epitaxial layer on the first temporary substrate, the first temporary substrate being on the second side.

24. The method of claim 23, wherein the micro-LED chip is formed by: Before forming the multi-layered reflective ring, further comprising: etching the first epitaxial layer from the first side to the second side to form a first via and a second via in the first epitaxial layer; forming a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflective ring respectively; after forming the multi-layered reflective ring, further comprising: forming a first lead in the first via, the first lead being electrically connected to the first reflective ring; forming a second lead in the second via, the second lead being electrically connected to the second reflective ring.

25. The method of claim 24, wherein the micro-LED chip is formed by: After forming the first lead and the second lead, further comprising: forming a microlens on the first side, a projection area of the multi-quantum well layer towards the first epitaxial layer being located in a projection area of the microlens towards the first epitaxial layer; providing a second temporary substrate; bonding the second temporary substrate to the microlens from the first side; removing the first temporary substrate after bonding.

26. The method of claim 25, wherein the micro-LED chip is formed by: After removing the first temporary substrate, further comprising: forming a first pad and a second pad on the second side, the first pad being electrically connected to the first lead, and the second pad being electrically connected to the second lead; removing the second temporary substrate after forming the first pad and the second pad.

27. The method of claim 26, wherein the micro-LED chip is formed by: Before forming the first epitaxial layer, further comprising: forming a buffer layer on the first temporary substrate; the buffer layer being located on the second side, and the buffer layer being located between the first epitaxial layer and the first temporary substrate.

28. The method of claim 27, wherein the micro-LED chip is formed by: After etching the first epitaxial layer, further comprising: etching the buffer layer from the first side to the second side, the first via and the second via being further located in the buffer layer.

29. The method of claim 28, wherein the micro-LED chip is formed by: After removing the first temporary substrate, further comprising: removing the buffer layer.

30. The method of claim 29, wherein the micro-LED chip is formed by: Before forming the first pad and the second pad, further comprising: forming a bottom reflective layer on the second side, the first via and the second via penetrating through the bottom reflective layer.

31. The method of claim 30, wherein the micro-LED chip is formed by: Before forming the bottom reflective layer, further comprising: forming an insulating layer on the second side; the insulating layer being located between the first epitaxial layer and the bottom reflective layer, the first via and the second via penetrating through the insulating layer.

32. The method of claim 30, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the target substrate. After forming the bottom reflective layer, further comprising: forming a protective layer on the second side; the protective layer covering the bottom reflective layer, and the bottom reflective layer being located between the first epitaxial layer and the protective layer, the first via and the second via penetrating through the protective layer.

33. The method of claim 21, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to a target substrate. A side wall of the multi-quantum well layer is an inclined surface, and a projection area of a surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer.

34. The method of claim 33, wherein the micro-LED chip is formed by: An inclined angle of the side wall of the multi-quantum well layer ranges from 70° to 80°.

35. The method of claim 22, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to a target substrate. A side wall of the first reflective ring is an inclined surface, and a projection area of a surface of the first reflective ring away from the first epitaxial layer towards the first epitaxial layer is located in a projection area of a surface of the first reflective ring close to the first epitaxial layer towards the first epitaxial layer.

36. The method of claim 35, wherein the micro-LED chip is formed by: An inclination angle of a sidewall of the first reflective ring ranges from 73° to 85°.

37. The method for forming a micro light-emitting diode chip according to claim 22, characterized in that, A sidewall of the second reflective ring is an inclined surface, and a projection area of the second reflective ring away from the surface of the first epitaxial layer towards the first epitaxial layer is located in a projection area of the second reflective ring close to the surface of the first epitaxial layer towards the first epitaxial layer.

38. The method of claim 37, wherein the micro-LED chip is formed by: An inclination angle of a sidewall of the second reflective ring ranges from 73° to 85°.

39. The method for forming a micro light-emitting diode chip according to claim 22, characterized in that, The first reflective ring has a first spacing dimension between a surface away from the first epitaxial layer and the first epitaxial layer, and the multi-quantum well layer has a second spacing dimension between a surface away from the first epitaxial layer and the first epitaxial layer, the first spacing dimension being greater than the second spacing dimension.

40. The method of claim 39, wherein the micro-LED chip is formed by: The second reflective ring has a third spacing dimension between a surface away from the first epitaxial layer and the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

41. The method for forming a micro light-emitting diode chip according to claim 25, characterized in that, Before forming the conductive layer, the method further comprises: forming a first passivation layer on the first side, the first via sidewall and the second via sidewall; the first passivation layer on the first side covers a part of the surface of the first epitaxial layer on the first side, and the second reflective ring is electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer on the first side also covers the sidewall of the second epitaxial layer, the part of the surface of the second epitaxial layer away from the first epitaxial layer, and the multi-quantum well layer, and the conductive layer is electrically connected to the second epitaxial layer exposed by the first passivation layer.

42. The method of claim 41, wherein the micro-LED chip is formed by: In the process of forming the microlens, the method further comprises: forming a second passivation layer on the first side, the second passivation layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer.

43. The method of claim 42, wherein the micro-LED chip is formed by: The material of the microlens and the second passivation layer is the same.

44. The method of claim 43, wherein the micro-LED chip is formed by: The forming method of the microlens and the second passivation layer comprises: forming a passivation material layer on the first side, the passivation material layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer; and performing a patterned etching treatment on the passivation material layer to form the microlens and the second passivation layer.

45. The method of claim 42, wherein the micro-LED chip is formed by: The material of the microlens and the second passivation layer is different.

46. The method of claim 45, wherein the micro-LED chip is formed by: The forming method of the microlens and the second passivation layer comprises: forming a passivation material layer on the first side, the passivation material layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer; forming a microlens material layer on the passivation material layer; and performing a patterned etching treatment on the passivation material layer and the microlens material layer to form the microlens and the second passivation layer.

47. The method for forming a micro light-emitting diode chip according to claim 21, characterized in that, After forming the multi-quantum well layer and before forming the second epitaxial layer, the method further comprises: forming an electron blocking layer on the first side, the electron blocking layer being located between the multi-quantum well layer and the second epitaxial layer.

48. The method of claim 21, wherein the micro light emitting diode chip is formed by a process comprising: The material of the first epitaxial layer and the second epitaxial layer comprises gallium nitride. ​

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