Silicon carbide metal-oxide-semiconductor field effect transistor and manufacturing method therefor

Abstract

The present application relates to a silicon carbide metal-oxide-semiconductor field effect transistor and a manufacturing method therefor. The silicon carbide metal-oxide-semiconductor field effect transistor comprises: a first epitaxial layer, which has a first conductivity type; a second epitaxial layer, which has a first conductivity type, is located on the first epitaxial layer and has a doping concentration greater than that of the first epitaxial layer, the first conductivity type and the second conductivity type being opposite conductivity types; a well region, which has the second conductivity type and is located in the second epitaxial layer; a doped region, which has the first conductivity type and is located in the well region, the doped region serving as a source region or a drain region; and a gate structure. The present application can more effectively reduce the device Rsp.

Description

Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application No. 2024106514820, filed on May 23, 2024, and entitled "Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor manufacturing, and in particular to a silicon carbide metal oxide semiconductor field effect transistor, and a manufacturing method thereof. BACKGROUND

[0003] The silicon carbide metal oxide semiconductor field effect transistor (SiC MOS) has a wider band gap than Si MOS, so it has a higher breakdown voltage (BV, breakdown voltage) at the same epitaxial layer thickness, and a lower on-resistance at the same BV. With the gradual improvement and progress of SiC device process technology, the characteristic on-resistance Rsp of the product has been continuously reduced, but due to the limitation of process capability, it is difficult to continue to reduce the size when the device size is reduced to a certain extent, and the JFET (junction field effect transistor) region of the device will cause the Rsp to rise. SUMMARY

[0004] Therefore, it is necessary to provide a silicon carbide metal oxide semiconductor field effect transistor with a lower Rsp.

[0005] A silicon carbide metal oxide semiconductor field effect transistor, comprising: a first epitaxial layer having a first conductivity type; a second epitaxial layer having the first conductivity type, located on the first epitaxial layer, and having a doping concentration greater than that of the first epitaxial layer; the first and second conductivity types are opposite conductivity types; a well region having a second conductivity type located in the second epitaxial layer; a doped region having a first conductivity type located in the well region, the doped region serving as a source region or a drain region; a gate structure.

[0006] The above-mentioned silicon carbide metal oxide semiconductor field effect transistor uses a double-layer epitaxial structure as the epitaxial layer of the drift region, and the doping concentration of the second epitaxial layer at the top is higher than that of the first epitaxial layer at the bottom, so as to reduce the Rsp. Moreover, since the doping of the silicon carbide epitaxial layer is more uniform than the silicon carbide layer using ion implantation, the Rsp can be more effectively reduced. The well region is arranged in the second epitaxial layer, which can further reduce the resistance of this region.

[0007] In one embodiment, the doping concentration of the second epitaxial layer is 5E15-7E16 / cm 3 .

[0008] In one of the embodiments, the thickness of the second epitaxial layer is 10% to 50% of the total thickness of the first and second epitaxial layers.

[0009] In one of the embodiments, the thickness of the second epitaxial layer is 1 μm to 6 μm.

[0010] In one of the embodiments, the bottom of the well region is separated from the first epitaxial layer by the second epitaxial layer.

[0011] In one of the embodiments, the thickness of the second epitaxial layer is 0.2 μm to 2 μm greater than the depth of the well region.

[0012] In one of the embodiments, the second epitaxial layer has a concentration distribution with a high central doping concentration and low top and bottom doping concentrations, and the lowest doping concentration in the second epitaxial layer is 40% to 99% of the highest doping concentration.

[0013] In one of the embodiments, the silicon carbide metal oxide semiconductor field effect transistor further comprises a substrate and a buffer layer on the substrate, the first epitaxial layer is on the buffer layer, the buffer layer has the first conductivity type and a doping concentration greater than that of the second epitaxial layer.

[0014] In one of the embodiments, the silicon carbide metal oxide semiconductor field effect transistor further comprises an extraction region in the well region, the extraction region is on the side of the doped region in the same well region away from the gate structure; the extraction region has the second conductivity type and a doping concentration greater than that of the well region.

[0015] In one of the embodiments, the first conductivity type is N type and the second conductivity type is P type.

[0016] It is also necessary to provide a method for manufacturing a silicon carbide metal oxide semiconductor field effect transistor.

[0017] A method for manufacturing a silicon carbide metal oxide semiconductor field effect transistor, comprising: forming a first epitaxial layer by an epitaxial process, the first epitaxial layer having a first conductivity type; forming a second epitaxial layer on the first epitaxial layer by an epitaxial process, the second epitaxial layer having the first conductivity type, the second epitaxial layer having a doping concentration greater than that of the first epitaxial layer; forming a well region in the second epitaxial layer, the well region having a second conductivity type, the first and second conductivity types being opposite conductivity types; forming a gate structure and a doped region, the doped region having the first conductivity type and being in the well region, the doped region serving as a source region or a drain region.

[0018] The manufacturing method of the silicon carbide metal oxide semiconductor field effect transistor uses a double-layer epitaxial structure for the epitaxial layer of the drift region, and the doping concentration of the second epitaxial layer on the top is higher than that of the first epitaxial layer on the bottom, so as to reduce the Rsp. Since the doping of the silicon carbide epitaxial layer is more uniform than that of the silicon carbide layer using ion implantation, the Rsp can be more effectively reduced. The well region is arranged in the second epitaxial layer, and the resistance of this region can be further reduced.

[0019] In one of the embodiments, before the step of forming the first epitaxial layer by the epitaxial process, the method further comprises a step of forming a buffer layer on the substrate, and the first epitaxial layer is formed on the buffer layer; the buffer layer has the first conductivity type, and the doping concentration is greater than that of the second epitaxial layer.

[0020] In one of the embodiments, after the step of forming the well region in the second epitaxial layer, the method further comprises a step of forming a lead-out region in the well region, and the lead-out region is located on the side of the doping region in the same well region away from the gate structure; the lead-out region has the second conductivity type, and the doping concentration is greater than that of the well region. BRIEF DESCRIPTION OF DRAWINGS

[0021] For better describing and illustrating the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0022] FIG. 1 is a structural schematic diagram of a silicon carbide metal oxide semiconductor field effect transistor according to an embodiment of the present application;

[0023] FIG. 2 is a reverse breakdown curve of a silicon carbide metal oxide semiconductor field effect transistor according to an embodiment of the present application and a comparative example;

[0024] FIG. 3 is a forward I-V curve of a silicon carbide metal oxide semiconductor field effect transistor according to an embodiment of the present application and a comparative example; D curve;

[0025] FIG. 4 is a flowchart of a manufacturing method of a silicon carbide metal oxide semiconductor field effect transistor according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] For the purpose of facilitating the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0029] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation will typically result in some implantation in a region between the buried region and a surface over which the implantation was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0032] The semiconductor field terms used herein are the technical terms commonly used by those skilled in the art, for example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P type represents P-type with medium doping concentration, P- type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N type represents N-type with medium doping concentration, N- type represents N-type with light doping concentration.

[0033] An exemplary SiC MOS uses a method of multiple ion implantation to form a JFET to reduce the Rsp of the device while reducing the pitch. However, in order to further reduce the resistance of the P-well, the depth of the P-well needs to be deepened, and therefore high-energy implantation is required, which requires a high-precision implantation device. At the same time, since the implanted impurities in SiC are difficult to diffuse uniformly through a thermal process as impurities in Si, multiple JFET implantations are required, and the number of implantations increases as the P-well is deepened, resulting in an increase in process time and cost. Furthermore, the high peak concentration of the JFET implantation can result in a decrease in BV of the device.

[0034] Another method is to adjust the doping concentration of the epitaxial layer to reduce the Rsp of the device. However, this method can significantly affect the high field distribution during reverse breakdown of the device, resulting in a decrease in BV of the device.

[0035] If two or more epitaxial layers are used, one solution is that the top epitaxial layer has normal epitaxial layer doping concentration and thickness accounts for 70% to 90% of the total thickness of the epitaxial layer, and the bottom epitaxial layer is thickened. The principle is that the MOS reverse voltage withstand electric field distribution of the depletion region is inverted trapezoidal, and at the bottom epitaxial layer, the electric field area is smaller, and the influence on BV is not as great as the top epitaxial layer, so that Rsp is reduced by reducing the voltage withstand of the bottom epitaxial layer and reducing BV. Another solution is that the top epitaxial layer accounts for 20% to 40% of the total thickness of the epitaxial layer, and the bottom epitaxial layer is a normal or slightly thickened EPI. The principle is to compensate for the loss of BV after the bottom epitaxial layer is thickened by the high value of the electric field of the depletion layer near the P-well-N-type epitaxial layer, but as the demand for R ON (On-resistance) increases, it is more difficult to compensate for BV, and finally BV still needs to be sacrificed to ensure R ON .

[0036] The application proposes a silicon carbide metal oxide semiconductor field effect transistor with a double-layer epitaxial drift region, which can further reduce Rsp without sacrificing BV. The thickness of the top layer of the double-layer epitaxial layer is thin and the concentration is high, and the bottom layer can use the traditional drift region epitaxial layer concentration.

[0037] FIG. 1 is a structural schematic diagram of a silicon carbide metal oxide semiconductor field effect transistor in an embodiment of the application, which includes a first epitaxial layer 132, a second epitaxial layer 134, a well region 142, a doped region 144, and a gate structure 150. The first epitaxial layer 132 and the second epitaxial layer 134 have a first conductivity type. The second epitaxial layer 134 is located on the first epitaxial layer 132, and the doping concentration of the second epitaxial layer 134 is greater than that of the first epitaxial layer 132. The well region 142 has a second conductivity type and is located in the second epitaxial layer 134. The doped region 144 has a first conductivity type and is located in the well region 142, and the doped region 144 serves as a source region or a drain region. In the embodiment shown in FIG. 1, the gate structure 150 is a planar gate structure, which includes a gate dielectric layer 152 and a gate electrode layer 154 on the gate dielectric layer 152. The gate structure 150 is located above a channel region between two adjacent doped regions 144. In the embodiment shown in FIG. 1, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0038] The above-mentioned silicon carbide metal oxide semiconductor field effect tube adopts a double-layer epitaxial structure for the epitaxial layer of the drift region, and the doping concentration of the second epitaxial layer 134 at the top is higher than that of the first epitaxial layer 132 at the bottom, so as to reduce Rsp. As the proportion of JFET resistance in SiC MOS gradually increases with the decrease of pitch, in the traditional scheme of forming JFET through multiple implantation, the JFET ion implantation is limited to the uniform gradient diffusion of the implanted impurity ions through thermal engineering in the SiC MOS process, and only the N-type concentration gradient can be adjusted as uniform as possible through multiple implantation. The doping of the silicon carbide double-layer epitaxial layer in the present application is more uniform than that of the silicon carbide layer using ion implantation, and therefore, compared with the traditional JFET ion implantation scheme, Rsp can be reduced more effectively. On the other hand, for the traditional JFET ion implantation scheme, when the implantation depth exceeds the peak implantation depth of the P-well, the aluminum ion implantation scattering part will be cut off to form a bottom Floating P-region, which will obviously affect the reverse voltage of the device. However, by increasing the doping concentration of the second epitaxial layer 134, the doping is very uniform, and such phenomenon is avoided. In addition, the well region 142 is arranged in the second epitaxial layer 134, which can further reduce the resistance of the JFET region. The surface electric field strength of the device can be adjusted by reducing the size of the JFET or increasing the doping concentration of the well region 142 at the center, and will not obviously affect the on-resistance.

[0039] In an embodiment of the present application, the doping concentration of the second epitaxial layer 134 is 5E15-7E16 / cm 3 .

[0040] In an embodiment of the present application, the second epitaxial layer 134 adopts a gradual concentration distribution with high central doping concentration and low top and bottom doping concentrations. Further, the doping concentration of the second epitaxial layer 134 at the lowest concentration position (for example, the top and the bottom) is 40% to 99% of the doping concentration at the highest concentration position (for example, the center). In an embodiment of the present application, the doping concentration of the second epitaxial layer 134 at the center ranges from 5E15 to 7E16 / cm 3 .

[0041] In an embodiment of the present application, the thickness d2 of the second epitaxial layer 134 accounts for 10% to 50% of the total thickness (d1+d2) of the first epitaxial layer 132 (thickness d1) and the second epitaxial layer 134. In an embodiment of the present application, the thickness of the second epitaxial layer 134 is 1 micrometer to 6 micrometers.

[0042] In an embodiment of the present application, the bottom of the well region 142 is separated from the first epitaxial layer 132 by the second epitaxial layer 134, and the thickness d2 of the second epitaxial layer 134 is greater than the depth D of the well region 142. Further, the range in which the thickness d2 is greater than the depth D is 0.2 micrometers to 2 micrometers.

[0043] In one embodiment of the present application, the SiC MOSFET further comprises a substrate 110 and a buffer layer 120 on the substrate 110, and the first epitaxial layer 132 is on the buffer layer 120. The buffer layer 120 has the first conductivity type and a doping concentration greater than that of the second epitaxial layer 134. In one embodiment of the present application, the doping concentration of the buffer layer 120 is greater than 1E17 / cm3. 3 In one embodiment of the present application, the thickness of the buffer layer 120 is less than 2 microns.

[0044] In one embodiment of the present application, the SiC MOSFET further comprises a lead-out region 146 in the well region 142, i.e., a doping region 144 and a lead-out region 146 are formed in one well region 142, and the lead-out region 146 is on the side of the doping region 144 (in the same well region 142) away from the gate structure 150. The lead-out region 146 has the second conductivity type and a doping concentration greater than that of the well region 142. In the embodiment shown in Fig. 1, the lead-out region 146 is a P+ region and the doping region 144 is an N+ region.

[0045] In one embodiment of the present application, the gate dielectric layer 152 can comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 152 can comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanate (BSTs) and lead zirconium titanate (PZTs).

[0046] In one embodiment of the present application, the gate layer 154 is made of polysilicon material, and in other embodiments, metals, metal nitrides, metal silicides or similar compounds can also be used as the gate material.

[0047] Fig. 2 is a reverse breakdown curve of the SiC MOSFET of one embodiment of the present application and comparative examples. The vertical axis is the drain current in amperes and the horizontal axis is the drain voltage in volts. Comparative example 1 is a SiC MOSFET with a JFET formed by multiple ion implantations, and comparative example 2 is a SiC MOSFET with a double epitaxial layer with a heavily doped bottom epitaxial layer. It can be seen that the BV of the embodiment of the present application is higher than that of comparative example 2. Fig. 3 is a forward I-V curve of the SiC MOSFET of one embodiment of the present application and comparative examples. The vertical axis is the drain current in amperes and the horizontal axis is the drain voltage in volts. It can be seen that the on-state resistance of the embodiment of the present application is lower than that of comparative example 2. Dthe drain current) curve (the curve of the embodiment of the present application and the curve of Comparative Example 2 are mostly coincident in FIG. 3). The vertical coordinate is the drain current, in units of 0.1 mA, and the horizontal coordinate is the drain voltage, in units of volts. It can be seen that the Rsp (Rsp = V D / I D ) of the embodiment of the present application is lower than that of Comparative Example 1. In summary, the embodiment of the present application can maintain a high BV on the basis of achieving a low Rsp.

[0048] The present application also provides a manufacturing method of a silicon carbide metal-oxide-semiconductor field-effect transistor, for manufacturing the silicon carbide metal-oxide-semiconductor field-effect transistor of any one of the above embodiments. FIG. 4 is a flow chart of the manufacturing method of the silicon carbide metal-oxide-semiconductor field-effect transistor in an embodiment of the present application, including the following steps:

[0049] S410, forming a first epitaxial layer by an epitaxial process.

[0050] The first epitaxial layer 132 has a first conductivity type. In an embodiment of the present application, the first conductivity type is N type, and the second conductivity type is P type; in other embodiments, the first conductivity type can also be P type, and the second conductivity type can be N type.

[0051] In an embodiment of the present application, before step S410, the method further includes forming a buffer layer 120 on the substrate 110, and then forming the first epitaxial layer 132 on the buffer layer 120 by step S410.

[0052] In an embodiment of the present application, the buffer layer 120 has the first conductivity type, and the doping concentration is greater than the doping concentration of the second epitaxial layer 134. In an embodiment of the present application, the doping concentration of the buffer layer 120 is greater than 1E17 / cm 3 . In an embodiment of the present application, the thickness of the buffer layer 120 is less than 2 microns.

[0053] S420, forming a second epitaxial layer on the first epitaxial layer by an epitaxial process.

[0054] The second epitaxial layer 134 has the first conductivity type, and the doping concentration of the second epitaxial layer 134 is greater than the doping concentration of the first epitaxial layer 132.

[0055] S430, forming a well region in the second epitaxial layer.

[0056] The well region 142 has a second conductivity type. In an embodiment of the present application, the well region 142 can be formed by patterning (for example, photolithography) and ion implantation process to implant ions of the second conductivity type into the second epitaxial layer 134.

[0057] S440, forming a gate structure and a doped region.

[0058] In one embodiment of the present application, the gate dielectric layer 152 and the gate layer 154 can be formed by first forming an oxide layer on the wafer surface by thermal oxidation, then depositing polysilicon on the oxide layer, and patterning (e.g., photolithography and etching) the polysilicon layer and the oxide layer. The well region 142 can also be formed by implanting ions of the first conductivity type into the well region 142 by an ion implantation process to form the doped region 144.

[0059] In one embodiment of the present application, the step of implanting ions of the second conductivity type into the well region 142 by an ion implantation process to form the lead-out region 146 is further included. The lead-out region 146 is located on the side of the doped region 144 away from the gate structure 150. The lead-out region 146 has the second conductivity type and a doping concentration greater than that of the well region 142.

[0060] In the method of manufacturing the silicon carbide metal oxide semiconductor field effect transistor, the epitaxial layer as the drift region adopts a double-layer epitaxial structure, the doping concentration of the second epitaxial layer 134 on the top is higher than that of the first epitaxial layer 132 on the bottom, so as to reduce Rsp. Since the doping of the silicon carbide epitaxial layer is more uniform than that of the silicon carbide layer by ion implantation, Rsp can be more effectively reduced. The well region 142 is arranged in the second epitaxial layer, so as to further reduce the resistance of the region.

[0061] The method of manufacturing the silicon carbide metal oxide semiconductor field effect transistor of the present application is based on the same inventive concept as the silicon carbide metal oxide semiconductor field effect transistor, and the contents not specifically described in the method of manufacturing the silicon carbide metal oxide semiconductor field effect transistor can be referred to the foregoing description of the silicon carbide metal oxide semiconductor field effect transistor.

[0062] It should be understood that, although each step in the flowchart of the present application is shown in sequence according to the direction of the arrow, these steps are not necessarily executed in sequence according to the direction of the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0063] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. The illustrative description of the above terms in the present specification does not necessarily refer to the same embodiment or example.

[0064] Any combination of the technical features described above can be made. For the sake of brevity, not all possible combinations are described, however, it should be understood that the scope of the specification includes all possible combinations.

[0065] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that, for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A silicon carbide metal oxide semiconductor field effect transistor, comprising: a first epitaxial layer having a first conductivity type; a second epitaxial layer having the first conductivity type on the first epitaxial layer and having a doping concentration greater than a doping concentration of the first epitaxial layer; the first and second conductivity types being opposite conductivity types; a well region having a second conductivity type in the second epitaxial layer; a doped region having the first conductivity type in the well region, the doped region acting as a source region or a drain region; a gate structure.

2. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 1, wherein, The second epitaxial layer has a doping concentration of 5E15 to 7E16 / cm 3 .

3. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 1, wherein, a thickness of the second epitaxial layer is 10% to 50% of a total thickness of the first and second epitaxial layers.

4. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 1, wherein, a thickness of the second epitaxial layer is 1 μm to 6 μm.

5. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 1, wherein, a bottom of the well region is separated from the first epitaxial layer by the second epitaxial layer.

6. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 5, wherein, a thickness of the second epitaxial layer is greater than a depth of the well region by 0.2 μm to 2 μm.

7. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 1, wherein, the second epitaxial layer has a concentration profile with a high central doping concentration and low top and bottom doping concentrations, and a doping concentration at a lowest concentration in the second epitaxial layer is 40% to 99% of a doping concentration at a highest concentration.

8. The silicon carbide metal oxide semiconductor field effect transistor of claim 1, further comprising a substrate and a buffer layer on the substrate, the first epitaxial layer being on the buffer layer, the buffer layer having the first conductivity type and a doping concentration greater than a doping concentration of the second epitaxial layer.

9. The silicon carbide metal oxide semiconductor field effect transistor of claim 1, further comprising an extraction region in the well region, the extraction region being on a side of the doped region in the same well region away from the gate structure; the extraction region having the second conductivity type and a doping concentration greater than a doping concentration of the well region.

10. The silicon carbide metal-oxide-semiconductor field-effect transistor of Claim 1, wherein, the first conductivity type is N-type and the second conductivity type is P-type.

11. A method of manufacturing a silicon carbide metal oxide semiconductor field effect transistor, comprising: forming a first epitaxial layer having a first conductivity type by an epitaxial process; forming a second epitaxial layer having the first conductivity type on the first epitaxial layer by an epitaxial process, the second epitaxial layer having a doping concentration greater than a doping concentration of the first epitaxial layer; forming a well region having a second conductivity type in the second epitaxial layer, the first and second conductivity types being opposite conductivity types; forming a gate structure and a doped region having the first conductivity type in the well region, the doped region acting as a source region or a drain region.

12. The manufacturing method of claim 11, further comprising: forming a buffer layer on a substrate before the forming the first epitaxial layer by an epitaxial process, wherein the first epitaxial layer is formed on the buffer layer; the buffer layer having the first conductivity type and a doping concentration greater than a doping concentration of the second epitaxial layer.

13. The manufacturing method of claim 11, further comprising: after the forming the well region in the second epitaxial layer, forming an extraction region in the well region, the extraction region being on a side of the doped region in the same well region away from the gate structure; the extraction region having the second conductivity type and a doping concentration greater than a doping concentration of the well region.

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