Laterally diffused metal oxide semiconductor device and preparation method therefor

Abstract

A laterally diffused metal oxide semiconductor device and a preparation method therefor. The preparation method comprises: providing a substrate (10), which comprises a first drift region (101) of a first conductivity type and a body region of a second conductivity type (102); forming a first gate structure (131) and a first blocking structure, wherein the first gate structure (131) is formed above part of the body region (102) and part of the first drift region (101), the body region (102) further comprises a first region not covered by the first gate structure (131), the first drift region (101) further comprises a second region not covered by the first gate structure (131), and the first blocking structure is formed above the second region of the first drift region (101); and executing an ion implantation process, wherein some ions are implanted into the first region of the body region (102) to form a body-region contact region (103) of the second conductivity type, and some ions pass through the first blocking structure, and are then implanted into the second region of the first drift region (101), so as to form a first doped region (104) of the second conductivity type.

Description

Laterally diffused metal oxide semiconductor device and method of manufacturing the same

[0001] Related Applications

[0002] This application claims priority to the Chinese patent application No. 202410627191.8, filed on May 21, 2024, entitled "Laterally diffused metal oxide semiconductor device and method of manufacturing the same", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of semiconductor technology, in particular to a laterally diffused metal oxide semiconductor device and a method of manufacturing the same. BACKGROUND

[0004] BCD (BJT-CMOS-DMOS) process technology is an important power integrated circuit manufacturing technology, which can integrate three different manufacturing technologies on the same chip. Specifically, it integrates bipolar transistors (BJT) for high-precision processing of analog signals, complementary metal oxide semiconductor transistors (CMOS) for designing digital control circuits, double-diffused metal oxide semiconductor transistors (DMOS) for developing power and high-voltage switching devices, and various electronic components such as resistors, capacitors, and diodes on the same chip. Therefore, it combines the high transconductance and strong load driving capability of BJT with the high integration and low power consumption of CMOS, and can realize the combination of high-speed devices and low-power devices, as well as high-voltage devices and low-voltage devices. Since the laterally diffused metal oxide semiconductor (LDMOS) device in DMOS is more compatible with CMOS technology, high-voltage LDMOS devices are often used in high-voltage power integrated circuits to meet the requirements of high-voltage resistance and power control.

[0005] The characteristics of high voltage and large current of power integrated circuits often require high-voltage devices to have high breakdown voltage (BV) and low specific on-resistance (Ron,sp). How to improve the breakdown voltage of LDMOS devices while maintaining a low specific on-resistance has always been a focus of research in the industry. SUMMARY

[0006] Therefore, embodiments of the present application provide a lateral diffusion metal oxide semiconductor device and a preparation method thereof to solve at least one problem in the background art.

[0007] In a first aspect, embodiments of the present application provide a preparation method of a lateral diffusion metal oxide semiconductor device. The method comprises: providing a substrate, the substrate comprising a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first barrier structure, wherein the first gate structure is formed above part of the body region and part of the first drift region, the body region further comprises a first region not covered by the first gate structure, the first drift region further comprises a second region not covered by the first gate structure, and the first barrier structure is formed above the second region of the first drift region; and performing an ion implantation process, part of the ion implantation being performed in the first region of the body region to form a body region contact region of the second conductivity type, and part of the ion implantation being performed in the second region of the first drift region through the first barrier structure to form a first doped region of the second conductivity type.

[0008] In combination with the first aspect of the present application, in an optional implementation, the first barrier structure comprises a first field plate structure, and the performing of the ion implantation process comprises: forming a first mask layer, the first mask layer exposing a surface of the first field plate structure and a surface of the first region; and performing an ion implantation process with the first mask layer as a mask to form the first doped region and the body region contact region.

[0009] In combination with the first aspect of the present application, in an optional implementation, the method further comprises forming a first field plate structure above the first drift region; the first barrier structure comprises a spacer structure, the spacer structure being located between the first field plate structure and the first gate structure and extending from a sidewall of the first field plate structure to a sidewall of the first gate structure, and the performing of the ion implantation process comprises: forming a second mask layer, the second mask layer exposing a surface of the spacer structure and a surface of the first region; and performing an ion implantation process with the second mask layer as a mask to form the first doped region and the body region contact region.

[0010] In combination with the first aspect of the present application, in an optional implementation, a doping concentration of the first doped region is less than a doping concentration of the first drift region.

[0011] In combination with the first aspect of the present application, in an optional implementation, the substrate further comprises a second drift region, the second drift region and the first drift region are respectively located on two sides of the body region; the method further comprises: forming a second gate structure and a second barrier structure, wherein the second gate structure is formed above part of the body region and part of the second drift region, the second drift region further comprises a third region which is not covered by the second gate structure, the second barrier structure is formed above the third region of the second drift region, and the second barrier structure is located on a side of the second gate structure which is away from the first gate structure; in the process of performing the ion implantation process, part of the ions pass through the second barrier structure and are implanted into the third region of the second drift region to form a second doped region of the second conductivity type.

[0012] In the second aspect, the embodiments of the present application provide a lateral diffusion metal oxide semiconductor device, which is manufactured by using the manufacturing method of the lateral diffusion metal oxide semiconductor device according to any one of the first aspect.

[0013] In the third aspect, the embodiments of the present application provide another lateral diffusion metal oxide semiconductor device, which comprises: a substrate; a first drift region of a first conductivity type and a body region of a second conductivity type, which are respectively located in the substrate; a first gate structure which is located above part of the body region and part of the first drift region; the body region further comprises a first region which is not covered by the first gate structure, and the first drift region further comprises a second region which is not covered by the first gate structure; a first barrier structure which is located above the second region of the first drift region; a body region contact region of the second conductivity type which is located in the first region of the body region; and a first doped region of the second conductivity type which is located in the second region of the first drift region, and the doping concentration of the first doped region is less than the doping concentration of the first drift region.

[0014] In combination with the third aspect of the present application, in an optional implementation, the first barrier structure comprises a first field plate structure, the first doped region is located in the second region below the first field plate structure, and the center of the vertical projection of the first doped region on the substrate thickness direction coincides with the center of the vertical projection of the first field plate structure on the substrate thickness direction.

[0015] In an optional embodiment, in combination with the third aspect of the present application, the lateral diffusion metal oxide semiconductor device further comprises a first field plate structure above the first drift region; the first blocking structure comprises a spacer structure between the first field plate structure and the first gate structure and extending from a sidewall of the first field plate structure to a sidewall of the first gate structure, the first doped region is in the second region below the spacer structure, and a center of a vertical projection of the first doped region on the substrate thickness direction coincides with a center of a vertical projection of the spacer structure on the substrate thickness direction.

[0016] In an optional embodiment, in combination with the third aspect of the present application, the substrate further comprises a second drift region on two sides of the body region respectively; the lateral diffusion metal oxide semiconductor device further comprises: a second gate structure above part of the body region and part of the second drift region, the second drift region further comprises a third region not covered by the second gate structure; a second blocking structure above the third region of the second drift region, the second blocking structure is on a side of the second gate structure away from the first gate structure; a second doped region of a second conductivity type in the third region of the second drift region; a doping concentration of the second doped region is less than a doping concentration of the second drift region, the second doped region and the contact region of the body region are formed in one ion implantation process.

[0017] The lateral diffusion metal oxide semiconductor device and the preparation method thereof provided by the embodiments of the present application include: providing a substrate, the substrate including a first drift region of a first conductive type and a body region of a second conductive type; forming a first gate structure and a first blocking structure, wherein the first gate structure is formed above part of the body region and part of the first drift region, the body region further includes a first region not covered by the first gate structure, the first drift region further includes a second region not covered by the first gate structure, and the first blocking structure is formed above the second region of the first drift region; and performing an ion implantation process, part of the ions being implanted into the first region of the body region to form a body region contact region of the second conductive type, and part of the ions being implanted into the second region of the first drift region through the first blocking structure to form a first doped region of the second conductive type. In this way, by forming the first doped region of the second conductive type in the first drift region of the first conductive type, the electric field of the first drift region can be effectively adjusted, so that the breakdown voltage of the device can be significantly improved, and the first doped region is formed in the second region below the first blocking structure by implanting part of the ions into the second region of the first drift region through the first blocking structure to form the first doped region, so that the first doped region and the body region contact region can be formed in one step of ion implantation process, the process is simplified, the mask is saved, and the cost is reduced. In addition, the first doped region is formed in the second region below the first blocking structure, so that the device area can be saved, and the integration degree can be improved.

[0018] Additional aspects and advantages of the present application will be made apparent by the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the principles of the present application, and do not limit the present application in any manner. In the drawings:

[0020] FIG. 1 is a schematic diagram of a cross-sectional structure of a lateral diffusion metal oxide semiconductor device in the related art;

[0021] FIG. 2 is a schematic diagram of a flow of a preparation method of a lateral diffusion metal oxide semiconductor device provided by the embodiments of the present application;

[0022] FIG. 3 is a schematic diagram of a cross-sectional structure of a substrate provided in a preparation process of a lateral diffusion metal oxide semiconductor device provided by the embodiments of the present application;

[0023] FIG. 4 is a schematic diagram of a cross-sectional structure of a lateral diffusion metal oxide semiconductor device provided by the embodiments of the present application in a preparation process of forming a first gate dielectric layer and a first field oxide layer;

[0024] FIG. 5 is a cross-sectional view of forming a conductive material layer in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0025] FIG. 6 is a cross-sectional view of forming a first gate structure and a first field plate structure in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0026] FIG. 7 is a cross-sectional view of forming a spacer material layer in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0027] FIG. 8 is a cross-sectional view of forming a spacer structure, a second spacer structure and a third spacer structure in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0028] FIG. 9 is a cross-sectional view of forming a first mask layer in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0029] FIG. 10 is a cross-sectional view of forming a first doped region and a body region contact region in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0030] FIG. 11 is a cross-sectional view of forming a second mask layer in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0031] FIG. 12 is a cross-sectional view of forming a first doped region and a body region contact region in the process of manufacturing another lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0032] FIG. 13 is a cross-sectional view of forming a first drain region, a first source region, a first drain, a first field plate contact, a first gate contact, a first source and a body region contact in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0033] FIG. 14 is a cross-sectional view of forming a first drain region, a first source region, a first drain, a first field plate contact, a first gate contact, a first source and a body region contact in the process of manufacturing another lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0034] FIG. 15 is a cross-sectional view of forming a second gate structure and a second barrier structure in the process of manufacturing the lateral diffusion metal oxide semiconductor device according to an embodiment of the present application;

[0035] FIG. 16 is a simulation diagram of the electric field intensity distribution of the lateral diffusion metal oxide semiconductor device according to the related art;

[0036] FIG. 17 is a simulation diagram of the electric field intensity distribution of a lateral diffusion metal oxide semiconductor device prepared in an embodiment of the present application.

[0037] Legend: 10, substrate; 101, first drift region; 102, body region; 100, first region; 200, second region; 11, first gate dielectric layer; 12, first field oxide layer; 13, conductive material layer; 131, first gate structure; 132, first field plate structure; 14, spacer material layer; 141, spacer structure; 1411, first portion; 1412, second portion; 142, second spacer structure; 143, third spacer structure; 161, first mask layer; 162, second mask layer; 103, body region contact region; 104, first doped region; 105, first drain region; 106, first source region; 171, first drain; 172, first field plate contact; 173, first gate contact; 174, first source; 175, body region contact; 201, second drift region; 231, second gate structure; 232, second field plate structure; 241, fourth spacer structure; 242, fifth spacer structure; 243, sixth spacer structure; 204, second doped region; 205, second drain region; 300, third region; 1, first unit; 2, second unit; 301, first side wall; 302, second side wall; 303, third side wall; 304, fourth side wall. DETAILED DESCRIPTION

[0038] Example embodiments of the present application will be described herein below with reference to the accompanying drawings. While example embodiments of the present application are illustrated, it will be understood that the present application can be carried out in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0039] In the following description, numerous specific details are given to provide a thorough understanding of the present application. However, it will be apparent that the present application can be practiced without one or more of these specific details. In other instances, well-known structures are not shown in detail in order not to obscure the present application. That is, well-known functions or constructions are not described in detail because they would be apparent to those skilled in the art.

[0040] In the drawings, the size of layers, regions, elements and the relative sizes of the same can be exaggerated for clarity. Like reference numbers in different drawings can indicate the same or similar elements.

[0041] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0042] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can also have other implementation manners.

[0045] FIG. 1 is a schematic structural cross-sectional view of a lateral diffusion metal oxide semiconductor device in the related art. As shown in FIG. 1, in the LDMOS device in the related art, a substrate 10 and a first drift region 101 and a body region 102 located in the substrate 10 are included, a first gate structure 131 is located above part of the body region 102 and part of the first drift region 101, a first side wall 301 and a second side wall 302 cover the side walls of the first gate structure 131 respectively, a first field plate structure 132 is located above the first drift region 101, a third side wall 303 and a fourth side wall 304 are located on the side walls covering the first field plate structure 132 respectively, a first drain region 105 is located in the first drift region 101 on the side of the first field plate structure 132 away from the first gate structure 131, a first source region 106 is located in the body region 102, the first drain region 105 and the first source region 106 are located on the two sides of the first gate structure 131 respectively, and a body contact region 103 is located in the body region 102 on the side of the first source region 106 away from the first gate structure 131. In addition, a first drain 171, a first field plate contact 172, a first gate contact 173, a first source 174, and a body contact 175 are conductively connected with the first drain region 105, the first field plate structure 132, the first gate structure 131, the first source region 106, and the body contact region 103 respectively, so that the first drain region 105, the first field plate structure 132, the first gate structure 131, the first source region 106, and the body contact region 103 can be connected to an external control circuit respectively to apply a control voltage to different components. In the related art, by arranging the first field plate structure 132 above the first drift region 101, the surface electric field of the first drift region 101 can be adjusted by the first field plate structure 132 to improve the withstand voltage level of the device. In order to effectively improve the breakdown voltage of the device, it is usually necessary to increase the extension length of the first field plate structure 132 in the horizontal direction, which on the one hand leads to a large lateral size of the device, thereby reducing the integration density of the chip, and on the other hand, while improving the withstand voltage of the device, the on-resistance also increases linearly, and the overall performance of the device is difficult to guarantee.

[0046] Based on this, the application embodiments provide a preparation method of a lateral diffusion metal oxide semiconductor device. FIG. 2 is a flowchart of the preparation method of the metal oxide semiconductor device provided by the application embodiments; as shown in FIG. 2, the method includes:

[0047] Step S101, providing a substrate, the substrate including a first drift region of a first conductive type and a body region of a second conductive type;

[0048] In step S102, a first gate structure and a first barrier structure are formed, wherein the first gate structure is formed above a part of the body region and a part of the first drift region, the body region further comprises a first region not covered by the first gate structure, the first drift region further comprises a second region not covered by the first gate structure, and the first barrier structure is formed above the second region of the first drift region.

[0049] In step S103, an ion implantation process is performed, part of the ions are implanted into the first region of the body region to form a body region contact region of the second conductive type, and part of the ions are implanted into the second region of the first drift region through the first barrier structure to form a first doped region of the second conductive type.

[0050] It can be understood that, by the above method, by forming the first doped region of the second conductive type in the first drift region of the first conductive type, the electric field of the first drift region can be effectively adjusted, so that the breakdown voltage of the device can be significantly improved, and part of the ions are implanted into the second region of the first drift region through the first barrier structure to form the first doped region, so that the first doped region and the body region contact region can be formed in one step of ion implantation process, the process is simplified, the mask is saved, and the cost is reduced. In addition, the first doped region is formed in the second region below the first barrier structure, which can also save the device area and improve the integration.

[0051] It should also be understood that, although each step in the above flowchart is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Moreover, at least part of the steps in the above flowchart can include multiple steps or multiple stages, which are not necessarily executed at the same time or in sequence.

[0052] Next, the metal oxide semiconductor device preparation method provided by the embodiment of the present application and its beneficial effects will be further described in detail in combination with FIGS. 3 to 15.

[0053] First, please refer to FIG. 3, step S101 is performed, and a substrate 10 is provided, the substrate 10 comprising a first drift region 101 of a first conductive type and a body region 102 of a second conductive type.

[0054] Exemplarily, the substrate 10 can include a semiconductor substrate, and a material of the substrate 10 can be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon germanium, or silicon carbide, etc. In an actual manufacturing process, an ion implantation process can be used to implant impurities of different conductive types in the substrate 10 to form the first drift region 101 and the body region 102. For example, impurities of a first conductive type can be implanted in the substrate 10 to form the first drift region 101 of the first conductive type, and impurities of a second conductive type can be implanted in the substrate 10 to form the body region 102 of the second conductive type, where the second conductive type is different from the first conductive type. In the case where the first conductive type is N-type or P-type, the second conductive type is P-type or N-type, respectively. For example, when the lateral diffusion metal oxide semiconductor device is an N-type LDMOS device, the first conductive type is N-type, and the second conductive type is P-type. When the lateral diffusion metal oxide semiconductor device is a P-type LDMOS device, the first conductive type is P-type, and the second conductive type is N-type.

[0055] It should be noted that the first drift region 101 and the body region 102 are adjacent to each other in FIG. 3, which is only an example. In some other embodiments of the present application, the body region 102 can be located in the first drift region 101, or the first drift region 101 can be located in the body region 102.

[0056] Next, referring to FIGS. 4 to 8, step S102 is performed to form the first gate structure 131 and the first blocking structure, where the first gate structure 131 is formed above part of the body region 102 and part of the first drift region 101, the body region 102 further includes a first region 100 not covered by the first gate structure 131, the first drift region 101 further includes a second region 200 not covered by the first gate structure 131, and the first blocking structure is formed above the second region 200 of the first drift region 101.

[0057] In some embodiments, performing step S102 can include the following steps:

[0058] Step S1021: Referring to FIG. 4, a first gate dielectric layer 11 and a first field oxide layer 12 are sequentially formed on a surface of the substrate 10, and the first field oxide layer 12 is located above the second region 200;

[0059] Step S1022: Referring to FIG. 5, a conductive material layer 13 is formed to cover the first gate dielectric layer 11 and the first field oxide layer 12;

[0060] Step S1023: Referring to FIG. 6, part of the conductive material layer 13 located above the first gate dielectric layer 11 and the first field oxide layer 12 is etched to form the first gate structure 131 and a first field plate structure 132 located above the second region 200.

[0061] Exemplarily, the first gate dielectric layer 11 can be formed by at least one of a thermal oxidation process, a physical vapor deposition, a chemical vapor deposition or an atomic layer deposition process. For the first field oxide layer 12, a first field oxide material layer (not shown in the figure) can be first formed by at least one of a physical vapor deposition, a chemical vapor deposition or an atomic layer deposition process, and then part of the first field oxide material layer is etched and removed, and the remaining first field oxide material layer and the first gate dielectric layer 11 located below the remaining first field oxide material layer jointly constitute the first field oxide layer 12 as shown in FIG. 4. In some other embodiments of the present application, the case where the first gate dielectric layer 11 and the first field oxide layer 12 are formed in one step is not excluded, for example, a dielectric layer (not shown in the figure) is first formed, and then part of the dielectric layer is etched and removed to simultaneously form the first gate dielectric layer 11 and the first field oxide layer 12, wherein the material of the dielectric layer may, for example, include an oxide. The conductive material layer 13 can be formed by a process such as sputtering and / or electroplating, wherein the material of the conductive material layer 13 may, for example, include at least one of a metal, doped polysilicon or any conductive material or semiconductor material. Etching the conductive material layer 13 can be completed by a dry etching process, for example, a plasma etching process.

[0062] The first field plate structure 132 in the embodiments of the present application can constitute a first blocking structure. The first field plate structure 132 can function as the first blocking structure on the one hand, and on the other hand, can also function as a field plate of the device, playing a role in voltage division, thereby further improving the withstand voltage level of the device. In the embodiments of the present application, the first gate structure 131 and the first field plate structure 132 are formed in one step, making the process relatively simple. In some other embodiments of the present application, the case where the first gate structure 131 and the first field plate structure 132 are respectively formed in different process steps is also not excluded.

[0063] In some embodiments, the method for manufacturing a lateral diffusion metal oxide semiconductor device can further include the following steps:

[0064] Step S1024: Please refer to FIG. 7, a spacer material layer 14 is formed to cover the first gate dielectric layer 11, the first field oxide layer 12, the first field plate structure 132 and the first gate structure 131 in a conformal manner;

[0065] Step S1025: Referring to FIG. 8, part of the spacer material layer 14 is removed to form a spacer structure 141 (may also be regarded as a first spacer structure) between the first gate structure 131 and the first field plate structure 132, a second spacer structure 142 and a third spacer structure 143, wherein the spacer structure 141 is between the first field plate structure 132 and the first gate structure 131 and extends from the sidewall of the first field plate structure 132 to the sidewall of the first gate structure 131, the second spacer structure 142 and the third spacer structure 143 cover the other sidewall of the first field plate structure 132 and the other sidewall of the first gate structure 131 respectively.

[0066] Exemplarily, at least one of physical vapor deposition, chemical vapor deposition or atomic layer deposition process can be adopted to form the spacer material layer 14, wherein the material of the spacer material layer 14 may, for example, include at least one of oxide, nitride or oxynitride. The removal of part of the spacer material layer 14 can adopt processes such as dry etching and / or wet etching.

[0067] In the embodiments of the present application, the spacer structure 141 can constitute a first blocking structure. It can be understood that, in the device, referring to FIG. 8, the spacer structure 141 can be divided into a first part 1411 located in the dashed box and a second part 1412 located outside the dashed box, wherein the first part 1411 and the third spacer structure 143 can serve as the sidewall of the first gate structure 131 and together with the first gate structure 131 and the first gate dielectric layer 11 constitute a complete gate electrode, which plays a role of gate electrode in the device, and the second part 1412 and the second spacer structure 142 can serve as the sidewall of the first field plate structure 132 and together with the first field plate structure 132 and the first field oxide layer 12 constitute a complete field plate, which plays a role of field plate in the device.

[0068] In the embodiments of the present application, the spacer structure 141, the second spacer structure 142 and the third spacer structure 143 are formed in one step, which makes the process simpler. In some other embodiments of the present application, it is also not excluded that the spacer structure 141, the second spacer structure 142 and the third spacer structure 143 are formed by a multi-step process, and the formation sequence of the spacer structure 141, the second spacer structure 142 and the third spacer structure 143 can not be limited, and the specific preparation process can adopt processes well known to those skilled in the art, which will not be described here.

[0069] In addition, the spacer material layer 14 formed is exemplarily shown as including one layer structure in FIG. 7, and in some other embodiments of the present application, the spacer material layer 14 can include two or more layer structures, for example, from bottom to top, including an oxide layer and a nitride layer in sequence, or from bottom to top, including an oxide layer, a nitride layer and an oxide layer in sequence.

[0070] Finally, referring to FIGS. 9-12, performing ion implantation process to implant ions into the first region 100 of the body region 102 to form a body contact region 103 of the second conductivity type, and implant ions into the second region 200 of the first drift region 101 through the first blocking structure to form a first doped region 104 of the second conductivity type.

[0071] In the LDMOS device, the body contact region 103 is usually a heavily doped region to connect the body region to the external circuit with a low contact resistance, so in the ion implantation process to form the body contact region 103, the implantation dose of the ions is relatively large, and the ion implantation concentration can be greater than or equal to 10 15 ions / cm 2 However, the first doped region 104 in the embodiments of the present application usually needs a lower doping concentration to effectively improve the withstand voltage of the device, so the first doped region 104 and the body contact region 103 cannot be formed in one step of ion implantation process, that is, to form the first doped region 104 to improve the withstand voltage of the device, an additional step of ion implantation process is needed, and an additional mask is needed to form the first doped region 104, which makes the process complex and the cost high. In the embodiments of the present application, by forming the first blocking structure, the ion concentration actually implanted into the second region 200 through the first blocking structure is lower than the ion concentration implanted into the first region 100, and the ion concentration implanted into the second region 200 through the first blocking structure is, for example, 10 11 ions / cm 2 -10 14 ions / cm 2 , so that the first doped region 104 and the body contact region 103 can be formed in one step of ion implantation process, the process is simplified, the mask is saved, and the cost is reduced. In the embodiments of the present application, by forming the first doped region 104 of the second conductivity type in the first drift region 101 of the first conductivity type, since the first doped region 104 and the first drift region 101 have different conductivity types, the first doped region 104 can assist the depletion of the first drift region 101, effectively adjust the electric field of the first drift region 101, flatten the peak electric field on the surface of the substrate 10, and improve the avalanche breakdown voltage on the surface of the substrate 10, thereby significantly improving the breakdown voltage of the device, and the first doped region 104 is formed below the first blocking structure, which can also save the device area and improve the integration.

[0072] In some embodiments, performing ion implantation process can include the following steps:

[0073] First, refer to Fig. 9, a first mask layer 161 is formed, the first mask layer 161 exposes the surface of the first field plate structure 132 and the surface of the first region 100;

[0074] Second, refer to Fig. 9 and Fig. 10, a first mask layer 161 is used as a mask, an ion implantation process is performed (refer to Fig. 9) to form a first doped region 104 and a body contact region 103 (refer to Fig. 10).

[0075] In an actual manufacturing process, a photoresist can be first spin-coated or sprayed on the first gate dielectric layer 11, the first field oxide layer 12, the second spacer structure 142, the first field plate structure 132, the spacer structure 141, the first gate structure 131 and the third spacer structure 143, then, exposure and development are performed to form the first mask layer 161 as shown in Fig. 9. Since the first gate dielectric layer 11 formed by the foregoing process covers the surface of the substrate 10, in this case, the first mask layer 161 exposes the surface of the first field plate structure 132 and the surface of the first gate dielectric layer 11 on the first region 100. It should be noted that the thickness of the first gate dielectric layer 11 is usually very thin, for example, the first gate dielectric layer 11 can be a thermal oxide layer formed by a thermal oxidation process, therefore, the first gate dielectric layer 11 has little effect on the subsequent ion implantation on the first region 100. In some other embodiments of the present application, the first gate dielectric layer 11 can not cover the first region 100, in this case, the first mask layer 161 formed can expose the surface of the first field plate structure 132 and the surface of the first region 100. In an actual manufacturing process, when the device is an N-type LDMOS, the first drift region 101 is of N-type and the body region 102 is of P-type, the implanted ions can be P-type ions, for example, boron ions and / or aluminum ions, when the device is a P-type LDMOS, the first drift region 101 is of P-type and the body region 102 is of N-type, the implanted ions can be N-type ions, for example, phosphorus ions and / or arsenic ions, the ions can be implanted along the direction shown by the arrow in Fig. 9 to form the first doped region 104 and the body contact region 103 as shown in Fig. 10.

[0076] In the embodiments of the present application, the first field plate structure 132 is usually formed by a photolithography and etching process, and thus the extension length of the first field plate structure 132 in the horizontal direction can be flexibly adjusted according to actual needs. Therefore, in the ion implantation process, the extension length of the first doped region 104 formed in the first drift region 101 by the blocking of the first field plate structure 132 in the horizontal direction can also be flexibly adjusted accordingly. For example, in some cases, the extension length of the first doped region 104 in the horizontal direction can be appropriately increased to better improve the withstand voltage level of the device. When the first field plate structure 132 is a semiconductor material, in the ion implantation process, the first field plate structure 132 is used as a block, which can also increase the doping concentration of the semiconductor material, which is beneficial to reducing the resistance of the first field plate structure 132.

[0077] It should be noted that, as shown in FIG. 9, the first field plate structure 132 is located above the first field oxide layer 12. In the embodiments of the present application, the first doped region 104 formed in the first drift region 101 by the blocking of the first field plate structure 132 can also be understood as the first doped region 104 formed in the first drift region 101 by the blocking of the first field plate structure 132 and the first field oxide layer 12.

[0078] In some embodiments, the ion implantation process can include the following steps:

[0079] First, referring to FIG. 11, a second mask layer 162 is formed, and the second mask layer 162 exposes the surface of the spacer structure 141 and the surface of the first region 100.

[0080] Second, referring to FIGS. 11 and 12, an ion implantation process is performed (please refer to FIG. 11) to form the first doped region 104 and the body region contact region 103 (please refer to FIG. 12) with the second mask layer 162 as a mask.

[0081] In the embodiments of the present application, the process of forming the second mask layer 162 and the process of performing ion implantation can be understood with reference to the above-mentioned process of forming the first mask layer 161 and the process of performing ion implantation, respectively, which will not be described here. Similar to the above-mentioned embodiments, when the first gate dielectric layer 11 covers the surface of the substrate 10, the second mask layer 162 exposes the surface of the spacer structure 141 and the surface of the first gate dielectric layer 11 located on the first region 100. In some other embodiments of the present application, the first gate dielectric layer 11 can not cover the first region 100, and in this case, the second mask layer 162 formed can expose the surface of the spacer structure 141 and the surface of the first region 100. In the actual preparation process, ions can be implanted in the direction indicated by the arrow in FIG. 11 to form the first doped region 104 and the body region contact region 103 as shown in FIG. 12.

[0082] In the embodiments of the present application, the spacer structure 141 is generally formed by dry etching and / or wet etching process, and thus the extension length of the spacer structure 141 in the horizontal direction depends on the process node and the actual preparation process. Generally, in a process with a smaller node, the first doped region 104 can be formed by the blocking of the spacer structure 141 in the ion implantation process. In addition, as shown in FIG. 12, in the actual preparation process, the surfaces of the spacer structure 141, the second spacer structure 142 and the third spacer structure 143 generally form an arc-shaped structure, so that the distance between the surfaces of the spacer structure 141, the second spacer structure 142 and the third spacer structure 143 and the substrate 10 gradually decreases in a direction away from the first field plate structure 132 or the first gate structure 131. By adjusting the dry etching and / or wet etching process in the actual preparation process, the topography of the spacer structure 141 can be adjusted, and thus the process of forming the first doped region 104 by the blocking of the spacer structure 141 in the ion implantation process can be more flexible.

[0083] In some other embodiments of the present application, when the ion implantation process is performed, it is not excluded that the first doped region 104 is formed by the combination of the first field plate structure 132, the spacer structure 141 and the second spacer structure 142 as a blocking. For example, the first doped region 104 is formed by the combination of part of the first field plate structure 132, part or all of the first field plate structure 132 and part or all of the second spacer structure 142, part or all of the first field plate structure 132 and part or all of the spacer structure 141, etc. as a blocking, and correspondingly, the first doped region 104 is formed in the second region 200 below the actual blocking structure part.

[0084] In some embodiments, the doping concentration of the first doped region 104 can be less than the doping concentration of the first drift region 101.

[0085] In the embodiments of the present application, the first drift region 101 is generally lightly doped to improve the withstand voltage level of the device, and the doping concentration of the first doped region 104 is less than the doping concentration of the first drift region 101, which can further improve the withstand voltage level of the device on the basis of the depletion of the auxiliary drift region.

[0086] In some specific embodiments, referring to FIG. 13 and FIG. 14, the preparation method of the lateral diffusion metal oxide semiconductor device can further include: forming a first drain region 105 in the first drift region 101 on the side of the first field plate structure 132 away from the first gate structure 131; and forming a first source region 106 in the body region 102, the first source region 106 being located between the first gate structure 131 and the body region contact region 103.

[0087] Exemplarily, the first drain region 105 and the first source region 106 can be formed by an ion implantation process, and the step of forming the first drain region 105 and the first source region 106 can be performed before the step of forming the body region contact region 103 or after the step of forming the body region contact region 103.

[0088] In some embodiments, please refer to FIG. 13 and FIG. 14, the method for manufacturing the lateral diffusion metal oxide semiconductor device can further include: forming a first drain 171, a first field plate contact 172, a first gate contact 173, a first source 174 and a body region contact 175 which are respectively electrically connected with the first drain region 105, the first field plate structure 132, the first gate structure 131, the first source region 106 and the body region contact region 103.

[0089] The first drain 171, the first field plate contact 172, the first gate contact 173, the first source 174 and the body region contact 175 in the embodiments of the present application are respectively used for leading out the first drain region 105, the first field plate structure 132, the first gate structure 131, the first source region 106 and the body region contact region 103 to an external control circuit. The processes of forming the first drain 171, the first field plate contact 172, the first gate contact 173, the first source 174 and the body region contact 175 can adopt processes well known to those skilled in the art, which will not be described here.

[0090] It can be understood that the structure shown in FIG. 13 is formed by using the above processes on the basis of the structure shown in FIG. 10, and the structure shown in FIG. 14 is formed by using the above processes on the basis of the structure shown in FIG. 12.

[0091] In some embodiments, please refer to FIG. 15, the substrate 10 can further include a second drift region 201, the second drift region 201 and the first drift region 101 are respectively located on two sides of the body region 102, and the method for manufacturing the lateral diffusion metal oxide semiconductor device can further include:

[0092] forming a second gate structure 231 and a second barrier structure, wherein the second gate structure 231 is formed above part of the body region 102 and above part of the second drift region 201, the second drift region 201 further includes a third region 300 which is not covered by the second gate structure 231, the second barrier structure is formed above the third region 300 of the second drift region 201, and the second barrier structure is located on a side of the second gate structure 231 which is away from the first gate structure 131; in the process of performing the ion implantation process, part of the ions pass through the second barrier structure and are implanted into the third region 300 of the second drift region 201 to form a second doped region 204 of the second conductivity type.

[0093] The function of the second doped region 204 formed in the embodiment of the present application can be understood by referring to the function of the first doped region 104 formed in the foregoing embodiment. Since the second doped region 204 and the first doped region 104 and the body contact region 103 can be formed in one ion implantation process, the process is simple and cost-saving. The process of forming the second gate structure 231 and the second barrier structure can be understood by referring to the process of forming the first gate structure 131 and the first barrier structure in the foregoing embodiment. The second barrier structure formed can include the second field plate structure 232 or the fourth spacer structure 241 as shown in FIG. 15, wherein the fourth spacer structure 241 is formed between the second gate structure 231 and the second field plate structure 232 and extends from the sidewall of the second gate structure 231 to the sidewall of the second field plate structure 232.

[0094] In some specific embodiments, the method for manufacturing the lateral diffusion metal oxide semiconductor device can further include: forming a sixth spacer structure 243 and a fifth spacer structure 242 covering another sidewall of the second gate structure 231 and the second field plate structure 232, and forming a second drain region 205, wherein the second drain region 205 is formed in the second drift region 201 away from the second gate structure 231 on one side of the second field plate structure 232.

[0095] As shown in FIG. 15, in the embodiment of the present application, the finally formed device structure can include two first units 1 and second units 2 similar in structure. The first unit 1 and the second unit 2 can share the first source region 106 and the body contact region 103 therebetween. The constituent structure, function and forming process of each component in the first unit 1 can be understood by referring to the foregoing embodiment. The constituent structure, function and forming process of each component in the second unit 2 can be understood by referring to the constituent structure, function and forming process of the corresponding component in the first unit 1. For example, the first drift region 101 corresponds to the second drift region 201, the first gate structure 131 corresponds to the second gate structure 231, the first barrier structure corresponds to the second barrier structure, the first doped region 104 corresponds to the second doped region 204, the first drain region 105 corresponds to the second drain region 205, and so on. It can be understood that the corresponding components in the first unit 1 and the second unit 2 can be formed in one process to simplify the process. Of course, it is not excluded that the corresponding components in the first unit 1 and the second unit 2 are formed in different process steps.

[0096] FIG. 16 is a simulation diagram of the electric field intensity distribution of the lateral diffusion metal oxide semiconductor device in the related art. The corresponding device structure in FIG. 16 can be understood by referring to the device structure shown in FIG. 1.

[0097] Referring to FIG. 16, in the prior art, the peak electric field near the surface of the substrate 10 of the device is concentrated under the first gate structure 131 (as shown by the dashed box in FIG. 16), and the electric field is mainly concentrated on the surface of the substrate 10, which reduces the avalanche breakdown voltage of the surface of the substrate 10, and the concentration of the electric field causes the surface of the substrate 10 to be broken down in advance.

[0098] FIG. 17 is a simulation diagram of the electric field intensity distribution of the lateral diffusion metal oxide semiconductor device prepared in the embodiment of the present application. The device structure corresponding to FIG. 17 can be understood with reference to the device structure shown in FIG. 13.

[0099] Referring to FIG. 17, the lateral diffusion metal oxide semiconductor device prepared in the embodiment of the present application has a more dispersed electric field distribution on the surface of the substrate 10 (as shown by the dashed box in FIG. 17) than the electric field distribution on the surface of the substrate 10 in the prior art, and the electric field is dispersed from the surface of the substrate 10 into the substrate 10, the peak electric field intensity under the first gate structure 131 is significantly reduced, the interface electric field distribution is changed by the regulation of the electric field by the first doped region 104 and the voltage division effect of the first field plate structure 132, the peak electric field on the surface of the substrate 10 is flattened, the breakdown point is transferred from the surface of the substrate 10 to the body of the substrate 10, and the avalanche breakdown voltage of the surface of the substrate 10 can be improved, thereby effectively improving the withstand voltage level of the device.

[0100] Table 1 shows the performance parameters of the lateral diffusion metal oxide semiconductor device prepared in the embodiment of the present application and the lateral diffusion metal oxide semiconductor device in the related art. The device structure in the embodiment of the present application can be understood with reference to the device structure shown in FIG. 13, and the device in the related art can be understood with reference to the device structure shown in FIG. 1.

[0101] Table 1

[0102] As can be seen from the data in Table 1, the BV value of the device in the embodiment of the present application is obviously improved relative to the BV value of the device in the related art. It can be understood that, in order to improve the BV, it is difficult to avoid the increase of Ron,sp. Although the Ron,sp value of the device in the embodiment of the present application is improved relative to the Ron,sp value of the device in the related art, the Ron,sp of the device in the embodiment of the present application is still relatively low compared with the high BV value of the device in the embodiment of the present application. The FOM (Figure of merit) in Table 1 can be used to evaluate the performance of the device, that is, in the case of constant Ron,sp, the greater the BV is, the better, or in the case of constant BV, the lower the Ron,sp is, the better, and therefore the greater the FOM value is, the better the performance of the device is. As can be seen from the data in Table 1, the performance of the device in the embodiment of the present application is obviously better than the performance of the device in the related art. At the same time of improving the performance of the device, the preparation process of the device in the embodiment of the present application is relatively simple and the cost is relatively low.

[0103] Based on this, the embodiment of the present application also provides a lateral diffusion metal oxide semiconductor device prepared by using the steps in the preparation method of the lateral diffusion metal oxide semiconductor device provided in any of the preceding embodiments.

[0104] Based on this, the embodiment of the present application also provides another lateral diffusion metal oxide semiconductor device. As shown in FIG. 13, the lateral diffusion metal oxide semiconductor device includes:

[0105] a substrate 10;

[0106] a first drift region 101 of a first conductivity type and a body region 102 of a second conductivity type, which are located in the substrate 10;

[0107] a first gate structure 131 located above part of the body region 102 and part of the first drift region 101; the body region 102 further includes a first region 100 not covered by the first gate structure 131, and the first drift region 101 further includes a second region 200 not covered by the first gate structure 131;

[0108] a first blocking structure located above the second region 200 of the first drift region 101;

[0109] a body region contact region 103 of the second conductivity type located in the first region 100 of the body region 102;

[0110] a first doped region 104 of the second conductivity type located in the second region 200 of the first drift region 101, and the doping concentration of the first doped region 104 is less than the doping concentration of the first drift region 101.

[0111] In the embodiment of the present application, the first doped region 104 of the second conductive type is located in the first drift region 101 of the first conductive type. Since the first doped region 104 and the first drift region 101 have different conductive types, the first doped region 104 can assist the depletion of the first drift region 101, effectively adjust the electric field of the first drift region 101, flatten the peak electric field on the surface of the substrate 10, and improve the avalanche breakdown voltage of the surface of the substrate 10. Generally, the first drift region 101 is lightly doped to improve the withstand voltage level of the device. The doping concentration of the first doped region 104 is less than the doping concentration of the first drift region 101, which can better improve the withstand voltage level of the device on the basis of assisting the depletion of the drift region, thereby significantly improving the breakdown voltage of the device. Moreover, the first doped region 104 is formed below the first blocking structure, which can save device area and improve the integration level.

[0112] In some embodiments, please continue to refer to FIG. 13. The first blocking structure includes the first field plate structure 132. The first doped region 104 is located below the second region 200 of the first field plate structure 132. The vertical projection center of the first doped region 104 in the thickness direction of the substrate 10 coincides with the vertical projection center of the first field plate structure 132 in the thickness direction of the substrate 10.

[0113] In the actual preparation process, the ion implantation process for forming the body region contact region 103 has a relatively large ion implantation dose. However, the first doped region 104 in the embodiment of the present application generally needs a lower doping concentration to effectively improve the withstand voltage level of the device. Therefore, the formation of the first doped region 104 and the formation of the body region contact region 103 generally cannot be formed in one step ion implantation process. In the embodiment of the present application, by setting the first blocking structure, part of the ions can be implanted into the second region 200 after passing through the first blocking structure in the ion implantation process. In this way, the body region contact region 103 and the first doped region 104 can be formed in one step ion implantation process, the process is simplified, the mask is saved, and the cost is reduced. The vertical projection center of the first doped region 104 formed by ion implantation with the first field plate structure 132 as the blocking structure in the thickness direction of the substrate 10 coincides with the vertical projection center of the first field plate structure 132 in the thickness direction of the substrate 10. In this way, the position of the formed first doped region 104 can be better controlled, thereby better playing the role of improving the withstand voltage level of the device.

[0114] In some embodiments, referring to FIG. 14, the lateral diffusion metal oxide semiconductor device further comprises a first field plate structure 132 located above the first drift region 101; the first blocking structure can comprise a spacer structure 141 located between the first field plate structure 132 and the first gate structure 131 and extending from the sidewall of the first field plate structure 132 to the sidewall of the first gate structure 131, the first doped region 104 is located in the second region 200 below the spacer structure 141, and the center of the vertical projection of the first doped region 104 in the thickness direction of the substrate 10 coincides with the center of the vertical projection of the spacer structure 141 in the thickness direction of the substrate 10.

[0115] In the actual manufacturing process, the first doped region 104 formed by ion implantation with the spacer structure 141 as the blocking structure, in which case the center of the vertical projection of the first doped region 104 in the thickness direction of the substrate 10 coincides with the center of the vertical projection of the spacer structure 141 in the thickness direction of the substrate 10, so that the position of the formed first doped region 104 is more controllable, thereby better playing the role of improving the withstand voltage level of the device.

[0116] In some embodiments, still referring to FIG. 14, the lateral diffusion metal oxide semiconductor device can further comprise: a second spacer structure 142 and a third spacer structure 143 covering the other sidewall of the first field plate structure 132 and the first gate structure 131, respectively.

[0117] In some embodiments, referring to FIG. 13 and FIG. 14, the lateral diffusion metal oxide semiconductor device can further comprise: a first gate dielectric layer 11 located at least below the first gate structure 131, a first field oxide layer 12 located at least below the first field plate structure 132, a first drain region 105 located in the first drift region 101, the first drain region 105 being located in the first drift region 101 away from the first gate structure 131 on one side of the first field plate structure 132; a first source region 106 located in the body region 102, the first source region 106 being located between the first gate structure 131 and the body contact region 103; a first drain 171, a first field plate contact 172, a first gate contact 173, a first source 174, and a body contact 175 electrically connected to the first drain region 105, the first field plate structure 132, the first gate structure 131, the first source region 106, and the body contact region 103, respectively.

[0118] In some embodiments, referring to FIG. 15, the substrate 10 further comprises a second drift region 201, the second drift region 201 and the first drift region 101 being located on both sides of the body region 102; the lateral diffusion metal oxide semiconductor device further comprises:

[0119] The second gate structure 231 is located above the partial body region 102 and above the partial second drift region 201, and the second drift region 201 further includes a third region 300 which is not covered by the second gate structure 231.

[0120] The second blocking structure is located above the third region 300 of the second drift region 201, and the second blocking structure is located at a side of the second gate structure 231 away from the first gate structure 131.

[0121] The second doped region 204 of the second conductivity type is located in the third region 300 of the second drift region 201, and the doping concentration of the second doped region 204 is less than the doping concentration of the second drift region 201, and the second doped region 204 and the first doped region 104 and the body contact region 103 are formed in a one-step ion implantation process.

[0122] The role of the second doped region 204 in the embodiments of the present application can be understood by referring to the role of the first doped region 104 in the foregoing embodiments, and since the second doped region 204 and the first doped region 104 and the body contact region 103 can be formed in a one-step ion implantation process, the process is simple and can save costs.

[0123] In some embodiments, the second blocking structure can include a second field plate structure 232 as shown in FIG. 15, in which case the second doped region 204 is located in the second drift region 201 below the second field plate structure 232. In some other embodiments of the present application, the second blocking structure can include a fourth spacer structure 241 as shown in FIG. 15, in which case the fourth spacer structure 241 is located between the second gate structure 231 and the second field plate structure 232 and extends from the sidewall of the second gate structure 231 to the sidewall of the second field plate structure 232, and it can be understood that in this case the second doped region 204 is located in the second drift region 201 below the fourth spacer structure 241.

[0124] In some embodiments, the lateral diffusion metal oxide semiconductor device can further include a sixth spacer structure 243 and a fifth spacer structure 242 covering another sidewall of the second gate structure 231 and the second field plate structure 232, respectively, and a second drain region 205 located in the second drift region 201 at a side of the second field plate structure 232 away from the second gate structure 231.

[0125] As shown in FIG. 15, in the embodiment of the present application, the finally formed device structure can include two first unit 1 and second unit 2 which are similar in structure, the first unit 1 and the second unit 2 can share the first source region 106 and the body region contact region 103, the component structure and the role of each component in the first unit 1 can be understood with reference to the foregoing embodiments, the component structure and the role of each component in the second unit 2 can be understood with reference to the component structure and the role of the corresponding component in the first unit 1, for example, the first drift region 101 corresponds to the second drift region 201, the first gate structure 131 corresponds to the second gate structure 231, the first blocking structure corresponds to the second blocking structure, the first doped region 104 corresponds to the second doped region 204, the first drain region 105 corresponds to the second drain region 205, and so on.

[0126] It should be noted that the lateral diffusion metal oxide semiconductor device embodiments provided by the present application and the preparation method embodiments of the lateral diffusion metal oxide semiconductor device belong to the same concept; the technical features of the technical solutions recorded in each embodiment can be combined arbitrarily without conflict. However, it should be further noted that the combination of technical features of the lateral diffusion metal oxide semiconductor device provided by the embodiments of the present application can already solve the technical problems to be solved by the present application; thus, the lateral diffusion metal oxide semiconductor device provided by the embodiments of the present application can not be limited by the preparation method of the lateral diffusion metal oxide semiconductor device provided by the embodiments of the present application, and any lateral diffusion metal oxide semiconductor device prepared by a preparation method that can form the lateral diffusion metal oxide semiconductor device structure provided by the embodiments of the present application is within the scope of protection of the present application.

[0127] It should be understood that the above embodiments are exemplary and are not intended to include all possible embodiments of the present application. Various modifications and changes can also be made to the above embodiments without departing from the scope of the present disclosure. Similarly, any combination of the technical features of the above embodiments can be made to form additional embodiments of the present application that can not be explicitly described. Therefore, the above embodiments only express several embodiments of the present application and do not limit the scope of protection of the patent of the present application.

Claims

1. A method for manufacturing a lateral diffusion metal oxide semiconductor device, the method comprising: providing a substrate, the substrate comprising a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first barrier structure, wherein the first gate structure is formed over part of the body region and part of the first drift region, the body region further comprising a first region not covered by the first gate structure, the first drift region further comprising a second region not covered by the first gate structure, the first barrier structure is formed over the second region of the first drift region; performing an ion implantation process, part of the ions are implanted into the first region of the body region to form a body region contact region of the second conductivity type, and part of the ions are implanted into the second region of the first drift region through the first barrier structure to form a first doped region of the second conductivity type.

2. The method of producing a lateral diffusion metal oxide semiconductor device according to claim 1, wherein, the first barrier structure comprises a first field plate structure, and the performing the ion implantation process comprises: forming a first mask layer, the first mask layer exposes a surface of the first field plate structure and a surface of the first region; performing an ion implantation process with the first mask layer as a mask to form the first doped region and the body region contact region.

3. The method of producing a lateral diffusion metal oxide semiconductor device according to claim 1, wherein, the method further comprises forming a first field plate structure over the first drift region, and the first barrier structure comprises a spacer structure located between the first field plate structure and the first gate structure and extending from a sidewall of the first field plate structure to a sidewall of the first gate structure, and the performing the ion implantation process comprises: forming a second mask layer, the second mask layer exposes a surface of the spacer structure and a surface of the first region; performing an ion implantation process with the second mask layer as a mask to form the first doped region and the body region contact region.

4. The method of producing a lateral diffusion metal oxide semiconductor device according to claim 1, wherein, a doping concentration of the first doped region is less than a doping concentration of the first drift region.

5. The method of producing a lateral diffusion metal oxide semiconductor device according to any one of claims 1 to 4, wherein the substrate further comprises a second drift region, the second drift region and the first drift region are located on two sides of the body region respectively; the method further comprises: forming a second gate structure and a second barrier structure, wherein the second gate structure is formed over part of the body region and part of the second drift region, the second drift region further comprising a third region not covered by the second gate structure, the second barrier structure is formed over the third region of the second drift region, and the second barrier structure is located on a side of the second gate structure away from the first gate structure; in the performing the ion implantation process, part of the ions are implanted into the third region of the second drift region through the second barrier structure to form a second doped region of the second conductivity type. 6.A lateral diffusion metal oxide semiconductor device manufactured by the method for manufacturing a lateral diffusion metal oxide semiconductor device according to any one of claims 1 to 5. 7.A lateral diffusion metal oxide semiconductor device, the lateral diffusion metal oxide semiconductor device comprising: a substrate; a first drift region of a first conductivity type and a body region of a second conductivity type in the substrate; a first gate structure over part of the body region and part of the first drift region; the body region further comprises a first region not covered by the first gate structure, and the first drift region further comprises a second region not covered by the first gate structure; a first blocking structure over the second region of the first drift region; a body region contact region of the second conductivity type in the first region of the body region; a first doped region of the second conductivity type in the second region of the first drift region, the first doped region having a doping concentration less than a doping concentration of the first drift region.

8. The lateral diffused metal oxide semiconductor device of claim 7, wherein, the first blocking structure comprises a first field plate structure, the first doped region is in the second region under the first field plate structure, and a center of a vertical projection of the first doped region on a substrate thickness direction coincides with a center of a vertical projection of the first field plate structure on the substrate thickness direction.

9. The lateral diffused metal oxide semiconductor device of claim 7, wherein, the lateral diffusion metal oxide semiconductor device further comprises a first field plate structure over the first drift region; the first blocking structure comprises a spacer structure between the first field plate structure and the first gate structure and extending from a sidewall of the first field plate structure to a sidewall of the first gate structure, the first doped region is in the second region under the spacer structure, and a center of a vertical projection of the first doped region on the substrate thickness direction coincides with a center of a vertical projection of the spacer structure on the substrate thickness direction.

10. The lateral diffused metal oxide semiconductor device of any one of claims 7 to 9, wherein, the substrate further comprises a second drift region, the second drift region and the first drift region are on two sides of the body region respectively; the lateral diffusion metal oxide semiconductor device further comprises: a second gate structure over part of the body region and part of the second drift region, the second drift region further comprises a third region not covered by the second gate structure; a second blocking structure over the third region of the second drift region, the second blocking structure is on a side of the second gate structure away from the first gate structure; a second doped region of the second conductivity type in the third region of the second drift region, the second doped region having a doping concentration less than a doping concentration of the second drift region, the second doped region and the first doped region and the body region contact region are formed in one ion implantation process.

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