Anti-fuse memory and programming method therefor

Abstract

The present disclosure relates to an anti-fuse memory and a programming method therefor. The anti-fuse memory comprises an anti-fuse memory array, which comprises a plurality of anti-fuse memory cells, wherein each anti-fuse memory cell comprises an anti-fuse transistor. The anti-fuse memory further comprises a bit line; and a feedback network, which is connected between the bit line and at least one of the anti-fuse memory cells, and the feedback network is used for disconnecting the bit line from the at least one anti-fuse memory cell when the magnitude of the current between the bit line and the at least one anti-fuse memory cell connected to the bit line meets a preset condition. In the present disclosure, a plurality of bits can be programmed at the same time, and unnecessary programming current can be eliminated, thereby reducing the power consumption.

Description

Antifuse memory and its programming method TECHNICAL FIELD

[0001] The present disclosure relates to memory, in particular to an antifuse memory and a programming method of the antifuse memory. BACKGROUND

[0002] Antifuse uses gate oxide breakdown as a programming mechanism, and the generated connection after programming is highly reliable without reverse growth problem, so the number of read times is not limited. The antifuse memory includes an antifuse memory array, and the antifuse memory array includes a plurality of antifuse memory cells. Generally, an antifuse memory cell is composed of two transistors, one is a selection transistor (NM1), and the other is a memory cell transistor (NM2), as shown in FIG. 1. The advantages of Antifuse lie in its programming mechanism, security, and power consumption.

[0003] The programming mechanism of Antifuse is that when programming, Antifuse generates a large potential difference between the two ends of its thin gate oxide, and through this large potential difference, avalanche breakdown occurs in the oxide, which makes the gate and source of the MOS tube short-circuit, realizing the programming of the Antifuse bit cell. Antifuse can be programmed about 18 times in general, and if the Antifuse bit cell fails to program for the first time, it can be programmed multiple times, which can improve the yield of programming.

[0004] Antifuse has better security compared with other OTP (One Time Programmable memory). Antifuse cannot distinguish between programmed CELL and unprogrammed CELL under a microscope, so it cannot read the programmed data. Not only can Antifuse not detect the programming information under a microscope, but it also cannot detect the voltage hot spot through FIB (Focused Ion Beam), which makes it difficult for unauthorized users to obtain the data stored in the Antifuse memory.

[0005] Antifuse has a high resistance in the unprogrammed state and a low resistance in the programmed state, so its static power consumption is low.

[0006] The traditional antifuse memory is programmed one bit at a time, which has low programming efficiency. SUMMARY

[0007] Therefore, it is necessary to provide an antifuse memory capable of programming multiple bits at the same time and a programming method thereof.

[0008] An anti-fuse memory includes an anti-fuse memory array including a plurality of anti-fuse memory cells, each anti-fuse memory cell including an anti-fuse transistor, the anti-fuse memory further including a bit line, and a feedback network connected between the bit line and at least one of the anti-fuse memory cells, the feedback network configured to disconnect the bit line from the at least one anti-fuse memory cell when a current between the bit line and the at least one anti-fuse memory cell connected to the bit line is detected to satisfy a predetermined condition.

[0009] The anti-fuse memory is configured to disconnect the bit line from the at least one anti-fuse memory cell when a large current between the bit line and the at least one anti-fuse memory cell connected to the bit line is detected, thereby preventing a programming voltage provided to the anti-fuse transistor from being insufficient due to the large current, and thus enabling multiple bits to be programmed simultaneously.

[0010] In one embodiment, the predetermined condition includes that the current between the bit line and the at least one anti-fuse memory cell connected to the bit line is greater than a predetermined threshold when programming data "1".

[0011] In one embodiment, the feedback network includes a current mirror, a reference current terminal of the current mirror being connected to the at least one anti-fuse memory cell connected to the bit line, a first input terminal of a comparator being connected to a copy current terminal of the current mirror, a second input terminal of the comparator being configured to input a reference signal, and a controlled switch unit, a control terminal of the controlled switch unit being connected to an output terminal of the comparator, and being configured to control a connection and disconnection between the bit line and the at least one anti-fuse memory cell connected to the bit line.

[0012] In one embodiment, the controlled switch unit includes a transmission gate, the transmission gate being configured to connect the bit line to the at least one anti-fuse memory cell connected to the bit line when the output terminal of the comparator outputs a first level, and disconnect the bit line from the at least one anti-fuse memory cell connected to the bit line when the output terminal of the comparator outputs a second level, wherein one of the first level and the second level is a low level, and the other is a high level.

[0013] In one embodiment, the controlled switch unit further includes a D flip-flop, a first input terminal of the D flip-flop being connected to the output terminal of the comparator, a first output terminal of the D flip-flop being directly connected to a first control terminal of the transmission gate, and an inverter, the first output terminal of the D flip-flop being connected to a second control terminal of the transmission gate through the inverter.

[0014] In one embodiment, the current mirror comprises: a first NMOS transistor, a drain of the first NMOS transistor being connected to a gate of the first NMOS transistor and at least one anti-fuse memory cell connected to the bit line, a source of the first NMOS transistor being connected to the controlled switch unit; a second NMOS transistor, a drain of the second NMOS transistor being connected to a first input of the comparator, a source of the second NMOS transistor being connected to the bit line.

[0015] In one embodiment, each of the anti-fuse memory cells further comprises a selection transistor, a controlled end of the selection transistor being connected to a word line of the anti-fuse memory array, a first end of the selection transistor being connected to the feedback network, a second end of the selection transistor being connected to the anti-fuse transistor; the controlled end of the anti-fuse transistor is used to receive a programming voltage.

[0016] In one embodiment, the anti-fuse memory further comprises a programming signal generation unit, the programming signal generation unit is used to output a third level to multiple bit lines at the same time when programming data "1", the third level is a level opposite to a level on the corresponding bit line when programming data "0".

[0017] In one embodiment, the anti-fuse memory array further comprises a sense amplifier, a common end of the first NMOS transistor and the anti-fuse memory cell is connected to the sense amplifier.

[0018] A programming method of an anti-fuse memory, comprising: in response to an operation of programming data "1" to an anti-fuse memory cell, detecting a current size between a corresponding bit line of an anti-fuse memory array and an anti-fuse memory cell connected to the bit line; if the current size meets a preset condition, disconnecting the bit line and the anti-fuse memory cell.

[0019] The programming method of the anti-fuse memory described above, by taking advantage of the feature that the current between the bit line and the anti-fuse memory cell connected to the bit line becomes very large after programming data "1", disconnecting the connection between the bit line and the anti-fuse memory cell when this large current is detected, avoiding the situation that the programming voltage provided to the anti-fuse transistor cannot reach the designed value due to the need to drive this large current, thus enabling multiple bits to be programmed at the same time.

[0020] In one embodiment, the operation of programming data "1" to the anti-fuse memory cell is an operation of programming data "1" to multiple anti-fuse memory cells connected to multiple bit lines at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0021] For purposes of the US, this description is subject to letters patent of the United States of America. For purposes of the European Patent Convention, this description is subject to the European Patent Convention. For purposes of the rest of the world, this description is subject to the Paris Convention or the equivalent.

[0022] Figure 1 is a circuit diagram of an exemplary antifuse memory cell.

[0023] Figure 2 is a circuit diagram of a row of an exemplary antifuse memory array.

[0024] Figure 3 is a circuit diagram of an antifuse memory array in one embodiment of the present disclosure.

[0025] Figure 4 is a circuit diagram of a feedback network connected antifuse memory cell in one embodiment of the present disclosure.

[0026] Figure 5 is a circuit diagram of a feedback network connected antifuse memory cell in another embodiment of the present disclosure.

[0027] Figure 6 is a circuit diagram of a feedback network connected antifuse memory cell in yet another embodiment of the present disclosure.

[0028] Figure 7 is a flow diagram of a programming method for an antifuse memory in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] For the purposes of this disclosure, reference will be made to the accompanying drawings in which first preferred embodiments of the present disclosure will be presented. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of associated items.

[0032] Figure 2 is a row in an exemplary anti-fuse memory array. If CELL0, CELL1, CELL2 are programmed simultaneously, bit lines BL0, BL1, BL2 should be set to zero first, and programming voltage VPPIN is set to a predetermined high voltage (e.g. 7.5V) after other programming control signals are ready. Taking CELL0 as an example, if CELL0 is programmed successfully, the gate oxide layer of the anti-fuse transistor is broken, and the resistance of the programmed CELL0 is very low, so a large current (hereinafter referred to as programming current) will flow between the gate of the anti-fuse transistor and BL0. The high voltage of the programming voltage VPPIN is generally generated by the internal circuit of the anti-fuse memory, and if its driving capability is insufficient, it cannot maintain the original 7.5V voltage value under the condition of maintaining this current, so there is a possibility of failure when programming CELL1 and CELL2. Taking an anti-fuse memory array with 8 IOs as an example, if 8-bit IOs are programmed simultaneously, VPPIN needs to maintain a programming voltage of 7.5V under the condition of 7 channels, which requires VPPIN to have strong driving capability, which is difficult to achieve in actual products, and large programming current will result in high power consumption.

[0033] The present disclosure provides an anti-fuse memory and a programming method thereof, which can program multiple-bit IOs simultaneously to improve programming efficiency. The anti-fuse memory includes an anti-fuse memory array, the anti-fuse memory array includes a plurality of anti-fuse memory cells, each anti-fuse memory cell includes an anti-fuse transistor NM2, and the anti-fuse memory array further includes a bit line and a feedback network.

[0034] The feedback network is connected between the bit line and the at least one antifuse memory cell, and is configured to disconnect the bit line from the at least one antifuse memory cell when it is detected that the current between the bit line and the at least one antifuse memory cell connected to the bit line satisfies a preset condition. For example, the bit line BL0 in FIG. 3 is connected to a feedback network. When programming data "1" (i.e., writing data "1"), if the feedback network connected to the bit line BL0 detects that the current between the bit line BL0 and the antifuse memory cell connected to the bit line BL0 is greater than a preset threshold, the bit line BL0 is disconnected from the antifuse memory cell connected thereto.

[0035] The antifuse memory described above uses the feature that the current between the bit line and the antifuse memory cell connected to the bit line becomes very large after programming data "1". A feedback network is provided to disconnect the bit line from the antifuse memory cell when the large current is detected, so that the programming voltage provided to the antifuse transistor does not drop below the design value due to the large current, and thus multiple IOs can be programmed simultaneously.

[0036] In the embodiment shown in FIG. 4, the feedback network includes a current mirror, a comparator, and a controlled switch unit.

[0037] The current at the reference current end of the current mirror is the current between the bit line BL and the antifuse memory cell connected to the bit line BL, and the reference current end is connected to the antifuse memory cell.

[0038] The first input end Ibl of the comparator is connected to the copy current end of the current mirror, and the second input end of the comparator is configured to input a reference signal Iref.

[0039] The controlled end of the controlled switch unit is connected to the output end of the comparator, and is configured to control the connection and disconnection between the bit line BL and the antifuse memory cell connected to the bit line BL.

[0040] Referring to FIG. 5, in one embodiment of the present disclosure, the controlled switch unit includes a transmission gate. When the output end of the comparator outputs a first level, the transmission gate connects the bit line BL to the antifuse memory cell connected to the bit line BL, and when the output end of the comparator outputs a second level, the transmission gate disconnects the bit line BL from the antifuse memory cell connected to the bit line BL. One of the first level and the second level is a low level, and the other is a high level.

[0041] In one embodiment of the present disclosure, the current mirror includes a first NMOS transistor NM3 and a second NMOS transistor NM4.

[0042] The drain of the first NMOS transistor NM3 is connected to the gate of the first NMOS transistor NM3 and the antifuse memory cell connected to the bit line BL, and the source of the first NMOS transistor NM3 is connected to the controlled switch unit.

[0043] The drain of the second NMOS transistor NM4 is connected to the first input of the comparator, the source of the second NMOS transistor NM4 is connected to the bit line BL, and the gate of the second NMOS transistor NM4 is connected to the gate of the NMOS transistor NM3.

[0044] Referring to FIG. 6, in one embodiment of the present disclosure, the controlled switch unit further comprises a D flip-flop and an inverter. The first input C1 of the D flip-flop is connected to the output of the comparator, the first output of the D flip-flop is directly connected to the first control end of the transmission gate, and the first output of the D flip-flop is also connected to the second control end of the transmission gate through the inverter.

[0045] In one embodiment of the present disclosure, each antifuse memory cell further comprises a selection transistor NM1. The controlled end of the selection transistor NM1 is connected to the word line WL of the antifuse memory array, the first end of the selection transistor NM1 is connected to the feedback network, and the second end of the selection transistor NM1 is connected to the antifuse transistor NM2. In the embodiment shown in FIG. 4, the drain of the selection transistor NM1 is connected to the feedback network, the source of the selection transistor NM1 is connected to the drain of the antifuse transistor NM2, and the source of the antifuse transistor NM2 is connected to ground. The controlled end of the antifuse transistor NM2 is used to receive the programming voltage VPPIN.

[0046] In one embodiment of the present disclosure, the antifuse memory array further comprises a sense amplifier SA. The drain of the first NMOS transistor NM3 is connected to the sense amplifier SA.

[0047] In one embodiment of the present disclosure, the antifuse memory further comprises a programming signal generation unit. The programming signal generation unit is used to output a third level to multiple bit lines at the same time when programming data "1". The third level is a level opposite to the level on the bit line when programming data "0" (i.e., writing data "0"). In one embodiment of the present disclosure, the programming signal generation unit is used to output a low level when programming data "1".

[0048] The working principle of the antifuse memory of the embodiment of the present disclosure is described below in combination with FIG. 6.

[0049] The first NMOS transistor NM3 and the second NMOS transistor NM4 form a current mirror. The drain of the first NMOS transistor NM3 is connected to the bl end of the antifuse memory cell, and the source is connected to the transmission gate and then to the bit line BL. The drain of the second NMOS transistor NM4 is connected to the positive input Ibl of the comparator, the source is connected to the bit line BL, and the gate of the second NMOS transistor NM4 is connected to the gate of the first NMOS transistor NM3. The reference current Iref is connected to the negative input of the comparator, the output of the comparator is connected to the first input of the D flip-flop (rising edge trigger), the output of the D flip-flop is connected to the control end of the transmission gate through the inverter. In this way, a feedback network is formed.

[0050] When the antifuse memory is in the programming state, it is divided into two cases, namely programming data "0" and programming data "1".

[0051] When the programming data "0" operation is performed, the D flip-flop is first reset through the reset end Rst of the D flip-flop, so that the transmission gate is in the on state. The antifuse memory selects the address of the antifuse storage unit that needs to be programmed data "0", that is, the corresponding word line WL is "1", and the corresponding bit line BL is "1". The "1" signal (i.e. high level) of the bit line BL is given to the bl end of the corresponding antifuse storage unit through the transmission gate and then through the first NMOS tube NM3, and then given to the drain of the antifuse transistor NM2 through the on selection transistor NM1. At this time, the programming voltage VPPIN is input high voltage, and since the bit line BL gives the drain of the antifuse transistor NM2 high level, the pressure difference between the gate and the drain of the antifuse transistor NM2 is VPP-VDD (VDD is the power supply voltage of the antifuse memory, which is 5V by way of example, and VPP is the voltage value of the programming voltage VPPIN), and since the pressure difference is small, the thin gate oxide of the antifuse transistor NM2 will not be broken down, and the programming data "0" operation of the antifuse storage unit is completed. During this period, there is almost no current flowing through the first NMOS tube NM3, and the output of the comparator is always "0", so the D flip-flop will not trigger, and the transmission gate is always on.

[0052] When the programming data "1" operation is performed, the D flip-flop is first reset, so that the pass gate is in the on state. The address of the antifuse memory unit that needs to be programmed with data "1" is selected, i.e., the corresponding word line WL is set to "1" and the corresponding bit line BL is set to "0". The "0" signal (i.e., low level) of the bit line BL is transmitted through the pass gate and then through the first NMOS transistor NM3 to the bl terminal of the corresponding antifuse memory unit, and then through the on selection transistor NM1 to the drain of the antifuse transistor NM2. At this time, the programming voltage VPPIN is input as a high voltage. Since the low level is input to the drain of the antifuse transistor NM2 through the bit line BL, the voltage difference between the gate and the drain of the antifuse transistor NM2 is VPP, which is relatively large, so that the thin gate oxide of the antifuse transistor NM2 is broken down, thereby completing the programming data "1" operation of the antifuse memory unit. Before the thin gate oxide of the antifuse transistor NM2 is broken down, almost no current flows through the first NMOS transistor NM3, the output of the comparator is "0", the D flip-flop is not triggered, and the pass gate is in the on state. When the thin gate oxide of the antifuse transistor NM2 is broken down, a large programming current will flow between the gate of the antifuse transistor NM2 and the bit line BL (the first NMOS transistor NM3). At this time, the current at the positive input terminal of the comparator suddenly increases, the output of the comparator changes to "1", the D flip-flop is triggered, and the pass gate is closed, so as to shield the large programming current. Therefore, the excess programming current is eliminated, and the power consumption of the antifuse memory is reduced. It can be understood that the disconnection of the feedback network between the corresponding bit line and the antifuse memory unit is performed during the programming data "1" operation.

[0053] In the read (unprogrammed) operation state, the address of the antifuse memory unit that needs to be read is first selected, i.e., the corresponding word line WL is set to "1", the sensitive amplifier SA is turned on between the sensitive amplifier SA and the antifuse memory unit (the antifuse memory unit that needs to be read), and the programming voltage VPPIN of the antifuse memory unit that needs to be read is set to "0".

[0054] Based on the above embodiment, the antifuse memory of the present disclosure can realize multi-bit IO programming, and improve the programming efficiency. In addition, the unnecessary programming current can be eliminated, so as to reduce the power consumption of the antifuse memory. In addition, the antifuse memory of the present disclosure can omit many high-voltage decoding circuits, level shift circuits, buffers, etc. required by the conventional antifuse memory that performs programming one bit at a time, so that the circuit of the antifuse memory can be simplified.

[0055] The present disclosure further provides a programming method of an antifuse memory. FIG. 7 is a flowchart of the programming method of the antifuse memory according to an embodiment of the present disclosure, which includes the following steps: S710 to S730.

[0056] S710, detecting the current between the bit line and the anti-fuse memory cell connected thereto when the "1" is programmed.

[0057] In the operation of programming the anti-fuse memory cell with data "1" (i.e. writing data "1"), the current between the corresponding bit line of the anti-fuse memory cell to which the data "1" is to be written and the anti-fuse memory cell connected to the bit line is detected.

[0058] S720, judging whether the current meets a preset condition.

[0059] If the current meets the preset condition, the step S730 is entered. In one embodiment of the present disclosure, the preset condition is that the current is greater than a preset threshold.

[0060] S730, disconnecting the connection between the bit line and the anti-fuse memory cell.

[0061] After the large current is detected, the bit line with the large current and the anti-fuse memory cell connected thereto are disconnected. It is noted that the disconnection is performed during the operation of programming the data "1".

[0062] The programming method of the anti-fuse memory described above takes advantage of the feature that the current between the bit line and the anti-fuse memory cell connected to the bit line becomes very large after the data "1" is programmed, and disconnects the connection between the bit line and the anti-fuse memory cell when the large current is detected, thereby avoiding the situation that the programming voltage provided to the anti-fuse transistor fails to reach the designed value due to the need to drive the large current, and thus the multiple bits can be programmed simultaneously.

[0063] In one embodiment of the present disclosure, the operation of programming the anti-fuse memory cell with data "1" is performed on the anti-fuse memory cells connected to multiple bit lines simultaneously, thereby realizing the simultaneous programming of multiple bits.

[0064] In one embodiment of the present disclosure, the feedback network is provided between the bit line and the anti-fuse memory cell connected thereto to realize the steps S710 to S730.

[0065] In one embodiment of the present disclosure, the feedback network comprises a current mirror, a comparator and a controlled switch unit.

[0066] The current at the reference current end of the current mirror is the current between the bit line and the anti-fuse memory cell connected to the bit line, and the reference current end is connected to the corresponding anti-fuse memory cell;

[0067] The first input end of the comparator is connected to the copy current end of the current mirror, and the second input end of the comparator is connected to a reference signal end.

[0068] The controlled end of the controlled switch unit is connected with the output end of the comparator, for controlling the connection and disconnection between the bit line and each anti-fuse storage unit connected with the bit line.

[0069] In one embodiment of the present disclosure, the controlled switch unit comprises a transmission gate, which connects the bit line with each anti-fuse storage unit connected with the bit line when the output end of the comparator outputs a first level, and disconnects the bit line from each anti-fuse storage unit connected with the bit line when the output end of the comparator outputs a second level; one of the first level and the second level is low level, and the other is high level.

[0070] In one embodiment of the present disclosure, the controlled switch unit further comprises a D flip-flop and an inverter.

[0071] The first input end of the D flip-flop is connected with the output end of the comparator, and the first output end of the D flip-flop is directly connected with the first control end of the transmission gate.

[0072] The first output end of the inverter is connected with the second control end of the transmission gate through the inverter.

[0073] In one embodiment of the present disclosure, the current mirror comprises a first NMOS tube NM3 and a second NMOS tube NM4.

[0074] The drain of the first NMOS tube NM3 is connected with its gate and each anti-fuse storage unit connected with the bit line, and the source of the NMOS tube NM3 is connected with the controlled switch unit.

[0075] The drain of the second NMOS tube NM4 is connected with the first input end of the comparator, and the source of the NMOS tube NM4 is connected with the bit line.

[0076] It should be understood that, although each step in the flowchart of the present disclosure is shown in sequence according to the direction of the arrow, these steps are not necessarily executed in sequence according to the direction of the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart of the present disclosure can comprise multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps. The intersection of the conductive lines in FIGS. 2 to 6 of the present disclosure is indicated by a black dot, indicating that the intersecting conductive lines are connected, and no black dot indicates that the intersection is not connected.

[0077] In the description of the specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0078] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present disclosure.

[0079] The above-described embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. An antifuse memory comprising an antifuse memory array, said antifuse memory array comprising a plurality of antifuse memory cells, each said antifuse memory cell comprising an antifuse transistor, characterized by, The antifuse memory further comprises: a bit line; and a feedback network connected between the bit line and the at least one antifuse memory cell, for disconnecting the bit line from the at least one antifuse memory cell when it is detected that the current between the bit line and the at least one antifuse memory cell connected to the bit line meets a preset condition.

2. The antifuse memory of claim 1, wherein, The preset condition comprises: when programming data "1", the current between the bit line and the at least one antifuse memory cell connected to the bit line is greater than a preset threshold.

3. The antifuse memory of claim 1 or 2, wherein, The feedback network comprises: a current mirror, a current at a reference current terminal of the current mirror is the current between the bit line and the at least one antifuse memory cell connected to the bit line, the reference current terminal is connected to the at least one antifuse memory cell connected to the bit line; a comparator, a first input terminal of the comparator is connected to a copy current terminal of the current mirror, a second input terminal of the comparator is used for inputting a reference signal; and a controlled switch unit, a controlled terminal of the controlled switch unit is connected to an output terminal of the comparator, for controlling the connection and disconnection between the bit line and the at least one antifuse memory cell connected to the bit line.

4. The antifuse memory of claim 3, wherein, The controlled switch unit comprises a transmission gate, the transmission gate is used for: when the output terminal of the comparator outputs a first level, connecting the bit line and the at least one antifuse memory cell connected to the bit line; and when the output terminal of the comparator outputs a second level, disconnecting the bit line and the at least one antifuse memory cell connected to the bit line; wherein one of the first level and the second level is a low level, and the other is a high level.

5. The antifuse memory of claim 4, wherein, The controlled switch unit further comprises: a D flip-flop, a first input terminal of the D flip-flop is connected to the output terminal of the comparator, a first output terminal of the D flip-flop is directly connected to a first control terminal of the transmission gate; and an inverter, the first output terminal of the D flip-flop is connected to a second control terminal of the transmission gate through the inverter.

6. The antifuse memory of claim 3, wherein, The current mirror comprises: a first NMOS transistor, a drain of the first NMOS transistor is connected to a gate of the first NMOS transistor and the at least one antifuse memory cell connected to the bit line, a source of the first NMOS transistor is connected to the controlled switch unit; and a second NMOS transistor, a drain of the second NMOS transistor is connected to the first input terminal of the comparator, a source of the second NMOS transistor is connected to the bit line.

7. The antifuse memory of claim 1, wherein, Each of the antifuse memory cells further comprises a selection transistor, a controlled terminal of the selection transistor is connected to a word line of the antifuse memory array, a first terminal of the selection transistor is connected to the feedback network, and a second terminal of the selection transistor is connected to an antifuse transistor; a controlled terminal of the antifuse transistor is used for receiving a programming voltage.

8. The antifuse memory of claim 1, wherein, Further comprising a programming signal generation unit, the programming signal generation unit is used for outputting a third level to a plurality of the bit lines at the same time when programming data "1", the third level is a level opposite to a level on the corresponding bit line when programming data "0".

9. A programming method of an antifuse memory, the antifuse memory comprising an antifuse memory array, the antifuse memory array comprising a plurality of antifuse memory cells, the method comprising: in response to an operation of programming data "1" to the plurality of antifuse memory cells, detecting a current magnitude between a corresponding bit line in the antifuse memory and at least one antifuse memory cell connected to the bit line; if the current magnitude meets a preset condition, disconnecting the bit line from the at least one antifuse memory cell.

10. The method of programming an antifuse memory of claim 9, wherein, The operation of programming data "1" to the plurality of antifuse memory cells is simultaneously performed on a plurality of antifuse memory cells connected to the bit line.

11. The method of programming an antifuse memory of claim 9 or 10, wherein, The preset condition comprises: the current between the bit line and the at least one antifuse memory cell connected to the bit line is greater than a preset threshold when the operation of programming data "1" is performed.

12. The method of programming an antifuse memory of any of claims 9 to 11, wherein, The feedback network comprises: a current mirror, a current of a reference current terminal of the current mirror is the current between the bit line and the at least one antifuse memory cell connected to the bit line, the reference current terminal is connected to the at least one antifuse memory cell connected to the bit line; a comparator, a first input terminal of the comparator is connected to a copy current terminal of the current mirror, a second input terminal of the comparator is used for inputting a reference signal; and a controlled switch unit, a controlled terminal of the controlled switch unit is connected to an output terminal of the comparator, used for controlling the connection and disconnection between the bit line and the at least one antifuse memory cell connected to the bit line.

13. The method of programming an antifuse memory of claim 12, wherein, The controlled switch unit comprises a transmission gate, the transmission gate is used for: when a first level is outputted from the output terminal of the comparator, connecting the bit line and the at least one antifuse memory cell connected to the bit line; and when a second level is outputted from the output terminal of the comparator, disconnecting the bit line and the at least one antifuse memory cell connected to the bit line; wherein one of the first level and the second level is a low level, and the other is a high level.

14. The method of programming an antifuse memory of claim 13, wherein, The controlled switch unit further comprises: a D flip-flop, a first input terminal of the D flip-flop is connected to the output terminal of the comparator, a first output terminal of the D flip-flop is directly connected to a first control terminal of the transmission gate; and an inverter, the first output terminal of the D flip-flop is connected to a second control terminal of the transmission gate through the inverter.

15. The method of programming an antifuse memory of claim 12, wherein, The current mirror comprises: a first NMOS transistor, a drain of the first NMOS transistor is connected to a gate of the first NMOS transistor and the at least one antifuse memory cell connected to the bit line, a source of the first NMOS transistor is connected to the controlled switch unit; and a second NMOS transistor, a drain of the second NMOS transistor is connected to the first input terminal of the comparator, a source of the second NMOS transistor is connected to the bit line.

16. The method of programming an antifuse memory of any of claims 9 to 15, wherein, Each of the antifuse memory cells further comprises a selection transistor, a controlled terminal of the selection transistor is connected to a word line of the antifuse memory array, a first terminal of the selection transistor is connected to the feedback network, and a second terminal of the selection transistor is connected to an antifuse transistor; a controlled terminal of the antifuse transistor is used for receiving a programming voltage.

17. The method of programming an antifuse memory of any of claims 9 to 15, wherein, Further comprising: When the programming data is "1", the programming signal generating unit in the anti-fuse memory simultaneously outputs a third level to the plurality of bit lines, the third level being opposite to the level on the corresponding bit line when the programming data is "0".

Images