Pixel circuit, pixel driving method, and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel driving method, and a display apparatus. The pixel circuit comprises a light-emitting element, a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first energy storage circuit, a second energy storage circuit, and an turning-on / turning-off control circuit, wherein a first end of the first energy storage circuit is electrically connected to a control node, and a second end of the first energy storage circuit is electrically connected to a connection node; a first end of the second energy storage circuit is electrically connected to the connection node, and a second end of the second energy storage circuit is electrically connected to a second node; and controlled by a turning-on / turning-off control signal, the turning-on / turning-off control circuit controls the second node to be connected to or disconnected from an external compensation line. The present disclosure allows for hybrid internal and external compensation, such that internal compensation is used to perform threshold-voltage compensation, and external compensation is used to compensate for a change in mobility caused by a temperature-rise effect.

Description

Pixel circuit, pixel driving method and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410669591.5, filed on May 24, 2024 in China, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0004] The related pixel circuit cannot simultaneously perform internal-external mixed compensation, cannot simultaneously utilize internal compensation to perform threshold voltage compensation, and utilizes external compensation to compensate for mobility changes caused by temperature rise effects. SUMMARY

[0005] The main purpose of the present disclosure is to provide a pixel circuit, a pixel driving method and a display device, which solve the problems in the prior art that internal-external mixed compensation cannot be simultaneously performed, internal compensation cannot be simultaneously utilized to perform threshold voltage compensation, and external compensation is utilized to compensate for mobility changes caused by temperature rise effects.

[0006] In one aspect, the pixel circuit comprises a light emitting element, a driving circuit, a first light emitting control circuit, a second light emitting control circuit, a first energy storage circuit, a second energy storage circuit and a on-off control circuit.

[0007] The control end of the driving circuit is electrically connected with a control node, the first end of the driving circuit is electrically connected with a first node, the second end of the driving circuit is electrically connected with a connection node, and the driving circuit is used to generate a driving current under the control of the potential of the control node.

[0008] The first light emitting control circuit is electrically connected with a first light emitting control line, a power supply voltage end and the first node respectively, and is used to control the communication or disconnection between the power supply voltage end and the first node under the control of a first light emitting control signal provided by the first light emitting control line.

[0009] The second light emitting control circuit is electrically connected with a second light emitting control line, the connection node and a second node respectively, and is used to control the communication or disconnection between the connection node and the second node under the control of a second light emitting control signal provided by the second light emitting control line.

[0010] The first end of the first energy storage circuit is electrically connected with the control node, the second end of the first energy storage circuit is electrically connected with the connection node, and the first energy storage circuit is used to store electrical energy.

[0011] a first terminal of the second energy storage circuit is electrically connected with the connection node, and a second terminal of the second energy storage circuit is electrically connected with the second node, the second energy storage circuit being configured to store electrical energy;

[0012] the on-off control circuit is electrically connected with an on-off control line, the second node and an external compensation line respectively, and is configured to control the second node to be in communication or disconnected with the external compensation line under control of an on-off control signal provided by the on-off control line;

[0013] a first pole of the light-emitting element is electrically connected with the second node, and a second pole of the light-emitting element is electrically connected with a first voltage terminal.

[0014] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a data writing circuit.

[0015] the data writing circuit is electrically connected with a writing control line, a data line and the control node respectively, and is configured to write a data voltage on the data line into the control node under control of a writing control signal provided by the writing control line.

[0016] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a switch control circuit.

[0017] a first terminal of the switch control circuit is electrically connected with the external compensation line, a second terminal of the switch control circuit is electrically connected with an initial voltage terminal, and a third terminal of the switch control circuit is electrically connected with an external detection circuit, the switch control circuit being configured to control the external compensation line to be in communication or disconnected with the initial voltage terminal, and control the external compensation line to be in communication or disconnected with the external detection circuit.

[0018] when the switch control circuit controls the external compensation line to be in communication with the external detection circuit, the external detection circuit is configured to detect a voltage signal on the external compensation line.

[0019] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises an initialization circuit.

[0020] the initialization circuit is electrically connected with a reset control line, a reference voltage terminal and the control node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the control node under control of a reset control signal provided by the reset control line.

[0021] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a third energy storage circuit.

[0022] the third energy storage circuit is electrically connected with the external compensation line, and is configured to store electrical energy.

[0023] Optionally, the driving circuit comprises a driving transistor, the first light-emitting control circuit comprises a first transistor, and the second light-emitting control circuit comprises a second transistor; and the on-off control circuit comprises a third transistor.

[0024] The gate of the driving transistor is electrically connected to the control node, the first pole of the driving transistor is electrically connected to the first node, and the second pole of the driving transistor is electrically connected to the connection node.

[0025] The gate of the first transistor is electrically connected to the first light-emitting control line, the first pole of the first transistor is electrically connected to the power voltage terminal, and the second pole of the first transistor is electrically connected to the first node.

[0026] The gate of the second transistor is electrically connected to the second light-emitting control line, the first pole of the second transistor is electrically connected to the connection node, and the second pole of the second transistor is electrically connected to the second node.

[0027] The gate of the third transistor is electrically connected to the on-off control line, the first pole of the third transistor is electrically connected to the second node, and the second pole of the third transistor is electrically connected to the external compensation line.

[0028] Optionally, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor.

[0029] The first end of the first capacitor is electrically connected to the control node, and the second end of the first capacitor is electrically connected to the connection node.

[0030] The first end of the second capacitor is electrically connected to the connection node, and the second end of the second capacitor is electrically connected to the second node.

[0031] Optionally, the data writing circuit comprises a fourth transistor.

[0032] The gate of the fourth transistor is electrically connected to the writing control line, the first pole of the fourth transistor is electrically connected to the data line, and the second pole of the fourth transistor is electrically connected to the control node.

[0033] Optionally, the switch control circuit comprises a control switch.

[0034] The first end of the control switch is electrically connected to the external compensation line, the second end of the control switch is electrically connected to the initial voltage terminal, and the third end of the control switch is electrically connected to the external detection circuit.

[0035] Optionally, the initialization circuit comprises a fifth transistor.

[0036] The gate of the fifth transistor is electrically connected with a reset control line, the first pole of the fifth transistor is electrically connected with a reference voltage terminal, and the second pole of the fifth transistor is electrically connected with the control node.

[0037] In a second aspect, the pixel driving method is applied to the pixel circuit, and the pixel driving method comprises:

[0038] The driving circuit is controlled by the potential of the control node to generate a driving current.

[0039] The first light emitting control circuit is controlled by the first light emitting control signal to control the communication or disconnection between the power supply voltage terminal and the first node.

[0040] The second light emitting control circuit is controlled by the second light emitting control signal to control the communication or disconnection between the connection node and the second node.

[0041] The on-off control circuit is controlled by the on-off control signal to control the communication or disconnection between the second node and the external compensation line.

[0042] Optionally, the pixel circuit further comprises a data writing circuit and a switch control circuit; the display period of the pixel circuit comprises an internal compensation stage, a first data writing stage and a first light emitting stage arranged in sequence; and the pixel driving method comprises:

[0043] In the internal compensation stage, the first light emitting control circuit is controlled by the first light emitting control signal to control the communication between the power supply voltage terminal and the first node.

[0044] At the beginning of the internal compensation stage, the driving circuit is controlled by the potential of the control node to control the communication between the first node and the connection node, and the power supply voltage signal provided by the power supply voltage terminal is used to charge the first energy storage circuit and the second energy storage circuit until the driving circuit is turned off.

[0045] In the first data writing stage, the data writing circuit is controlled by the writing control signal to write the original data voltage on the data line into the control node.

[0046] In the first light emitting stage, the first light emitting control circuit is controlled by the first light emitting control signal to control the communication between the power supply voltage terminal and the first node; the second light emitting control circuit is controlled by the second light emitting control signal to control the communication between the connection node and the second node; and the driving circuit drives the light emitting element to emit light.

[0047] Optionally, the pixel circuit comprises an initialization circuit; the display period further comprises a reset stage arranged before the internal compensation stage; and the pixel driving method further comprises:

[0048] In the reset stage and the internal compensation stage, the initialization circuit writes the reference voltage provided by the reference voltage terminal into the control node under the control of a reset control signal;

[0049] In the reset stage, the switch control circuit controls the external compensation line to be connected with the initial voltage terminal, the second light emitting control circuit controls the connection node to be connected with the second node under the control of a second light emitting control signal, and the on-off control circuit controls the second node to be connected with the external compensation line under the control of an on-off control signal; the drive circuit controls the first node to be connected with the connection node under the control of the potential of the control node.

[0050] Optionally, the pixel circuit further comprises a third energy storage circuit; the display period further comprises a charging stage, a detection stage and a second data writing stage arranged in sequence after the first light emitting stage; and the pixel driving method further comprises:

[0051] In the charging stage, the switch control circuit controls the external compensation line to be disconnected with the initial voltage terminal and controls the external compensation line to be disconnected with the external detection circuit, the on-off control circuit controls the second node to be connected with the external compensation line under the control of an on-off control signal, the first light emitting control circuit controls the power voltage terminal to be connected with the first node under the control of a first light emitting control signal, the second light emitting control circuit controls the connection node to be connected with the second node under the control of a second light emitting control signal, and the drive circuit controls the first node to be connected with the connection node under the control of the potential of the control node; the third energy storage circuit is charged by the power voltage signal;

[0052] In the detection stage, the on-off control circuit controls the second node to be disconnected with the external compensation line under the control of an on-off control signal, and the switch control circuit controls the external compensation line to be connected with the external detection circuit; and the external detection circuit detects the detection voltage on the external compensation line.

[0053] In the second data writing stage, the on-off control circuit controls the second node to be connected with the external compensation line under the control of an on-off control signal, the switch control circuit controls the external compensation line to be connected with the initial voltage terminal, and the data writing circuit writes the compensation data voltage on the data line into the control node under the control of a writing control signal; the compensation data voltage is a compensated data voltage calculated according to the original data voltage and a compensation coefficient, and the compensation coefficient can be calculated according to the detection voltage.

[0054] Optionally, the pixel driving method further comprises:

[0055] In the detection stage, the first light emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light emitting control signal; and the initialization circuit writes the reference voltage into the control node under the control of the reset control signal.

[0056] At the beginning of the detection stage, the driving circuit controls the communication between the first node and the connection node under the control of the potential of the control node, and charges the second energy storage circuit by the power voltage signal provided by the power voltage terminal until the driving circuit is turned off.

[0057] Optionally, the display period further comprises a second light emitting stage arranged after the second data writing stage; and the pixel driving method further comprises:

[0058] In the second light emitting stage, the first light emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light emitting control signal; the second light emitting control circuit controls the communication between the connection node and the second node under the control of the second light emitting control signal; and the driving circuit drives the light emitting element to emit light.

[0059] In a third aspect, the embodiments of the present disclosure provide a display device, comprising a plurality of rows and columns of pixels, wherein each pixel comprises a plurality of pixel circuits as described above.

[0060] Optionally, the pixel circuits comprised by at least one pixel in the same row are electrically connected to the same column of external compensation lines.

[0061] Optionally, the display device described in at least one embodiment of the present disclosure further comprises a switch control module, wherein the switch control module comprises a plurality of switch control circuits.

[0062] The first end of the switch control circuit is electrically connected to the external compensation line, the second end of the switch control circuit is electrically connected to the initial voltage terminal, and the third end of the switch control circuit is electrically connected to the external detection circuit; and the switch control circuit is used to control the communication or disconnection between the external compensation line and the initial voltage terminal, and control the communication or disconnection between the external compensation line and the external detection circuit.

[0063] When the switch control circuit controls the communication between the external compensation line and the external detection circuit, the external detection circuit is used to detect the voltage signal on the external compensation line.

[0064] Optionally, the at least one pixel in the same row comprises N pixel circuits.

[0065] The at least one pixel in the same row includes a pass-through control circuit in an nth pixel circuit, which is electrically connected with an nth pass-through control line, for controlling the second node in the nth pixel circuit to be in communication or disconnected with the external compensation line under the control of an nth pass-through control signal provided by the nth pass-through control line.

[0066] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0067] The pixel circuit described in the embodiments of the present disclosure can perform internal and external mixed compensation, utilize internal compensation to compensate threshold voltage, and utilize external compensation to compensate mobility change caused by temperature rise effect. BRIEF DESCRIPTION OF DRAWINGS

[0068] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0071] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] FIG. 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] FIG. 6 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 5;

[0074] FIG. 7 is a schematic diagram of three pixel circuits sharing an external compensation line;

[0075] FIG. 8 is a schematic diagram of six pixel circuits sharing an external compensation line. DETAILED DESCRIPTION

[0076] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present disclosure.

[0077] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole, and the other is referred to as the second pole.

[0078] In actual operation, when the transistor is a thin-film transistor or a field effect transistor, the first pole can be a drain, and the second pole can be a source; or the first pole can be a source, and the second pole can be a drain.

[0079] As shown in FIG. 1, the pixel circuit according to the embodiment of the present disclosure includes a light emitting element E1, a driving circuit 10, a first light emitting control circuit 11, a second light emitting control circuit 12, a first energy storage circuit 13, a second energy storage circuit 14, and a pass-through control circuit 15.

[0080] The control end of the driving circuit 10 is electrically connected with a control node G, the first end of the driving circuit 10 is electrically connected with a first node N1, the second end of the driving circuit 10 is electrically connected with a connection node S, and the driving circuit 10 is configured to generate a driving current under the control of the potential of the control node G.

[0081] The first light emitting control circuit 11 is electrically connected with a first light emitting control line EM1, a power voltage end ELVDD, and the first node N1, respectively, and is configured to control the communication or disconnection between the power voltage end ELVDD and the first node N1 under the control of a first light emitting control signal provided by the first light emitting control line EM1.

[0082] The second light emitting control circuit 12 is electrically connected with a second light emitting control line EM2, the connection node S, and a second node N2, respectively, and is configured to control the communication or disconnection between the connection node S and the second node N2 under the control of a second light emitting control signal provided by the second light emitting control line EM2.

[0083] The first end of the first energy storage circuit 13 is electrically connected with the control node G, and the second end of the first energy storage circuit 13 is electrically connected with the connection node S, and the first energy storage circuit 13 is configured to store electrical energy.

[0084] The first end of the second energy storage circuit 14 is electrically connected with the connection node S, and the second end of the second energy storage circuit 14 is electrically connected with the second node N2, and the second energy storage circuit 14 is configured to store electrical energy.

[0085] The pass-through control circuit 15 is electrically connected with a pass-through control line G3, the second node N2, and an external compensation line SL, respectively, and is configured to control the communication or disconnection between the second node N2 and the external compensation line SL under the control of a pass-through control signal provided by the pass-through control line G3.

[0086] The first pole of the light emitting element E1 is electrically connected with the second node N2, and the second pole of the light emitting element 31 is electrically connected with a first voltage end V1.

[0087] Optionally, the first voltage terminal can be a low voltage terminal.

[0088] The pixel circuit disclosed in the embodiments of the present disclosure can perform internal and external mixed compensation, utilize internal compensation to compensate threshold voltage, and utilize external compensation to compensate mobility change caused by temperature rise effect.

[0089] In at least one embodiment of the present disclosure, the pixel circuit further comprises a data writing circuit;

[0090] The data writing circuit is electrically connected with a writing control line, a data line and the control node respectively, and is configured to write a data voltage on the data line to the control node under control of a writing control signal provided by the writing control line.

[0091] In specific implementation, the pixel circuit can further comprise a data writing circuit, which writes a data voltage to a control node under control of a writing control signal, and performs data voltage writing.

[0092] The pixel circuit disclosed in at least one embodiment of the present disclosure further comprises a switch control circuit;

[0093] The first end of the switch control circuit is electrically connected with the external compensation line, the second end of the switch control circuit is electrically connected with the initial voltage terminal, and the third end of the switch control circuit is electrically connected with the external detection circuit; the switch control circuit is configured to control the external compensation line and the initial voltage terminal to be connected or disconnected, and control the external compensation line and the external detection circuit to be connected or disconnected;

[0094] When the switch control circuit controls the external compensation line and the external detection circuit to be connected, the external detection circuit is configured to detect a voltage signal on the external compensation line.

[0095] In specific implementation, the pixel circuit can further comprise a switch control circuit; the switch control circuit controls the external compensation line and the initial voltage terminal to be connected or disconnected, and controls the external compensation line and the external detection circuit to be connected or disconnected; when the switch control circuit controls the external compensation line and the external detection circuit to be connected, the external detection circuit detects a voltage signal on the external compensation line.

[0096] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the pixel circuit further comprises a data writing circuit 21 and a switch control circuit 22;

[0097] The data writing circuit 21 is electrically connected with the write control line G1, the data line DL and the control node G, respectively, for writing the data voltage on the data line DL to the control node G under the control of the write control signal provided by the write control line G1;

[0098] The first end of the switch control circuit 22 is electrically connected with the external compensation line SL, the second end of the switch control circuit 22 is electrically connected with the initial voltage terminal I1, and the third end of the switch control circuit 22 is electrically connected with the external detection circuit 20. The switch control circuit 22 is used for controlling the communication or disconnection between the external compensation line SL and the initial voltage terminal I1, and controlling the communication or disconnection between the external compensation line SL and the external detection circuit 20. The initial voltage terminal I1 is used for providing an initial voltage Vini.

[0099] When the switch control circuit 22 controls the communication between the external compensation line SL and the external detection circuit 20, the external detection circuit 20 is used for detecting the voltage signal on the external compensation line SL.

[0100] At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure, when in operation, the display period of the pixel circuit can include an internal compensation stage, a first data writing stage and a first light emitting stage arranged in sequence.

[0101] In the internal compensation stage, the first light emitting control circuit 11 controls the communication between the power voltage terminal ELVDD and the first node N1 under the control of the first light emitting control signal.

[0102] At the beginning of the internal compensation stage, the driving circuit 10 controls the communication between the first node N1 and the connection node S under the control of the potential of the control node G, and the power voltage signal provided by the power voltage terminal ELVDD charges the first energy storage circuit 13 and the second energy storage circuit 14 until the driving circuit 10 is turned off, so as to compensate the threshold voltage of the driving transistor included in the driving circuit 10.

[0103] In the first data writing stage, the data writing circuit 21 writes the original data voltage Vdata on the data line DL to the control node under the control of the write control signal.

[0104] In the first light emitting stage, the first light emitting control circuit 11 controls the communication between the power voltage terminal ELVDD and the first node N1 under the control of the first light emitting control signal; the second light emitting control circuit 12 controls the communication between the connection node S and the second node N2 under the control of the second light emitting control signal, and the driving circuit drives the light emitting element E1 to emit light.

[0105] At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure works as follows. In the internal compensation stage, the on-off control circuit 15 controls the second node N2 to communicate with the external compensation line SL under the control of the on-off control signal provided by the on-off control line G3, and the switch control circuit 22 controls the external compensation line SL to communicate with the initial voltage terminal I1; the initial voltage terminal I1 is used to provide an initial voltage Vini.

[0106] In at least one embodiment of the present disclosure, the pixel circuit further comprises an initialization circuit.

[0107] The initialization circuit is electrically connected with a reset control line, a reference voltage terminal and the control node respectively, and is used to write a reference voltage provided by the reference voltage terminal into the control node under the control of a reset control signal provided by the reset control line.

[0108] In specific implementation, the pixel circuit can further comprise an initialization circuit, which writes a reference voltage into a control node under the control of a reset control signal, and initializes the potential of the control node.

[0109] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit according to at least one embodiment of the present disclosure further comprises an initialization circuit 31.

[0110] The initialization circuit 31 is electrically connected with a reset control line G2, a reference voltage terminal REF and the control node G respectively, and is used to write a reference voltage Vref provided by the reference voltage terminal REF into the control node G under the control of a reset control signal provided by the reset control line G2.

[0111] At least one embodiment of the pixel circuit shown in FIG. 3 of the present disclosure works as follows. The display period further comprises a reset stage arranged before the internal compensation stage.

[0112] In the reset stage and the internal compensation stage, the initialization circuit 31 writes a reference voltage Vref provided by the reference voltage terminal REF into the control node G under the control of a reset control signal.

[0113] In the reset stage, the switch control circuit 22 controls the external compensation line SL to communicate with the initial voltage terminal I1, the second light-emitting control circuit 12 controls the connection node S to communicate with the second node N2 under the control of a second light-emitting control signal, the on-off control circuit 15 controls the second node N2 to communicate with the external compensation line SL under the control of an on-off control signal, and the drive circuit 10 controls the first node N1 to communicate with the connection node S under the control of the potential of the control node G; the initial voltage terminal I1 provides an initial voltage Vini to N1, N2 and S.

[0114] The pixel circuit in at least one embodiment of the present disclosure further comprises a third energy storage circuit;

[0115] The third energy storage circuit is electrically connected with the external compensation line, and is used for storing electric energy.

[0116] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit in at least one embodiment of the present disclosure further comprises a third energy storage circuit 32;

[0117] The third energy storage circuit 32 is electrically connected with the external compensation line SL, and is used for storing electric energy.

[0118] In at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure, in operation, the display period further comprises a charging stage, a detection stage and a second data writing stage which are arranged in sequence after the first light-emitting stage;

[0119] In the charging stage, the switch control circuit 22 controls the external compensation line SL to be disconnected with the initial voltage terminal I1, controls the external compensation line SL to be disconnected with the external detection circuit 20, the on-off control circuit 15 controls the second node N2 to be connected with the external compensation line SL under the control of the on-off control signal, the first light-emitting control circuit 11 controls the power voltage terminal ELVDD to be connected with the first node N1 under the control of the first light-emitting control signal, the second light-emitting control circuit 12 controls the connection node S to be connected with the second node N2 under the control of the second light-emitting control signal, the driving circuit 10 controls the first node N1 to be connected with the connection node S under the control of the potential of the control node G, and the third energy storage circuit 32 is charged by the power voltage signal;

[0120] In the detection stage, the on-off control circuit 15 controls the second node N2 to be disconnected with the external compensation line SL under the control of the on-off control signal, the switch control circuit 22 controls the external compensation line SL to be connected with the external detection circuit 20, and the external detection circuit 20 detects the detection voltage on the external compensation line SL; the compensation coefficient can be calculated according to the detection voltage;

[0121] In the second data writing stage, the on-off control circuit 15 controls the second node N2 to be connected with the external compensation line SL under the control of the on-off control signal, the switch control circuit 22 controls the external compensation line SL to be connected with the initial voltage terminal I1, and the data writing circuit 21 writes the compensation data voltage on the data line SL into the control node G under the control of the writing control signal; the compensation data voltage is a compensated data voltage calculated according to the original data voltage Vdata and the compensation coefficient, so as to compensate the mobility change caused by the temperature rise effect by using external compensation.

[0122] At least one embodiment of the pixel circuit shown in Figure 4 of the present disclosure works as follows. In the detection phase, the first light emitting control circuit 11 controls the communication between the power voltage terminal ELVDD and the first node N1 under the control of the first light emitting control signal; the initialization circuit 31 writes the reference voltage Vref into the control node G under the control of the reset control signal;

[0123] At the beginning of the detection phase, the driving circuit 10 controls the communication between the first node N1 and the connection node S under the control of the potential of the control node G, and charges the second energy storage circuit 14 by the power voltage signal provided by the power voltage terminal ELVDD until the driving circuit 10 is turned off, so as to compensate the threshold voltage of the driving transistor included in the driving circuit 10;

[0124] The display period further includes a second light emitting phase arranged after the second data writing phase.

[0125] In the second light emitting phase, the first light emitting control circuit 11 controls the communication between the power voltage terminal ELVDD and the first node N1 under the control of the first light emitting control signal; the second light emitting control circuit 12 controls the communication between the connection node S and the second node N2 under the control of the second light emitting control signal, and the driving circuit 10 drives the light emitting element E1 to emit light.

[0126] Optionally, the external compensation circuit can be an ADC (analog-to-digital conversion) circuit, but is not limited thereto.

[0127] Optionally, the driving circuit includes a driving transistor, the first light emitting control circuit includes a first transistor, the second light emitting control circuit includes a second transistor, and the on-off control circuit includes a third transistor.

[0128] The gate of the driving transistor is electrically connected with the control node, the first pole of the driving transistor is electrically connected with the first node, and the second pole of the driving transistor is electrically connected with the connection node.

[0129] The gate of the first transistor is electrically connected with the first light emitting control line, the first pole of the first transistor is electrically connected with the power voltage terminal, and the second pole of the first transistor is electrically connected with the first node.

[0130] The gate of the second transistor is electrically connected with the second light emitting control line, the first pole of the second transistor is electrically connected with the connection node, and the second pole of the second transistor is electrically connected with the second node.

[0131] The gate of the third transistor is electrically connected with the on-off control line, the first pole of the third transistor is electrically connected with the second node, and the second pole of the third transistor is electrically connected with the external compensation line.

[0132] Optionally, the first tank circuit comprises a first capacitor, and the second tank circuit comprises a second capacitor.

[0133] A first end of the first capacitor is electrically connected with the control node, and a second end of the first capacitor is electrically connected with the connection node.

[0134] A first end of the second capacitor is electrically connected with the connection node, and a second end of the second capacitor is electrically connected with the second node.

[0135] Optionally, the data writing circuit comprises a fourth transistor.

[0136] A gate of the fourth transistor is electrically connected with the writing control line, a first pole of the fourth transistor is electrically connected with the data line, and a second pole of the fourth transistor is electrically connected with the control node.

[0137] Optionally, the switch control circuit comprises a control switch.

[0138] A first end of the control switch is electrically connected with the external compensation line, a second end of the control switch is electrically connected with the initial voltage end, and a third end of the control switch is electrically connected with the external detection circuit.

[0139] Optionally, the initialization circuit comprises a fifth transistor.

[0140] A gate of the fifth transistor is electrically connected with the reset control line, a first pole of the fifth transistor is electrically connected with the reference voltage end, and a second pole of the fifth transistor is electrically connected with the control node.

[0141] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the light emitting element is an organic light emitting diode O1.

[0142] The driving circuit comprises a driving transistor DT, the first light emitting control circuit comprises a first transistor T1, the second light emitting control circuit comprises a second transistor T2, and the on-off control circuit comprises a third transistor T3.

[0143] A gate of the driving transistor DT is electrically connected with the control node G, a drain of the driving transistor DT is electrically connected with the first node N1, and a source of the driving transistor DT is electrically connected with the connection node S.

[0144] A gate of the first transistor T1 is electrically connected with the first light emitting control line EM1, a drain of the first transistor T1 is electrically connected with the power voltage end ELVDD, and a source of the first transistor T1 is electrically connected with the first node N1.

[0145] The gate of the second transistor T2 is electrically connected with a second light-emitting control line EM2, the drain of the second transistor T2 is electrically connected with the connection node S, and the source of the second transistor T2 is electrically connected with a second node N2; the anode of O1 is electrically connected with the second node N2, and the cathode of O1 is electrically connected with a low-voltage terminal ELVSS;

[0146] The gate of the third transistor T3 is electrically connected with a turn-on / off control line G3, the drain of the third transistor T3 is electrically connected with the second node N2, and the source of the third transistor T3 is electrically connected with an external compensation line SL;

[0147] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0148] The first end of the first capacitor C1 is electrically connected with the control node G, and the second end of the first capacitor C1 is electrically connected with the connection node S;

[0149] The first end of the second capacitor C2 is electrically connected with the connection node S, and the second end of the second capacitor C2 is electrically connected with the second node N2;

[0150] The data writing circuit comprises a fourth transistor T4;

[0151] The gate of the fourth transistor T4 is electrically connected with the writing control line G1, the drain of the fourth transistor T4 is electrically connected with the data line DL, and the source of the fourth transistor T4 is electrically connected with the control node G;

[0152] The switch control circuit comprises a control switch K;

[0153] The first end of the control switch K is electrically connected with the external compensation line SL, the second end of the control switch K is electrically connected with an initial voltage terminal I1, and the third end of the control switch K is electrically connected with an external detection circuit 20;

[0154] The initialization circuit comprises a fifth transistor T5;

[0155] The gate of the fifth transistor T5 is electrically connected with a reset control line G2, the drain of the fifth transistor T5 is electrically connected with a reference voltage terminal REF, and the source of the fifth transistor T5 is electrically connected with the control node G;

[0156] The third energy storage circuit comprises a third capacitor C3;

[0157] The first end of C3 is electrically connected with the external compensation line SL, and the second end of C3 is electrically connected with a ground terminal GND.

[0158] In at least one embodiment of the pixel circuit shown in FIG. 5, all transistors are n-type transistors, but not limited thereto.

[0159] As shown in FIG. 6, in at least one embodiment of the pixel circuit shown in FIG. 5, during operation, a display period can include a reset stage S1, an internal compensation stage S2, a first data writing stage S3, a first light emitting stage S4, a charging stage S5, a detection stage S6, a second data writing stage S7 and a second light emitting stage S8 arranged in sequence.

[0160] In the reset stage S1, EM1 provides a low voltage signal, EM2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a high voltage signal, T2 is turned on, T5 is turned on, T3 is turned on, REF provides a reference voltage Vref to G, K controls the communication between SL and I1, and I1 provides an initial voltage Vini to N1, N2 and S.

[0161] In the internal compensation stage S2, EM1 provides a high voltage signal, EM2 provides a low voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a high voltage signal, K controls the communication between SL and I1, T3 is turned on, T1 is turned on, T5 is turned on, and REF provides a reference voltage Vref to G.

[0162] At the beginning of the internal compensation stage S2, DT is turned on, and ELVDD provides a power voltage signal to charge C1 and C2 until the potential of S is Vref-Vth, and then DT is turned off, and Vth is the threshold voltage of DT.

[0163] In the first data writing stage S3, EM1 provides a low voltage signal, EM2 provides a low voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, G3 provides a high voltage signal, K controls the communication between SL and I1, T4 is turned on, T3 is turned on, DL provides an original data voltage Vdata to G, and the potential Vs of S becomes Vref-Vth+(Vdata-Vref)×(C1z / (C1z+C2z)) due to the voltage division of C1 and C2; wherein C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0164] In the first light emitting stage S4, EM1 provides a high voltage signal, EM2 provides a high voltage signal, G1, G2 and G3 all provide low voltage signals, K controls the communication between SL and I1, T1 and T2 are turned on, and DT drives O1 to emit light.

[0165] In the first light emitting stage S4, Id is equal to K×(Vgs-Vth) 2 ;

[0166] Id equals to K x ((Vdata-Vref) x (C1z / (C1z+C2z)) 2 , so as to eliminate the influence of threshold voltage of DT on Id;

[0167] Id is driving current generated by DT, and K is current coefficient of DT;

[0168] In the charging stage S5, K controls SL to be disconnected with I1, K controls SL to be disconnected with external detection circuit 20, EM1 provides high voltage signal, EM2 provides high voltage signal, G1 provides low voltage signal, G2 provides high voltage signal, G3 provides high voltage signal, SL is in floating state, T1 is turned on, T2 is turned on, DT is turned on, REF provides reference voltage Vref to G, T3 is turned on, and ELVDD charges C3 through DT; Id equals to K x (Vgs-Vth) 2 ; Vgs is gate-source voltage of DT;

[0169] In the detection stage S6, EM1 and EM2 provide high voltage signal, G1 provides low voltage signal, G2 provides high voltage signal, G3 provides low voltage signal, K controls SL to be connected with external detection circuit 20, K controls SL to be disconnected with I1, T1 and T2 are turned on, T5 is turned on, and REF provides reference voltage Vref to G; external detection circuit 20 detects detection voltage on SL;

[0170] At the beginning of the detection stage S6, DT is turned on, and ELVDD provides power voltage signal to charge C1 and C2, changes potential of S, until potential of S is Vref-Vth, DT is turned off, and threshold voltage Vth of DT is compensated;

[0171] In the second data writing stage S7, EM1 and EM2 both provide low voltage signal, G1 provides high voltage signal, G2 provides low voltage signal, G3 provides high voltage signal, K controls SL to be disconnected with external detection circuit 20, K controls SL to be connected with I1, T3 is turned on, I1 provides initial voltage Vini to N2, T4 is turned on, and compensation data voltage Vdata2 on DL is written to G, so as to feed back change amount of mobility to compensation data voltage, Vdata2 equals to 0.5 (K1 / K2) x (Vdata-Vref)+Vref, wherein K1 / K2 is compensation coefficient, and the compensation coefficient equals to ratio of detection voltage and initial detection voltage; K1 / K2 can be ratio between current mobility of DT and original mobility of DT;

[0172] In the second light emitting stage S8, EM1 and EM2 both provide high voltage signal, G1, G2 and G3 all provide low voltage signal, K controls SL to be connected with I1, T1 and T2 are turned on, and DT drives O1 to emit light.

[0173] In at least one embodiment of the present disclosure, the initial detection voltage can be a detection voltage corresponding to an initial state of the mobility of the driving transistor DT when the display panel is powered on.

[0174] The pixel driving method according to the embodiments of the present disclosure is applied to the pixel circuit described above, and the pixel driving method comprises:

[0175] The driving circuit controls the driving current under the control of the potential of the control node;

[0176] The first light-emitting control circuit controls the communication or disconnection between the power supply voltage terminal and the first node under the control of the first light-emitting control signal;

[0177] The second light-emitting control circuit controls the communication or disconnection between the connection node and the second node under the control of the second light-emitting control signal;

[0178] The on-off control circuit controls the communication or disconnection between the second node and the external compensation line under the control of the on-off control signal.

[0179] In at least one embodiment of the present disclosure, the pixel circuit further comprises a data writing circuit and a switch control circuit; the display period of the pixel circuit comprises an internal compensation stage, a first data writing stage and a first light-emitting stage arranged in sequence; and the pixel driving method comprises:

[0180] In the internal compensation stage, the first light-emitting control circuit controls the communication between the power supply voltage terminal and the first node under the control of the first light-emitting control signal;

[0181] At the beginning of the internal compensation stage, the driving circuit controls the communication between the first node and the connection node under the control of the potential of the control node, and charges the first energy storage circuit and the second energy storage circuit by the power supply voltage signal provided by the power supply voltage terminal until the driving circuit is turned off;

[0182] In the first data writing stage, the data writing circuit writes the original data voltage on the data line to the control node under the control of the writing control signal;

[0183] In the first light-emitting stage, the first light-emitting control circuit controls the communication between the power supply voltage terminal and the first node under the control of the first light-emitting control signal; the second light-emitting control circuit controls the communication between the connection node and the second node under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

[0184] Optionally, the pixel circuit comprises an initialization circuit; the display period further comprises a reset stage arranged before the internal compensation stage; and the pixel driving method further comprises:

[0185] In the reset stage and the internal compensation stage, the initialization circuit writes the reference voltage provided by the reference voltage terminal into the control node under the control of a reset control signal;

[0186] In the reset stage, the switch control circuit controls the external compensation line to be in communication with the initial voltage terminal, the second light emitting control circuit controls the connection node to be in communication with the second node under the control of a second light emitting control signal, and the on-off control circuit controls the second node to be in communication with the external compensation line under the control of an on-off control signal; and the drive circuit controls the first node to be in communication with the connection node under the control of the potential of the control node.

[0187] In at least one embodiment of the present disclosure, the pixel circuit further comprises a third energy storage circuit; the display period further comprises, sequentially arranged after the first light emitting stage, a charging stage, a detection stage and a second data writing stage; and the pixel driving method further comprises:

[0188] In the charging stage, the switch control circuit controls the external compensation line to be disconnected from the initial voltage terminal and controls the external compensation line to be disconnected from the external detection circuit, the on-off control circuit controls the second node to be in communication with the external compensation line under the control of an on-off control signal, the first light emitting control circuit controls the power voltage terminal to be in communication with the first node under the control of a first light emitting control signal, the second light emitting control circuit controls the connection node to be in communication with the second node under the control of a second light emitting control signal, and the drive circuit controls the first node to be in communication with the connection node under the control of the potential of the control node; and the third energy storage circuit is charged by the power voltage signal.

[0189] In the detection stage, the on-off control circuit controls the second node to be disconnected from the external compensation line under the control of an on-off control signal, and the switch control circuit controls the external compensation line to be in communication with the external detection circuit; and the external detection circuit detects the detection voltage on the external compensation line.

[0190] In the second data writing stage, the on-off control circuit controls the second node to be in communication with the external compensation line under the control of an on-off control signal, the switch control circuit controls the external compensation line to be in communication with the initial voltage terminal, and the data writing circuit writes the compensation data voltage on the data line into the control node under the control of a writing control signal; the compensation data voltage is a compensated data voltage calculated according to the original data voltage and a compensation coefficient, and the compensation coefficient can be calculated according to the detection voltage.

[0191] The pixel driving method according to at least one embodiment of the present disclosure further comprises:

[0192] In the detection stage, the first light emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light emitting control signal; and the initialization circuit writes the reference voltage into the control node under the control of the reset control signal.

[0193] At the beginning of the detection stage, the driving circuit controls the communication between the first node and the connection node under the control of the potential of the control node, and charges the second energy storage circuit by the power voltage signal provided by the power voltage terminal until the driving circuit is turned off.

[0194] Optionally, the display cycle further comprises a second light emitting stage arranged after the second data writing stage; and the pixel driving method further comprises:

[0195] In the second light emitting stage, the first light emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light emitting control signal; the second light emitting control circuit controls the communication between the connection node and the second node under the control of the second light emitting control signal; and the driving circuit drives the light emitting element to emit light.

[0196] The display device disclosed in the embodiments of the present disclosure comprises a plurality of rows and columns of pixels, and each pixel comprises a plurality of pixel circuits as described above.

[0197] In at least one embodiment of the present disclosure, at least one pixel in the same row comprises pixel circuits electrically connected to the same column of external compensation lines, so as to reduce the number of columns of external compensation lines used and facilitate the realization of a narrow frame.

[0198] The display device disclosed in at least one embodiment of the present disclosure further comprises a switch control module, and the switch control module comprises a plurality of switch control circuits.

[0199] The first end of the switch control circuit is electrically connected to the external compensation line, the second end of the switch control circuit is electrically connected to the initial voltage terminal, and the third end of the switch control circuit is electrically connected to the external detection circuit. The switch control circuit is used to control the communication or disconnection between the external compensation line and the initial voltage terminal, and control the communication or disconnection between the external compensation line and the external detection circuit.

[0200] When the switch control circuit controls the communication between the external compensation line and the external detection circuit, the external detection circuit is used to detect the voltage signal on the external compensation line.

[0201] Optionally, the switch control circuit can comprise a control switch.

[0202] Optionally, the at least one pixel in the same row comprises N pixel circuits.

[0203] The at least one pixel in the same row includes a pass-through control circuit in an nth pixel circuit, which is electrically connected with an nth pass-through control line, for controlling the second node in the nth pixel circuit to be in communication or disconnected with the external compensation line under the control of an nth pass-through control signal provided by the nth pass-through control line.

[0204] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0205] In at least one embodiment of the present disclosure, the display device can include a plurality of rows and columns of pixels, and the pixels can include a plurality of pixel circuits. For example, the pixels can include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit can be a green pixel circuit, the second pixel circuit can be a red pixel circuit, and the third pixel circuit can be a blue pixel circuit.

[0206] As shown in FIG. 7, the three pixel circuits in one pixel can share one external compensation line SL.

[0207] P1 is the first pixel circuit, P2 is the second pixel circuit, and P3 is the third pixel circuit.

[0208] In FIG. 7, DT1 is the first drive transistor, T11 is the first first transistor, T12 is the first second transistor, T13 is the first third transistor, T14 is the first fourth transistor, T15 is the first fifth transistor, C11 is the first first capacitor, and C12 is the first second capacitor. O11 is the first organic light-emitting diode.

[0209] DT2 is the second drive transistor, T21 is the second first transistor, T22 is the second second transistor, T23 is the second third transistor, T24 is the second fourth transistor, T25 is the second fifth transistor, C21 is the second first capacitor, and C22 is the second second capacitor. O12 is the second organic light-emitting diode.

[0210] DT3 is the third drive transistor, T31 is the third first transistor, T32 is the third second transistor, T33 is the third third transistor, T34 is the third fourth transistor, T35 is the third fifth transistor, C31 is the third first capacitor, and C32 is the third second capacitor. O13 is the third organic light-emitting diode.

[0211] C3 is a third capacitor; G01 is a first control node, G02 is a second control node, and G03 is a third control node; N12 is a first second node, N22 is a second second node, and N32 is a third second node; K is a control switch, and SL is an external compensation line;

[0212] DLG is a first data line, DLR is a second data line, and DLB is a third data line; the first data line DLG is configured to provide a first data voltage, the second data line DLR is configured to provide a second data voltage, and the third data line DLB is configured to provide a third data voltage; the first data voltage can be a green data voltage, the second data voltage can be a red data voltage, and the third data voltage can be a blue data voltage;

[0213] G1 is a write control line, G2 is a reset control line, REF is a reference voltage terminal, ELVDD is a power voltage terminal, and ELVSS is a low voltage terminal; EM1 is a first light-emitting control line, and EM2 is a second light-emitting control line;

[0214] G13 is a first on-off control line, G23 is a second on-off control line, and G33 is a third on-off control line;

[0215] The gate of T13 is electrically connected to G13, the gate of T23 is electrically connected to G23, and the gate of T33 is electrically connected to G33;

[0216] The drain of T13 is electrically connected to the anode of O11, and the source of T13 is electrically connected to the external compensation line SL;

[0217] The drain of T23 is electrically connected to the anode of O12, and the source of T23 is electrically connected to the external compensation line SL;

[0218] The drain of T33 is electrically connected to the anode of O13, and the source of T33 is electrically connected to the external compensation line SL.

[0219] In at least one embodiment shown in FIG. 7, all transistors are n-type transistors.

[0220] In at least one embodiment of the pixel shown in FIG. 7, one display period can include three charging detection time periods which are independent of each other; the display period can further include a second data writing stage which is arranged after the three charging detection time periods;

[0221] The first charging detection time period can include a first charging stage and a first detection stage arranged in sequence, the second charging detection time period can include a second charging stage and a second detection stage arranged in sequence, and the third charging detection time period can include a third stage and a third detection stage arranged in sequence.

[0222] In the first charging stage, K control SL is disconnected with I1, K control SL is disconnected with the external detection circuit 20, EM1 provides a high voltage signal, EM2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G13 provides a high voltage signal, G23 and G33 both provide a low voltage signal, SL is in a floating state, T11 is turned on, T12 is turned on, DT1 is turned on, REF provides a reference voltage Vref to G01, T13 is turned on, ELVDD charges C3 through DT1;

[0223] In the first detection stage, EM1 and EM2 provide a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G13 provides a low voltage signal, K control SL is connected with the external detection circuit 20, K control SL is disconnected with I1, T11 and T12 are turned on, T15 is turned on, REF provides a reference voltage Vref to G01; the external detection circuit 20 detects the first detection voltage on SL; according to the first detection voltage on SL in the first detection stage, a first compensation coefficient can be obtained; the first compensation coefficient is the compensation coefficient of DT1;

[0224] In the second charging stage, K control SL is disconnected with I1, K control SL is disconnected with the external detection circuit 20, EM1 provides a high voltage signal, EM2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G23 provides a high voltage signal, G13 and G33 both provide a low voltage signal, SL is in a floating state, T21 is turned on, T22 is turned on, DT2 is turned on, REF provides a reference voltage Vref to G02, T23 is turned on, ELVDD charges C3 through DT2;

[0225] In the second detection stage, EM1 and EM2 provide a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G23 provides a low voltage signal, K control SL is connected with the external detection circuit 20, K control SL is disconnected with I1, T21 and T22 are turned on, T25 is turned on, REF provides a reference voltage Vref to G02; the external detection circuit 20 detects the second detection voltage on SL; according to the second detection voltage on SL in the second detection stage, a second compensation coefficient can be obtained; the second compensation coefficient is the compensation coefficient of DT2;

[0226] In the third charging stage, K control SL is disconnected with I1, K control SL is disconnected with external detection circuit 20, EM1 provides a high voltage signal, EM2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G33 provides a high voltage signal, G13 and G23 both provide a low voltage signal, SL is in a floating state, T31 is turned on, T32 is turned on, DT3 is turned on, REF provides a reference voltage Vref to G03, T33 is turned on, ELVDD charges C3 through DT3;

[0227] In the third detection stage, EM1 and EM2 provide a high voltage signal, G1 provides a low voltage signal, G2 provides a high voltage signal, G33 provides a low voltage signal, K control SL is connected with external detection circuit 20, K control SL is disconnected with I1, T31 and T32 are turned on, T35 is turned on, REF provides a reference voltage Vref to G03; external detection circuit 20 detects the third detection voltage on SL; according to the third detection voltage on SL in the second detection stage, a third compensation coefficient can be obtained; the third compensation coefficient is the compensation coefficient of DT3;

[0228] In the second data writing stage, G1 provides a high voltage signal, G2 provides a low voltage signal, G13, G23 and G33 all provide a high voltage signal, T13, T23 and T33 are all turned on, I1 provides an initial voltage Vini to N12, N22 and N32, T14 is turned on, the first compensation data voltage on DLG is written to G01, the second compensation data voltage on DLR is written to G02, and the third compensation data voltage on DLB is written to G03, the first compensation data voltage is a compensation data voltage calculated according to the first compensation coefficient and the first original data voltage, the second compensation data voltage is a compensation data voltage calculated according to the second compensation coefficient and the second original data voltage, and the third compensation data voltage is a compensation data voltage calculated according to the third compensation coefficient and the third original data voltage; EM1 and EM2 both provide a high voltage signal, T11 and T12 are turned on, T21 and T22 are turned on, T31 and T32 are turned on, DT1 drives O11 to emit light under the control of the potential of G01, DT2 drives O12 to emit light under the control of the potential of G02, and DT3 drives O13 to emit light under the control of the potential of G03.

[0229] At least one embodiment of the present disclosure shown in FIG. 7, when working, before the three charging detection time periods, the display period can include a reset stage, an internal compensation stage, a first data writing stage and a first light emitting stage;

[0230] After the second data writing stage, the display period can include a second light emitting stage.

[0231] In at least one embodiment of the present disclosure, the pixel circuits located in the same row can be electrically connected with the same row of write control lines, the same row of reset control lines, the same row of first light-emitting control lines and the same row of second light-emitting control lines, and the pixel circuits located in the same column can be electrically connected with the same column of data lines.

[0232] As shown in FIG. 8, one pixel can include three pixel circuits, and six pixel circuits included in two pixels can share one external compensation line SL;

[0233] P1 is the first pixel circuit, P2 is the second pixel circuit, P3 is the third pixel circuit, P4 is the fourth pixel circuit, P5 is the fifth pixel circuit, and P6 is the sixth pixel circuit;

[0234] In FIG. 8, DT1 is the first drive transistor, T11 is the first first transistor, T12 is the first second transistor, T13 is the first third transistor, T14 is the first fourth transistor, T15 is the first fifth transistor, C11 is the first first capacitor, and C12 is the first second capacitor; O11 is the first organic light-emitting diode;

[0235] DT2 is the second drive transistor, T21 is the second first transistor, T22 is the second second transistor, T23 is the second third transistor, T24 is the second fourth transistor, T25 is the second fifth transistor, C21 is the second first capacitor, and C22 is the second second capacitor; O12 is the second organic light-emitting diode;

[0236] DT3 is the third drive transistor, T31 is the third first transistor, T32 is the third second transistor, T33 is the third third transistor, T34 is the third fourth transistor, T35 is the third fifth transistor, C31 is the third first capacitor, and C32 is the third second capacitor; O13 is the third organic light-emitting diode;

[0237] DT4 is the fourth drive transistor, T41 is the fourth first transistor, T42 is the fourth second transistor, T43 is the fourth third transistor, T44 is the fourth fourth transistor, T45 is the fourth fifth transistor, C41 is the fourth first capacitor, and C42 is the fourth second capacitor; O14 is the fourth organic light-emitting diode;

[0238] The fifth driving transistor is labeled as DT5, the fifth first transistor is labeled as T51, the fifth second transistor is labeled as T52, the fifth third transistor is labeled as T53, the fifth fourth transistor is labeled as T54, the fifth fifth transistor is labeled as T55, the fifth first capacitor is labeled as C51, and the fifth second capacitor is labeled as C52; the fifth organic light emitting diode is labeled as O15;

[0239] The sixth driving transistor is labeled as DT6, the sixth first transistor is labeled as T61, the sixth second transistor is labeled as T62, the sixth third transistor is labeled as T63, the sixth fourth transistor is labeled as T64, the sixth fifth transistor is labeled as T65, the sixth first capacitor is labeled as C61, and the sixth second capacitor is labeled as C62; the sixth organic light emitting diode is labeled as O16;

[0240] The third capacitor is labeled as C3;

[0241] The first data line is labeled as DLG1, the second data line is labeled as DLR1, and the third data line is labeled as DLB1; the fourth data line is labeled as DLG2, the fifth data line is labeled as DLR2, and the sixth data line is labeled as DLB2;

[0242] The first data line DLG1 is used to provide a first data voltage, the second data line DLR1 is used to provide a second data voltage, and the third data line DLB1 is used to provide a third data voltage; the fourth data line DLG2 is used to provide a fourth data voltage, the fifth data line DLR2 is used to provide a fifth data voltage, and the sixth data line DLB2 is used to provide a sixth data voltage; the first data voltage and the fourth data voltage can be green data voltages, the second data voltage and the fifth data voltage can be red data voltages, and the third data voltage and the sixth data voltage can be blue data voltages;

[0243] The write control line is labeled as G1, the reset control line is labeled as G2, the reference voltage terminal is labeled as REF, the power voltage terminal is labeled as ELVDD, and the low voltage terminal is labeled as ELVSS; the first emission control line is labeled as EM1, and the second emission control line is labeled as EM2;

[0244] The first on-off control line is labeled as G13, the second on-off control line is labeled as G23, and the third on-off control line is labeled as G33; the fourth on-off control line is labeled as G43, the fifth on-off control line is labeled as G53, and the sixth on-off control line is labeled as G63;

[0245] The gate of T13 is electrically connected with G13, the gate of T23 is electrically connected with G23, and the gate of T33 is electrically connected with G33; the gate of T43 is electrically connected with G43, the gate of T53 is electrically connected with G53, and the gate of T63 is electrically connected with G63;

[0246] The drain of T13 is electrically connected with the anode of O11, and the source of T13 is electrically connected with the external compensation line SL;

[0247] The drain of T23 is electrically connected with the anode of O12, and the source of T23 is electrically connected with the external compensation line SL;

[0248] The drain of T33 is electrically connected with the anode of O13, and the source of T33 is electrically connected with the external compensation line SL;

[0249] The drain of T43 is electrically connected with the anode of O14, and the source of T43 is electrically connected with the external compensation line SL;

[0250] The drain of T53 is electrically connected with the anode of O15, and the source of T53 is electrically connected with the external compensation line SL;

[0251] The drain of T63 is electrically connected with the anode of O16, and the source of T63 is electrically connected with the external compensation line SL.

[0252] In at least one embodiment shown in FIG. 8, all the transistors are n-type transistors.

[0253] The above is the preferred embodiment of the present disclosure, it should be noted that for those skilled in the art, without departing from the principles of the present disclosure, can make several improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising a light emitting element, a driving circuit, a first light emitting control circuit, a second light emitting control circuit, a first energy storage circuit, a second energy storage circuit and a pass control circuit; a control terminal of the driving circuit is electrically connected with a control node, a first terminal of the driving circuit is electrically connected with a first node, a second terminal of the driving circuit is electrically connected with a connection node, and the driving circuit is configured to generate a driving current under the control of a potential of the control node; the first light emitting control circuit is electrically connected with a first light emitting control line, a power voltage terminal and the first node respectively, and is configured to control the communication or disconnection between the power voltage terminal and the first node under the control of a first light emitting control signal provided by the first light emitting control line; the second light emitting control circuit is electrically connected with a second light emitting control line, the connection node and a second node respectively, and is configured to control the communication or disconnection between the connection node and the second node under the control of a second light emitting control signal provided by the second light emitting control line; a first terminal of the first energy storage circuit is electrically connected with the control node, and a second terminal of the first energy storage circuit is electrically connected with the connection node, and the first energy storage circuit is configured to store electric energy; a first terminal of the second energy storage circuit is electrically connected with the connection node, and a second terminal of the second energy storage circuit is electrically connected with the second node, and the second energy storage circuit is configured to store electric energy; the pass control circuit is electrically connected with a pass control line, the second node and an external compensation line respectively, and is configured to control the communication or disconnection between the second node and the external compensation line under the control of a pass control signal provided by the pass control line; a first pole of the light emitting element is electrically connected with the second node, and a second pole of the light emitting element is electrically connected with a first voltage terminal.

2. The pixel circuit of claim 1, wherein, further comprising a data writing circuit; the data writing circuit is electrically connected with a writing control line, a data line and the control node respectively, and is configured to write a data voltage on the data line into the control node under the control of a writing control signal provided by the writing control line.

3. The pixel circuit of claim 1, wherein, further comprising a switch control circuit; a first terminal of the switch control circuit is electrically connected with the external compensation line, a second terminal of the switch control circuit is electrically connected with an initial voltage terminal, and a third terminal of the switch control circuit is electrically connected with an external detection circuit, and the switch control circuit is configured to control the communication or disconnection between the external compensation line and the initial voltage terminal, and control the communication or disconnection between the external compensation line and the external detection circuit; when the switch control circuit controls the communication between the external compensation line and the external detection circuit, the external detection circuit is configured to detect a voltage signal on the external compensation line.

4. The pixel circuit of claim 1, wherein, further comprising an initialization circuit; the initialization circuit is electrically connected with a reset control line, a reference voltage terminal and the control node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the control node under the control of a reset control signal provided by the reset control line.

5. The pixel circuit of claim 1, wherein, further comprising a third energy storage circuit; the third energy storage circuit is electrically connected with the external compensation line, and is configured to store electric energy.

6. The pixel circuit of claim 1, wherein, The driving circuit comprises a driving transistor, the first light-emitting control circuit comprises a first transistor, and the second light-emitting control circuit comprises a second transistor; and the on-off control circuit comprises a third transistor; The gate of the driving transistor is electrically connected with the control node, the first electrode of the driving transistor is electrically connected with the first node, and the second electrode of the driving transistor is electrically connected with the connection node; The gate of the first transistor is electrically connected with the first light-emitting control line, the first electrode of the first transistor is electrically connected with the power voltage terminal, and the second electrode of the first transistor is electrically connected with the first node; The gate of the second transistor is electrically connected with the second light-emitting control line, the first electrode of the second transistor is electrically connected with the connection node, and the second electrode of the second transistor is electrically connected with the second node; The gate of the third transistor is electrically connected with the on-off control line, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the external compensation line.

7. The pixel circuit of claim 1, wherein, The first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor; The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the connection node; The first end of the second capacitor is electrically connected with the connection node, and the second end of the second capacitor is electrically connected with the second node.

8. The pixel circuit of claim 2, wherein, The data writing circuit comprises a fourth transistor; The gate of the fourth transistor is electrically connected with the writing control line, the first electrode of the fourth transistor is electrically connected with the data line, and the second electrode of the fourth transistor is electrically connected with the control node.

9. The pixel circuit of claim 3, wherein, The switch control circuit comprises a control switch; The first end of the control switch is electrically connected with the external compensation line, the second end of the control switch is electrically connected with the initial voltage terminal, and the third end of the control switch is electrically connected with the external detection circuit.

10. The pixel circuit of claim 4, wherein, The initialization circuit comprises a fifth transistor; The gate of the fifth transistor is electrically connected with the reset control line, the first electrode of the fifth transistor is electrically connected with the reference voltage terminal, and the second electrode of the fifth transistor is electrically connected with the control node.

11. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 10, the pixel driving method comprising: The driving circuit generates a driving current under the control of the potential of the control node; The first light-emitting control circuit controls the communication or disconnection between the power voltage terminal and the first node under the control of the first light-emitting control signal; The second light-emitting control circuit controls the communication or disconnection between the connection node and the second node under the control of the second light-emitting control signal; The on-off control circuit controls the communication or disconnection between the second node and the external compensation line under the control of the on-off control signal.

12. The pixel driving method of claim 11, wherein, The pixel circuit further comprises a data writing circuit and a switch control circuit; The display period of the pixel circuit comprises an internal compensation stage, a first data writing stage and a first light-emitting stage arranged in sequence; The pixel driving method comprises: In the internal compensation stage, the first light-emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light-emitting control signal; At the beginning of the internal compensation stage, the driving circuit controls the communication between the first node and the connection node under the control of the potential of the control node, and charges the first energy storage circuit and the second energy storage circuit by the power voltage signal provided by the power voltage terminal until the driving circuit is turned off; In the first data writing stage, the data writing circuit writes the original data voltage on the data line into the control node under the control of the writing control signal; In the first light emitting stage, the first light emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light emitting control signal; the second light emitting control circuit controls the communication between the connection node and the second node under the control of the second light emitting control signal, and the driving circuit drives the light emitting element to emit light.

13. The pixel driving method of claim 12, wherein, The pixel circuit comprises an initialization circuit; the display cycle further comprises a reset stage arranged before the internal compensation stage; and the pixel driving method further comprises: In the reset stage and the internal compensation stage, the initialization circuit writes the reference voltage provided by the reference voltage terminal into the control node under the control of the reset control signal; In the reset stage, the switch control circuit controls the communication between the external compensation line and the initial voltage terminal, the second light emitting control circuit controls the communication between the connection node and the second node under the control of the second light emitting control signal, the on-off control circuit controls the communication between the second node and the external compensation line under the control of the on-off control signal, and the driving circuit controls the communication between the first node and the connection node under the control of the potential of the control node.

14. The pixel driving method of claim 13, wherein, The pixel circuit further comprises a third energy storage circuit; the display cycle further comprises a charging stage, a detection stage and a second data writing stage arranged in sequence after the first light emitting stage; The pixel driving method further comprises: In the charging stage, the switch control circuit controls the disconnection between the external compensation line and the initial voltage terminal, controls the disconnection between the external compensation line and the external detection circuit, the on-off control circuit controls the communication between the second node and the external compensation line under the control of the on-off control signal, the first light emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the first light emitting control signal, the second light emitting control circuit controls the communication between the connection node and the second node under the control of the second light emitting control signal, and the driving circuit controls the communication between the first node and the connection node under the control of the potential of the control node, and charges the third energy storage circuit by the power voltage signal; In the detection stage, the on-off control circuit controls the disconnection between the second node and the external compensation line under the control of the on-off control signal, the switch control circuit controls the communication between the external compensation line and the external detection circuit, and the external detection circuit detects the detection voltage on the external compensation line; In the second data writing stage, the on-off control circuit controls the second node to be in communication with the external compensation line under the control of the on-off control signal, the switch control circuit controls the external compensation line to be in communication with the initial voltage terminal, and the data writing circuit writes the compensation data voltage on the data line into the control node under the control of the writing control signal; the compensation data voltage is a compensated data voltage calculated according to the original data voltage and a compensation coefficient, and the compensation coefficient can be calculated according to the detection voltage.

15. The pixel driving method of claim 14, wherein, Further comprising: In the detection stage, the first light-emitting control circuit controls the power supply voltage terminal to be in communication with the first node under the control of the first light-emitting control signal; The initialization circuit writes the reference voltage into the control node under the control of the reset control signal; At the beginning of the detection stage, the driving circuit controls the first node to be in communication with the connection node under the control of the potential of the control node, and charges the second energy storage circuit by the power supply voltage signal provided by the power supply voltage terminal until the driving circuit is turned off.

16. The pixel driving method according to claim 14 or 15, wherein The display cycle further comprises a second light-emitting stage arranged after the second data writing stage; and the pixel driving method further comprises: In the second light-emitting stage, the first light-emitting control circuit controls the power supply voltage terminal to be in communication with the first node under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection node to be in communication with the second node under the control of the second light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

17. A display device comprising a plurality of rows and columns of pixels, the pixels comprising a plurality of pixel circuits according to any one of claims 1 to 10.

18. The display device of claim 17, wherein, At least one pixel located in the same row comprises a pixel circuit electrically connected with an external compensation line in the same column.

19. The display device of claim 18, wherein, Further comprising a switch control module, the switch control module comprising a plurality of switch control circuits; The first end of the switch control circuit is electrically connected with the external compensation line, the second end of the switch control circuit is electrically connected with the initial voltage terminal, and the third end of the switch control circuit is electrically connected with the external detection circuit; the switch control circuit is used for controlling the external compensation line to be in communication or disconnected with the initial voltage terminal, and controlling the external compensation line to be in communication or disconnected with the external detection circuit; When the switch control circuit controls the external compensation line to be in communication with the external detection circuit, the external detection circuit is used for detecting the voltage signal on the external compensation line.

20. A display device as claimed in claim 18 or 19, wherein, The at least one pixel located in the same row comprises N pixel circuits; The on-off control circuit in the nth pixel circuit of the at least one pixel located in the same row is electrically connected with an nth on-off control line, and is used for controlling the second node in the nth pixel circuit to be in communication or disconnected with the external compensation line under the control of an nth on-off control signal provided by the nth on-off control line; N is an integer greater than 1, and n is a positive integer less than or equal to N.

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