3D vertical interconnection packaging structure and preparation method therefor

Abstract

Provided in the present invention are a 3D vertical interconnection packaging structure and a preparation method therefor. A 3D interconnection structure with metal wires arranged at intervals and in parallel is prepared by means of combining wire bonding, packaging and cutting; and during bonding, the 3D interconnection structure is vertically arranged to form a 3D vertical interconnection structure. Thus, the spacing between metal wires in the 3D vertical interconnection structure can be controlled by means of controlling a wire bonding spacing in the 3D interconnection structure, the height of the metal wires in the 3D vertical interconnection structure is controlled by means of controlling the length of the metal wires in the 3D interconnection structure, and the size of contact points of the metal wires in the 3D vertical interconnection structure is controlled by means of controlling the wire diameter of the metal wires in the 3D interconnection structure. The present invention can realize high-density packaging with a flexible manufacturing process, has a wide application range, and can avoid the offset of the metal wires, thereby ensuring product quality.

Description

3D vertical interconnection packaging structure and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and relates to a 3D vertical interconnection packaging structure and a preparation method thereof. BACKGROUND

[0002] The rapid development of electronic products is the main driving force for the evolution of packaging technology today. Miniaturization, high density, high frequency, high speed, high reliability and low cost are the mainstream development direction of advanced packaging. Among them, system in package (SIP) is one of the most important and most potential technologies to meet this high-density system integration.

[0003] SIP packaging refers to a packaging method in which multiple functional chips such as processors, memories, etc. are integrated in a packaging structure according to application scenarios or packaging substrate layers, so as to realize complete functions through a packaging structure.

[0004] At present, in order to realize packaging miniaturization, 3D stacking is directly used for packaging. There are many methods for vertical interconnection, such as the metal wire interconnection formed by the vertical wire bonding method as shown in FIG. 1. However, in the metal wire interconnection formed by the vertical wire bonding method, since the vertical wire bonding does not have a second solder joint, but directly performs a pull-up and mechanical shearing operation after the first solder joint 10 is fixed, the metal wire formed thereby is not fixed and is prone to deviation, thereby making it difficult to ensure product quality.

[0005] Therefore, it is necessary to provide a 3D vertical interconnection packaging structure and a preparation method thereof. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a 3D vertical interconnection packaging structure and a preparation method thereof, which are used to solve the problem of metal wire deviation based on vertical wire bonding in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a 3D vertical interconnection packaging structure, comprising the following steps:

[0008] providing a first support substrate;

[0009] forming a solder joint contact layer on the first support substrate;

[0010] forming spaced metal wires on the solder joint contact layer by wire bonding, the first solder joint and the second solder joint of each metal wire being located on the solder joint contact layer, and each metal wire having a metal wire horizontal region with overlapping projections therebetween;

[0011] forming a first encapsulation layer on the solder contact layer, the first encapsulation layer covering the metal wires;

[0012] removing the first support substrate and the solder contact layer;

[0013] performing cutting to leave the horizontal section of the metal wires to form a 3D interconnection structure, and the opposite sides of the 3D interconnection structure each expose the first end and the second end of each of the metal wires;

[0014] providing a second support substrate;

[0015] forming a first re-wiring layer on the second support substrate;

[0016] rotating the 3D interconnection structure to bond the 3D interconnection structure on the first re-wiring layer to form a 3D vertical interconnection structure, so that the exposed first end of the metal wires is electrically connected with the first re-wiring layer, and a first chip is bonded on the first re-wiring layer and electrically connected with the first re-wiring layer;

[0017] forming a second encapsulation layer covering the 3D vertical interconnection structure and the first chip, and the second encapsulation layer exposing the second end of the metal wires;

[0018] forming a second re-wiring layer on the second encapsulation layer, the second re-wiring layer being electrically connected with the exposed second end of the metal wires;

[0019] bonding a second chip on the second re-wiring layer, the second chip being electrically connected with the second re-wiring layer;

[0020] removing the second support substrate to expose the first re-wiring layer;

[0021] forming a metal bump on the first re-wiring layer, the metal bump being electrically connected with the first re-wiring layer.

[0022] Optionally, the spaced metal wires formed on the solder contact layer are arranged in parallel or the metal wires are stacked from bottom to top.

[0023] Optionally, the spacing between the metal wires in the 3D vertical interconnection structure is 50-300 μm.

[0024] Optionally, the metal wires are perpendicular to the first re-wiring layer and the second re-wiring layer.

[0025] Optionally, the first support substrate comprises a wafer-level support substrate; and the second support substrate comprises a wafer-level support substrate.

[0026] Optionally, the method of cutting to form the 3D interconnection structure comprises one or a combination of mechanical cutting or laser cutting.

[0027] The present application also provides a 3D vertical interconnection package structure, comprising:

[0028] a first re-routed layer;

[0029] a 3D vertical interconnection structure bonded on the first re-routed layer, the 3D vertical interconnection structure comprising a first package layer and spaced and parallel metal wires in the first package layer, the 3D vertical interconnection structure exposing first ends and second ends of the metal wires, and the exposed first ends of the metal wires being electrically connected with the first re-routed layer;

[0030] a first chip bonded on the first re-routed layer, and the first chip being electrically connected with the first re-routed layer;

[0031] a second package layer covering the 3D vertical interconnection structure and the first chip, and the second package layer exposing the second ends of the metal wires;

[0032] a second re-routed layer on the second package layer, and the second re-routed layer being electrically connected with the exposed second ends of the metal wires;

[0033] a second chip bonded on the second re-routed layer, and the second chip being electrically connected with the second re-routed layer;

[0034] a metal bump on the first re-routed layer and electrically connected with the first re-routed layer.

[0035] Optionally, the spacing between the metal wires in the 3D vertical interconnection structure is 50-300 μm.

[0036] Optionally, the metal wires are perpendicular to the first re-routed layer and the second re-routed layer.

[0037] Optionally, there is an underfill layer filling the gap between the second chip and the second re-routed layer.

[0038] As described above, the 3D vertical interconnection packaging structure and the preparation method thereof can prepare the 3D interconnection structure with the spaced and parallel metal wires by the combination of the wire bonding, the packaging and the cutting, and the 3D interconnection structure is vertically arranged during the bonding to form the 3D vertical interconnection structure, so that the distance between the metal wires in the 3D vertical interconnection structure can be controlled by controlling the wire bonding distance in the 3D interconnection structure, the height of the metal wires in the 3D vertical interconnection structure can be controlled by controlling the length of the metal wires in the 3D interconnection structure, and the size of the contact points of the metal wires in the 3D vertical interconnection structure can be controlled by controlling the wire diameter of the metal wires in the 3D interconnection structure.

[0039] Therefore, the present application can realize the high-density packaging, the process is flexible, the application range is wide, the offset of the metal wires can be avoided, and the product quality can be ensured. BRIEF DESCRIPTION OF DRAWINGS

[0040] Fig. 1 shows a structure schematic diagram of the vertical wire bonding in the prior art.

[0041] Fig. 2 shows a process flow schematic diagram of preparing the 3D vertical interconnection packaging structure in the embodiment of the present application.

[0042] Fig. 3 shows a structure schematic diagram after forming the solder contact layer in the embodiment of the present application.

[0043] Fig. 4 shows a structure schematic diagram after forming the metal wires in the embodiment of the present application.

[0044] Fig. 5 shows a top view structure schematic diagram of the spaced metal wires formed in the embodiment of the present application.

[0045] Fig. 6 shows another top view structure schematic diagram of the spaced metal wires formed in the embodiment of the present application.

[0046] Fig. 7 shows a structure schematic diagram after forming the first packaging layer in the embodiment of the present application.

[0047] Fig. 8 shows a structure schematic diagram after removing the first support substrate and the solder contact layer in the embodiment of the present application.

[0048] Fig. 9 shows a structure schematic diagram during the cutting in the embodiment of the present application.

[0049] Fig. 10 shows a structure schematic diagram after forming the 3D interconnection structure in the embodiment of the present application.

[0050] Fig. 11 shows a structure schematic diagram after forming the first re-wiring layer in the embodiment of the present application.

[0051] Fig. 12 shows a structure schematic diagram after bonding the 3D interconnection structure and the first chip in the embodiment of the present application.

[0052] Figure 13 shows a schematic diagram of the structure after the formation of the second encapsulation layer in an embodiment of the present invention.

[0053] Figure 14 shows a schematic diagram of the structure after the formation of the second redistribution layer in an embodiment of the present invention.

[0054] Figure 15 shows a schematic diagram of the structure after bonding the second chip in an embodiment of the present invention.

[0055] Figure 16 shows a schematic diagram of the structure after removing the second support substrate to form metal bumps in an embodiment of the present invention.

[0056] Explanation of reference numerals in the attached figures: 111-First support substrate; 112-First separation layer; 113-First metal seed layer; 121-Second support substrate; 122-Second separation layer; 123-Second metal seed layer; 200-Solder contact layer; 300-Metal line; 301, 10-First solder joint; 302-Second solder joint; 303-Horizontal region of metal line; 410-First encapsulation layer; 420-Second encapsulation layer; 110-3D vertical interconnect structure; 510-First redistribution layer; 511-First metal wiring; 512-First dielectric layer; 520-Second redistribution layer; 521-Second metal wiring; 522-Second dielectric layer; 610-First chip; 620-Second chip; 700-Bottom fill layer; 800-Metal bump. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0059] For convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that these spatial relationship words are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. For example, the spatial relationship words can include embodiments in which the first and second features are arranged in direct contact, and embodiments in which other features are arranged between the first and second features such that the first and second features can not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0060] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and thus only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shape, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0061] As shown in FIG. 2, the present embodiment provides a preparation method of a 3D vertical interconnection packaging structure, wherein FIGS. 3-16 schematically show the structure diagrams of each step in the preparation of the 3D vertical interconnection packaging structure. The preparation of the 3D vertical interconnection packaging structure will be introduced below in combination with the drawings.

[0062] First, referring to FIG. 3, step S1 is performed to provide a first support substrate 111.

[0063] Specifically, the material of the first support substrate 111 can include an insulating material such as glass, silicon, epoxy resin, etc., and the specific type is not limited herein.

[0064] Preferably, the size of the first support substrate 111 is wafer level, so that subsequent preparation can be based on wafer level preparation, and after the cutting and separating process, a plurality of independent 3D interconnection structures can be prepared at the same time to improve the working efficiency of the process. For example, as shown in FIG. 10, the structure can be regarded as a schematic diagram of the independent 3D interconnection structure after rotation after cutting, but is not limited thereto. For example, according to the needs, the first support substrate 111 can also be non-wafer level.

[0065] When the first support substrate 111 is wafer level, the size of the first support substrate 111 can include, for example, 4 feet, 6 inches, 8 inches, 12 inches, etc., which are not limited herein.

[0066] In order to facilitate the subsequent removal of the first support substrate 111, in the embodiment, a first separation layer 112 is preferably formed on the surface of the first support substrate 111. The first separation layer 112 can be an optional light-thermal conversion (LTHC) layer formed by a light-thermal conversion (LTHC) coating material. In the subsequent operation, the LTHC coating material can be decomposed under heat to release the first support substrate 111, so as to facilitate the separation operation.

[0067] Next, referring to FIG. 3, step S2 is performed to form a solder contact layer 200 on the first support substrate 111.

[0068] In the embodiment, the solder contact layer 200 is formed by electroplating, so that the solder contact layer 200 and the first separation layer 112 have a first metal seed layer 113 therebetween. However, the preparation method of the solder contact layer 200 is not limited thereto. The first metal seed layer 113 can be, for example, a Ti / Cu stack. The material of the first metal seed layer 113 is not limited herein. The material of the solder contact layer 200 can be copper metal, but is not limited thereto.

[0069] Next, referring to FIG. 4, step S3 is performed to form spaced metal wires 300 on the solder contact layer 200 by wire bonding. The first solder joint 301 and the second solder joint 302 of each metal wire 300 are located on the solder contact layer 200. The metal wires 300 have overlapping metal wire horizontal regions 303.

[0070] Specifically, in the formed 3D interconnection structure, the number of metal wires 300 can be set as needed, such as 2, 3, 5, etc. The embodiment only illustrates the case of 3, but is not limited thereto.

[0071] During the wire bonding process, the first solder joint 301 and the second solder joint 302 corresponding to the metal wire 300 are both welded on the solder contact layer 200, so that a relatively firm weld can be formed. By controlling the wire bonding process, the metal wire 300 with the metal wire horizontal region 303 can be obtained.

[0072] The material of the metal wire 300 can be, for example, copper metal, but is not limited thereto.

[0073] Wherein, as shown in FIG. 5 and FIG. 6, the top view structure diagram of the formed spaced metal wires 300 is shown, as shown in FIG. 5, a plurality of parallel spaced metal wires 300 can be understood as a plurality of metal wires 300 horizontally spaced, and as shown in FIG. 6, a plurality of metal wires 300 are stacked from bottom to top, which can be understood as a plurality of metal wires 300 vertically spaced. The 3D interconnection structure formed in the two ways can constitute a 3D vertical interconnection structure 110 as shown in FIG. 10 after rotation to meet the needs of subsequent processes.

[0074] Next, referring to FIG. 7, step S4 is performed to form a first encapsulation layer 410 on the solder contact layer 200, and the first encapsulation layer 410 covers the metal wires 300.

[0075] Specifically, the method for forming the first encapsulation layer 410 can include but is not limited to compression molding, transfer molding and spin coating, and the material of the first encapsulation layer 410 can include but is not limited to epoxy resin and polyamide, and the material and preparation method of the first encapsulation layer 410 are not limited here.

[0076] Next, referring to FIG. 8, step S5 is performed to remove the first support substrate 111 and the solder contact layer 200.

[0077] Specifically, based on the first separation layer 112, the first support substrate 111 can be released by light / radiation, and after removing the first support substrate 111, the first metal seed layer 113 and the solder contact layer 200 can be removed by wet etching, but the method for removing the first support substrate 111 and the solder contact layer 200 is not limited to this.

[0078] Next, as shown in FIG. 9, step S6 is performed to cut and keep the metal wire horizontal region 303 to form the 3D interconnection structure, and the opposite sides of the 3D interconnection structure are exposed to the first end and the second end of each metal wire 300.

[0079] Wherein, during the cutting process, one or a combination of mechanical cutting or laser cutting can be used, which can be selected as needed and is not limited here. As shown in FIG. 9, in this embodiment, based on the wafer mount, mechanical cutting is used for cutting and separating operation, but the cutting method is not limited to this.

[0080] After cutting, the metal wire horizontal region 303 of the metal wire 300 in the 3D interconnection structure can be retained, and the first end and the second end of the metal wire 300 are exposed to facilitate subsequent electrical connection. As shown in FIG. 10, after cutting, the 3D vertical interconnection structure 110 formed by rotating the obtained 3D interconnection structure is shown.

[0081] Next, referring to FIG. 11, step S7 is performed to provide a second support substrate 121.

[0082] Specifically, the material of the second support substrate 121 can include materials such as glass, silicon, epoxy resin, metal, etc., and the specific type is not limited here, as long as it has a certain supporting effect.

[0083] Preferably, the size of the second support substrate 121 is wafer level, so that subsequent preparation can be based on wafer level preparation, and after the cutting and separating process, multiple independent packages can be prepared at the same time, to improve the working efficiency of the process. As shown in FIG. 16, the structure can be considered as an independent package formed after cutting, but is not limited thereto. For example, according to needs, the second support substrate 121 can also be non-wafer level.

[0084] When the second support substrate 121 is wafer level, the size of the second support substrate 121 can include, for example, 4 feet, 6 inches, 8 inches, 12 inches, etc., which are not limited here.

[0085] To facilitate subsequent removal of the second support substrate 121, in the present embodiment, a second separation layer 122 is preferably formed on the surface of the second support substrate 121. For example, the second separation layer 122 can be a light-heat conversion layer formed by light-heat conversion (LTHC) coating material, so that the LTHC coating material can be decomposed under heat, for example, by light / radiation (such as laser), to release the second support substrate 121, thereby achieving the convenience of separation operation.

[0086] Next, referring to FIG. 11, step S8 is performed to form a first re-wiring layer 510 on the second support substrate 121.

[0087] Specifically, the first re-wiring layer 510 includes a first metal wiring 511 and a first dielectric layer 512. The material of the first dielectric layer 512 can include polymers such as polybenzoxazole and polyimide, or inorganic dielectric materials such as silicon nitride and silicon oxide, which are not limited herein. The material of the first metal wiring 511 can include aluminum, copper, tungsten or alloys thereof, which are not limited herein. The specific structure, material and preparation method of the first re-wiring layer 510 are not limited herein, and can be referred to the prior art, such as a process combining photolithography, etching, electroplating or deposition to form the first re-wiring layer 510.

[0088] In this embodiment, the first metal wiring 511 is formed by electroplating, so that the first re-wiring layer 510 has a second metal seed layer 123, such as a Ti / Cu stack, between the first re-wiring layer 510 and the second separation layer 122. The material of the second metal seed layer 123 is not limited herein.

[0089] Then, referring to FIG. 12, step S9 is performed to rotate the 3D interconnection structure and bond the 3D interconnection structure on the first re-wiring layer 510 to form the 3D vertical interconnection structure 110, so that the first end of the exposed metal wire 300 is electrically connected to the first re-wiring layer 510, and a first chip 610 is bonded on the first re-wiring layer 510, and the first chip 610 is electrically connected to the first re-wiring layer 510.

[0090] Specifically, the sequence of bonding the 3D interconnection structure and the first chip 610 on the first re-wiring layer 510 is not limited herein, and can be selected as required, such as bonding the 3D interconnection structure first and then bonding the first chip 610, or bonding the first chip 610 first and then bonding the 3D interconnection structure. The bonding method of the 3D interconnection structure and the first chip 610 can be reflow soldering process or die attach (DA) process, which are not limited herein.

[0091] In the bonding of the 3D interconnection structure, the 3D interconnection structure needs to be rotated, so that the 3D interconnection structure is converted into the 3D vertical interconnection structure 110, and the first end of the exposed metal wire 300 is electrically connected to the first re-wiring layer 510. The rotation operation can be completed before bonding or during bonding, which is not limited herein.

[0092] The type of the first chip 610 is not limited herein and can be selected as required. The distribution and number of the first chip 610 and the 3D vertical interconnection structure 110 are not limited herein.

[0093] As an example, the pitch P between the metal wires 300 in the 3D vertical interconnection structure 110 can be 50-300 μιη.

[0094] Specifically, as shown in FIG. 10 and FIG. 16, by controlling the pitch between the metal wires 300 in the 3D interconnection structure, the pitch P between the metal wires 300 in the 3D vertical interconnection structure 110 can be reduced to, for example, 50-300 μιη, such as 50 μιη, 100 μιη, 150 μιη, 200 μιη, 300 μιη, etc. By controlling the length of the metal wires 300 in the 3D interconnection structure, the height H of the metal wires 300 in the 3D vertical interconnection structure 110 can be controlled to, for example, 200 μιη or more, such as 300 μιη, 500 μιη, etc. By controlling the diameter of the metal wires 300 in the 3D interconnection structure, the size of the contact points of the metal wires 300 in the 3D vertical interconnection structure 110, i.e., the size S shown in FIG. 10, can be controlled.

[0095] Therefore, high-density packaging can be achieved by the 3D vertical interconnection structure 110, and the process is flexible and has a wide range of applications. The offset of the metal wires 300 can be avoided to ensure product quality.

[0096] Next, as shown in FIG. 13, a second encapsulation layer 420 is formed in step S10, which encapsulates the 3D vertical interconnection structure 110 and the first chip 610, and exposes the second ends of the metal wires 300.

[0097] Specifically, the method for forming the second encapsulation layer 420 can include, but is not limited to, compression molding, transfer molding, and spin coating. The material of the second encapsulation layer 420 can include, but is not limited to, epoxy resin and polyamide. The material and preparation method of the second encapsulation layer 420 are not limited herein.

[0098] Preferably, a polishing step, such as chemical mechanical polishing (CMP), is performed when forming the second encapsulation layer 420 to expose the metal wires 300 and to planarize the surface, thereby facilitating subsequent process operations.

[0099] Further, in the polishing process, the back surface of the first chip 610 can also be thinned to facilitate size reduction of the package and to facilitate heat dissipation of the first chip 610.

[0100] Next, as shown in FIG. 14, a second redistribution layer 520 is formed on the second encapsulation layer 420 in step S11, which is electrically connected to the exposed second ends of the metal wires 300.

[0101] Specifically, the second re-wiring layer 520 comprises a second metal wiring 521 and a second dielectric layer 522, the material of the second dielectric layer 522 can comprise polymers such as polybenzoxazole, polyimide, or be formed by inorganic dielectric materials such as silicon nitride, silicon oxide, etc., which are not limited here; the material of the second metal wiring 521 can comprise aluminum, copper, tungsten, or alloys thereof, which are not limited here. The specific structure, material and preparation method of the second re-wiring layer 520 are not limited here, and can be referred to the prior art, such as the process of photolithography, etching, electroplating or deposition, etc. combined to form the second re-wiring layer 520.

[0102] Preferably, in the 3D vertical interconnection structure 110 after bonding, the metal wire 300 is vertically arranged with the first re-wiring layer 510 and the second re-wiring layer 520, that is, through the 3D vertical interconnection structure 110, an electric transmission path arranged vertically between the first re-wiring layer 510 and the second re-wiring layer 520 can be formed, thereby shortening the transmission path, reducing the transmission power consumption and improving the transmission efficiency.

[0103] Then, referring to FIG. 15, step S12 is performed to bond a second chip 620 on the second re-wiring layer 520, and the second chip 620 is electrically connected with the second re-wiring layer 520.

[0104] Specifically, the type of the second chip 620 is not limited here and can be selected as needed. To improve the stability of the bonding between the second chip 620 and the second re-wiring layer 520, a bottom filling layer 700 filling the gap is preferably formed between the second chip 620 and the second re-wiring layer 520 after bonding the second chip 620, and the material of the bottom filling layer 700 is not limited here as long as it ensures insulation.

[0105] Then, referring to FIG. 16, step S13 is performed to remove the second support substrate 121 to expose the first re-wiring layer 510.

[0106] Specifically, based on the second separation layer 122, the second support substrate 121 can be released by, for example, light / radiation, and after removing the second support substrate 121, the second metal seed layer 123 can be removed by, for example, wet etching, but the method for removing the second support substrate 121 is not limited thereto.

[0107] Then, referring to FIG. 16, step S14 is performed to form a metal bump 800 on the first re-wiring layer 510, and the metal bump 800 is electrically connected with the first re-wiring layer 510.

[0108] Specifically, the metal bump 800 can include a solder ball bump, a C4 metal bump, or the like, and the specific type and material of the metal bump 800 are not limited here.

[0109] Referring to FIG. 16, the present application also provides a 3D vertical interconnection packaging structure, which comprises:

[0110] a first re-wiring layer 510;

[0111] a 3D vertical interconnection structure 110 bonded on the first re-wiring layer 510, the 3D vertical interconnection structure 110 comprising a first packaging layer 410 and spaced and parallel metal wires 300 in the first packaging layer 410, the 3D vertical interconnection structure 110 exposing first and second ends of the metal wires 300, and the exposed first ends of the metal wires 300 being electrically connected with the first re-wiring layer 510;

[0112] a first chip 610 bonded on the first re-wiring layer 510, and the first chip 610 being electrically connected with the first re-wiring layer 510;

[0113] a second packaging layer 420 covering the 3D vertical interconnection structure 110 and the first chip 610, and the second packaging layer 420 exposing the second ends of the metal wires 300;

[0114] a second re-wiring layer 520 on the second packaging layer 420, and the second re-wiring layer 520 being electrically connected with the exposed second ends of the metal wires 300;

[0115] a second chip 620 bonded on the second re-wiring layer 520, and the second chip 620 being electrically connected with the second re-wiring layer 520;

[0116] a metal bump 800 on the first re-wiring layer 510 and electrically connected with the first re-wiring layer 510.

[0117] Specifically, the preparation method of the 3D vertical interconnection packaging structure can be prepared by the above-mentioned preparation method of the 3D vertical interconnection packaging structure, such as FIGS. 2-16, but is not limited thereto, and the present embodiment directly uses the above-mentioned preparation process to prepare the 3D vertical interconnection packaging structure, so that the preparation, material and specific structure of the 3D vertical interconnection packaging structure can be referred to the above-mentioned method.

[0118] As an example, the pitch between the metal wires 300 in the 3D vertical interconnection structure 110 can be 50-300 μm.

[0119] Specifically, as shown in FIG. 10 and FIG. 16, by controlling the pitch between the metal wires 300 in the 3D interconnection structure, the pitch P between the metal wires 300 in the 3D vertical interconnection structure 110 can be controlled to be reduced to, for example, 50-300 μm, such as 50 μm, 100 μm, 150 μm, 200 μm, 300 μm, etc., by controlling the length of the metal wires 300 in the 3D interconnection structure, the height H of the metal wires 300 in the 3D vertical interconnection structure 110 can be controlled to be, for example, 200 μm or more, such as 300 μm, 500 μm, etc., and by controlling the diameter of the metal wires 300 in the 3D interconnection structure, the size of the contact point of the metal wires 300 in the 3D vertical interconnection structure 110, i.e., the size S shown in FIG. 10, can be controlled.

[0120] Therefore, high-density packaging can be achieved by the 3D vertical interconnection structure 110, and the process is flexible and has a wide range of applications.

[0121] As an example, the metal wires 300 are perpendicular to the first re-routed layer 510 and the second re-routed layer 520.

[0122] Specifically, it is preferred that, after bonding, the metal wires 300 are arranged perpendicularly to the first re-routed layer 510 and the second re-routed layer 520 in the 3D vertical interconnection structure 110, i.e., by the 3D vertical interconnection structure 110, an electric transmission path arranged vertically between the first re-routed layer 510 and the second re-routed layer 520 can be formed, thereby shortening the transmission path, reducing transmission power consumption, and improving transmission efficiency.

[0123] As an example, the second chip 620 and the second re-routed layer 520 have a bottom filling layer 700 filling the gap therebetween.

[0124] Specifically, the bottom filling layer 700 can improve the stability of the bonding between the second chip 620 and the second re-routed layer 520, and the material of the bottom filling layer 700 is not limited here as long as it ensures insulation.

[0125] In summary, the 3D vertical interconnection packaging structure and the preparation method thereof can prepare the 3D interconnection structure with the spaced and parallel metal wires by the combination of wire bonding, packaging and cutting, and vertically arrange the 3D interconnection structure to form the 3D vertical interconnection structure during the bonding, so that the spacing between the metal wires in the 3D vertical interconnection structure can be controlled by controlling the wire bonding spacing in the 3D interconnection structure, the height of the metal wires in the 3D vertical interconnection structure can be controlled by controlling the length of the metal wires in the 3D interconnection structure, and the size of the contact points of the metal wires in the 3D vertical interconnection structure can be controlled by controlling the wire diameter of the metal wires in the 3D interconnection structure.

[0126] Therefore, the present application can realize high-density packaging, the process is flexible, the application range is wide, the offset of the metal wires can be avoided, and the product quality can be ensured.

[0127] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a 3D vertical interconnect packaging structure, characterized in that, The method comprises the following steps: providing a first support substrate; forming a solder contact layer on the first support substrate; forming spaced metal wires on the solder contact layer by wire bonding, each of the metal wires having a first solder joint and a second solder joint on the solder contact layer, and the metal wires having horizontally overlapped metal wire regions; forming a first encapsulation layer on the solder contact layer, the first encapsulation layer covering the metal wires; removing the first support substrate and the solder contact layer; cutting to form a 3D interconnection structure with the metal wire horizontal regions, and the 3D interconnection structure having exposed first ends and second ends of the metal wires on opposite sides; providing a second support substrate; forming a first re-wiring layer on the second support substrate; rotating the 3D interconnection structure to bond the 3D interconnection structure to the first re-wiring layer to form a 3D vertical interconnection structure, so that the exposed first ends of the metal wires are electrically connected to the first re-wiring layer, and a first chip is bonded to the first re-wiring layer and electrically connected to the first re-wiring layer; forming a second encapsulation layer covering the 3D vertical interconnection structure and the first chip, and the second encapsulation layer exposing the second ends of the metal wires; forming a second re-wiring layer on the second encapsulation layer, the second re-wiring layer being electrically connected to the exposed second ends of the metal wires; bonding a second chip to the second re-wiring layer, the second chip being electrically connected to the second re-wiring layer; removing the second support substrate to expose the first re-wiring layer; forming a metal bump on the first re-wiring layer, the metal bump being electrically connected to the first re-wiring layer.

2. The method of claim 1, wherein: The spaced metal wires formed on the solder contact layer are arranged in parallel or stacked from bottom to top.

3. The method of claim 1, wherein: The spacing between the metal wires in the 3D vertical interconnection structure is 50-300 μm.

4. The method of claim 1, wherein: The metal wires are perpendicular to the first re-wiring layer and the second re-wiring layer.

5. The method of claim 1, wherein: The first support substrate comprises a wafer-level support substrate, and the second support substrate comprises a wafer-level support substrate.

6. The method of claim 1, wherein: The method of cutting to form the 3D interconnection structure comprises one or a combination of mechanical cutting and laser cutting.

7. A 3D vertical interconnect package structure, characterized by, The 3D vertical interconnection package structure comprises: a first re-wiring layer; a 3D vertical interconnection structure bonded to the first re-wiring layer, the 3D vertical interconnection structure comprising a first encapsulation layer and spaced and parallel metal wires in the first encapsulation layer, the 3D vertical interconnection structure exposing first ends and second ends of the metal wires, and the exposed first ends of the metal wires being electrically connected to the first re-wiring layer; a first chip bonded to the first re-wiring layer and electrically connected to the first re-wiring layer; a second encapsulation layer covering the 3D vertical interconnection structure and the first chip, and the second encapsulation layer exposing the second ends of the metal wires. a second re-wiring layer on the second packaging layer, and the second re-wiring layer is electrically connected with the second end of the exposed metal wire; a second chip bonded on the second re-wiring layer, and the second chip is electrically connected with the second re-wiring layer; a metal bump on the first re-wiring layer and electrically connected with the first re-wiring layer.

8. The 3D vertical interconnect package structure of claim 7, wherein: The distance between the metal wires in the 3D vertical interconnection structure is 50-300 μm.

9. The 3D vertical interconnect package structure of claim 7, wherein: The metal wires are perpendicular to the first re-wiring layer and the second re-wiring layer.

10. The 3D vertical interconnect package structure of claim 7, wherein: There is an underfill layer filling the gap between the second chip and the second re-wiring layer.

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