Driving backplane, display panel, and display apparatus

Abstract

A driving backplane. The driving backplane comprises an output signal line (OSL), wherein the output signal line (OSL) is connected, by means of a first via hole (225), to the side of a first transfer portion (2141) that is away from a base substrate (1) and the side of a first active layer (204) that is away from the base substrate (1). Therefore, an electrically conductive path from the first transfer portion (2141) to the output signal line (OSL) and then from the output signal line (OSL) to the first active layer (204) can be formed. Further provided are a display panel comprising the driving backplane, and a display apparatus comprising the display panel.

Description

Driving backboard, display panel and display device

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410649675.2, filed May 23, 2024, entitled “Driving backboard, display panel and display device,” the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to a driving backboard, a display panel and a display device. BACKGROUND

[0004] With the increase of the pixel density (PPI) of the display device, the area of a single sub-pixel becomes smaller and smaller, so it is necessary to reduce the density of metal traces or the number of vias to reduce the area of the pixel driving circuit.

[0005] It should be noted that the information disclosed in the above background section of the application is only used to strengthen the understanding of the background of the application, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The present application aims to overcome the problem that the connection resistance between the first active layer and the first adapter becomes large, which reduces the current transmitted to the output signal line, thereby affecting the display effect of the display panel, and provides a driving backboard, a display panel and a display device.

[0007] According to one aspect of the present application, a driving backboard is provided, comprising a pixel driving circuit, the pixel driving circuit comprising a first transistor, a second transistor and an output signal line, the drain of the first transistor, the drain of the second transistor and the output signal line being connected to each other, the driving backboard further comprising a substrate, a first active layer, a first adapter layer and a first source-drain conductive layer, the first adapter layer being provided on one side of the substrate, the first adapter layer comprising a first adapter; the first active layer is provided in the same layer as the first adapter layer, and the first active layer is provided with a channel region, a source and a drain of the second transistor; the first source-drain conductive layer is provided on the side of the first active layer away from the substrate, and the first source-drain conductive layer is provided with the output signal line, the output signal line being connected to the side of the first adapter away from the substrate and the side of the first active layer away from the substrate through a first via.

[0008] In an embodiment of the present application, the first active layer extends from a side of the first transfer part to a side of the first transfer part away from the substrate, the part of the first active layer overlapping the first transfer part is a first overlap part, and a projection of the first via on the substrate overlaps a projection of the first overlap part on the substrate and a projection of the first transfer part on the substrate.

[0009] In an embodiment of the present application, the part of the first active layer not overlapping the first transfer part is a first non-overlap part, and a projection of the first via on the substrate overlaps a projection of the first non-overlap part on the substrate.

[0010] In an embodiment of the present application, the first active layer is spaced apart from the first transfer part along a first direction, and a projection of the first via on the substrate overlaps an end of the first transfer part on the substrate and an end of the first active layer on the substrate, respectively, which are close to each other along the first direction, the first direction being a direction in which the first active layer extends towards the first transfer part.

[0011] In an embodiment of the present application, the first transfer part extends from a side of the first active layer to a side of the first transfer part away from the substrate, the part of the first transfer part overlapping the first active layer is a second overlap part, and a projection of the first via on the substrate overlaps a projection of the second overlap part on the substrate and a projection of the first transfer part on the substrate.

[0012] In an embodiment of the present application, the projection of the first active layer on the substrate is located between the two edges of the projection of the first transfer part on the substrate along a second direction, and the projection of the first via on the substrate is located between the two edges of the projection of the first active layer on the substrate along the second direction, the second direction intersecting the first direction.

[0013] In an embodiment of the present application, the projection of the first active layer on the substrate is located between the two edges of the projection of the first transfer part on the substrate along a second direction, and the projection of the first via on the substrate is located between the two edges of the projection of the first active layer on the substrate along the second direction, the second direction intersecting the first direction.

[0014] In one embodiment of the present application, the driving backplane further comprises a second active layer, the second active layer is arranged between the substrate and the first transfer layer, the second active layer is provided with a channel region, a source and a drain of the first transistor, and the first transfer part is connected to a side of the second active layer away from the substrate through the second via.

[0015] In one embodiment of the present application, the pixel driving circuit further comprises a third transistor, a storage capacitor, a detection switch, a data signal line, a reset signal line and a power signal line, the power signal line is connected to the source of the first transistor for loading a power voltage, the drain of the first transistor is connected to the light emitting device, the gate of the first transistor is connected to the first node, the reset signal line is connected to the source of the second transistor for loading a capacitor reset control signal, the drain of the second transistor is connected to the second node, the gate of the second transistor is used for loading a scanning signal, the data signal line is connected to the source of the third transistor for loading a data signal, the drain of the third transistor is connected to the first node, the gate of the third transistor is used for loading a scanning signal, one end of the storage capacitor is connected to the first node, and the other end is connected to the second node, the detection switch is connected to the data signal line, and the detection switch is opened when the first transistor is closed, for outputting a detection voltage of the second node.

[0016] In one embodiment of the present application, the driving backplane further comprises a third active layer, the third active layer is arranged in the same layer as the second active layer, the third active layer is provided with a channel region, a source and a drain of the third transistor, the driving backplane further comprises a first gate layer, the first gate layer comprises a first scanning line and a first plate of the storage capacitor, a normal projection of the first plate of the storage capacitor on the substrate overlaps a normal projection of the channel region of the second active layer on the substrate, and is reused as the gate of the first transistor, a normal projection of the first scanning line on the substrate overlaps a normal projection of the channel region of the first active layer on the substrate, and is reused as the gate of the second transistor, and a normal projection of the first scanning line on the substrate overlaps a normal projection of the channel region of the third active layer on the substrate, and is reused as the gate of the third transistor.

[0017] In one embodiment of the present application, the driving backplane further comprises a second gate layer and a gate insulation part, the second gate layer comprises a second scanning line, a normal projection of the second scanning line on the substrate overlaps a normal projection of the first scanning line on the substrate, the gate insulation part is arranged between the first active layer and the second scanning line, and a normal projection of the gate insulation part on the substrate coincides with a normal projection of the second scanning line on the substrate.

[0018] In an embodiment of the present application, the driving backplane further comprises a second transfer layer, the second transfer layer is arranged between the first gate layer and the first transfer layer, the second transfer layer comprises a second plate of a storage capacitor, the second plate of the storage capacitor is connected with the first transfer part, the drain of the second transistor is connected with the storage capacitor, the first transfer layer further comprises a second transfer part, the second transfer part is connected with the first scan line and the drain of the third active layer, the drain of the third transistor is connected with the gate of the first transistor.

[0019] In an embodiment of the present application, the driving backplane further comprises a second source-drain conductive layer, the second source-drain conductive layer is arranged between the second active layer and the substrate, the second source-drain conductive layer is provided with a data signal line, the second transfer layer further comprises a third transfer part, the third transfer part is connected with the drain of the third active layer and the data signal line through a third via hole and a fourth via hole respectively, the first source-drain conductive layer is further provided with a power signal line, the power signal line is connected with the source of the second active layer through a fifth via hole, the driving backplane further comprises a third source-drain conductive layer, the third source-drain conductive layer is provided with a reset signal line, the reset signal line is connected with the drain of the first active layer through a sixth via hole or is connected with the drain of the first active layer through the source-drain transfer part of the first source-drain conductive layer.

[0020] According to still another aspect of the present application, there is provided a display panel comprising the driving backplane provided by any one of the aspects of the present application.

[0021] According to still another aspect of the present application, there is provided a display device comprising the display panel provided by the still another aspect of the present application.

[0022] The driving backplane of the present application comprises an output signal line, the output signal line is connected with the side of the first transfer part away from the substrate and the side of the first active layer away from the substrate through a first via hole, an electrically conductive path from the first transfer part to the output signal line and from the output signal line to the first active layer can be formed, even if the resistance between the first active layer and the first transfer part is large or even if the first active layer is broken, the mutual conduction between the output signal line, the first active layer and the first transfer part will not be affected, and the size of the electrical signal transmitted to the output signal line will not be affected, thus ensuring the display effect of the display panel.

[0023] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. It is to be understood that the drawings are only illustrations of some embodiments of the application and that, to one of ordinary skill in the art, other embodiments can be clearly inferred from the drawings without paying creative labor.

[0025] Fig. 1 is a circuit schematic diagram of a pixel driving circuit according to an embodiment of the present application.

[0026] Fig. 2 is a driving timing diagram of the pixel driving circuit according to an embodiment of the present application.

[0027] Fig. 3 is a sectional view of a driving backplane according to an embodiment of the present application, in which an output signal line is connected to a first non-lap portion through a first via.

[0028] Fig. 4 is an enlarged view of a portion A in Fig. 3.

[0029] Fig. 5 is a diagram of a distribution of doping ions in a first active layer according to an embodiment of the present application.

[0030] Fig. 6 is a sectional view of a driving backplane according to an embodiment of the present application, in which an output signal line is connected to a first adapter portion away from a substrate and a first active layer away from the substrate through a first via.

[0031] Fig. 7 is an enlarged view of a portion B in Fig. 6.

[0032] Fig. 8 is a diagram of a plane in which a normal projection of a first via on a substrate overlaps with a normal projection of a first lap portion and a second non-lap portion on the substrate, respectively, according to an embodiment of the present application.

[0033] Fig. 9 is a diagram of a structure in which a climbing height of a first active layer increases when a distance between a side of a second buffer layer away from a substrate and a side of a first adapter portion away from the substrate increases, according to an embodiment of the present application.

[0034] Fig. 10 is a sectional view of a driving backplane according to an embodiment of the present application, in which a first adapter portion extends from a side of a first active layer to a side of the first adapter portion away from a substrate.

[0035] Fig. 11 is a sectional view of a driving backplane according to an embodiment of the present application, in which a normal projection of a first via on a substrate overlaps with a normal projection of a first lap portion, a first non-lap portion and a second non-lap portion on the substrate, respectively, in a first direction.

[0036] Fig. 12 is an enlarged view of a portion C in Fig. 11.

[0037] FIG. 13 is a schematic view of a planar view of the first via in the first direction on the substrate wafer and the first overlap portion, the first non-overlap portion and the second non-overlap portion on the substrate wafer, according to an embodiment of the present application.

[0038] FIG. 14 is a schematic view of a cross section of the driving backplane when the three gate insulating layers in the first active layer non-channel region are removed and only the first active layer channel region is reserved, according to an embodiment of the present application.

[0039] FIG. 15 is a schematic view of a cross section of the driving backplane when the first active layer and the first transition portion are spaced apart in the first direction, according to an embodiment of the present application.

[0040] FIG. 16 is a schematic view of a planar view of the first via on the substrate wafer and the gap, the first transition portion on the substrate wafer and the first active layer on the substrate wafer, according to an embodiment of the present application.

[0041] FIG. 17 is a schematic view of a planar view of the first via, the first active layer and the first transition portion, according to an embodiment of the present application, when the first via on the substrate wafer in the first direction is located between the first active layer on the substrate wafer and the first transition portion on the substrate wafer. DETAILED DESCRIPTION

[0042] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as example embodiments so that this disclosure will be thorough and complete, and will fully convey the scope thereof to those skilled in the art. Like reference numerals refer to like elements throughout the specification. It will be understood that, although the terms first, second, first, second, first, second etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. It will be understood that when an element is referred to as being connected to or coupled to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., logically connected, logically coupled, communicatively connected, communicatively coupled, electrically connected, electrically coupled, operatively connected, operatively coupled, etc.).

[0043] Although relative terms such as "upper", "lower", "front", "rear", "left", "right", "horizontal", "vertical", "top" and "bottom" can be used herein to describe one component's or feature's relationship to another component or feature, these terms are used only to delineate one component or feature from another component or feature as illustrated in the drawings. It will be understood that if the device of the icon is turned upside down, the component described as being "on" will become the component described as being "under". When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" disposed on the other structure or that the structure is "indirectly" disposed on the other structure through another structure.

[0044] The terms "one", "a", "an", "the", and "at least one" are used to indicate the existence of one or more elements / components / etc.; the term "comprising" and "having" are used to indicate an open-ended inclusion of one or more elements / components / etc. in the description of a process, a method, an article, a creation, or a product, and that not only "comprising" and "having" but also "including" are used in the same way; the terms "first", "second", and "third" etc. are used only as labels, not as a numerical limitation.

[0045] In recent years, with the application of display devices in the field of augmented reality and virtual reality, the pixel density (PPI) of the display device gradually increases, and the area of a single sub-pixel becomes smaller and smaller, which puts higher and higher requirements on layout design and process capability, especially for some complex processes, such as low-temperature polycrystalline oxide display devices. When designing the layout, on the one hand, the space of the wire is squeezed due to the decrease of the area of a single pixel, which is prone to short circuit problems, thereby affecting the pixel density of the display panel; on the other hand, a plurality of vias are needed for electrical connection between different layers, and the increase of the number of vias will make the line width of the wire connected to the via larger, further affecting the pixel density of the display panel. Therefore, how to optimize from the aspects of layout design and process, etc., to reduce the density of metal wires and the number of vias, to improve the pixel density of the display panel, is also paid more and more attention.

[0046] As shown in FIG. 1, in order to improve the pixel density of the display panel and reduce the area of a single sub-pixel, the sub-pixel can adopt a 3T1C pixel driving circuit to improve the pixel density of the display panel by reducing the number of transistors in the pixel driving circuit. As shown, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C1, the source of the first transistor T1 is used to load a power supply voltage, the drain of the first transistor T1 is connected to a light emitting device OLED, the light emitting device OLED is connected to a common ground voltage VSS, the gate of the first transistor T1 is connected to a first node N1, the source of the second transistor T2 is used to load a storage capacitor C1 reset control signal V REF , the drain of the second transistor T2 is connected to a second node N2, the gate of the second transistor T2 is used to load a scan signal SCAN1, the source of the third transistor T3 is used to load a data signal Vdata, the drain of the third transistor T3 is connected to the first node N1, the gate of the third transistor T3 is used to load the scan signal SCAN1, one end of the storage capacitor C1 is connected to the first node N1, and the other end is connected to the second node N2.

[0047] The pixel driving circuit further comprises a data signal line DAL, a reset signal line VIL, a power signal line VDDL, a reset switch S_REF and a detection switch S_SAMP, the power signal line VDDL is connected with the source of the first transistor T1, and is used for loading a power voltage VDD, the reset signal line VIL is connected with the source of the second transistor T2, and is used for loading a reset control signal VREF of the storage capacitor C1, the data signal line DAL is connected with the source of the third transistor T3, and is used for loading a data signal Vdata, the detection switch S_SAMP is connected with the data signal line DAL, and is opened when the first transistor T1 is closed, and is used for outputting a detection voltage of the second node N2, and the detection switch S_SAMP is opened when the second transistor T2 and the third transistor T3 are opened, and is used for inputting the reset control signal VREF of the storage capacitor C1 to the first node N1 and the second node N2. The pixel driving circuit further comprises a scan signal line GL, the scan signal line GL is connected with the gate of the second transistor T2 and the gate of the third transistor T3, and is used for inputting a scan signal SCAN1.

[0048] The working principle of the 3T1C pixel circuit will be described in detail in combination with the circuit timing of FIG. 2.

[0049] The reset phase t1: the second transistor T2 and the third transistor T3 are opened, the gate of the first transistor T1, the first node N1 and the second node N2 are reset, at this time, V_N1=Vdata, V_N2=Vref; the compensation phase t2: Vgs=Vdata-Vref>Vth, the first transistor T1 is opened, VDD continuously charges N2 point through the first transistor T1, the potential of N2 point continuously rises with the charging process, Vgs gradually decreases, and the opening degree of the first transistor T1 gradually decreases, until Vs is charged to Vth different from Vg, the first transistor T1 is completely closed, at this time, V_N1=Vdata, V_N2=Vdata-Vth; the detection phase t3: the reset switch S_REF is opened, and V SENS =Vdata-Vth is read. The driving chip extracts Vdata-Vth and outputs it to the FPGA chip, and the FPGA chip outputs the compensation value after the algorithm to the driving chip, and then compensates Vdata. In this embodiment, the change range of Vdata can be within 5V.

[0050] As shown in FIG. 3, the driving backplane includes a substrate substrate 1 and a driving circuit layer 2, which can include a first buffer layer 201, a second buffer layer 202, a second active layer 203, a first active layer 204, a third active layer 205, a first gate insulation layer 206, a second gate insulation layer 207, a third gate insulation layer 208, a first gate layer 209, a second gate layer 210, a first interlayer dielectric layer 212, a second interlayer dielectric layer 213, a first transfer layer 214 and a second transfer layer 215. The first buffer layer 201 is arranged on one side of the substrate substrate 1, the second active layer 203 and the third active layer 205 are arranged on the side of the first buffer layer 201 away from the substrate substrate 1, the first gate insulation layer 206 is arranged on the side of the second active layer 203 away from the substrate substrate 1, the first gate layer 209 is arranged on the side of the first gate insulation layer 206 away from the substrate substrate 1, the second gate insulation layer 207 is arranged on the side of the first gate layer 209 away from the substrate substrate 1, the second transfer layer 215 is arranged on the side of the second gate insulation layer 207 away from the substrate substrate 1, the first interlayer dielectric layer 212 is arranged on the side of the second transfer layer 215 away from the substrate substrate 1, the second buffer layer 202 is arranged on the side of the first interlayer dielectric layer 212 away from the substrate substrate 1, the first transfer layer 214 and the first active layer 204 are arranged on the side of the second buffer layer 202 away from the substrate substrate 1, the third gate insulation layer 208 is arranged on the side of the first transfer layer 214 and the first active layer 204 away from the substrate substrate 1, the second gate layer 210 is arranged on the side of the third gate insulation layer 208 away from the substrate substrate 1, and the first interlayer dielectric layer 212 is arranged on the side of the second gate layer 210 away from the substrate substrate 1.

[0051] The first gate layer 209 can include a first plate CP1 of a storage capacitor, the first plate CP1 of the storage capacitor C1 has an orthogonal projection on the substrate substrate 1 overlapping the orthogonal projection of the channel region of the second active layer 203 on the substrate substrate 1, and is reused as the gate of the first transistor. The scan signal line GL can include a first scan line GL1 and a second scan line GL2, and the first gate layer 209 can further include the first scan line GL1, the orthogonal projection of the first scan line GL1 on the substrate substrate 1 overlapping the orthogonal projection of the channel region of the first active layer 204 on the substrate substrate 1, and being reused as the gate of the second transistor. The orthogonal projection of the first scan line GL1 on the substrate substrate 1 overlaps the orthogonal projection of the channel region of the third active layer 205 on the substrate substrate 1, and is reused as the gate of the third transistor. The second transfer layer includes a second plate CP2 of the storage capacitor C1, and the orthogonal projection of the second plate CP2 on the substrate substrate 1 overlaps the orthogonal projection of the first plate CP1 on the substrate substrate 1. The materials of the second active layer 203 and the third active layer 205 are low-temperature polysilicon, and the material of the first active layer 204 is indium gallium zinc oxide. The driving circuit layer 2 further includes a second gate layer 210, and the second gate layer includes a second scan line GL2, and the orthogonal projection of the second scan line GL2 on the substrate substrate 1 overlaps the orthogonal projection of the channel region of the first active layer on the substrate substrate 1, and is also reused as the gate of the second transistor. As shown in FIG. 10, the orthogonal projection of the second scan line GL2 on the substrate substrate 1 can overlap the orthogonal projection of the channel region of the third active layer 205 on the substrate substrate 1, and is also reused as the gate of the third transistor.

[0052] As shown in FIG. 3, the driving circuit layer 2 can further include a light shielding layer 216, a blocking layer 217, a first source-drain conductive layer 218, a second source-drain conductive layer 219, a third source-drain conductive layer 220, and a protective layer 221. The first source-drain conductive layer 218 is arranged on the side of the second interlayer dielectric layer 213 away from the substrate substrate 1, the protective layer 221 is arranged on the side of the first source-drain conductive layer 218 away from the substrate substrate 1, the third source-drain conductive layer 220 is arranged on the side of the protective layer 221 away from the substrate substrate 1, the blocking layer 217 is arranged between the first buffer layer 201 and the substrate substrate 1, the second source-drain conductive layer 219 is arranged between the blocking layer 217 and the substrate substrate 1, and the light shielding layer 216 is arranged between the blocking layer 217 and the first buffer layer 201. As shown in FIG. 10, the light shielding layer 216 can be arranged between the first buffer layer 201 and the blocking layer 217.

[0053] The first transfer layer 214 includes a first transfer part 2141 connected with the drain of the second active layer 203 through the second via hole 224, the first active layer 204 extends from the side of the first transfer part 2141 to the side of the first transfer part 2141 away from the substrate 1, and the first transfer part 2141 is connected with the second plate CP2 of the storage capacitor C1, so as to connect the second plate CP2 of the storage capacitor C1, the gate of the first transistor and the drain of the second transistor to the second node N2. The first transfer layer 214 further includes a second transfer part 2142 connected with the first scan line GL1 and the drain of the third active layer 205, and the drain of the third transistor, the first plate CP1 of the storage capacitor C1 and the gate of the first transistor are connected to the first node N1.

[0054] As shown in FIG. 3 and FIG. 4, the first source-drain conductive layer 218 is provided with an output signal line OSL connected with the side of the first active layer 204 away from the substrate 1 through the first via hole 225, the part of the first active layer 204 overlapped with the first transfer part 2141 is a first overlapped part, and the part of the first active layer 204 not overlapped with the first transfer part 2141 is a first non-overlapped part, and the output signal line OSL is connected with the first non-overlapped part. The second transfer layer 215 further includes a third transfer part 2151 connected with the drain of the third active layer 205 and the data signal line DAL through the third via hole 226 and the fourth via hole 227 respectively, the first source-drain conductive layer 218 is further provided with a power signal line VDDL connected with the source of the second active layer 203 through the fifth via hole 228, the second source-drain conductive layer 219 is provided with the data signal line DAL, and the third source-drain conductive layer 220 is provided with the reset signal line VIL. The source-drain transfer part 2181 can be arranged in the first source-drain conductive layer 218 and connected with the drain of the first active layer 204, and the reset signal line VIL is connected with the source-drain transfer part 2181. As shown in FIG. 10, the reset signal line VIL can be connected with the drain of the first active layer 204 through the sixth via hole.

[0055] The light shielding layer 216 includes a first light shielding part 2161 and a second light shielding part 2162, the first light shielding part 2161 is overlapped with the channel region of the second active layer 203 on the substrate 1, the first source-drain metal layer further includes a voltage adjustment trace DSL, the second transfer layer 215 further includes a fourth transfer part 2152, the voltage adjustment trace DSL is connected with the fourth transfer part 2152 through the seventh via hole, and the fourth transfer part 2152 is connected with the second light shielding part 2162 through the eighth via hole.

[0056] As shown in FIG. 5, since indium gallium zinc oxide is a semiconductor material, the source and the drain of the first active layer 204 generally need to be conductorized, but the doping ions 2041 generally make the first active layer 204 conductorized only on the side of the first active layer 204 far from the substrate 1, and the source and the drain are completely conductorized on the side of the source and the drain far from the substrate 1, but the source and the drain near the substrate 1 can not be conductorized. Of course, we can improve the energy, dose and other process parameters during implantation to implant the ions near the middle layer of the first active layer 204, or even implant the ions on the side of the first active layer 204 near the substrate 1. However, due to the blocking effect of the atoms of the first active layer 204 itself, the number of ions implanted on the side of the first active layer 204 far from the substrate 1 is much higher than the number of ions implanted on the side of the first active layer 204 near the substrate 1, that is, when the side of the first active layer 204 far from the substrate 1 is sufficiently conductorized, the side of the first active layer 204 near the substrate 1 can not be conductorized. Therefore, when the lower surface of the first active layer 204 in FIG. 4 forms a conductive path with the upper surface of the output signal line OSL, the side of the first active layer 204 near the substrate 1 can not be completely conductorized, resulting in an increase in the connection resistance between the drain of the first active layer 204 and the output signal line OSL, and directly affecting the display effect of the display panel.

[0057] To solve the problem that the current transmitted to the output signal line OSL is small due to the increase in the connection resistance between the first active layer 204 and the first transition part 2141, a display panel as shown in FIG. 6 is provided. As shown in FIG. 6, the output signal line OSL is connected to the side of the first transition part 2141 far from the substrate 1 and the side of the first active layer 204 far from the substrate 1 through the first via 225. As shown in FIG. 7, a conductive path from the first transition part 2141 to the output signal line OSL, and then from the output signal line OSL to the first active layer 204 can be formed, so that even if the resistance between the first active layer 204 and the first transition part 2141 is large, the mutual conduction between the output signal line OSL, the first active layer 204 and the first transition part 2141 is not affected, and the size of the electrical signal transmitted to the output signal line OSL is not affected, thereby ensuring the display effect of the display panel.

[0058] As shown in FIG. 8, the portion of the first transfer part 2141 that is not overlapped with the first active layer 204 is a second non-overlapped part, and the orthographic projection of the first transfer part 2141 on the substrate 1 along the first direction and the orthographic projection of the first active layer 204 on the substrate 1 along the first direction overlap with each other, specifically, the orthographic projection of the first via 225 on the substrate 1 along the first direction and the orthographic projection of the first overlapped part and the second non-overlapped part on the substrate 1 along the first direction overlap with each other respectively. The two edges of the orthographic projection of the first active layer 204 on the substrate 1 along the second direction are located between the two edges of the orthographic projection of the first transfer part 2141 on the substrate 1 along the second direction, and the two edges of the orthographic projection of the first via 225 on the substrate 1 along the second direction are located between the two edges of the orthographic projection of the first active layer 204 on the substrate 1 along the second direction, and the second direction is perpendicular to the first direction.

[0059] Generally, the thickness of the first transfer layer 214 is 100 nm, and the thickness of the first active layer 204 is 40 nm. When the first transfer layer 214 is thicker, such as more than 100 nm, the climbing difficulty of the first active layer 204 to the first transfer layer 214 increases, and even the first active layer 204 may be broken at the climbing position, thereby affecting the connection path at the position. When the slope angle of the sidewall of the first transfer part 2141 is larger, the climbing difficulty of the first active layer 204 to the first transfer part 2141 also increases, and even the first active layer 204 may be broken at the climbing position, thereby affecting the connection path at the position.

[0060] As shown in FIG. 9, the first transfer layer 214 is a metal layer. When the first transfer layer 214 is etched, dry etching may cause certain etching damage to the second buffer layer 202 below the first transfer layer 214, so that the distance between the side of the second buffer layer 202 away from the substrate 1 and the side of the first transfer part 2141 away from the substrate 1 increases, the climbing height of the first active layer 204 increases, and thus the climbing difficulty of the first active layer 204 increases, which may cause the first active layer 204 to be broken at the climbing position, thereby affecting the connection path at the position.

[0061] The thickness of the first active layer 204 is generally 40 nm. When the thickness of the first active layer 204 is reduced to less than 40 nm, the climbing ability of the first active layer 204 to the first transition part 2141 is weakened, and the first active layer 204 may even be broken at the climbing position, thereby affecting the connection path at the position. In order to reduce the thickness of the display panel, the part of the third gate insulating layer 208 in the non-channel region is considered to be etched, and only the gate insulating part 223 in the channel region is reserved. The dry etching plasma gas will cause etching damage to the climbing position of the first active layer 204. Since the climbing ability of the first active layer 204 at the position is weak in itself, after the etching damage is superimposed, the climbing ability of the first active layer 204 at the position is further affected, and in severe cases, the first active layer 204 may even be broken at the climbing position, thereby affecting the connection path at the position.

[0062] As shown in FIG. 10, the first transition part 2141 can be extended from the side of the first active layer 204 to overlap the side of the first transition part 2141 away from the substrate substrate 1. The part of the first transition part 2141 overlapping the first active layer 204 is a second overlap part. In the first direction, the orthogonal projection of the first via 225 on the substrate substrate 1 overlaps the orthogonal projection of the second overlap part on the substrate substrate 1 and the orthogonal projection of the first transition part 2141 on the substrate substrate 1. In this case, the first active layer 204 does not need to climb the slope angle of the first transition part 2141, and the breaking of the first active layer 204 is avoided.

[0063] As shown in FIGS. 11 and 12, the orthogonal projection of the first via 225 on the substrate substrate 1 can also overlap the orthogonal projection of the first transition part 2141 on the substrate substrate 1 and the orthogonal projection of the first active layer 204 on the substrate substrate 1 in the first direction. Compared with FIG. 6, the orthogonal projection of the first via 225 on the substrate substrate 1 overlaps the orthogonal projection of the first overlap part and the first non-overlap part on the substrate substrate 1. The output signal line OSL is connected to the first non-overlap part through the first via 225. Even if the climbing ability of the first active layer 204 to the first transition part 2141 is poor, or the first active layer 204 is broken at the climbing position, the mutual conduction between the output signal line OSL, the first active layer 204 and the first transition part 2141 is not affected, and the display effect of the display panel is ensured. The first active layer 204 has not been formed when the first transition layer 214 is etched, and therefore the etching damage to the first active layer 204 is avoided, thereby affecting the device characteristics of the second transistor.

[0064] As shown in FIG. 13, the orthogonal projection of the first via hole 225 on the substrate 1 along the first direction overlaps the orthogonal projection of the first lap portion, the first non-lap portion and the second non-lap portion on the substrate 1 respectively. The orthogonal projection of the first active layer 204 on the substrate 1 along the second direction is between the two edges of the orthogonal projection of the first transition portion 2141 on the substrate 1 along the second direction, and the orthogonal projection of the first via hole 225 on the substrate 1 along the second direction is between the two edges of the orthogonal projection of the first active layer 204 on the substrate 1 along the second direction, and the second direction is perpendicular to the first direction.

[0065] As shown in FIG. 14, the difference from FIG. 11 is that the third gate insulating layer 208 is removed at the part of the first active layer 204 non-channel region, only the part of the first active layer 204 channel region is reserved to form the gate insulating portion 223, the gate insulating portion 223 is arranged between the first active layer 204 and the second scan line GL2, and the orthogonal projection of the gate insulating portion 223 on the substrate 1 overlaps the orthogonal projection of the second scan line GL2 on the substrate 1. Even if the third gate insulating layer 208 is etched, the dry etching plasma gas causes the first active layer 204 to break at the ramp, which does not affect the connection path here.

[0066] As shown in FIG. 15 and FIG. 16, the first active layer 204 and the first transition portion 2141 can also be arranged apart along the first direction, along the first direction, the orthogonal projection of the first transition portion 2141 on the substrate 1 and the orthogonal projection of the first active layer 204 on the substrate 1 form a gap, and the orthogonal projection of the first via hole 225 on the substrate 1 overlaps the gap, the orthogonal projection of the first transition portion 2141 on the substrate 1, and the orthogonal projection of the first active layer 204 on the substrate 1 respectively. The orthogonal projection of the first active layer 204 on the substrate 1 along the second direction is between the two edges of the orthogonal projection of the first transition portion 2141 on the substrate 1 along the second direction, and the orthogonal projection of the first via hole 225 on the substrate 1 along the second direction is between the two edges of the orthogonal projection of the first active layer 204 on the substrate 1 along the second direction, and the second direction is perpendicular to the first direction.

[0067] As shown in Figure 17, the orthographic projection of the first transition portion 2141 on the substrate 1 along the first direction overlaps with the orthographic projection of the first active layer 204 on the substrate 1. The orthographic projection of the first via 225 on the substrate 1 along the first direction overlaps with the orthographic projections of the first overlapping portion, the first non-overlapping portion, and the second non-overlapping portion on the substrate 1, respectively. The orthographic projection of the first via 225 on the substrate 1 along the first direction is located between the two sides of the orthographic projection of the first transition portion 2141. The orthographic projection of the first via 225 on the substrate 1 along the other side of the first direction is located between one side of the orthographic projection of the first transition portion 2141 and the other side of the orthographic projection of the first active layer 204 that does not overlap. The two sides of the orthographic projection of the first active layer 204 on the substrate 1 along the second direction are located between the two sides of the orthographic projection of the first transition portion 2141 on the substrate 1 along the second direction. One side of the orthographic projection of the first via 225 on the substrate 1 along the second direction is located between the two sides of the orthographic projection of the first active layer 204 on the substrate 1 along the second direction. The other side of the orthographic projection of the first via 225 on the substrate 1 along the second direction is located between one side of the orthographic projection of the first active layer 204 on the substrate 1 and one side of the orthographic projection of the first transition portion 2141 on the substrate 1. The second direction is perpendicular to the first direction.

[0068] It should be noted that the first direction is the direction in which the first active layer 204 extends to the first transition part 2141, which is the x direction in Figures 8, 13, 16, and 17, and the second direction is the y direction in Figures 8, 13, 16, and 17. The second direction intersects with the first direction.

[0069] This invention also provides a display panel, which may include the driving backplate of any of the embodiments described above. The specific structure and beneficial effects of the display panel can be referred to the driving backplate, whose specific structure and beneficial effects have been described in detail above, and therefore will not be repeated here.

[0070] The display panel may also include a light-emitting layer 3, which is disposed on the side of the driving circuit layer 2 away from the substrate 1. The light-emitting layer 3 includes a pixel definition layer 32, which has a pixel opening. A light-emitting device is disposed in the pixel opening. The light-emitting device includes a pixel electrode 31, which is disposed on the side of the planarization layer 222 away from the substrate 1 and is at least partially exposed in the pixel opening.

[0071] This invention also provides a display device, which may include the display panel described in any of the above embodiments of this invention. The specific structure and beneficial effects of the display device can also be found in the driving backplate, and therefore will not be repeated here.

[0072] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts, such as the casing, circuit board, power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0073] When the display panel has the structure mentioned above, the display device can be a traditional electronic device, such as a mobile phone, computer, television and video recorder, or an emerging wearable device, such as virtual reality device and augmented reality device, which will not be listed here.

[0074] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention described herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not invented herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. A drive backplane, wherein, The pixel driving circuit comprises a first transistor, a second transistor and an output signal line, the drain of the first transistor, the drain of the second transistor and the output signal line are connected to each other, and the driving backplane further comprises: a substrate substrate; a first transfer layer is arranged on one side of the substrate substrate, the first transfer layer comprises a first transfer part; a first active layer is arranged in the same layer as the first transfer layer, the first active layer is provided with a channel region, a source and a drain of the second transistor; a first source-drain conductive layer is arranged on the side of the first active layer away from the substrate substrate, the first source-drain conductive layer is provided with the output signal line, and the output signal line is connected to the side of the first transfer part away from the substrate substrate and the side of the first active layer away from the substrate substrate through a first via hole.

2. The drive backplane of claim 1, wherein, The first active layer extends from the side of the first transfer part to overlap on the side of the first transfer part away from the substrate substrate, the part of the first active layer overlapping with the first transfer part is a first overlapping part, and the orthographic projection of the first via hole on the substrate substrate overlaps with the orthographic projection of the first overlapping part on the substrate substrate and the orthographic projection of the first transfer part on the substrate substrate along a first direction, the first direction being the direction in which the first active layer extends to the first transfer part.

3. The drive backplane of claim 2, wherein, The part of the first active layer not overlapping with the first transfer part is a first non-overlapping part, and the orthographic projection of the first via hole on the substrate substrate overlaps with the orthographic projection of the first non-overlapping part on the substrate substrate.

4. The drive backplane of claim 1, wherein, The first active layer and the first transfer part are arranged apart along a first direction, and along the first direction, the orthographic projection of the first via hole on the substrate substrate and the orthographic projection of the first transfer part on the substrate substrate and the orthographic projection of the first active layer on the substrate substrate are close to each other at one end, respectively, the first direction being the direction in which the first active layer extends to the first transfer part.

5. The drive backplane of claim 1, wherein, The first transfer part extends from the side of the first active layer to overlap on the side of the first transfer part away from the substrate substrate, the part of the first transfer part overlapping with the first active layer is a second overlapping part, and along a first direction, the orthographic projection of the first via hole on the substrate substrate overlaps with the orthographic projection of the second overlapping part on the substrate substrate and the orthographic projection of the first transfer part on the substrate substrate.

6. The drive backplane of claim 2, 3, or 5, wherein, The orthographic projection of the first active layer on the substrate substrate is located between the two edges of the orthographic projection of the first transfer part on the substrate substrate along a second direction, and the orthographic projection of the first via hole on the substrate substrate is located between the two edges of the orthographic projection of the first active layer on the substrate substrate along a second direction, the second direction intersecting the first direction.

7. The drive backplane of claim 3, wherein, A projection of the first active layer on the substrate substrate is located between projections of the first transfer part and the first via on the substrate substrate along a second direction, the first via is located between projections of the first active layer on the substrate substrate along the second direction, and the first via is located between a projection of the first active layer on the substrate substrate along the second direction and a projection of the first transfer part on the substrate substrate along the second direction.

8. The drive backplane of claim 1, wherein, The driving backplane further comprises a second active layer, the second active layer is arranged between the substrate substrate and the first transfer layer, and the second active layer is provided with a channel region, a source and a drain of the first transistor.

9. The drive backplane of claim 8, wherein, The pixel driving circuit further comprises a third transistor, a storage capacitor, a detection switch, a data signal line, a reset signal line and a power signal line, the power signal line is connected with the source of the first transistor and used for loading a power voltage, the drain of the first transistor is connected with a light emitting device, the gate of the first transistor is connected with a first node, the reset signal line is connected with the source of the second transistor and used for loading a capacitor reset control signal, the drain of the second transistor is connected with a second node, the gate of the second transistor is used for loading a scanning signal, the data signal line is connected with the source of the third transistor and used for loading a data signal, the drain of the third transistor is connected with the first node, the gate of the third transistor is used for loading a scanning signal, one end of the storage capacitor is connected with the first node, and the other end is connected with the second node, the detection switch is connected with the data signal line, and the detection switch is opened when the first transistor is closed, and is used for outputting a detection voltage of the second node.

10. The drive backplane of claim 9, wherein, The driving backplane further comprises a third active layer, the third active layer is arranged in the same layer as the second active layer, and the third active layer is provided with a channel region, a source and a drain of the third transistor, the driving backplane further comprises a first gate layer, the first gate layer comprises a first scanning line and a first plate of the storage capacitor, a projection of the first plate of the storage capacitor on the substrate substrate overlaps with a projection of the channel region of the second active layer on the substrate substrate, and is reused as a gate of the first transistor, a projection of the first scanning line on the substrate substrate overlaps with a projection of the channel region of the first active layer on the substrate substrate, and is reused as a gate of the second transistor, and a projection of the first scanning line on the substrate substrate overlaps with a projection of the channel region of the third active layer on the substrate substrate, and is reused as a gate of the third transistor.

11. The drive backplane of claim 10, wherein, The driving backplate further comprises a second gate layer and a gate insulation part, the second gate layer comprises a second scan line, a normal projection of the second scan line on the substrate substrate overlaps with a normal projection of the first scan line on the substrate substrate, the gate insulation part is arranged between the first active layer and the second scan line, a normal projection of the gate insulation part on the substrate substrate overlaps with a normal projection of the second scan line on the substrate substrate.

12. The drive backplane of claim 10, wherein, The driving backplate further comprises a second transfer layer, the second transfer layer is arranged between the first gate layer and the first transfer layer, the second transfer layer comprises a second plate of the storage capacitor, the second plate of the storage capacitor is connected with the first transfer part, the drain of the second transistor and the storage capacitor are connected, the first transfer layer further comprises a second transfer part, the second transfer part is connected with the first scan line and the drain of the third active layer, the drain of the third transistor and the gate of the first transistor are connected.

13. The drive backplane of claim 12, wherein, The driving backplate further comprises a second source-drain conductive layer, the second source-drain conductive layer is arranged between the second active layer and the substrate substrate, the second source-drain conductive layer is provided with the data signal line, the second transfer layer further comprises a third transfer part, the third transfer part is connected with the drain of the third active layer and the data signal line through a third via hole and a fourth via hole respectively, the first source-drain conductive layer is further provided with the power signal line, the power signal line is connected with the source of the second active layer through a fifth via hole, the driving backplate further comprises a third source-drain conductive layer, the third source-drain conductive layer is provided with the reset signal line, the reset signal line is connected with the drain of the first active layer through a sixth via hole, or is connected to the drain of the first active layer through a source-drain transfer part of the first source-drain conductive layer.

14. A display panel, wherein, The driving backplate comprises any one of claims 1 to 13.

15. A display device, wherein, The display panel comprises claim 14.

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