Embedded packaging structure, power supply, and manufacturing method

Abstract

Embodiments of the present application provide an embedded packaging structure, comprising a substrate frame, an inductor, a first capacitor, a second capacitor, a first chip, and a first plastic packaging layer. The inductor is embedded in the substrate frame; a first accommodating recess is formed at a first side of the inductor, and the first side is close to the upper surface of the substrate frame; a second accommodating recess is formed at a second side of the inductor, and the second side is close to the lower surface of the substrate frame; the first capacitor is arranged in the first accommodating recess; the second capacitor is arranged in the second accommodating recess; the first chip is surface-attached to the upper surface of the substrate frame and is covered by the first plastic packaging layer; and an electrical link is provided between the first capacitor and the first chip.

Description

An embedded packaging structure, power supply, and manufacturing method

[0001] This application claims priority to Chinese Patent Application No. CN202410649907.4, filed on May 23, 2024, entitled "An Embedded Packaging Structure, Power Supply and Manufacturing Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic component packaging, and more particularly to an embedded packaging structure, power supply, and manufacturing method. Background Technology

[0003] As power modules continue to evolve towards smaller size and higher integration, embedded component package (ECP) technology has been applied. This technology is a packaging method that embeds chips or components into a substrate.

[0004] As products iterate and upgrade, as shown in Figure 1, ECP packaging has evolved from embedding chips and capacitors to embedding inductors. In this technology, inductor devices are placed in the through-hole of the substrate, forming an embedded inductor structure. Capacitors and other resistors, capacitors, and surface-mount chips are mounted on the substrate surface. To protect these surface-mount devices and enhance their connection to the substrate, an organic molding compound is used to seal the surface-mount devices onto the substrate, forming a protective layer. The thickness of this molding compound depends on the maximum thickness of the surface-mount devices (to ensure coverage of all surface-mount devices).

[0005] However, in some scenarios, the thickness of the capacitor is greater than the thickness of the chip, which increases the thermal resistance of the chip to dissipate heat upwards, making it impossible to achieve the ideal heat dissipation effect. Summary of the Invention

[0006] This application provides an embedded packaging structure, a power supply, and a manufacturing method for improving the heat dissipation efficiency of a chip.

[0007] The first aspect of this application provides an embedded packaging structure:

[0008] The system includes a substrate frame, an inductor, a first capacitor, a second capacitor, a first chip, and a first molding compound. The inductor is embedded in the substrate frame, with a first receiving groove on one side near the upper surface of the substrate frame, and a second receiving groove on the other side near the lower surface of the substrate frame. The first capacitor is disposed in the first receiving groove, and the second capacitor is disposed in the second receiving groove. The first chip is surface-mounted on the upper surface of the substrate frame and is encapsulated by the first molding compound. An electrical link is established between the first capacitor and the first chip.

[0009] In this application, since the capacitors are embedded in the substrate frame and the chip is surface-mounted on the surface of the substrate frame, the first molding layer does not need to match the thickness of the capacitors, thereby improving the chip's heat dissipation efficiency. Furthermore, since capacitors are disposed in the receiving slots on both sides of the inductor, the integration density of the capacitor placement is improved.

[0010] In one possible implementation, the electrical link between the first capacitor and the first chip is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

[0011] In this application, the electrical link between the first capacitor and the first chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0012] In one possible implementation, the embedded package structure further includes a second chip and a second molding compound. The second chip is surface-mounted on the lower surface of the substrate frame and is encapsulated by the second molding compound. An electrical link is established between the second capacitor and the second chip.

[0013] In this application, the embedded packaging structure allows for surface mounting of chips on both sides, further improving integration.

[0014] In one possible implementation, the electrical link between the second capacitor and the second chip is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

[0015] In this application, the electrical link between the second capacitor and the second chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0016] In one possible implementation, the embedded package structure further includes a first pin disposed on the left and right sides of the substrate frame.

[0017] In this application, the embedded package structure can have pins coming out from the side, which improves the flexibility of connecting the embedded package structure with other electronic devices.

[0018] In one possible implementation, the embedded package structure further includes a second pin disposed on the upper and lower surfaces of the substrate frame.

[0019] In this application, the embedded package structure can also have pins coming out from the top and bottom surfaces, further improving the integration density.

[0020] A second aspect of this application provides a power source:

[0021] The power supply includes the embedded package structure as described in the first aspect above.

[0022] A third aspect of this application provides a manufacturing method, comprising:

[0023] An inductor, a first capacitor, and a tubular rigid resin are surface-mounted onto a first film. A first receiving groove is formed on the first side of the inductor, near the upper surface of the substrate frame. A second receiving groove is formed on the second side of the inductor, near the lower surface of the substrate frame. The first capacitor is disposed in the second receiving groove, and the inductor is disposed within a cavity formed by the tubular rigid resin and the first film. A second capacitor is surface-mounted onto a second film, and the second film is surface-mounted onto the upper surface of the tubular rigid resin, thus disposing the second capacitor within the first receiving groove. Liquid resin is injected into the cavity until the liquid resin completely fills the first receiving groove, the second receiving groove, and the cavity. The first and second films are removed to obtain a preliminary substrate frame. Resin material is pressed onto the upper and lower surfaces of the preliminary substrate frame to obtain the substrate frame. A first chip is surface-mounted onto the upper surface of the substrate frame and encapsulated by a first molding layer. An electrical link is established between the first chip and the first capacitor.

[0024] In this application, the manufacturing method described above embeds the capacitor within the substrate frame, while the chip is surface-mounted on the surface of the substrate frame. Therefore, the first molding layer does not need to match the thickness of the capacitor, thereby improving the chip's heat dissipation efficiency. Furthermore, since capacitors are disposed in the receiving slots on both sides of the inductor, the integration density of the capacitor placement is improved.

[0025] In one possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

[0026] In this application, the electrical link between the first capacitor and the first chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0027] In one possible implementation, the method also includes:

[0028] A second chip is surface-mounted on the lower surface of the substrate frame and wrapped with a second molding layer. An electrical link is established between the second chip and the second capacitor.

[0029] In this application, the embedded packaging structure allows for surface mounting of chips on both sides, further improving integration.

[0030] In one possible implementation, the electrical link between the second chip and the second capacitor is arranged in the vertical direction.

[0031] In this application, the electrical link between the second capacitor and the second chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0032] The fourth aspect of this application provides a manufacturing method, comprising:

[0033] The first capacitor and the tubular resin are surface-attached to the first membrane material, and the first capacitor is disposed in the cavity formed by the tubular rigid resin and the first membrane material.

[0034] A second capacitor is surface-mounted onto a second film, and the second film is surface-mounted onto the upper surface of a tubular rigid resin, thereby placing the second capacitor within a cavity. Magnetic slurry is injected into the cavity until it completely fills the cavity. The first and second films are removed to obtain a preliminary substrate frame. Resin material is pressed onto the upper and lower surfaces of the preliminary substrate frame to obtain the substrate frame itself. A first chip is surface-mounted onto the upper surface of the substrate frame and encapsulated by a first molding layer, establishing an electrical link between the first chip and the first capacitor.

[0035] In this application, the manufacturing method described above embeds the capacitor within the substrate frame, while the chip is surface-mounted on the surface of the substrate frame. Therefore, the first molding layer does not need to match the thickness of the capacitor, thereby improving the chip's heat dissipation efficiency. When the magnetic slurry solidifies, an inductor is formed, with receiving grooves formed on both sides of the inductor, each containing a capacitor, thus increasing the integration density of the capacitor placement. Furthermore, since the inductor can be manufactured by injecting magnetic slurry, the manufacturing cost of the inductor is reduced.

[0036] In one possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

[0037] In this application, the electrical link between the first capacitor and the first chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0038] In one possible implementation, the method also includes:

[0039] A second chip is surface-mounted on the lower surface of the substrate frame and wrapped with a second molding layer. An electrical link is established between the second chip and the second capacitor.

[0040] In this application, the embedded packaging structure allows for surface mounting of chips on both sides, further improving integration.

[0041] In one possible implementation, the electrical link between the second chip and the second capacitor is arranged in the vertical direction.

[0042] In this application, the electrical link between the second capacitor and the second chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0043] The fifth aspect of this application provides a manufacturing method, comprising:

[0044] An inductor, a first capacitor, and tubular rigid resin are surface-mounted onto a first film. A first receiving groove is formed on the first side of the inductor, near the upper surface of the substrate frame. A second receiving groove is formed on the second side of the inductor, near the lower surface of the substrate frame. The first capacitor is disposed in the second receiving groove, and the inductor is disposed within a cavity formed by the tubular rigid resin and the first film. Liquid resin is injected into the cavity until it completely fills the first receiving groove and half of the cavity. A second capacitor is surface-mounted onto a second film, and the second film is surface-mounted onto the upper surface of the tubular rigid resin, thus placing the second capacitor within the first receiving groove. Liquid resin is injected into the cavity until it completely fills the second receiving groove and the cavity. The first and second films are removed to obtain a preliminary substrate frame. Resin material is pressed onto the upper and lower surfaces of the preliminary substrate frame to obtain the substrate frame. A first chip is surface-mounted onto the upper surface of the substrate frame and encapsulated by a first molding layer. An electrical link is established between the first chip and the first capacitor.

[0045] In this application, the manufacturing method described above embeds the capacitor within the substrate frame, while the chip is surface-mounted on the surface of the substrate frame. Therefore, the first molding layer does not need to match the thickness of the capacitor, thereby improving the chip's heat dissipation efficiency. Furthermore, since capacitors are disposed in the receiving slots on both sides of the inductor, the integration density of the capacitor placement is improved.

[0046] In one possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

[0047] In this application, the electrical link between the first capacitor and the first chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0048] In one possible implementation, the method also includes:

[0049] A second chip is surface-mounted on the lower surface of the substrate frame and wrapped with a second molding layer. An electrical link is established between the second chip and the second capacitor.

[0050] In this application, the embedded packaging structure allows for surface mounting of chips on both sides, further improving integration.

[0051] In one possible implementation, the electrical link between the second chip and the second capacitor is arranged in the vertical direction.

[0052] In this application, the electrical link between the second capacitor and the second chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0053] The sixth aspect of this application provides a manufacturing method, comprising:

[0054] The first capacitor and the tubular resin are surface-attached to the first membrane material, and the first capacitor is disposed in the cavity formed by the tubular rigid resin and the first membrane material.

[0055] A second capacitor is surface-mounted onto a second film, and the second film is surface-mounted onto the upper surface of a tubular rigid resin, thereby placing the second capacitor within a cavity. Magnetic slurry is injected into the cavity until it completely fills the cavity. The first and second films are removed to obtain a preliminary substrate frame. Resin material is pressed onto the upper and lower surfaces of the preliminary substrate frame to obtain the substrate frame itself. A first chip is surface-mounted onto the upper surface of the substrate frame and encapsulated by a first molding layer, establishing an electrical link between the first chip and the first capacitor.

[0056] In this application, the manufacturing method described above embeds the capacitor within the substrate frame, while the chip is surface-mounted on the surface of the substrate frame. Therefore, the first molding layer does not need to match the thickness of the capacitor, thereby improving the chip's heat dissipation efficiency. When the magnetic slurry solidifies, an inductor is formed, with receiving grooves formed on both sides of the inductor, each containing a capacitor, thus increasing the integration density of the capacitor placement. Furthermore, since the inductor can be manufactured by injecting magnetic slurry, the manufacturing cost of the inductor is reduced.

[0057] In one possible implementation, the electrical link between the first chip and the first capacitor is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

[0058] In this application, the electrical link between the first capacitor and the first chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links.

[0059] In one possible implementation, the method also includes:

[0060] A second chip is surface-mounted on the lower surface of the substrate frame and wrapped with a second molding layer. An electrical link is established between the second chip and the second capacitor.

[0061] In this application, the embedded packaging structure allows for surface mounting of chips on both sides, further improving integration.

[0062] In one possible implementation, the electrical link between the second chip and the second capacitor is arranged in the vertical direction.

[0063] In this application, the electrical link between the second capacitor and the second chip is set vertically, which avoids the problems of large parasitic parameters and high risk of electrical stress caused by excessively long links compared to horizontally set links. Attached Figure Description

[0064] Figure 1 is a schematic diagram of an existing packaging structure;

[0065] Figure 2 is a schematic diagram of an existing power module;

[0066] Figure 3 is another schematic diagram of an existing power module;

[0067] Figure 4 is a schematic diagram of an embedded packaging structure in this application;

[0068] Figure 5 is a schematic diagram of an embedded packaging structure in this application;

[0069] Figure 6 is a schematic diagram of an embedded packaging structure in this application;

[0070] Figure 7 is a structural schematic diagram of the power module in this application;

[0071] Figures 8 to 23 are schematic diagrams of the manufacturing of the embedded packaging structure in this application. Detailed Implementation

[0072] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will understand, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0073] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0074] To facilitate understanding of this application, the concepts involved in this application are introduced below:

[0075] ECP: ECP is an advanced packaging technology. In this process, the chip or component is embedded inside the substrate, rather than simply placed on top of it. This technology uses a multi-step manufacturing process to embed the chip or component into the substrate and connects them using copper-plated vias. The main advantages of ECP packaging are its ability to achieve greater miniaturization, reliable interconnection, higher performance, and improved integrated component protection. It is widely used in various high-tech fields, such as medical technology, consumer electronics, and smartphones. Especially in the smartphone field, ECP packaging technology enables thinner and lighter circuit board designs, allowing for larger, longer-lasting batteries. Chargers using ECP technology can also accelerate battery charging. Unlike traditional wafer remodeling molding compound processes, ECP does not use liquid or powder molding compounds but instead uses an overlay molding film. By replacing wafer molding with an overlay leveling process, ECP technology enables ultra-thin chip packaging and avoids voids during the overlay process. Simultaneously, this process can effectively reduce chip misalignment issues, achieving high fan-out ratio packaging for small-sized chips.

[0076] Capacitors: In ECP packages, capacitors mainly play the following key roles:

[0077] Power Supply Filtering and Decoupling: Capacitors are commonly used in ECP packages for power supply filtering and decoupling. They absorb and release transient energy in the circuit, thereby stabilizing the power supply voltage and reducing the impact of power supply noise on circuit performance. Signal Conditioning: Capacitors play a conditioning role in signal transmission, helping to adjust the waveform, frequency response, and phase relationship of the signal, making the signal better suited to the needs of subsequent circuit processing. Energy Storage: Capacitors can store charge and release it when needed. In ECP packages, capacitors can be used to provide the required instantaneous energy at critical moments, such as initiation current or other high peak current demands. Timing Control: In some applications, capacitors are also used to implement timing control functions. By controlling the charging and discharging process of the capacitor, the timing sequence of certain events in the circuit can be precisely controlled. Electromagnetic Shielding: Capacitors can also be used for electromagnetic shielding, reducing the impact of electromagnetic interference on circuit performance. They can absorb and disperse electromagnetic field energy, protecting the circuit from external electromagnetic noise interference. In ECP packages, the selection and placement of capacitors need to comprehensively consider factors such as the specific requirements of the circuit, operating conditions, and space limitations of the package. Appropriate capacitor types and parameters can improve circuit stability and performance, ensuring reliable operation of ECP packages in complex environments.

[0078] Inductors: Inductors in ECP packages mainly play the following key roles:

[0079] Filtering: Inductors are often used in filtering circuits in ECP packages. They can effectively block high-frequency noise signals from passing through and only allow low-frequency signals to pass through, thus stabilizing the signals in the circuit and reducing noise interference.

[0080] Energy storage: Inductors have the characteristic of storing magnetic field energy. When the current changes, inductors can absorb or release energy, which helps to smooth current fluctuations in the circuit and prevent sudden current changes from damaging the circuit.

[0081] Impedance matching: In ECP packages, inductors can be used to adjust the impedance of a circuit to match the impedance between the signal source and the load, thereby improving the efficiency of signal transmission.

[0082] Resonant circuits: Inductors and capacitors can be combined to form resonant circuits, which are very useful in certain specific applications (such as frequency selection, signal amplification, etc.).

[0083] Embedded inductors: Embedded inductors in ECP packaging are a technique that embeds inductor components within the package substrate. Instead of simply placing the inductor on the package surface, it is directly integrated into the internal structure of the package substrate. Through specific manufacturing processes, the inductor coil is embedded into the substrate material, thereby achieving tight integration between the inductor component and the package substrate.

[0084] Embedded inductors have the following significant advantages:

[0085] Space optimization: Since the inductor is directly embedded inside the package substrate, it does not require additional space to be placed on the package surface, thus saving valuable circuit board space.

[0086] Performance Improvement: The tight integration of embedded inductors with the packaging substrate can reduce signal loss and interference, thereby improving the overall performance of the circuit.

[0087] Enhanced reliability: Since the inductor is encapsulated inside the substrate, it is less affected by external environmental interference, thereby improving the reliability of the circuit.

[0088] Electromagnetic Compatibility (EMC): Embedded inductors in ECP packages can more effectively control electromagnetic radiation, reduce electromagnetic interference (EMI), and improve the EMC of circuits. In ECP packages, embedded inductors are widely used in electronic devices requiring high performance, high reliability, and compact space, such as smartphones, wearable devices, and high-speed communication equipment. The use of this technology helps improve the performance, efficiency, and reliability of these devices, driving further development in electronic technology.

[0089] Inductor winding: An inductor winding refers to a set of coils with a specified function, and it is the basic component of an inductor. Windings can be single-layered or multi-layered. Single-layered windings have two forms: close winding (the wires are wound one turn next to another) and spaced winding (the wires are wound with a certain distance between each turn). Multi-layered windings have various methods such as layered flat winding, random winding, and honeycomb winding.

[0090] Inductors play a crucial role in circuits, serving functions such as energy storage and release, filtering, signal transmission, and power regulation. When current flows through an inductor, a magnetic field is generated within the winding, storing electromagnetic energy. When the current stops flowing through the coil, the magnetic field collapses, releasing the stored energy. By selecting an appropriate inductance value, an inductor can block high-frequency signals, allowing the circuit to transmit only the desired signal frequency range. Furthermore, inductors can also be used for signal transmission and power regulation.

[0091] Parasitic parameters: Parasitic parameters refer to non-essential elements present in electronic components or circuits, usually caused by the physical characteristics of wires, circuit boards, and other circuit elements. These parasitic parameters can adversely affect the normal operation of components or circuits, typically manifesting as problems such as increased power consumption, limited signal transmission rates, or impaired signal quality.

[0092] Electrical stress: Electrical stress is a measure of the force generated by changes in the electric field intensity in a dielectric. Specifically, it refers to the magnitude of the force between two parallel, charged surfaces in a dielectric under the influence of an electric field. When the electric field intensity changes in a dielectric, a charge distribution occurs within the dielectric, which generates an electric field force within the dielectric, resulting in a certain stress within the dielectric. This stress is called electrical stress.

[0093] Referring to Figure 2, an existing power module design involves laying out electronic components such as chips (ICs), capacitors (C), resistors (R), and inductors (L) on a printed circuit board (PCB) for power supply and control. This type of power module occupies a very large area of ​​the PCB, which is not conducive to miniaturization and integration.

[0094] Referring to Figure 3, another existing power module design involves embedding a chip (IC), capacitor (C), and resistor (R) into a substrate to form an ECP module. Then, an inductor (L) is mounted on the surface of the ECP module, creating a three-dimensional stacked power module. While this stacked inductor (L) configuration can reduce the footprint to some extent and the high integration of components results in low parasitic parameters, the main heat source of the power module, the IC, is integrated inside the ECP module and surrounded by a dielectric layer. This leads to poor heat dissipation, and the IC's heat dissipation channels rely on the ECP substrate, which is also a significant limitation. Therefore, with product iteration and upgrades, the design shown in Figure 1 was proposed. However, this design still suffers from drawbacks such as difficult chip heat dissipation, high parasitic parameters in the link between capacitors and the chip, high electrical stress risk, and insufficient overall integration.

[0095] Please refer to Figure 4. This application provides an embedded package structure. Figure 4 is a cross-sectional view of the embedded package structure, including a substrate frame 401, an inductor 402, an inductor winding 4021, one or more first capacitors 403, one or more second capacitors 404, one or more first chips 405, a first molding compound 406, a copper layer 407 (excluding the black lines of the inductor winding 4021, not all are shown in the figure), a first pin 4071, and a second pin 4072. The inductor 402 is embedded in the substrate frame 401. A first receiving groove 4021 is provided on the first side of the inductor 402, and a second receiving groove 4022 is provided on the second side of the inductor 402. The first side is close to the upper surface of the substrate frame 401, and the second side is close to the lower surface of the substrate frame 401. The inductor 402 can be configured as an "H" shape as shown in Figure 4, or it can be configured as other shapes, as long as the first receiving groove 4021 and the second receiving groove 4022 are provided. A first capacitor 403 is disposed in a first receiving groove 4021, and a second capacitor 404 is disposed in a second receiving groove 4022. A first chip 405 is surface-mounted on the upper surface of the substrate frame 401 and is encapsulated by a first molding compound 406. This arrangement eliminates the need for the capacitor to be surface-mounted on the upper surface of the substrate. Since the first molding compound 406 only needs to match the thickness of the first chip 405, its thickness is significantly reduced, thus enabling the first chip 405 to achieve good heat dissipation. An electrical link is established between the first capacitor 404 and the first chip 405. In one optional embodiment, this electrical link can be arranged vertically, that is, perpendicular to the upper and lower surfaces of the substrate frame, thereby shortening the length of the electrical link and effectively avoiding problems such as large parasitic parameters and high electrical stress risk. A first pin 4071 and a second pin 4072 are disposed on the side of the substrate frame 401. It should be noted that there may be multiple first receiving slots 4021, with each first receiving slot 4021 containing a first capacitor 403; similarly, there may be multiple second receiving slots 4022, with each second receiving slot 4022 containing a second capacitor 404.

[0096] Referring to Figure 5, this application provides another embedded packaging structure. Figure 5 is a cross-sectional view of this embedded packaging structure, including a substrate frame 401, an inductor 402, an inductor winding 4021, one or more first capacitors 403, one or more second capacitors 404, one or more first chips 405, a first molding compound 406, a copper layer 407, a first pin 4071, a second pin 4072, one or more second chips 408, and a second molding compound 409. Similarly, the inductor 402 is embedded in the substrate frame 401. A first receiving groove 4021 is provided on the first side of the inductor 402, and a second receiving groove 4022 is provided on the second side of the inductor 402. The first side is close to the upper surface of the substrate frame 401, and the second side is close to the lower surface of the substrate frame 401. The inductor 402 can be configured as an "H" shape as shown in Figure 4, or it can be configured as other shapes, as long as the first receiving groove 4021 and the second receiving groove 4022 are provided. A first capacitor 403 is disposed in a first receiving groove 4021, and a second capacitor 404 is disposed in a second receiving groove 4022. A first chip 405 is surface-mounted on the upper surface of the substrate frame 401 and is encapsulated by a first molding compound 406. This arrangement eliminates the need for the capacitor to be surface-mounted on the upper surface of the substrate. Since the first molding compound 406 only needs to match the thickness of the first chip 405, its thickness is significantly reduced, allowing the first chip 405 to achieve good heat dissipation. An electrical link is established between the first capacitor 404 and the first chip 405. In one optional embodiment, this electrical link can be arranged vertically to shorten its length and effectively avoid problems such as large parasitic parameters and high electrical stress risk. A second chip 408 is surface-mounted on the lower surface of the substrate frame 401 and is encapsulated by a second molding compound 409. An electrical link is established between the second capacitor 404 and the second chip 408. In one optional embodiment, this electrical link can be arranged vertically to shorten its length and effectively avoid problems such as large parasitic parameters and high electrical stress risk. The first pin 4071 and the second pin 4072 are disposed on the side of the substrate frame 401. In this embedded package structure, the chip is surface-mounted on both the upper and lower surfaces of the substrate frame 401, thus improving the integration density. It should be noted that there can be multiple first receiving slots 4021, with each first receiving slot 4021 containing a first capacitor 403; similarly, there can be multiple second receiving slots 4022, with each second receiving slot 4022 containing a second capacitor 404.

[0097] Referring to Figure 6, based on the embedded package structure shown in Figure 5, it further includes pins 4073 and 4074 respectively disposed on the upper and lower surfaces of the substrate frame 401, further improving the integration. Through pin 4074, the embedded package structure of this application can be connected to the PCB substrate.

[0098] It should also be noted that in the various embedded packaging structures described above, one or more chips can be arranged with external heat dissipation, and the chips can be placed with the front facing up or the front facing down.

[0099] This application also provides a power supply comprising the embedded package structure of any one of Figures 4 to 6. In one possible implementation, referring to Figure 7, the power supply includes a PCB substrate and an embedded package structure mounted on the PCB substrate. In addition, the PCB substrate also includes its circuitry and electronic components, which are not shown here for the sake of brevity.

[0100] The embedded packaging structure in this application has been described above. The following describes a manufacturing process for the embedded packaging structure in this application:

[0101] Referring to Figure 8, firstly, the second capacitor 404 is surface-mounted onto the first membrane material 410, and then the inductor 402 is also surface-mounted onto the first membrane material 410. The inductor 402 also includes an inductor winding 4021. At this time, the second capacitor 404 is disposed in the second receiving groove 4022 of the inductor. A tubular rigid resin 4011 is also disposed on the first membrane material 410. The tubular rigid resin 4011 and the first membrane material 410 together form a filling chamber. After the second capacitor 404 and the inductor 402 are surface-mounted onto the first membrane material 410, liquid resin is injected into the filling chamber until the liquid resin completely fills the second receiving groove 4022, reaching half the height of the filling chamber.

[0102] Referring to Figure 9, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the inductor 402. At this point, the first capacitor 403 is positioned in the first receiving groove 4021 of the inductor 402. Liquid resin 4012 is then continuously injected into the filling chamber until the liquid resin 4012 completely fills the first receiving groove 4021 and the entire filling chamber.

[0103] Next, referring to Figure 10, after the liquid resin 4012 has completely solidified, the first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are pressed on to form a substrate frame. Then, build-up processing is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072. Build-up processing typically refers to a layer-addition process, a commonly used technique in multilayer board manufacturing. The layer-addition process originated from IBM's SLC process. This method, based on traditional double-sided boards, increases the number of layers in a multilayer board through a series of steps (such as coating liquid photosensitive pre-substrate, semi-curing and photosensitive imaging, comprehensive addition of conductor layers through chemical copper and electroplated copper, circuit imaging and etching, etc.). This method eliminates the costly cost of mechanical drilling, and its aperture can be reduced to below 10 mil. In ECP packaging, the application of build-up processing is mainly to increase the number of substrate layers or complexity to meet specific packaging requirements. By using build-up processing, the product size can be reduced without affecting the overall performance of the device, while also helping with heat dissipation of components and external protection.

[0104] Please refer to Figure 11. After the build-up process is completed, the first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by the first molding compound 406.

[0105] The above describes one manufacturing process of the embedded packaging structure in this application. The following describes another manufacturing process of the embedded packaging structure in this application:

[0106] Similar to Figure 8 above, the second capacitor 404 is first surface-mounted onto the first membrane material 410, and then the inductor 402 is also surface-mounted onto the first membrane material 410. At this time, the second capacitor 404 is disposed in the second receiving groove 4022 of the inductor. A tubular rigid resin 4011 is also disposed on the first membrane material 410. The tubular rigid resin 4011 and the first membrane material 410 together form a filling chamber. After the second capacitor 404 and the inductor 402 are surface-mounted onto the first membrane material 410, liquid resin is injected into the filling chamber until the liquid resin completely fills the second receiving groove 4022 and fills to half the height of the filling chamber.

[0107] Similar to Figure 9 above, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the inductor 402. At this point, the first capacitor 403 is positioned in the first receiving groove 4021 of the inductor 402. Liquid resin 4012 is then continuously injected into the filling chamber until the liquid resin 4012 completely fills the first receiving groove 4021 and the entire filling chamber.

[0108] Similar to Figure 10 above, after the liquid resin 4012 has completely solidified, the first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are pressed on to form a substrate frame. Then, a build-up process is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072.

[0109] Referring to Figure 12, after the build-up process is completed, a first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by a first molding compound 406. A second chip 408 is surface-mounted on the lower surface of the substrate frame and protected by a second molding compound 409.

[0110] The following describes another manufacturing process of the embedded packaging structure in this application:

[0111] Similar to Figure 8 above, the second capacitor 404 is first surface-mounted onto the first membrane material 410, and then the inductor 402 is also surface-mounted onto the first membrane material 410. At this time, the second capacitor 404 is disposed in the second receiving groove 4022 of the inductor. A tubular rigid resin 4011 is also disposed on the first membrane material 410. The tubular rigid resin 4011 and the first membrane material 410 together form a filling chamber. After the second capacitor 404 and the inductor 402 are surface-mounted onto the first membrane material 410, liquid resin is injected into the filling chamber until the liquid resin completely fills the second receiving groove 4022 and fills to half the height of the filling chamber.

[0112] Similar to Figure 9 above, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the inductor 402. At this point, the first capacitor 403 is positioned in the first receiving groove 4021 of the inductor 402. Liquid resin 4012 is then continuously injected into the filling chamber until the liquid resin 4012 completely fills the first receiving groove 4021 and the entire filling chamber.

[0113] Similar to Figure 10 above, after the liquid resin 4012 has completely solidified, the first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are pressed on to form a substrate frame. Then, a build-up process is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072.

[0114] Referring to Figure 13, after the build-up process is completed, a first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by a first molding compound 406. A second chip 408 is surface-mounted on the lower surface of the substrate frame and protected by a second molding compound 409. Furthermore, pins 4073 and 4074 are fabricated.

[0115] In the manufacturing process described above, the inductor is directly embedded in the substrate frame. In another implementation, the inductor can also be formed in the substrate frame through a potting process, which will be described below:

[0116] Please refer to Figure 14. First, the second capacitor 404 and the inductor winding 501 are surface-mounted on the first film material 410. A tubular rigid resin 4011 is also disposed on the first film material 410. The tubular rigid resin 4011 and the first film material 410 together form a filling chamber. After the second capacitor 404 and the inductor winding 501 are surface-mounted on the first film material 410, magnetic slurry 402 is injected into the filling chamber until the magnetic slurry 402 fills half the height of the filling chamber.

[0117] Referring to Figure 15, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the tubular rigid resin 4011. Magnetic slurry 402 is then continuously injected into the filling chamber until it completely fills the entire chamber.

[0118] In one possible implementation, after the second capacitor 404 and the inductor winding 501 are surface-mounted on the first membrane 410 as shown in FIG14, the magnetic slurry may not be injected first. Instead, the second membrane 411 and the first capacitor 403 may be further arranged as shown in FIG15, and then the magnetic slurry may be completely filled into the entire filling chamber at once.

[0119] Referring to Figure 16, after the magnetic slurry 402 has completely solidified, the inductor 402 is formed. The first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are laminated to form a substrate frame. Then, a build-up process is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072.

[0120] Please refer to Figure 17. After the build-up process is completed, the first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by the first molding layer 406.

[0121] The following describes another manufacturing process of the embedded packaging structure in this application:

[0122] Similar to Figure 14, the second capacitor 404 and the inductor winding 501 are first surface-mounted on the first film material 410. A tubular rigid resin 4011 is also disposed on the first film material 410. The tubular rigid resin 4011 and the first film material 410 together form a filling chamber. After the second capacitor 404 and the inductor winding 501 are surface-mounted on the first film material 410, magnetic slurry 402 is injected into the filling chamber until the magnetic slurry 402 fills half the height of the filling chamber.

[0123] Similar to Figure 15, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the tubular rigid resin 4011. Magnetic slurry 402 is then continuously injected into the filling chamber until it completely fills the entire chamber.

[0124] Similar to Figure 16, after the magnetic slurry 402 has completely solidified to form the inductor 402, the first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are laminated to form the substrate frame. Then, a build-up process is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072.

[0125] Referring to Figure 18, after the build-up process is completed, a first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by a first molding compound 406. A second chip 408 is surface-mounted on the lower surface of the substrate frame and protected by a second molding compound 409.

[0126] The following describes another manufacturing process of the embedded packaging structure in this application:

[0127] Similar to Figure 14, the second capacitor 404 and the inductor winding 501 are first surface-mounted on the first film material 410. A tubular rigid resin 4011 is also disposed on the first film material 410. The tubular rigid resin 4011 and the first film material 410 together form a filling chamber. After the second capacitor 404 and the inductor winding 501 are surface-mounted on the first film material 410, magnetic slurry 402 is injected into the filling chamber until the magnetic slurry 402 fills half the height of the filling chamber.

[0128] Similar to Figure 15, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the tubular rigid resin 4011. Magnetic slurry 402 is then continuously injected into the filling chamber until it completely fills the entire chamber.

[0129] Similar to Figure 16, after the magnetic slurry 402 has completely solidified to form the inductor 402, the first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are laminated to form the substrate frame. Then, a build-up process is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072.

[0130] Referring to Figure 19, after the build-up process is completed, a first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by a first molding compound 406. A second chip 408 is surface-mounted on the lower surface of the substrate frame and protected by a second molding compound 409. Furthermore, pins 4073 and 4074 are fabricated.

[0131] The following describes another manufacturing process of the embedded packaging structure in this application:

[0132] Referring to Figure 20, firstly, the second capacitor 404 is surface-mounted onto the first membrane material 410. Then, the inductor 402 is also surface-mounted onto the first membrane material 410. The inductor 402 also has an inductor winding 4021. At this time, the second capacitor 404 is disposed in the second receiving groove 4022 of the inductor. A tubular rigid resin 4011 is also disposed on the first membrane material 410. The tubular rigid resin 4011 and the first membrane material 410 together form a filling chamber.

[0133] Referring to Figure 21, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the inductor 402. At this point, the first capacitor 403 is positioned in the first receiving groove 4021 of the inductor 402. Liquid resin 4012 is then injected into the filling chamber through the injection molding hole until the liquid resin 4012 completely fills the first receiving groove 4021, the second receiving groove 4022, and the entire filling chamber.

[0134] Subsequently, similar to Figure 10, after the liquid resin 4012 has completely solidified, the first film 410 and the second film 411 are removed, and hard resin 4013 and hard resin 4014 are pressed on to form a substrate frame. Then, a build-up process is performed inside the substrate frame to construct the copper layer 407, pins 4071 and 4072.

[0135] Similar to Figure 11, after the build-up process is completed, the first chip 405 is surface-mounted on the upper surface of the substrate frame and protected by the first molding compound 406.

[0136] The following describes another manufacturing process:

[0137] Similar to Figure 20 above, the second capacitor 404 is first surface-mounted onto the first film material 410, and then the inductor 402 is also surface-mounted onto the first film material 410. The inductor 402 also includes an inductor winding 4021. At this time, the second capacitor 404 is disposed in the second receiving groove 4022 of the inductor. A tubular rigid resin 4011 is also disposed on the first film material 410, and the tubular rigid resin 4011 and the first film material 410 together form a filling chamber.

[0138] Similar to Figure 21 above, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the inductor 402. At this point, the first capacitor 403 is positioned in the first receiving groove 4021 of the inductor 402. Liquid resin 4012 is then injected into the filling chamber through the injection molding hole until the liquid resin 4012 completely fills the first receiving groove 4021, the second receiving groove 4022, and the entire filling chamber.

[0139] The subsequent process is similar to that described in Figures 10 and 12 above, and will not be repeated here.

[0140] In another manufacturing process, similar to that in Figure 20 above, the second capacitor 404 is first surface-mounted onto the first film material 410, and then the inductor 402 is also surface-mounted onto the first film material 410. The inductor 402 also includes an inductor winding 4021. At this time, the second capacitor 404 is disposed in the second receiving groove 4022 of the inductor. A tubular rigid resin 4011 is also disposed on the first film material 410, and the tubular rigid resin 4011 and the first film material 410 together form a filling chamber.

[0141] Similar to Figure 21 above, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the inductor 402. At this point, the first capacitor 403 is positioned in the first receiving groove 4021 of the inductor 402. Liquid resin 4012 is then injected into the filling chamber through the injection molding hole until the liquid resin 4012 completely fills the first receiving groove 4021, the second receiving groove 4022, and the entire filling chamber.

[0142] The subsequent process is similar to that described in Figures 10 and 13 above, and will not be repeated here.

[0143] The following describes another manufacturing process:

[0144] Please refer to Figure 22. First, the second capacitor 404 and the inductor winding 501 are surface-mounted on the first film material 410. A tubular hard resin 4011 is also disposed on the first film material 410. The tubular hard resin 4011 and the first film material 410 together form a filling chamber.

[0145] Referring to Figure 23, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the tubular rigid resin 4011. Magnetic slurry 402 is then injected into the filling chamber until it completely fills the entire chamber.

[0146] The subsequent process is similar to that described in Figures 16 and 17 above, and will not be repeated here.

[0147] The following describes another manufacturing process of the embedded packaging structure in this application:

[0148] Similar to Figure 22 above, the second capacitor 404 and the inductor winding 501 are first surface-mounted on the first film material 410. A tubular hard resin 4011 is also disposed on the first film material 410. The tubular hard resin 4011 and the first film material 410 together form a filling chamber.

[0149] Similar to Figure 23 above, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the tubular rigid resin 4011. Magnetic slurry 402 is then injected into the filling chamber until the magnetic slurry 402 completely fills the entire filling chamber.

[0150] The subsequent process is similar to that described in Figures 16 and 18 above, and will not be repeated here.

[0151] The following describes another manufacturing process of the embedded packaging structure in this application:

[0152] Similar to Figure 22 above, the second capacitor 404 and the inductor winding 501 are first surface-mounted on the first film material 410. A tubular hard resin 4011 is also disposed on the first film material 410. The tubular hard resin 4011 and the first film material 410 together form a filling chamber.

[0153] Similar to Figure 23 above, the first capacitor 403 is then surface-mounted onto the second film 411, and the second film 411 is then surface-mounted onto the tubular rigid resin 4011. Magnetic slurry 402 is then injected into the filling chamber until the magnetic slurry 402 completely fills the entire filling chamber.

[0154] The subsequent process is similar to that described in Figures 16 and 19 above, and will not be repeated here.

[0155] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0156] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0157] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0158] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0159] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. An embedded packaging structure, characterized in that, It includes a substrate frame, an inductor, a first capacitor, a second capacitor, a first chip, and a first molding compound; The inductor is embedded in the substrate frame. A first receiving groove is provided on a first side of the inductor, which is close to the upper surface of the substrate frame. A second receiving groove is provided on a second side of the inductor, which is close to the lower surface of the substrate frame. The first capacitor is disposed in the first receiving slot, and the second capacitor is disposed in the second receiving slot; The first chip is surface-mounted on the upper surface of the substrate frame and is encapsulated by the first molding layer; An electrical link is established between the first capacitor and the first chip.

2. The embedded packaging structure according to claim 1, characterized in that, The electrical link between the first capacitor and the first chip is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

3. The embedded packaging structure according to claim 1 or 2, characterized in that, The embedded packaging structure also includes a second chip and a second molding layer; The second chip is surface-mounted on the lower surface of the substrate frame and is encapsulated by the second molding layer; An electrical link is established between the second capacitor and the second chip.

4. The embedded packaging structure according to claim 3, characterized in that, The electrical link between the second capacitor and the second chip is arranged in a vertical direction, which is perpendicular to the upper and lower surfaces of the substrate frame.

5. The embedded packaging structure according to any one of claims 1 to 4, characterized in that, The embedded packaging structure also includes a first pin, which is disposed on the left and right sides of the substrate frame.

6. The embedded packaging structure according to claim 5, characterized in that, The embedded package structure also includes a second pin, which is disposed on the upper and lower surfaces of the substrate frame.

7. A power supply, characterized in that, The power supply includes an embedded package structure as described in any one of claims 1 to 6.

8. A manufacturing method, characterized in that, include: An inductor, a first capacitor, and a tubular rigid resin are surface-mounted on a first film material. A first receiving groove is provided on a first side of the inductor, which is close to the upper surface of the substrate frame. A second receiving groove is provided on a second side of the inductor, which is close to the lower surface of the substrate frame. The first capacitor is disposed in the second receiving groove, and the inductor is disposed in the cavity formed by the tubular rigid resin and the first film material. The second capacitor is attached to the second film material, and the second film material is attached to the upper surface of the tubular rigid resin, so that the second capacitor is disposed in the first receiving groove; Liquid resin is injected into the chamber until the liquid resin completely fills the first receiving tank, the second receiving tank, and the chamber; Remove the first film and the second film to obtain a preliminary substrate frame; Resin material is pressed onto the upper and lower surfaces of the preliminary substrate frame to obtain the substrate frame; A first chip is surface-mounted on the upper surface of the substrate frame and wrapped with a first molding compound. An electrical link is established between the first chip and the first capacitor.

9. The method according to claim 8, characterized in that, The electrical link between the first chip and the first capacitor is arranged in a vertical direction.

10. The method according to claim 8 or 9, characterized in that, The method further includes: A second chip is surface-mounted on the lower surface of the substrate frame and wrapped with a second molding layer. An electrical link is provided between the second chip and the second capacitor.

11. The method according to claim 10, characterized in that, The electrical link between the second chip and the second capacitor is arranged in a vertical direction.

12. A manufacturing method, characterized in that, include: A first capacitor and a tubular resin are surface-attached to a first membrane material, wherein the first capacitor is disposed in a cavity formed by the tubular rigid resin and the first membrane material. The second capacitor is attached to the second membrane material, and the second membrane material is attached to the upper surface of the tubular rigid resin, so that the second capacitor is disposed in the chamber. Inject magnetic slurry into the chamber until the chamber is completely filled with magnetic slurry; Remove the first film and the second film to obtain a preliminary substrate frame; Resin material is pressed onto the upper and lower surfaces of the preliminary substrate frame to obtain the substrate frame; A first chip is surface-mounted on the upper surface of the substrate frame and wrapped with a first molding compound. An electrical link is established between the first chip and the first capacitor.

13. The method according to claim 12, characterized in that, The electrical link between the first chip and the first capacitor is arranged in a vertical direction.

14. The method according to claim 12 or 13, characterized in that, The method further includes: A second chip is surface-mounted on the lower surface of the substrate frame and wrapped with a second molding layer. An electrical link is provided between the second chip and the second capacitor.

15. The method according to claim 14, characterized in that, The electrical link between the second chip and the second capacitor is arranged in a vertical direction.

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