Field-limiting ring structure of power semiconductor device, and preparation method therefor

Abstract

The present application discloses a field-limiting ring structure of a power semiconductor device, and a preparation method therefor. The method comprises: providing a substrate, and depositing and growing a first epitaxial layer on the substrate, wherein both the substrate and the first epitaxial layer are of first-type doping; etching a plurality of spaced-apart field-limiting ring trenches in a field-limiting ring region of the first epitaxial layer; depositing and growing a second epitaxial layer on the etched first epitaxial layer, such that the second epitaxial layer completely fills the field-limiting ring trenches, wherein the second epitaxial layer is of second-type doping; grinding off the part of the second epitaxial layer located on a surface of the first epitaxial layer, such that the second epitaxial layer only fills the plurality of field-limiting ring trenches; and injecting second-type doping into a main junction region of the first epitaxial layer to form a main junction. The present solution can precisely control device parameters and improve the voltage withstand performance of a power semiconductor device.

Description

Field limiting ring structure of power semiconductor device and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device preparation, in particular to a field limiting ring structure of a power semiconductor device and a preparation method thereof. BACKGROUND

[0002] The field limiting ring structure is one of the terminal structures commonly used in high-voltage power devices, and is mainly used to enhance the voltage resistance of the device. In the field limiting ring terminal structure of the conventional high-voltage power device, a plurality of floating field limiting rings surrounding the main junction are usually arranged outside the main junction and are not connected to any potential. The doping type and the junction depth of the field limiting ring are the same as those of the main junction and are formed by diffusion together with the main junction. When the PN junction is manufactured, since the impurities not only diffuse longitudinally from the surface to the inside, but also diffuse laterally in the horizontal direction, a cylindrical junction is formed at the edge of the diffusion window, and a spherical junction is formed at the four corners of the rectangular diffusion window. In the process of gradually increasing the reverse bias voltage of the main junction, the depletion layer of the main junction continuously expands until it is connected to the depletion layer of the field limiting ring, which reduces the curvature of the cylindrical / spherical junction at the edge of the main junction and reduces the possibility of surface electric field concentration, thereby improving the breakdown voltage of the main junction.

[0003] Generally, the main junction and the field limiting ring are formed at the same time, that is, the doping concentration and the junction depth of the main junction and the field limiting ring are the same. However, the field limiting ring cannot be optimized according to the actual voltage resistance requirement, which is not conducive to improving the voltage resistance of the field limiting ring itself and the device. SUMMARY

[0004] In order to enhance the voltage resistance of the device, the present application provides a field limiting ring structure of a power semiconductor device and a preparation method thereof. The field limiting ring is prepared by the trench plus epitaxy method, and then the main junction is prepared. The voltage resistance of the field limiting ring and the device is enhanced by increasing the depth of the field limiting ring trench and reducing the doping concentration in the field limiting ring trench.

[0005] According to one aspect of the present application, a preparation method of a field limiting ring structure of a power semiconductor device is provided, comprising: providing a substrate, depositing and growing a first epitaxial layer on the substrate, the substrate and the first epitaxial layer being doped with a first type; etching a plurality of field limiting ring trenches arranged at intervals in the field limiting ring region of the first epitaxial layer; depositing and growing a second epitaxial layer on the first epitaxial layer after etching, so that the second epitaxial layer completely fills the field limiting ring trenches, and the second epitaxial layer is doped with a second type; grinding away the part of the second epitaxial layer located on the surface of the first epitaxial layer, so that the second epitaxial layer is only retained in the plurality of field limiting ring trenches; and implanting the second type of doping in the main junction region of the first epitaxial layer to form a main junction.

[0006] Optionally, in the preparation method of the field limiting ring structure of the power semiconductor device, the finite element analysis method is used to evaluate the electric field distribution and voltage withstand capability of the power semiconductor device under different field limiting ring structures; and the optimal number of the field limiting ring grooves, the distance between the grooves, and the distance between the grooves and the main junction are determined according to the voltage withstand value requirement of the power semiconductor device.

[0007] Optionally, in the preparation method of the field limiting ring structure of the power semiconductor device, the photolithography mask is designed according to the optimal number of the field limiting ring grooves, the distance between the grooves, and the distance between the grooves and the main junction; the photolithography mask is applied to the photoresist on the surface of the first epitaxial layer to form a photolithography pattern, and the photoresist is removed after the ion etching in the etching area to form the plurality of field limiting ring grooves arranged at intervals.

[0008] Optionally, in the preparation method of the field limiting ring structure of the power semiconductor device, the depths of the field limiting ring grooves are the same or gradually increase from the side close to the main junction to the side away from the main junction.

[0009] Optionally, in the preparation method of the field limiting ring structure of the power semiconductor device, the photoresist is coated on the surface of the main junction area of the first epitaxial layer, and the main junction groove is exposed in the main junction area after development.

[0010] Optionally, in the preparation method of the field limiting ring structure of the power semiconductor device, the depths of the field limiting ring grooves are greater than the junction depth of the main junction, and the doping concentration of the second epitaxial layer in the field limiting ring grooves is less than the doping concentration of the main junction.

[0011] Optionally, in the preparation method of the field limiting ring structure of the power semiconductor device, when the first type of doping is P-type doping, the second type of doping is N-type doping; or when the first type of doping is N-type doping, the second type of doping is P-type doping.

[0012] According to the second aspect of the present application, a field limiting ring structure of a power semiconductor device is provided, which is prepared by the preparation method of the field limiting ring structure of the power semiconductor device as described above, and includes a substrate and a first epitaxial layer grown on the substrate, the first epitaxial layer internally includes a main junction and a plurality of field limiting ring grooves arranged outside the main junction, the plurality of field limiting ring grooves are filled with a second epitaxial layer, the depths of the plurality of field limiting ring grooves are greater than the junction depth of the main junction, and the doping concentration of the second epitaxial layer in the plurality of field limiting ring grooves is less than the doping concentration of the main junction.

[0013] Optionally, in the field limiting ring structure of the power semiconductor device provided in the present application, the substrate is a heavily doped substrate, and when the substrate and the first epitaxial layer are N-type doped, the field limiting ring groove is filled with a P-type doped second epitaxial layer; or when the substrate and the first epitaxial layer are P-type doped, the field limiting ring groove is filled with an N-type doped second epitaxial layer.

[0014] Optionally, in the field limiting ring structure of the power semiconductor device provided in the present application, the number, depth, distance between each field limiting ring groove, and distance between the field limiting ring groove and the main junction are determined according to the withstand voltage of the power semiconductor device.

[0015] According to the preparation method of the field limiting ring structure of the power semiconductor device provided in the present application, the field limiting ring is prepared first and then the main junction is prepared by epitaxial growth, so that the different functional regions are grown separately, the depth of the field limiting ring groove is increased, the doping concentration in the field limiting ring groove is reduced, the withstand voltage of the field limiting ring structure and the power semiconductor device is enhanced, and thus the device parameters are accurately controlled.

[0016] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the present application, the specific embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0017] FIG. 1 shows a schematic diagram of a field limiting ring structure of a power semiconductor device according to an embodiment of the present application;

[0018] FIG. 2 shows a flowchart of a preparation method 200 of a field limiting ring structure of a power semiconductor device according to an embodiment of the present application;

[0019] FIG. 3 shows a schematic diagram of a substrate and an epitaxial layer of a power semiconductor device according to an embodiment of the present application;

[0020] FIG. 4 shows a schematic diagram of groove etching in a field limiting ring region according to an embodiment of the present application;

[0021] FIG. 5 shows a schematic diagram of epitaxy of a P-EPI layer on a slotted N-EPI layer according to an embodiment of the present application;

[0022] FIG. 6 shows a schematic diagram of grinding off the P-EPI layer on the surface of the N-EPI layer according to an embodiment of the present application;

[0023] FIG. 7 shows a schematic diagram of manufacturing a P-type main junction on the surface of the N-EPI layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0025] FIG. 1 shows a schematic diagram of a field-limiting ring structure of a power semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 1, the field-limiting ring structure includes a substrate, a first epitaxial layer grown on the substrate, a plurality of field-limiting ring trenches disposed outside a main junction and filled with a second epitaxial layer.

[0026] The plurality of field-limiting ring trenches are disposed outside the main junction, each of the plurality of field-limiting ring trenches has a depth greater than a junction depth of the main junction, and the second epitaxial layer in each of the plurality of field-limiting ring trenches has a doping concentration less than a doping concentration of the main junction.

[0027] By making the depth of each of the field-limiting ring trenches greater than the junction depth of the main junction, it can be ensured that the depletion layer of the field-limiting ring and the depletion layer of the main junction have a certain overlap, so as to better control the electric field distribution, reduce the possibility of electric field concentration, and improve the breakdown voltage of the main junction.

[0028] The doping concentration of each of the plurality of field-limiting ring trenches is less than the doping concentration of the main junction, which helps to reduce the surface electric field of the power semiconductor device and improve the withstand voltage of the power semiconductor device. At the same time, the difference in doping concentration also helps to form a proper electric field distribution, further improving the performance and reliability of the power semiconductor device.

[0029] When the substrate and the first epitaxial layer are N-type doped, the second epitaxial layer filled in the field-limiting ring trenches is P-type doped, and correspondingly, the main junction is a P-type main junction. When the substrate and the first epitaxial layer are P-type doped, the second epitaxial layer filled in the field-limiting ring trenches is N-type doped, and correspondingly, the main junction is an N-type main junction.

[0030] In order to obtain the field-limiting ring structure of the power semiconductor device shown in FIG. 1, FIG. 2 shows a flowchart of a preparation method 200 of a field-limiting ring structure of a power semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 2, in step S210, a substrate is provided, and a first epitaxial layer is deposited and grown on the substrate, both the substrate and the first epitaxial layer being first-type doped.

[0031] Subsequently, in step S220, a plurality of field-limiting ring trenches are etched and spaced apart in the field-limiting ring region of the first epitaxial layer.

[0032] Before performing this step, the electric field distribution and voltage withstand capability of the power semiconductor device under different field limiting ring structures can be evaluated by using finite element analysis method. For example, a three-dimensional model of the device is established by using CAD software, the established three-dimensional model is divided into finite element grid, different field limiting ring structures are added in the model, and the influence is analyzed to obtain the electric field distribution result, so as to evaluate the influence of different structures on the electric field distribution and voltage withstand capability.

[0033] According to the voltage withstand value requirement of the power semiconductor device, the optimal number of grooves, the distance between grooves, and the distance between grooves and the main junction can be determined.

[0034] In actual application, the photolithography mask can be designed according to the optimal number of grooves, the distance between grooves, and the distance between grooves and the main junction of the field limiting ring. The photolithography mask is applied on the photoresist on the surface of the first epitaxial layer to form a photolithography pattern, and the photoresist is developed to expose the area to be etched; after etching in the area to be etched, the photoresist is removed, and the first epitaxial layer after etching is cleaned to form a plurality of field limiting ring grooves arranged at intervals.

[0035] In an embodiment of the present application, the depths of the plurality of field limiting ring grooves are the same or can gradually increase from the side close to the main junction to the side away from the main junction.

[0036] Then step S230 is performed, and a second epitaxial layer is deposited and grown on the first epitaxial layer after etching, so that the second epitaxial layer completely fills the field limiting ring grooves, and the second epitaxial layer is of the second type of doping.

[0037] During the growth process, the growth parameters are adjusted as needed to ensure that the second epitaxial layer can completely fill the field limiting ring grooves and be seamlessly connected with the first epitaxial layer. The doping concentration of the second epitaxial layer in the field limiting ring grooves is less than the doping concentration of the main junction.

[0038] Subsequently, step S240 is performed, and the part of the second epitaxial layer on the surface of the first epitaxial layer is ground away, so that the second epitaxial layer is only left in each of the plurality of field limiting ring grooves. Chemical mechanical polishing (CMP) can be used to grind away the part of the second epitaxial layer on the surface of the first epitaxial layer, and only the second epitaxial layer is left in the field limiting ring grooves.

[0039] Finally, step S250 is performed, and the second type of doping is injected in the main junction region of the first epitaxial layer to form the main junction. The second type of doping can be injected into the main junction region of the first epitaxial layer by using an injection process to form a P-N junction or an N-P junction. For example, photoresist is coated on the surface of the main junction region of the first epitaxial layer, and after development, the main junction groove is exposed in the main junction region; the second type of doping is injected in the main junction region.

[0040] For an N-type semiconductor, the following steps can be used to manufacture it:

[0041] First, deposit and grow an N-type epitaxial layer on an N-type substrate, the N-type epitaxial layer including a main junction region and a field limiting ring region.

[0042] FIG. 3 shows a schematic diagram of a substrate and an epitaxial layer of a power semiconductor device according to an embodiment of the present application. As shown in FIG. 3, a high-concentration N-type doped substrate can be used to reduce the resistance of the device, improve the conductivity, and provide support. The N-type epitaxial layer (N-EPI layer) serves as the voltage-withstanding layer of the power semiconductor device.

[0043] Then, etch a plurality of trenches in the field limiting ring region of the N-type epitaxial layer, i.e., etch field limiting ring trenches in the reserved main junction outside region, the depth of the trenches being greater than the junction depth of the main junction, i.e., the depth of the P-N junction.

[0044] FIG. 4 shows a schematic diagram of trench etching in the field limiting ring region according to an embodiment of the present application. By etching trenches in the field limiting ring region, the performance and structure of the power semiconductor device can be controlled to meet specific design requirements and application needs.

[0045] Next, deposit and grow a P-type epitaxial layer on the slotted N-type epitaxial layer, so that the P-type epitaxial layer completely fills the field limiting ring trenches.

[0046] FIG. 5 shows a schematic diagram of epitaxy of a P-EPI layer on a slotted N-EPI layer according to an embodiment of the present application. As shown in FIG. 5, the P-EPI layer completely fills the field limiting ring trenches.

[0047] Then, grind off the P-type epitaxial layer on the surface of the N-type epitaxial layer, so that the P-type epitaxial layer only fills the field limiting ring trenches.

[0048] FIG. 6 shows a schematic diagram of grinding off the P-EPI layer on the surface of the N-EPI layer according to an embodiment of the present application. Chemical mechanical polishing (CMP) can be used to grind off the P-EPI layer on the surface of the N-EPI layer.

[0049] Finally, make a P-type main junction in the main junction region of the N-type epitaxial layer. FIG. 7 shows a schematic diagram of making a P-type main junction on the surface of the N-EPI layer according to an embodiment of the present application.

[0050] For a P-type semiconductor device, the following steps can be used to make it:

[0051] First, deposit and grow a P-type epitaxial layer on a P-type substrate, the P-type epitaxial layer including a main junction region and a field limiting ring region. The substrate serves as the support layer of the power semiconductor device, and the P-type epitaxial layer serves as the voltage-withstanding layer of the power semiconductor device.

[0052] Then, a plurality of trenches are etched in the field limiting ring region of the P-type epitaxial layer, i.e. field limiting ring trenches are etched in the reserved region outside the main junction, the depth of the trenches is greater than the junction depth of the main junction, and the junction depth of the main junction is the depth of the N-P junction.

[0053] Then, the N-type epitaxial layer is deposited and grown on the slotted P-type epitaxial layer, so that the N-type epitaxial layer completely fills the field limiting ring trenches. The concentration of the N-EPI layer needs to be lower than that of the N-type main junction.

[0054] Then, the N-type epitaxial layer on the surface of the P-type epitaxial layer is ground away, so that the N-type epitaxial layer only fills the field limiting ring trenches.

[0055] Finally, the N-type main junction is made in the main junction region of the P-type epitaxial layer.

[0056] According to the preparation method of the field limiting ring structure of the power semiconductor device provided in the present application, the field limiting ring is prepared first and then the main junction is prepared by epitaxial growth, so that the growth of different functional regions is separated, the depth of the field limiting ring trench is increased, the doping concentration in the field limiting ring trench is reduced, the withstand voltage capability of the field limiting ring and the device is enhanced, and thus the precise regulation of the device parameters is realized.

[0057] By reasonably designing the structural parameters of the deep trench epitaxial type field limiting ring, the electric field control characteristics of the power semiconductor device can be effectively improved, the breakdown voltage can be increased, and finally the performance of the power semiconductor device can be optimized.

[0058] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the present specification.

[0059] As used herein, unless otherwise defined, the use of the ordinal adjectives "first", "second", "third", etc., merely to distinguish between two or more objects of a common designation does not imply that the objects are in a given order, either in time, space, in ranking or in any other manner.

[0060] While the present application has been described in terms of limited number of embodiments, those skilled in the art will appreciate that other embodiments can be devised in accordance with the teachings of the preceding description. Additionally, it is intended that the description of the application set forth herein be considered as illustrative and not restrictive, and that future modifications and improvements can be made by those skilled in the art without departing from the scope of the application as set forth in the following claims.

Claims

1. A method of fabricating a field-limiting ring structure of a power semiconductor device, characterized by, The method comprises: providing a substrate, depositing and growing a first epitaxial layer on the substrate, both the substrate and the first epitaxial layer being doped with a first type of dopant; etching a plurality of field-limiting ring grooves in a field-limiting ring region of the first epitaxial layer; depositing and growing a second epitaxial layer on the first epitaxial layer after etching, so that the second epitaxial layer completely fills the plurality of field-limiting ring grooves, the second epitaxial layer being doped with a second type of dopant; grinding away a portion of the second epitaxial layer on the surface of the first epitaxial layer, so that the second epitaxial layer is retained only in the plurality of field-limiting ring grooves; injecting the second type of dopant into a main junction region of the first epitaxial layer to form a main junction.

2. The method for fabricating the field-limiting ring structure of the power semiconductor device according to claim 1, characterized in that, Before the step of etching a plurality of field-limiting ring grooves in a field-limiting ring region of the first epitaxial layer, the method further comprises: evaluating the electric field distribution and voltage withstand capability of the power semiconductor device under different field-limiting ring structures by using a finite element analysis method; determining the optimal number of grooves, distance between grooves, and distance between grooves and the main junction of the field-limiting ring structure according to the voltage withstand value requirement of the power semiconductor device.

3. The method for fabricating the field-limiting ring structure of the power semiconductor device according to claim 2, characterized in that, The step of etching a plurality of field-limiting ring grooves in a field-limiting ring region of the first epitaxial layer comprises: designing a photolithography mask according to the optimal number of grooves, distance between grooves, and distance between grooves and the main junction of the field-limiting ring structure; applying the photolithography mask to a photoresist on the surface of the first epitaxial layer to form a photolithography pattern, developing to expose the region to be etched; removing the photoresist after ion etching in the region to be etched to form the plurality of field-limiting ring grooves arranged at intervals.

4. The method for fabricating the field-limiting ring structure of the power semiconductor device according to claim 3, characterized in that, The plurality of field-limiting ring grooves have the same depth or gradually increase from the side close to the main junction to the side away from the main junction.

5. The method for fabricating the field-limiting ring structure of the power semiconductor device according to claim 3, characterized in that, The step of injecting the second type of dopant into a main junction region of the first epitaxial layer to form a main junction comprises: covering the photoresist on the surface of the main junction region of the first epitaxial layer, developing to expose a main junction groove in the main junction region; injecting the second type of dopant into the main junction region.

6. The method for fabricating the field-limiting ring structure of the power semiconductor device according to claim 3, characterized in that, The depth of each field-limiting ring groove in the plurality of field-limiting ring grooves is greater than the junction depth of the main junction, and the doping concentration of the second epitaxial layer in each field-limiting ring groove in the plurality of field-limiting ring grooves is less than the doping concentration of the main junction.

7. The method for fabricating the field-limiting ring structure of the power semiconductor device according to claim 1, characterized in that, When the first type of dopant is P-type doping, the second type of dopant is N-type doping; or when the first type of dopant is N-type doping, the second type of dopant is P-type doping.

8. A field limiting ring structure of a power semiconductor device produced by the method for producing a field limiting ring structure of a power semiconductor device according to any one of claims 1 to 7, characterized by The field-limiting ring structure comprises a substrate and a first epitaxial layer grown on the substrate, the first epitaxial layer internally comprising a main junction and a plurality of field-limiting ring grooves arranged outside the main junction, each field-limiting ring groove in the plurality of field-limiting ring grooves being filled with a second epitaxial layer, the depth of each field-limiting ring groove in the plurality of field-limiting ring grooves being greater than the junction depth of the main junction, and the doping concentration of the second epitaxial layer in the field-limiting ring groove being less than the doping concentration of the main junction.

9. The field limit ring structure of a power semiconductor device according to claim 3, characterized by, The substrate is a heavily doped substrate, when the substrate and the first epitaxial layer are N-type doped, a P-type doped second epitaxial layer is filled in each of the plurality of field limiting ring trenches; or when the substrate and the first epitaxial layer are P-type doped, an N-type doped second epitaxial layer is filled in each of the plurality of field limiting ring trenches.

10. The field limit ring structure of a power semiconductor device according to claim 3, characterized by, The number, depth, distance between each of the plurality of field limiting ring trenches and the distance between the plurality of field limiting ring trenches and the main junction are determined according to the withstand voltage value of the power semiconductor device.

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