Display apparatus and control method for display apparatus

Abstract

A display apparatus and a control method for the display apparatus. The display apparatus comprises a timing control chip and a power management integrated circuit. The timing control chip acquires a timing control signal, and, in a blanking interval of the timing control signal, sends a first instruction to the power management integrated circuit (S11). The power management integrated circuit comprises a switching frequency switching circuit and a voltage regulation circuit. The switching frequency switching circuit stops outputting a switching frequency signal in response to the first instruction, and the voltage regulation circuit stops outputting a regulation voltage in response to the switching frequency switching circuit stopping outputting the switching frequency signal (S12). Thus, the present application can reduce the power consumption of the display apparatus.

Description

Display device and control method of display device

[0001] The present application claims priority to the Chinese patent application No. 202410658254.6, filed on May 24, 2024, and entitled "A display device and a control method of the display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to a display device and a control method of the display device. BACKGROUND

[0003] With the development of technology, display devices are widely used in various fields and scenarios, and the power consumption of display devices has become a concern. SUMMARY

[0004] The present application provides a display device and a control method of the display device.

[0005] In a first aspect, the present application provides a display device, comprising a timing control chip and a power management integrated circuit; wherein,

[0006] The timing control chip is configured to obtain a timing control signal, and send a first instruction to the power management integrated circuit in a blanking area of the timing control signal.

[0007] The power management integrated circuit comprises a switching frequency switching circuit and a voltage regulation circuit, the switching frequency switching circuit is configured to stop outputting a switching frequency signal in response to the first instruction; and the voltage regulation circuit is configured to stop outputting a regulated voltage in response to the switching frequency switching circuit stopping outputting the switching frequency signal.

[0008] Optionally, the first instruction comprises a first input signal, and the switching frequency switching circuit comprises a reset-set (RS) flip-flop circuit; the timing control chip is configured to send the first instruction to the power management integrated circuit, comprising: the timing control chip is configured to send the first input signal to the S terminal of the RS flip-flop circuit.

[0009] Optionally, the timing control chip comprises a general-purpose input-output pin; the timing control chip is configured to send the first input signal to the S terminal of the RS flip-flop circuit, comprising: the timing control chip is configured to send the first input signal to the S terminal of the RS flip-flop circuit through the general-purpose input-output pin.

[0010] Optionally, the first instruction comprises a control instruction, and the switching frequency switching circuit comprises an oscillator and an RS trigger circuit; the timing control chip is configured to send the first instruction to the power management integrated circuit, comprising: the timing control chip is configured to send the control instruction to the oscillator; and the oscillator is configured to send a second input signal to an S terminal of the RS trigger circuit in response to the control instruction.

[0011] Optionally, the RS trigger circuit comprises a comparator and an RS flip-flop; a positive phase input terminal of the comparator is configured to input an external signal, a negative phase input terminal of the comparator is connected with an output terminal of the voltage regulation circuit, and an output terminal of the comparator is connected with an R terminal of the RS flip-flop; and the RS flip-flop is configured to stop outputting the switching frequency signal based on the first input signal or the second input signal received by the S terminal.

[0012] Optionally, the voltage regulation circuit comprises a boost circuit, a voltage dividing circuit and a signal amplification circuit; the boost circuit is configured to output a bias voltage after boosting based on a switching frequency signal output by the switching frequency switching circuit; a first input terminal of the signal amplification circuit is connected with an output terminal of the boost circuit through the voltage dividing circuit, a second input terminal of the signal amplification circuit is configured to input a reference voltage, and an output terminal of the signal amplification circuit is connected with the switching frequency switching circuit.

[0013] Optionally, the boost circuit comprises an inductor, a resistor, a switch tube, a diode, a filter capacitor and a load resistor.

[0014] One end of the inductor is configured to input the bias voltage, the other end of the inductor is connected with one end of the resistor, and the other end of the resistor is connected with an anode of the diode.

[0015] One end of the switch tube is connected between the resistor and the anode of the diode, the other end of the switch tube is grounded, a control terminal of the switch tube is connected with an output terminal of the RS flip-flop, and the control terminal of the switch tube is configured to input the switching frequency signal output by the RS flip-flop;

[0016] One end of the filter capacitor is connected with a cathode of the diode, and the other end of the filter capacitor is grounded through the load resistor.

[0017] Optionally, the voltage dividing circuit comprises a first resistor and a second resistor, one end of the first resistor is connected with an output terminal of the boost circuit, the other end of the first resistor is connected with one end of the second resistor, and the other end of the second resistor is grounded.

[0018] Optionally, the signal amplification circuit comprises an operational transconductance amplifier (OTA), a resistor and a capacitor.

[0019] The first input end of the OTA is connected between the first resistor and the second resistor, the second input end of the OTA is used for inputting a reference voltage, the output end of the OTA is connected with the negative phase input end of the comparator, and the OTA is used for comparing the voltage input by the first input end with the reference voltage input by the second input end and amplifying the comparison result.

[0020] One end of the resistor is connected with the output end of the OTA, and the other end of the resistor is grounded through the capacitor.

[0021] Optionally, the timing control chip is further configured to send a second instruction to the power management integrated circuit in the blanking area of the timing control signal, and the second instruction is used for controlling the power management integrated circuit to stop outputting the power supply voltage.

[0022] Optionally, the timing control chip is further configured to send a third instruction to the power management integrated circuit in the display area of the timing control signal, and the third instruction is used for controlling the power management integrated circuit to output the power supply voltage.

[0023] Optionally, the display device further comprises an external signal source, and the external signal source is used for providing an external source signal for the switch frequency switching circuit.

[0024] The timing control chip is further configured to:

[0025] send a fourth instruction to the switch frequency switching circuit and send a fifth instruction to the external signal source in the display area of the timing control signal, and the fourth instruction, the fifth instruction and the signal output by the voltage regulation circuit are used for controlling the switch frequency switching circuit to output a first preset switch frequency signal.

[0026] and send a sixth instruction to the external signal source after the output voltage of the voltage regulation circuit is stabilized, and the sixth instruction is used for controlling the external signal source to switch the external source signal, so that the switch frequency switching circuit outputs a second preset switch frequency signal based on the switched external source signal, and the frequency of the second preset switch frequency signal is smaller than the frequency of the first preset switch frequency signal.

[0027] In a second aspect, the present application provides a control method of a display device, the display device comprising a timing control chip and a power management integrated circuit, and the method comprising:

[0028] The timing control chip acquires a timing control signal, and sends a first instruction to the power management integrated circuit in a blanking area of the timing control signal;

[0029] The switch frequency switching circuit in the power management integrated circuit stops outputting a switch frequency signal in response to the first instruction; and the voltage regulating circuit in the power management integrated circuit stops outputting a regulating voltage in response to the switch frequency switching circuit stopping outputting the switch frequency signal.

[0030] Optionally, the first instruction comprises a first input signal, and the switch frequency switching circuit comprises an RS flip-flop circuit; and the timing control chip sending the first instruction to the power management integrated circuit comprises the timing control chip sending the first input signal to an S terminal of the RS flip-flop circuit.

[0031] Optionally, the timing control chip comprises a general input and output pin; and the timing control chip sending the first input signal to the S terminal of the RS flip-flop circuit comprises the timing control chip sending the first input signal to the S terminal of the RS flip-flop circuit through the general input and output pin.

[0032] Optionally, the first instruction comprises a control instruction, and the switch frequency switching circuit comprises an oscillator and an RS flip-flop circuit;

[0033] The timing control chip sending the first instruction to the power management integrated circuit comprises the timing control chip sending the control instruction to the oscillator.

[0034] The method further comprises: the oscillator sending a second input signal to an S terminal of the RS flip-flop circuit in response to the control instruction.

[0035] Optionally, the method further comprises:

[0036] The timing control chip sends a second instruction to the power management integrated circuit in a blanking area of the timing control signal, the second instruction being used to control the power management integrated circuit to stop outputting a power supply voltage;

[0037] The power management integrated circuit stops outputting the power supply voltage according to the second instruction.

[0038] Optionally, the method further comprises:

[0039] The timing control chip sends a third instruction to the power management integrated circuit in a display area of the timing control signal, the third instruction being used to control the power management integrated circuit to output the power supply voltage;

[0040] The power management integrated circuit outputs a supply voltage according to the third instruction.

[0041] Optionally, the display device further comprises an external signal source configured to provide an external signal to the switch frequency switching circuit, and the method further comprises:

[0042] The timing control chip sends a fourth instruction to the switch frequency switching circuit and a fifth instruction to the external signal source in the display area of the timing control signal, and the fourth instruction, the fifth instruction and the signal output by the voltage regulation circuit are configured to control the switch frequency switching circuit to output a first preset switch frequency signal.

[0043] The timing control chip sends a sixth instruction to the external signal source after the output voltage of the voltage regulation circuit is stabilized, and the sixth instruction is configured to control the external signal source to switch the external signal, so that the switch frequency switching circuit outputs a second preset switch frequency signal based on the switched external signal, and the frequency of the second preset switch frequency signal is less than the frequency of the first preset switch frequency signal.

[0044] The present application provides a display device, comprising a timing control chip and a power management integrated circuit. The timing control chip is configured to obtain a timing control signal and send a first instruction to the power management integrated circuit in a blanking area of the timing control signal. The power management integrated circuit comprises a switch frequency switching circuit and a voltage regulation circuit. The switch frequency switching circuit is configured to stop outputting a switch frequency signal in response to the first instruction. The voltage regulation circuit is configured to stop outputting a regulated voltage in response to the switch frequency switching circuit stopping outputting the switch frequency signal. The technical solution provided by the present application realizes the regulation of the switch frequency signal inside the power management integrated circuit by configuring the power management integrated circuit to comprise the switch frequency switching circuit and sending the first instruction by the timing control chip. By stopping outputting the switch frequency signal, the power consumption of the power management integrated circuit can be reduced, thereby reducing the power consumption of the display device.

[0045] In addition, in the technical solution provided by the present application, the switch frequency switching circuit can be controlled to output a first preset switch frequency signal with a larger frequency in the display area of the timing control signal, so as to establish the output voltage of the voltage regulation circuit at a faster voltage ramping speed, and then switch to output a second preset switch frequency signal with a smaller frequency when the output voltage is stabilized. This avoids the problem that the color of the display device cannot be saturated during the process of recovering the display device from the low power consumption mode to the normal working mode, and improves the display quality. BRIEF DESCRIPTION OF DRAWINGS

[0046] Optional embodiments of the present application will be described below with reference to the accompanying drawings, in which:

[0047] FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application;

[0048] FIG. 2 is a schematic diagram of another display device according to an embodiment of the present application;

[0049] FIG. 3 is a schematic diagram of a switching frequency switching circuit according to an embodiment of the present application;

[0050] FIG. 4 is a schematic diagram of another switching frequency switching circuit according to an embodiment of the present application;

[0051] FIG. 5 is a schematic diagram of a power management integrated circuit according to an embodiment of the present application;

[0052] FIG. 6 is a signal timing diagram of a comparator according to an embodiment of the present application;

[0053] FIG. 7 is a signal timing diagram of a display device according to an embodiment of the present application;

[0054] FIG. 8 is a flowchart of a control method of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the principles, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described below with reference to the drawings. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the described embodiments, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0056] Unless otherwise defined, technical terms or scientific terms used in the present application are intended to have the meanings commonly understood by those of ordinary skill in the art. The terms “first”, “second” and similar terms used in the present application do not denote any order, quantity or importance, but are used to distinguish different components. The terms “include”, “contain” and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, and do not exclude other components or objects.

[0057] In the related art, a variety of methods can be used to reduce the power consumption of a display device. For example, for an organic light-emitting diode (OLED) display device, the power consumption of the display device can be reduced by reducing the refresh rate of the display device, or the power consumption of the display device can be reduced by turning off the power supply voltage provided by a power management integrated circuit (PMIC) in the display device to the display panel.

[0058] Referring to FIG. 1, FIG. 1 is a schematic diagram of a display device provided in an embodiment of the present application. The display device includes a system controller and a display module. In the related art, the display device can be controlled to work in a low-power mode.

[0059] The system controller can include a graphics processing unit (GPU), a first voltage module, and a second voltage module. The display module can include a timing control chip, a power management integrated circuit, a source driving circuit, a light-emitting power supply unit, and a display panel. The image processor can transmit information to the timing control chip. For example, the image processor can send pixel data, a synchronization signal, or a control command to the timing control chip through an embedded display port interface (eDP) to control the display content of the display panel. As an example, the image processor can send an auxiliary command (AUX CMD) to the timing control chip to enable or disable certain display functions. The first voltage module can be a bias voltage module configured to provide a bias voltage for the power management integrated circuit. The second voltage module can be a battery component configured to supply power to the light-emitting power supply unit. The timing control chip can send a control signal to the source driving circuit, and send a control signal and an enable signal to the power management integrated circuit and the light-emitting power supply unit, respectively. The light-emitting power supply unit provides a light-emitting voltage (i.e., a voltage used for the display panel to emit light) for the display panel based on the received control signal and enable signal. The power management integrated circuit supplies power to the source driving circuit and the display panel based on the received control signal and enable signal. In some embodiments, the power management integrated circuit can supply power to a gate driving circuit in the display panel. The source driving circuit is configured to control the display of the display panel based on the supply voltage provided by the power management integrated circuit and the received control signal.

[0060] In the related art, the power consumption of the display device can be reduced by controlling the timing control chip to not send an enable signal to the power management integrated circuit, thereby stopping the supply of power to the source driving circuit and the display panel. Alternatively, the refresh rate of the display device can be reduced by controlling the timing control chip to send a timing control signal with a lower refresh rate to the source driving circuit, thereby reducing the power consumption of the display device.

[0061] However, the above methods have poor effects on reducing the power consumption of the display device. In addition, during the switching of the display device from the low-power mode to the normal working mode, the display quality can also be easily deteriorated.

[0062] Embodiments of the present application provide a display device. Referring to FIG. 2, FIG. 2 is a schematic diagram of a display device according to an embodiment of the present application. The display device includes a timing control chip and a power management integrated circuit. The timing control chip can also be referred to as a timing controller (TCON).

[0063] The timing control chip is configured to obtain a timing control signal and send a first instruction to the power management integrated circuit in a blanking region of the timing control signal. For example, the timing control chip is configured to send the first instruction to the power management integrated circuit in a blanking region of each frame of the timing control signal. In some embodiments, the timing control signal is also referred to as a system timing control signal, which is not limited in the embodiments of the present application.

[0064] The power management integrated circuit includes a switching frequency switching circuit and a voltage regulation circuit. The switching frequency switching circuit is configured to stop outputting a switching frequency signal in response to the first instruction. The voltage regulation circuit is configured to stop outputting a regulated voltage in response to the switching frequency switching circuit stopping outputting the switching frequency signal.

[0065] In the embodiments of the present application, the display device can include a system controller as shown in FIG. 1. The timing control signal can be sent from an image processor in the system controller to the timing control chip. The timing control chip receives the timing control signal sent by the image processor to obtain the timing control signal. Each frame period of the timing control signal can include an active display stage (i.e., a display region) and a blanking stage (i.e., a blanking region). Each frame of the timing control signal is also referred to as a frame period of the timing control signal.

[0066] The timing control chip can determine the display region and the blanking region of the timing control signal based on the timing control signal, and send the first instruction to the switching frequency switching circuit in the blanking region of the timing control signal. In some embodiments, the timing control signal can include at least a vertical synchronization signal.

[0067] In some embodiments, the timing control chip can include a general input and output pin. The timing control chip can send the first instruction to the power management integrated circuit through the general input and output pin. In some embodiments, the general input and output pin can be a pre-set and idle pin on the timing control chip, or a newly added pin for transmitting the first instruction, which is not limited in the embodiments of the present application.

[0068] In the embodiment of the present application, the switching frequency signal affects the working state of the voltage regulation circuit. In the related art, in the display area and the blanking area of the timing control signal, the switching frequency signal is a fixed frequency signal, and the voltage regulation circuit outputs the regulation voltage based on the fixed frequency switching frequency signal. In the embodiment of the present application, the switching frequency signal can be adjusted by setting the switching frequency switching circuit, which is conducive to stopping the switching frequency switching circuit from outputting the switching frequency signal in the blanking phase, thereby reducing the energy consumption of the display device.

[0069] The display device provided in the embodiment of the present application can adjust the switching frequency signal in the blanking area of the timing control signal by setting the switching frequency switching circuit and sending the first instruction by the timing control chip, thereby controlling the voltage regulation circuit to stop working, reducing the power consumption of the power management integrated circuit, and reducing the power consumption of the display device.

[0070] In some embodiments, the switching frequency switching circuit provided in the embodiment of the present application can be as shown in FIG. 3 or FIG. 4.

[0071] Referring to FIG. 3, FIG. 3 is a schematic diagram of a switching frequency switching circuit provided in the embodiment of the present application. The first instruction can include a first input signal, and the switching frequency switching circuit can include a reset-set (RS) flip-flop circuit. The timing control chip for sending the first instruction to the power management integrated circuit can include that the timing control chip is configured to send the first input signal to a set (S) terminal of the RS flip-flop circuit. The first input signal is configured to control the RS flip-flop circuit to stop outputting the switching frequency signal.

[0072] In some embodiments, the first input signal can be directly provided by the timing control chip to the S terminal of the RS flip-flop circuit, and the first input signal is configured to control the RS flip-flop circuit to stop outputting the switching frequency signal.

[0073] In some embodiments, the timing control chip includes a general input-output pin, and the timing control chip for sending the first input signal to the S terminal of the RS flip-flop circuit can include that the timing control chip is configured to send the first input signal to the S terminal of the RS flip-flop circuit through the general input-output pin.

[0074] Referring to FIG. 4, which is a schematic diagram of another switching frequency switching circuit according to an embodiment of the present application. The first instruction can include a control instruction, and the switching frequency switching circuit can include an oscillator and an RS trigger circuit. The timing control chip can be configured to send the control instruction to the oscillator, and the oscillator can be configured to send a second input signal to an S terminal of the RS trigger circuit in response to the control instruction. The second input signal can be configured to control the RS trigger circuit to stop outputting a switching frequency signal. The second input signal can be the same as the first input signal.

[0075] In optional embodiments, in the switching frequency switching circuit shown in FIG. 3 or FIG. 4, the RS trigger circuit can include a comparator and an RS flip-flop. The positive input terminal of the comparator can be configured to input an external signal, the negative input terminal of the comparator can be connected to an output terminal of the voltage regulation circuit, and the output terminal of the comparator can be connected to a reset (R) terminal of the RS flip-flop. The RS flip-flop can be configured to stop outputting a switching frequency signal based on the first input signal or the second input signal received by the S terminal.

[0076] In some embodiments, the first input signal or the second input signal can be a low-level signal.

[0077] In some embodiments, referring to FIG. 5, which is a schematic diagram of a power management integrated circuit according to an embodiment of the present application. The power management integrated circuit can include a switching frequency switching circuit and a voltage regulation circuit. The switching frequency switching circuit can be as shown in FIG. 3 or FIG. 4. FIG. 5 is described by taking the switching frequency switching circuit as shown in FIG. 3 as an example. Referring to FIG. 5, the RS trigger circuit can include a comparator and an RS flip-flop. The positive input terminal of the comparator can be configured to input an external signal, the negative input terminal of the comparator can be connected to an output terminal of the voltage regulation circuit, and the output terminal of the comparator can be connected to an R terminal of the RS flip-flop. The RS flip-flop can be configured to stop outputting a switching frequency signal based on the first input signal or the second input signal received by the S terminal.

[0078] In the embodiments of the present application, the voltage regulation circuit can be configured to regulate a bias voltage based on the switching frequency signal to obtain an adjusted output voltage (i.e., a regulated voltage), and provide the adjusted output voltage to other functional units (e.g., a source driving circuit and / or a display panel, etc.) in the display device.

[0079] In some embodiments, as shown in FIG. 5, the voltage regulating circuit includes a voltage boosting circuit, a voltage dividing circuit, and a signal amplifying circuit. The voltage boosting circuit is configured to output a boosted bias voltage VI based on a switching frequency signal output by the switching frequency switching circuit. The first input terminal of the signal amplifying circuit is connected to the output terminal of the voltage boosting circuit through the voltage dividing circuit, the second input terminal of the signal amplifying circuit is configured to input a reference voltage Vref, and the output terminal of the signal amplifying circuit is connected to the switching frequency switching circuit (specifically, the negative input terminal of the comparator).

[0080] In some embodiments, as shown in FIG. 5, the voltage boosting circuit can include an inductor L, a resistor RL, a switch tube G, a diode D, a filter capacitor C, and a load resistor RC. The inductor L is connected in series with the resistor RL, one end of the inductor L is configured to input the bias voltage VI, the other end of the inductor L is connected to one end of the resistor RL, and the other end of the resistor RL is connected to the anode of the diode D. One end of the switch tube G is connected between the resistor RL and the anode of the diode D, the other end of the switch tube G is grounded, the control terminal of the switch tube G is connected to the output terminal Q of the RS flip-flop, and the control terminal of the switch tube G is configured to input the switching frequency signal output by the RS flip-flop. One end of the filter capacitor C is connected to the cathode of the diode D, and the other end of the filter capacitor C is grounded through the load resistor RC. The output voltage of the voltage boosting circuit can be represented as V0, and the cathode of the diode D can also be grounded through the resistor RL.

[0081] In some embodiments, as shown in FIG. 5, the voltage dividing circuit can include a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the output terminal of the voltage boosting circuit, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0082] In some embodiments, as shown in FIG. 5, the signal amplifying circuit can include an operational transconductance amplifier (OTA), a resistor Rc, and a capacitor Cc. The first input terminal of the OTA is connected between the first resistor R1 and the second resistor R2, the second input terminal of the OTA is configured to input the reference voltage Vref (i.e., the desired output voltage), the output terminal of the OTA is connected to the negative input terminal of the comparator in the switching frequency switching circuit, and the OTA is configured to compare the voltage input at the first input terminal with the reference voltage input at the second input terminal and amplify the comparison result. One end of the resistor Rc is connected to the output terminal of the OTA, and the other end of the resistor Rc is grounded through the capacitor Cc. The first input terminal of the OTA can be the negative input terminal of the OTA, and the second input terminal of the OTA can be the positive input terminal of the OTA.

[0083] In some embodiments, referring to FIG. 6, which is a signal timing diagram of a comparator according to an embodiment of the present application, the signal output by the OTA can be a sine wave signal, and the signal input to the negative input terminal of the comparator can be the sine wave signal. The signal input to the positive input terminal of the comparator can be a triangular wave signal. The comparator can be configured to compare the triangular wave signal input to the positive input terminal of the comparator with the sine wave signal input to the negative input terminal of the comparator, and output a square wave signal.

[0084] In some embodiments, the timing control chip can be further configured to send a second instruction to the power management integrated circuit in a blanking region of the timing control signal, the second instruction being configured to control the power management integrated circuit to stop outputting the supply voltage. For example, the timing control chip can be configured to send the second instruction to the power management integrated circuit in a blanking region of each frame of the timing control signal. The power management integrated circuit can be further configured to stop outputting the supply voltage in response to the second instruction. In this way, the power consumption of the power management integrated circuit can be reduced, and thus the power consumption of the display device can be reduced.

[0085] In some embodiments, the second instruction can be configured to control the power management integrated circuit to stop outputting the supply voltage to the source driving circuit and / or the display panel. The power management integrated circuit can be further configured to stop outputting the supply voltage to the source driving circuit and / or the display panel in response to the second instruction.

[0086] In some embodiments, the timing control chip can be further configured to send a third instruction to the power management integrated circuit in a display region of the timing control signal, the third instruction being configured to control the power management integrated circuit to output the supply voltage. For example, the timing control chip can be configured to send the third instruction to the power management integrated circuit in a display region of each frame of the timing control signal. The power management integrated circuit can be further configured to output the supply voltage in response to the third instruction, so as to resume supplying power to other functional units (e.g., the source driving circuit and / or the display panel).

[0087] In some embodiments, the third instruction can be configured to control the power management integrated circuit to output the supply voltage to the source driving circuit and / or the display panel. The power management integrated circuit can be further configured to output the supply voltage to the source driving circuit and / or the display panel in response to the third instruction.

[0088] In some embodiments, the third instruction can include an enable signal configured to control the power management integrated circuit to start. The power management integrated circuit can be further configured to start the power management integrated circuit in response to the third instruction.

[0089] In some embodiments, the display device can further include an external signal source configured to provide an external signal to the switch frequency switching circuit. The timing control chip is further configured to: send a fourth instruction to the switch frequency switching circuit and a fifth instruction to the external signal source in the display area of the timing control signal, the fourth instruction, the fifth instruction and the signal output by the voltage regulation circuit being configured to control the switch frequency switching circuit to output the first preset switch frequency signal. For example, the timing control chip sends the fourth instruction to the switch frequency switching circuit and the fifth instruction to the external signal source in the display area of each frame of the timing control signal. The switch frequency switching circuit is configured to output the first preset switch frequency signal based on the fourth instruction, the fifth instruction and the signal output by the voltage regulation circuit.

[0090] In addition, the timing control chip is further configured to: send a sixth instruction to the external signal source after the output voltage of the voltage regulation circuit is stabilized, the sixth instruction being configured to control the external signal source to switch the external signal, so that the switch frequency switching circuit outputs a second preset switch frequency signal based on the switched external signal. The switch frequency switching circuit is configured to output the second preset switch frequency signal based on the switched external signal.

[0091] In some embodiments, the frequency of the second preset switch frequency signal is less than the frequency of the first preset switch frequency signal.

[0092] In the embodiments of the present application, since the switch frequency switching circuit stops outputting the switch frequency signal and the voltage regulation circuit stops outputting the regulated voltage in the blanking area of the timing control signal, and the power management integrated circuit can stop outputting the supply voltage, the power consumption of the power management integrated circuit is low, and the power consumption of the display device is low. In the blanking area of the timing control signal, the display device is in a low power consumption mode.

[0093] Since the power management integrated circuit outputs the supply voltage to restore power supply to other functional units (such as the source drive circuit and / or the display panel) in the display area of the timing control signal, the display device can realize normal display function. In the display area of the timing control signal, the power consumption of the power management integrated circuit is high, the power consumption of the display device is high, and the display device is in a normal working mode.

[0094] Therefore, the display device is in the low power consumption mode in the blanking area of the timing control signal, and is in the normal working mode in the display area of the timing control signal. Since the frequency of the second preset switching frequency signal is less than the frequency of the first preset switching frequency signal, in the process of switching the display device from the low power consumption mode to the normal working mode, the switching frequency switching circuit outputs the first preset switching frequency signal with the larger frequency first, so as to realize the voltage ramping up at a faster speed to establish the output voltage of the voltage regulating circuit. After the output voltage of the voltage regulating circuit is stabilized, the switching frequency switching circuit switches to output the second preset switching frequency signal with the smaller frequency, so that the problem of color saturation of the display device can be avoided, and the display quality is improved and the power consumption is reduced.

[0095] In some embodiments, the switching frequency switching circuit is shown in FIG. 3, and the fourth instruction sent by the timing control chip to the switching frequency switching circuit can include that the timing control chip sends a clock signal to the S terminal of the RS trigger circuit to start the RS trigger circuit. The RS trigger circuit can start according to the clock signal.

[0096] In some other embodiments, the switching frequency switching circuit is shown in FIG. 4, and the fourth instruction sent by the timing control chip to the switching frequency switching circuit can include that the timing control chip sends another control instruction to the oscillator, and the oscillator is configured to send a clock signal to the S terminal of the RS trigger circuit to start the RS trigger circuit in response to the another control instruction. The RS trigger circuit can start according to the clock signal.

[0097] In some embodiments, the timing control chip is configured to send a fifth instruction or a sixth instruction to an external signal source, so as to adjust the external signal by the fifth instruction or the sixth instruction. The adjusted external signal and the signal output by the voltage regulating circuit are used to control the switching frequency switching circuit to output the preset switching frequency signal required, such as the first preset switching frequency signal or the second preset switching frequency signal. In some embodiments, the second preset switching frequency signal can be a signal of a target switching frequency required in the normal working mode.

[0098] In some embodiments, referring to FIG. 7, which is a signal timing diagram of the display device provided by the embodiments of the present application, the signal timing diagram can be obtained based on the display device provided by any of the embodiments of the present application.

[0099] In the formula, VSYNC represents a vertical synchronization signal, which can be transmitted by a system controller to the timing control chip. Display Data represents display data of a display device, which can include a blanking region (i.e., a blanking area) and a display region (i.e., an AA area). The blanking region of the display data can correspond to the blanking region of the timing control signal. The display region of the display data can correspond to the display region of the timing control signal. For example, the length of the blanking region of the display data is equal to the length of the blanking region of the timing control signal, and the blanking region of the display data is aligned with the blanking region of the timing control signal. The length of the display region of the display data is equal to the length of the display region of the timing control signal, and the display region of the display data is aligned with the display region of the timing control signal. PMIC LX represents a switching frequency signal output by a switching frequency switching circuit. Voltage represents an output voltage of a voltage regulation circuit. As shown in FIG. 7, in the blanking area, the switching frequency switching circuit stops outputting the switching frequency signal, and the voltage regulation circuit stops outputting the voltage. The state of the PMIC LX can be represented as disable, indicating that the voltage regulation circuit does not output the voltage. In the process of switching the display data from the blanking area to the AA area (correspondingly, in the process of switching the display device from the low-power mode to the normal working mode), the initial frequency of the switching frequency signal output by the switching frequency switching circuit is 2.2 MHz (megahertz), and the output voltage of the voltage regulation circuit can be restored to the voltage required for normal display at a fast ramping speed. After the output voltage of the voltage regulation circuit is stabilized, the switching frequency switching circuit switches to output the switching frequency signal with a frequency of 1.0 MHz, thereby reducing power consumption.

[0100] In some embodiments, the display device provided by the embodiments of the present application can further include functional units (for example, a system controller, a source driving circuit, a light-emitting power supply unit, and a display panel) other than the timing control chip and the power management integrated circuit in FIG. 1, and achieve the same effect as the corresponding functional units in FIG. 1.

[0101] By way of example, the display device provided by the embodiments of the present application can include electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0102] In another aspect of the embodiments of the present application, a control method of a display device is provided, which can be implemented based on the display device provided by any of the above embodiments. The display device includes a timing control chip and a power management integrated circuit. Referring to FIG. 8, which is a flowchart of a control method of a display device provided by an embodiment of the present application, the control method of the display device can include steps S11 to S12.

[0103] Step S11: The timing control chip acquires the timing control signal, and sends a first instruction to the power management integrated circuit in the blanking area of the timing control signal. For example, the timing control chip sends the first instruction to the power management integrated circuit in the blanking area of the timing control signal of each frame.

[0104] Step S12: The switching frequency switching circuit in the power management integrated circuit stops outputting the switching frequency signal in response to the first instruction; the voltage regulating circuit in the power management integrated circuit stops outputting the regulated voltage in response to the switching frequency switching circuit stopping outputting the switching frequency signal.

[0105] The method realizes the adjustment of the switching frequency signal inside the power management integrated circuit, and can reduce the power consumption of the power management integrated circuit by stopping outputting the switching frequency signal, thereby reducing the power consumption of the display device.

[0106] In some embodiments, the first instruction can include a first input signal, and the switching frequency switching circuit can include an RS flip-flop circuit; the timing control chip sending the first instruction to the power management integrated circuit can include the timing control chip sending the first input signal to the S terminal of the RS flip-flop circuit.

[0107] In some embodiments, the timing control chip can include a general-purpose input-output pin; the timing control chip sending the first input signal to the S terminal of the RS flip-flop circuit can include the timing control chip sending the first input signal to the S terminal of the RS flip-flop circuit through the general-purpose input-output pin.

[0108] In some embodiments, the first instruction can include a control instruction, and the switching frequency switching circuit can include an oscillator and an RS flip-flop circuit; the timing control chip sending the first instruction to the power management integrated circuit can include the timing control chip sending the control instruction to the oscillator. The display device control method provided by the embodiments of the present application can further include: the oscillator sending a second input signal to the S terminal of the RS flip-flop circuit in response to the control instruction.

[0109] In some embodiments, the display device control method provided by the embodiments of the present application can further include: the timing control chip sending a second instruction to the power management integrated circuit in the blanking area of the timing control signal, the second instruction being used to control the power management integrated circuit to stop outputting the power supply voltage; and the power management integrated circuit stopping outputting the power supply voltage according to the second instruction. In this way, the power consumption of the power management integrated circuit can be reduced, thereby reducing the power consumption of the display device. For example, the timing control chip sends the second instruction to the power management integrated circuit in the blanking area of the timing control signal of each frame.

[0110] In some embodiments, the method for controlling the display device further includes: sending, by the timing control chip, a third instruction to the power management integrated circuit in the display area of the timing control signal, the third instruction being used to control the power management integrated circuit to output the power supply voltage; and outputting, by the power management integrated circuit, the power supply voltage according to the third instruction. Thus, the power management integrated circuit can supply power to other functional units (e.g., the display panel and / or the source driving circuit). For example, the timing control chip sends the third instruction to the power management integrated circuit in the display area of each frame of the timing control signal.

[0111] In some embodiments, the display device further includes an external signal source used to provide an external signal to the switching frequency switching circuit. The method for controlling the display device further includes: sending, by the timing control chip, a fourth instruction to the switching frequency switching circuit and a fifth instruction to the external signal source in the display area of the timing control signal, the fourth instruction, the fifth instruction, and the signal output by the voltage regulation circuit being used to control the switching frequency switching circuit to output a first preset switching frequency signal; and sending, by the timing control chip, a sixth instruction to the external signal source after the output voltage of the voltage regulation circuit is stabilized, the sixth instruction being used to control the external signal source to switch the external signal, so that the switching frequency switching circuit outputs a second preset switching frequency signal based on the switched external signal, the frequency of the second preset switching frequency signal being smaller than the frequency of the first preset switching frequency signal. For example, the timing control chip sends the fourth instruction to the switching frequency switching circuit and the fifth instruction to the external signal source in the display area of each frame of the timing control signal.

[0112] Thus, in the process of switching the display device from the low-power mode to the normal working mode, the switching frequency switching circuit outputs the first preset switching frequency signal with a larger frequency to establish the output voltage of the voltage regulation circuit at a faster voltage ramping speed, and then switches to output the second preset switching frequency signal with a smaller frequency after the output voltage of the voltage regulation circuit is stabilized. Thus, the problem of color unsaturation of the display device can be avoided, and the display quality can be improved and the power consumption can be reduced.

[0113] The technical solutions of the present application have been described in combination with the embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the present application is not limited to these embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical solutions after the changes or replacements will fall within the protection scope of the present application.

Claims

1. A display device comprising a timing control chip and a power management integrated circuit; the timing control chip is configured to acquire a timing control signal and send a first instruction to the power management integrated circuit in a blanking area of the timing control signal; the power management integrated circuit comprises a switching frequency switching circuit and a voltage regulating circuit, the switching frequency switching circuit is configured to stop outputting a switching frequency signal in response to the first instruction; and the voltage regulating circuit is configured to stop outputting a regulated voltage in response to the switching frequency switching circuit stopping outputting the switching frequency signal.

2. The display device according to claim 1, wherein the first instruction comprises a first input signal, and the switching frequency switching circuit comprises a reset-set RS flip-flop circuit; and the timing control chip is configured to send the first instruction to the power management integrated circuit by sending the first input signal to an S terminal of the RS flip-flop circuit.

3. The display device according to claim 2, wherein the timing control chip comprises a general-purpose input-output pin; the timing control chip is configured to send the first input signal to the S terminal of the RS flip-flop circuit by sending the first input signal to the S terminal of the RS flip-flop circuit through the general-purpose input-output pin.

4. The display device according to claim 1, wherein the first instruction comprises a control instruction, and the switching frequency switching circuit comprises an oscillator and an RS flip-flop circuit; the timing control chip is configured to send the first instruction to the power management integrated circuit by sending the control instruction to the oscillator; and the oscillator is configured to send a second input signal to the S terminal of the RS flip-flop circuit in response to the control instruction.

5. The display device according to any one of claims 2 to 4, wherein the RS flip-flop circuit comprises a comparator and an RS flip-flop; a positive input terminal of the comparator is configured to input an external signal, a negative input terminal of the comparator is connected to an output terminal of the voltage regulating circuit, and an output terminal of the comparator is connected to an R terminal of the RS flip-flop; the RS flip-flop is configured to stop outputting the switching frequency signal based on the first input signal or the second input signal received by the S terminal.

6. The display device of claim 5, wherein, the voltage regulating circuit comprises a boost circuit, a voltage dividing circuit, and a signal amplification circuit; the boost circuit is configured to output a bias voltage after boosting based on a switching frequency signal output by the switching frequency switching circuit; a first input terminal of the signal amplification circuit is connected to an output terminal of the boost circuit through the voltage dividing circuit, a second input terminal of the signal amplification circuit is configured to input a reference voltage, and an output terminal of the signal amplification circuit is connected to the switching frequency switching circuit.

7. The display device of claim 6, wherein, the boost circuit comprises an inductor, a resistor, a switch tube, a diode, a filter capacitor, and a load resistor; one end of the inductor is configured to input the bias voltage, the other end of the inductor is connected to one end of the resistor, and the other end of the resistor is connected to an anode of the diode; one end of the switch tube is connected between the resistor and the anode of the diode, the other end of the switch tube is grounded, a control terminal of the switch tube is connected to an output terminal of the RS flip-flop, and the control terminal of the switch tube is configured to input the switching frequency signal output by the RS flip-flop; One end of the filter capacitor is connected with the cathode of the diode, and the other end of the filter capacitor is grounded through the load resistor.

8. The display device according to claim 6 or 7, wherein The voltage dividing circuit comprises a first resistor and a second resistor, one end of the first resistor is connected with the output end of the voltage boosting circuit, the other end of the first resistor is connected with one end of the second resistor, and the other end of the second resistor is grounded.

9. The display device of claim 8, wherein, The signal amplification circuit comprises a transconductance operational amplifier (OTA), a resistor and a capacitor; The first input end of the OTA is connected between the first resistor and the second resistor, the second input end of the OTA is used for inputting a reference voltage, the output end of the OTA is connected with the negative phase input end of the comparator, and the OTA is used for comparing the voltage inputted by the first input end with the reference voltage inputted by the second input end and amplifying the comparison result; One end of the resistor is connected with the output end of the OTA, and the other end of the resistor is grounded through the capacitor.

10. The display device according to any one of claims 1 to 9, wherein, The timing control chip is further configured to send a second instruction to the power management integrated circuit in a blanking area of the timing control signal, and the second instruction is used to control the power management integrated circuit to stop outputting a supply voltage.

11. The display device of claim 10, wherein, The timing control chip is further configured to send a third instruction to the power management integrated circuit in a display area of the timing control signal, and the third instruction is used to control the power management integrated circuit to output a supply voltage.

12. The display device according to any one of claims 1 to 11, wherein, The display device further comprises an external signal source configured to provide an external signal to the switch frequency switching circuit. The timing control chip is further configured to: send a fourth instruction to the switch frequency switching circuit and send a fifth instruction to the external signal source in the display area of the timing control signal, and the fourth instruction, the fifth instruction and a signal outputted by the voltage regulation circuit are used to control the switch frequency switching circuit to output a first preset switch frequency signal; and after the output voltage of the voltage regulation circuit is stabilized, send a sixth instruction to the external signal source, and the sixth instruction is used to control the external signal source to switch the external signal, so that the switch frequency switching circuit outputs a second preset switch frequency signal based on the switched external signal, and the frequency of the second preset switch frequency signal is smaller than the frequency of the first preset switch frequency signal.

13. A control method of a display device, the display device comprising a timing control chip and a power management integrated circuit, the method comprising: the timing control chip acquires a timing control signal, and sends a first instruction to the power management integrated circuit in a blanking area of the timing control signal; a switch frequency switching circuit in the power management integrated circuit stops outputting a switch frequency signal in response to the first instruction, and a voltage regulation circuit in the power management integrated circuit stops outputting a regulated voltage in response to the switch frequency switching circuit stopping outputting the switch frequency signal.

14. The method of claim 13, wherein, the first instruction comprises a first input signal, and the switch frequency switching circuit comprises a reset-set (RS) flip-flop circuit; The timing control chip sends the first instruction to the power management integrated circuit includes that the timing control chip sends the first input signal to the S end of the RS trigger circuit.

15. The method of claim 14, wherein, The timing control chip includes a general input and output pin; The timing control chip sends the first input signal to the S end of the RS trigger circuit includes that the timing control chip sends the first input signal to the S end of the RS trigger circuit through the general input and output pin.

16. The method of claim 13, wherein, The first instruction includes a control instruction, and the switching frequency switching circuit includes an oscillator and a reset-set RS trigger circuit; The timing control chip sends the first instruction to the power management integrated circuit includes that the timing control chip sends the control instruction to the oscillator; The method further includes that the oscillator sends a second input signal to the S end of the RS trigger circuit in response to the control instruction.

17. The method of any one of claims 13 to 16, wherein, The method further includes: The timing control chip sends a second instruction to the power management integrated circuit in the blanking area of the timing control signal, and the second instruction is used to control the power management integrated circuit to stop outputting a supply voltage; The power management integrated circuit stops outputting the supply voltage according to the second instruction.

18. The method of claim 17, wherein, The method further includes: The timing control chip sends a third instruction to the power management integrated circuit in the display area of the timing control signal, and the third instruction is used to control the power management integrated circuit to output the supply voltage; The power management integrated circuit outputs the supply voltage according to the third instruction.

19. The method of any one of claims 13 to 18, wherein, The display device further includes an external signal source used to provide an external source signal for the switching frequency switching circuit, and the method further includes: The timing control chip sends a fourth instruction to the switching frequency switching circuit and a fifth instruction to the external signal source in the display area of the timing control signal, and the fourth instruction, the fifth instruction and a signal output by the voltage regulation circuit are used to control the switching frequency switching circuit to output a first preset switching frequency signal; The timing control chip sends a sixth instruction to the external signal source after the output voltage of the voltage regulation circuit is stabilized, and the sixth instruction is used to control the external signal source to switch the external source signal, so that the switching frequency switching circuit outputs a second preset switching frequency signal based on the switched external source signal, and the frequency of the second preset switching frequency signal is smaller than the frequency of the first preset switching frequency signal.

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