Transmitter arrangement with centralized supply modulator

Abstract

A transmitter arrangement (400) comprises a number N of signal chains (S1, S2,... SN) is provided. Each signal chain comprises a transmitter circuit (TX1, TX2,... TXN), a power amplifier circuit (PA1, PA2,... PAN) and an antenna element (Ant1, Ant2,... AntN); The transmitter arrangement (400) further comprises a single baseband integrated circuit (ICBB) configured to receive data (D) to be transmitted and generate a baseband signal and a single supply modulator integrated circuit (ICSM) configured to receive the baseband signal and generate a modulated supply voltage to each of the N power amplifier circuits (PA1, PA2,... PAN). The modulated supply voltage comprises a first modulated supply voltage (VDD1) and a second modulated supply voltage (VDD2). A level of each of the first and a second modulated supply voltages is changing over time, and the first and the second modulated supply voltage are alternately larger than the other such that a polarity of the voltage difference between the first and second modulated supply voltages is changing over time.

Description

[0001] TRANSMITTER ARRANGEMENT WITH CENTRALIZED SUPPLY MODULATOR

[0002] TECHNICAL FIELD

[0003] Embodiments herein relate to transmitter arrangement. In particular, they relate to transmitter arrangement with centralized supply modulator, as well as antenna array system and wireless communication devices comprising the transmitter arrangement.

[0004] BACKGROUND

[0005] Nowadays there is a focus on power consumption and energy efficiency of electronic products and their hardware. For products and hardware associated with wireless communication systems like Third Generation (3G), Fourth Generation (4G), Fifth Generation (5G), Wireless Local -Area Network (WLAN), Wireless-Fidelity (Wi-Fi), and upcoming Sixth Generation (6G), the radio power consumption is dominated by the Radio Frequency (RF) Power Amplifier (PA) in the Transmitter (TX). In order to reduce the power consumption of the PA, hardware concepts like a Doherty PA (DPA), out phasing PAs, and / or supply modulated PA can be used to reduce the average power consumption of the TX, when modulated carrier signals with a non-constant envelope are transmitted.

[0006] For supply modulated PAs, the main advantages are large frequency-range and improved back-off efficiency, and the main disadvantages are higher hardware cost and large physical size or dimensions, due to the need for multiple Integrated Circuits (IC) in different technologies. The disadvantages are also further increased when supply modulated PAs are used within an Antenna-Array System (AAS), as disclosed in patent application US 2011 / 0151806 Al, since space in such systems is often highly limited and the multitude of transceivers further increases the hardware cost of ICs and Printed Circuit Board (PCB). Another well-known problem is the so-called bandwidth expansion related to the coordinate transformation from Cartesian to Polar coordinates.

[0007] An example of a supply-modulated polar transmitter system for an AAS is shown in Figure 1(a). In Figure 1(a), each antenna element Anti, Ant2, ...AntN is connected to an individual supplymodulating transmitter chain Tl, T2, ...TN. Each transmitter chain Tl, T2, ...TN includes a base band (BB) circuit ICij, a TX circuit IC24,aPA circuit ICj,,. and a Low-Pass Filter (LPF) and Supply Modulator (SM) circuit IC4,i, where i=l,2. . .N. Each TX circuit ICS includes a frequency generator FG, a mixer or frequency up converter Mx, a PA driver PPA, and a phase-shifter PhS. The phase shift PhS in the figure represents a system block, which implements and enables beam-forming functionality. The beam-forming functionality may also be placed for example in the frequency generator FG, in the frequency up-converter Mx, prior to the PPA, and may also after the PA (less preferred). An example PCB floorplan for an AAS with high frequency, e.g. a mm -wave frequency range 2 (FR2), is shown in Figure 1(b). As can be seen from the figure, the number of ICs required is 3 per antenna element, i.e. one BB circuit ICij, one TX and PA circuit IC2.i / IC3,i and one supply modulator circuit IC4,i. If a central BB IC is used, the number of ICs required will be 2 per antenna element. In this example, the TX and PA is implemented on the same die or chip in the same technology, or on different dies / chips with different technologies but in the same package. For an implementation appropriate for a high power AAS with Frequency Range 1 (FRl) / sub-6 GHz band, the number of ICs required will be 4 per antenna element or 3 if a central BB IC is used, since the PA and TX circuits are in separate packages.

[0008] In order to reduce the bandwidth-expansion of a supply modulated system, a pseudo-cartesian transmitter system may be used as disclosed in patent application US 7,773,693 B2. Figure 2(a) shows an example pseudo-cartesian transmitter system for an AAS. Each antenna element Anti, . . . AntN is connected to an individual supply-modulating transmitter chain Tl, . . . TN. Each transmitter chain Tl, ... TN comprises a BB circuit ICij, a TX circuit IC24,aPA circuit ICs,i, and a LPF and SM circuit IC4,i, where i= 1 ,2.. .N. Each TX circuit IC includes a frequency generator FG, a phase shifter PhS, a signal splitter and phase shifter- / +45° and phase swappers PhSw, to generate a quadrature LO-signal LOqand an in-phase LOi signal. The PA circuit IC3. comprises two PAs, one in-phase power amplifier PAi and one quadrature power amplifier PAQ. The SM circuit IC4,i comprises two LPFs and two SMs, one for in- phase power amplifier PAi and one for quadrature power amplifier PAQ. TO enable four-quadrant modulation, the phase-swappers PhSw are used in this system, because the control signals IBBand QBBfed to the SMs are absolute-values i.e. rectified versions of the I and Q baseband coordinates. When a PA output should change the sign of its carrier signal due to a change of sign of its baseband signal, then the phase-shift from positive to negative values is performed by swapping the phase of the corresponding LO-signal. The in-phase PAi provides the I-baseband signal up-converted by the LOi, and the quadrature PAQ provides the Q-baseband signal up-converted by the LOQ, and by combining the outputs from the two PAs, a modulated output signal is generated. An example PCB floorplan for an AAS at FR2 is shown in Figure 2(b), which may also apply to higher frequencies applications, e.g. higher than FR2. The number of ICs required is 3 per antenna element, i.e. one baseband circuit ICij, one TX and PA circuit IC2.i / IC3,i and one supply modulator circuit IC4,i. If a central BB IC is used, the number of ICs required will be 2 per antenna element. In this example, the TX and PA circuits are implemented on the same die in the same technology, or on different dies in different technologies but in the same package. For an implementation appropriate for a high power AAS at FRl / sub-6 GHz, the number of ICs required is 4 per antenna element or 3 if a central BB IC is used, since the PA and TX circuits are separated into individual packages.

[0009] The most significant drawback of these solutions is that individual SM is used for each PA and the multiple SMs are not utilized to their full potential. For reducing the cost of the multiple SMs, each individual SM is implemented with sub-optimal semiconductor processes and low-performance discrete components to reduce the cost of the overall transmitter system. In these solutions, either the SM or the AAS is used sub-optimally or with limited functionality, which again leads to compromises in performance. Further, these systems have a high ratio of bandwidth expansion, and are thus not usable for frequencies above FR1 or 6 GHz.

[0010] SUMMARY

[0011] Therefore, it is an object of embodiments herein to provide a transmitter arrangement and an AAS with improved performance on power efficiency and reduced bandwidth expansion.

[0012] According to one aspect of embodiments herein, the object is achieved by a transmitter arrangement comprises a number N of signal chains. Each signal chain comprises a transmitter circuit, a power amplifier circuit and an antenna element. The transmitter arrangement further comprises a single baseband integrated circuit configured to receive data to be transmitted and generate a baseband signal. The transmitter arrangement further comprises a single supply modulator integrated circuit configured to receive the baseband signal and generate a modulated supply voltage to each of the N power amplifier circuits. The modulated supply voltage comprises a first and a second modulated supply voltages. The level of each of the first and a second modulated supply voltages are changing over time, and the first and a second modulated supply voltages are alternately larger than the other such that the polarity of the difference between the first and a second modulated supply voltages can be changed. In other words, the level of each of the first and a second modulated supply voltages may vary over time, and the polarity of their voltage difference may change over time. For example, the first modulated supply voltage at a time is larger than the second modulated supply voltage, and at other time it is smaller than the second modulated supply voltage. During the polarity change of the voltage difference between the first and a second modulated supply voltages, i.e. when it passes a zero-crossing, the first and a second modulated supply voltages may be equal. Each of the first and a second modulated supply voltages may be positive or negative.

[0013] According to some embodiments herein, each signal chain may be a bipolar envelope transmitter chain. Each of the power amplifier circuits may comprise a power amplifier with dual polarity configured to receive the two modulated supply voltages from the single supply modulator integrated circuit. A part of the baseband signal is input to each of the transmitter circuits for beamforming.

[0014] According to some embodiments herein, each signal chain may be a cartesian transmitter chain. Each power amplifier circuit may comprise a quadrature power amplifier comprising a power amplifier with dual polarity and an in-phase power amplifier comprising a power amplifier with dual polarity. The single supply modulator integrated circuit comprises a first supply modulator configured to generate a first and second modulated supply voltages for the in-phase power amplifier, and a second supply modulator configured to generate a first and second modulated supply voltages for the quadrature power amplifier. For each power amplifier circuit, outputs of the quadrature and in-phase power amplifiers are combined to an output of the power amplifier circuit and coupled to the corresponding antenna element. According to some embodiments herein, an antenna array system comprising one or more transmitter arrangement described above is provided.

[0015] According to some embodiments herein, a wireless communication device comprising one or more AAS comprising one or more transmitter arrangement described above is provided. The wireless communication device may be a user equipment or a base station for a cellular communications system.

[0016] In other words, embodiments herein provide a transmitter arrangement using one single SM integrated circuit for supply modulation to improve power efficiency and an AAS comprising one or more such transmitter arrangement. By using a single SM integrated circuit that can handle both positive and negative output voltage differences, very linear switched-mode power amplification can be used. This is important in reducing or mitigating bandwidth expansion due to the non-linear transformation to polar coordinates. Both cartesian and bipolar envelope systems can be used.

[0017] Some advantages of embodiments herein are but not limited to:

[0018] • By using a single SM integrated circuit, it can be fabricated with high performance components while still maintaining an attractive cost level of the whole system. The complete AAS requires only a single SM integrated circuit with one SM or a pair of SMs per antenna array or per antenna sub-array, which means it can be implemented in a more advanced technology with more expensive discrete components like inductors and transformers, ensuring high performance, while still reducing the overall product Bill-Of- Material (BOM) of the whole system.

[0019] • Enabling optimal use of supply modulation within an AAS, by reducing or removing the well-known bandwidth expansion and by enabling the possibility for maximum performance from the single SM integrated circuit.

[0020] • The single SM integrated circuit may be placed at the center of the power supply plane to all PAs to mitigate delay variations.

[0021] • The beamforming can be implemented by phase shifts without any signal modulation properties, e.g. in the LO phase, which results in a simplified implementation of the phaseshifter circuit and a low-complexity system.

[0022] • Enabling the maximum possible modulation bandwidth, by using a purely cartesian supply modulation, which also enables the transmitter arrangement to be used at higher frequencies where the bandwidths are higher.

[0023] • By only using a single SM integrated circuit with one SM or a pair of SMs per antenna array or per antenna sub-array, the use of low loss high Q components is possible without affecting the BOM, and the required amount of decoupling capacitance between the SM and PAs is also reduced, enabling the use of higher modulation bandwidth.

[0024] Therefore, embodiments herein provide a transmitter arrangement and an AAS with improved performance on power efficiency and reduced bandwidth expansion while reducing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Examples of embodiments herein are described in more detail with reference to attached drawings in which:

[0026] Figure 1 (a) is a schematic block view of a polar transmitter system according to an example, and (b) is a schematic block view of an example PCB floorplan of the polar transmitter system;

[0027] Figure 2 (a) is a schematic block view of a pseudo-cartesian transmitter system according to an example, and (b) is a schematic block view of an example PCB floorplan of the pseudocartesian transmitter system;

[0028] Figure 3 (a) is a schematic block view of a bipolar envelope transmitter system according to an example, and (b) is a schematic block view of an example PCB floorplan of the bipolar envelope transmitter system;

[0029] Figure 4 is a schematic block view of a transmitter arrangement according to embodiments herein;

[0030] Figure 5 (a) and (b) are diagrams illustrating an example of two modulated supply voltages according to embodiments herein;

[0031] Figure 6 is a schematic block view of an example power amplifier with dual polarity according to embodiments herein;

[0032] Figure 7 (a) is a schematic block view of a transmitter arrangement according to an example embodiment; (b) is a schematic block view of an example floorplan of the transmitter arrangement shown in (a);

[0033] Figure 8 (a) is a schematic block view of a transmitter arrangement according to another example embodiment; (b) is a schematic block view of an example floorplan of the transmitter arrangement shown in (a); (c) is a schematic block view of another example floorplan of the transmitter arrangement shown in (a);

[0034] Figure 9 is a schematic block view of an example quadrature power amplifier with dual polarity according to embodiments herein;

[0035] Figure 10 is a schematic block view of an example transmitter arrangement with attenuator according to embodiments herein;

[0036] Figure 11 is a schematic block view of an example attenuator;

[0037] Figure 12 (a)-(d) are schematic block views illustrating different types of supply modulators; and

[0038] Figure 13 is a block diagram illustrating a wireless communication device in which a transmitter arrangement according to embodiments herein may be implemented. DETAILED DESCRIPTION

[0039] As discussed in the Background, in the transmitter systems shown in Figures 1-2, individual SM is used for each PA which leads to multiple SMs with increased complexity and cost. Further, these systems have a high ratio of bandwidth expansion. Due to these limitations, these systems are not suitable solutions for high-performance cost-effective AASs at frequencies higher than e.g. 6 GHz. These high- performance cost-effective AASs will be needed for future power savings and environmentally friendly electronic products.

[0040] An approach to reduce the bandwidth-expansion of a supply modulated system is to use a bipolar envelope transmitter system, where an envelope signal in addition to magnitude also has a sign, so it may have both negative and positive values. A bipolar envelope transmitter uses both positive and negative voltage levels to transmit digital data. It alternates between different voltage levels to represent digital symbols, typically around a zero voltage reference point. In a supply modulated system, the abrupt transitions in phase and magnitude occurring as the signal passes near the origin, i.e. the zero voltage reference point, will cause bandwidth-expansion. This abrupt transitions in phase and magnitude can be reduced in a bipolar envelope transmitter system by changing the sign of the envelope signal near the signal amplitude minimum, representing a 180° phase-shift, so that the phase-coordinate does not have to perform this 180° step / shift, and the envelope coordinate does not have to change sign of its derivative. An example bipolar envelope transmitter system for an AAS is shown in Figure 3(a), where each antenna element Anti, ... AntN is connected to an individual supply-modulating transmitter chain Tl, ... TN. Each transmitter chain Tl, ... TN includes a BB circuit ICij, a TX circuit IC24,aPA circuit ICj,i. and a SM with LPF circuit IC4,i, where i=l,2. . .N. Each TX circuit IC2,i includes a frequency generator FG, a mixer or frequency up converter Mx, a PA driver PPA, and a phase-shifter PhS. An example PCB floorplan for an AAS with FR2 is shown in Figure 3(b), which may also apply to higher frequencies applications, e.g. higher than FR2. The number of ICs required is 3 per antenna element, i.e. one BB circuit ICi.i, one TX and PA circuit IC2.i / IC3,i and one SM circuit IC4,i. If a central BB IC is used, the number of ICs required will be 2 per antenna element. The TX and PA circuits may be implemented on the same die in the same technology, or on different dies in different technologies but in the same package. For an implementation appropriate for a high power AAS with FRl / sub-6 GHz, the number of ICs required will be 4 per antenna element or 3 if a central BB IC is used, since the PA and TX circuits are separated into individual packages.

[0041] To remove all bandwidth expansion completely, a purely cartesian supply modulated transmitter system may be used. However, similar as the pseudo-cartesian transmitter system shown in Figure 2(a), multiple SMs may be used, and the number of ICs required is still 3 per antenna element, i.e. one BB circuit ICi.i, one TX and PA circuit IC2.i / IC3,i and one supply modulator circuit IC4,i.

[0042] The multiple SMs in these systems are used sub-optimally or with limited functionality, which again leads to compromises in system performance. Embodiments herein propose to use a single SM integrated circuit for the complete or a large portion of an AAS. By using a single SM integrated circuit, the cost problem of the multiple SM integrated circuits can be reduced. The single SM integrated circuit may comprise one SM for a bipolar transmitter system or a pair of SMs for a cartesian transmitter system. The SM can generate two supply voltages such that the difference between the two supply voltages may be positive and negative enabling amplifiers with output signal envelope of both signs which is important in reducing or mitigating the bandwidth expansion due to the non-linear transformation to polar coordinates.

[0043] Figure 4 shows a schematic block diagram of a transmitter arrangement 400 according to embodiments herein. The transmitter arrangement 400 comprises a number N of signal chains Si, S2, ... SN. Each signal chain Si, S2, . . . SN comprises a transmitter circuit TXi, TX2, ...TXN, a power amplifier circuit PAi, PA2, ...PAN and an antenna element Anti, Ant2, ...AntN. The transmitter arrangement 400 further comprises a single baseband integrated circuit ICBB configured to receive data D to be transmitted and generate a baseband signal SBB. The transmitter arrangement 400 further comprises a single supply modulator integrated circuit ICSM configured to receive the baseband signal or a portion of the baseband signal SBB and generate a modulated supply voltage to each of the N power amplifier circuits PAi, PA2, . . . PAN. The modulated supply voltage comprises a first modulated supply voltage VDDI and a second modulated supply voltage VDD2. The levels of the first and second supply voltages are changing over time such that the polarity of the voltage difference between the first and second modulated supply voltages is changing over time.

[0044] Figure 5 (a) is a diagram schematically showing the level changing over time for the first and the second modulated supply voltages VDDI, VDD2, and the difference between the first and second modulated supply voltages VDDI, VDD2 is shown as Vout. Figure 5 (b) is a diagram schematically showing the level (on Y-axis) changing for the first and the second modulated supply voltages VDDI, VDD2 and the difference between the first and second modulated supply voltages VDDI, VDD2 is shown as Vout on X-axis. The level of each of the first and second supply voltages VDDI, VoD2may vary within a range, e.g. between normalized values 0 and 1 over time. As can be seen, the first and a second modulated supply voltages VDDI VDD2 are alternately larger than the other over time and may be equal at a time. For example, the first modulated supply voltage VDDI at a time, e.g. during time 0-t 1 , is larger than the second modulated supply voltage VDD2, and at other time, e.g. during tl-t2, VDDI is smaller than VDD2. The difference between the first and second modulated supply voltages VDDI, VDD2 is shown as Vout and it is changing between 1 and -1 over time. During a polarity change of the Vout, the first and a second modulated supply voltages may be equal, i.e. when Vout passes zero-crossing, the levels of the first and second modulated supply voltages VDDI, VDD2 are equal.

[0045] The first and second modulated supply voltages VDDI, VDD2 may be supplied to a PA with dual polarity comprised in each power amplifier circuit PAi, PA2, . . . PAN. Then an output voltage Vout with either a negative or positive amplitude proportional to the difference between the first and second modulated supply voltages, i.e. Vout=VDDi-VoD2, is created and provided to a load RL of the PA. According to some embodiments herein, each power amplifier in the PA circuits PAi, PA2, . . . PAN may be implemented by a PA 600 with dual polarity, as shown in Figure 6. The PA 600 comprises a first transistor arrangement Ml comprising a first terminal Tl, a second terminal T2 and a third terminal T3.

[0046] The PA 600 further comprises a first inductor Ln and a second inductor L12 and a third inductor L21, L22 coupled to a load RL which represents the total impedance of an antenna element. The first terminal Tl of the first transistor arrangement Ml is coupled to the input signal Vin which represents the output signal from one of the transmitter circuits TXi, TX2, . . . TXN. The second terminal T2 of the first transistor arrangement Ml is coupled to a first supply voltage VDDI via the first inductor Ln, the third terminal T3 of the first transistor arrangement Ml is coupled to a second supply voltage VDD2 via the second inductor L12.

[0047] The third inductor may be a single inductor or comprise two inductors L21, L22 connected in series with each other and with the load RL, and the first and second inductors Ln, L12 are coupled to the two inductors L21, L22 respectively, k is coupling coefficient between the first / second inductor L11 / L12 and the third inductor L21, L22.

[0048] The third inductor, i.e. the two inductors L21, L22 may form a differential inductor connected in parallel to the load RL, and the first and second inductors Ln, L12 are coupled to the differential inductor.

[0049] The first and second supply voltages VDDI, VDD2 may be modulated between a first voltage level and a second voltage level. The second voltage level is higher than the first voltage level. The first transistor arrangement Ml is operating in a switching mode such that an output signal voltage Vout with either a negative or positive amplitude proportional to the difference between the first and second supply voltages, i.e. Vout=Vddl-Vdd2, is created and provided to the load RL.

[0050] VB is a bias voltage source and coupled to the first terminal Tl via a bias inductor LB or a resistor RB, RS is the source impedance or resistance of the input signal Vin, and Cd is an AC-coupling capacitor preventing unnecessary DC current flow between the voltage sources VB and Vin.

[0051] The first transistor arrangement Ml may comprise a metal-oxide-semiconductor (MOS) fieldeffect transistor. The MOS transistor Ml will operate as a switch, connecting its two supply voltages VDDI, VDD2 together when closing, making the output signal amplitude Vout equal to the supply voltage difference. The direction of the current flow through the MOS transistor Ml will depend on which supply voltage is larger.

[0052] The first and second supply voltages VDDI, VDD2 may be generated linearly by the single supply modulator integrated circuit ICSM as a function of a target amplitude of the output signal voltage Vout. For examples, when the first supply voltage VDDI is at the first voltage level, e.g. 0 or a minimum value Vmin, and the second supply voltage VDD2 is at the second voltage level, e.g. a maximum value Vmax, the output signal voltage Vout is negative with the maximum value, i.e. -Vmax, when the first supply voltage VDDI is at the maximum Vmax and the second supply voltage VDD2 is at the minimum value, the output signal voltage Vout is positive with the maximum value, i.e. +Vmax, and when the first and second supply voltages VDDI, VDD2 are both halfway between the first and second voltage levels, e.g. between the minimum value and the maximum value, the output signal voltage Vout is zero or at the minimum value Vmin. The ranges of the first and second voltage levels may be located at any level with respect to the signal ground, including both positive and negative voltages. Modulating the two supply voltages between the first and second voltage levels, e.g. between the minimum and maximum values, voltage differences of both polarities can be created.

[0053] Figure 7(a) shows a schematic block diagram of a transmitter arrangement 700 according to embodiments herein, where the transmitter arrangement 700 is implemented as a bipolar envelope system with one SM in the single SM integrated circuit. That is each signal chain Si, S2, ... SN is a bipolar envelope transmitter chain Tl, ...TN as shown in Figure 3(a). The transmitter arrangement 700 comprises a base band circuit BB ICi, a single SM circuit IC4, and a number N TX TXi,i circuits IC24, where i=l, 2. . .N. Each TX circuit IC2,i comprises a frequency generator FG configured to generate a local oscillator signal LO, a mixer or frequency up converter Mx configured to up convert a phase component 0 of a polar base band signal, a PA driver PPA configured to provide necessary signal amplification and condition to drive the PA, and a phase-shifter PhS configured to shift the phase of the signal input to the PA. A part of the baseband signal, i.e. the phase component 0 of the polar baseband signal is input to each of the transmitter circuits TXi, TX2, . . . TXN for beamforming using the phase shifters PhS. The single SM circuit IC4 receives an envelope component EUVBP of the baseband signal from the BB circuit ICi .

[0054] The key functionality of the bipolar envelope transmitter chain is that for each PAi, PA2, . . . PAN which comprises a dual polarity PA 600 as shown in Figure 6, its power supply is controlled by the modulated supply voltage generated by the single SM circuit IC4 which means the up-conversion or mixing of the envelope information is performed within each PA. This means that each PA can be fed with the same envelope-based signals, while the beamforming is performed on the phase modulated LO signal, i.e. LO+0, using phase shifters PhS at the PA inputs. This means the proposed solution is appropriate and usable for small to medium sized antenna arrays, sub-arrays, and / or all types of devices including user equipment (UEs).

[0055] The transmitter arrangement 700 with dual polarity PA has an advantage over a standard polar transmitter. It can do a 180-degree phase shift by crossing the origin in the IQ-constellation diagram without any abrupt signal transitions occurring inside the circuit. This helps to mitigate the well-known problem with bandwidth expansion when going from cartesian coordinates to polar coordinates.

[0056] Compared to a conventional polar transmitter, where the positive supply voltage is always positive, and the negative supply voltage is always negative, i.e. the differential supply voltage never change polarity, the difference between the first and second modulated supply voltages generated by the single SM for the dual polarity PA can change polarity over time.

[0057] By implementing the beamforming functionality of the AAS by phase-shifting or time-delaying the LO signal, i.e. LO+0, a single SM is better utilized for all the PAs in the AAS. An example PCB floorplan for an AAS at Frequency Range 2 (FR2) or higher frequencies than FR2 is shown in Figure 7(b). As can be seen, each antenna element requires only 1 TX / PA IC, i.e. IC24+ IC3 1. All the antenna elements Anti, Ant2, . . . AntN share one BB circuit ICi and one SM circuit IC4. An implementation appropriate for a high power AAS with FRl / sub-6 GHz band will require 2 ICs per antenna element if TX circuit and PA circuit are implemented in 2 different packages, and one BB circuit ICi and one SM circuit IC4 can be shared by all the antenna elements together. By further integrating the AAS system into a single die, or single component, or single package, the antenna elements may also be placed inside the component or package, only 3 ICs are needed for the whole AAS. A special version of this solution may be to divide the antenna array into 2 to 4 sub-arrays and feed each sub-array with an individual SM, i.e. 2 to 4 SM chips may be used for the complete AAS. This highly integrated AAS is appropriate for mm-wave and sub-THz, but one drawback of this solution is that all the bandwidth expansion is not removed, only reduced to a large extent by using a bipolar envelope signal representation.

[0058] To remove the bandwidth expansion within the supply modulated AAS, a purely cartesian supply modulated system with two SMs, one for I base band signal IBB and one for Q base band signal QBB, is proposed, and the two SMs are implemented on the same die or chip, i.e. a single SM integrated circuit comprise a pair of SMs. Figure 8(a) shows an example block diagram of a transmitter arrangement 800, where each signal chain is a cartesian transmitter chain. The transmitter arrangement 800 comprises a BB circuit ICi, a number N of transmitter circuits TXI,...TXN, i.e. IC24 ■> where i=l, . . .N, and a single SM circuit IC4 comprising a first SM SMi with an LPF configured to generate a supply modulated voltage comprising a first and second supply modulated voltages VIDDI, VIDD2 for I power amplifier, and a second SM SM2 with an LPF configured to generate a supply modulated voltage comprising a first and second supply modulated voltages VQDDI, VQDD2 for Q power amplifier. The transmitter arrangement 800 further comprises a number N of PA circuits PAi, . . . PAN, i.e. IC3, 1, where i= 1 , . . .N, each PA circuit comprises two PAs, one in-phase PA PAi, one quadrature PA PAQ. Each of the in-phase and quadrature power amplifiers PAi, PAQ comprises a power amplifier with dual polarity as shown in Figure 6. Each transmitter circuit TXI,...TXN comprises a frequency generator FG configured to generate an LO signal, a phase-shifter PhS configured to shift phase of the LO signal and a signal splitter and phase shifter - / +45° configured to generate quadrature LO-signals LOi, LOQ. The in-phase PA PAi provides the I-baseband signal up-converted by the LOi, and the quadrature PA PAQ provides the Q-baseband signal up-converted by the LOQ. Then by combining the outputs from the two PAs, any modulated signals can be generated, such as high bandwidth orthogonal frequency-division multiplexing (OFDM) signals. The outputs of the quadrature and in-phase power amplifiers are combined to an output of the power amplifier circuit. The output of each power amplifier circuit PAi, PAN is coupled to its corresponding antenna element Anti, ... AntN.

[0059] An example PCB floorplan of an AAS for FR2 or higher frequencies than FR2 is shown in Figure 8(b). As can be seen, each antenna element Anti, Ant2. . . AntN requires only 1 TX / PA IC, i.e. IC24+ IC34. All the antenna elements Anti, Ant2, . . . AntN share one BB circuit ICi and one SM with LPF circuit IC4. An example of further integrated floorplan of an AAS is shown in Figure 8(c), where all TXs / PAs are integrated on the same IC.

[0060] The transmitter arrangement 800 with purely cartesian supply modulated system is very similar to the transmitter arrangement 700 with bipolar supply modulated system, i.e. both systems operate with positive and negative differential output voltages i.e. bipolar coordinates, uses a single SM integrated circuit per antenna array or sub-array, and performs the beamforming functionality on the LO signal. However, the differences are that the purely cartesian supply modulated system requires one SM for the I baseband signal IBB and another SM for the Q baseband signal QBB and a quadrature LO signal, such that no bandwidth expansion occurs for the baseband signals. The transmitter arrangement 800 with purely cartesian supply modulated system is applicable for high power AAS at FRl / sub-6 GHz band and the further integrated floorplan shown in Figure 8(c) can be used for AAS at FR2 and beyond.

[0061] According to some embodiments herein, each of the PA circuits PAi, PA2, . . . PAN in transmitter arrangement 800 may be implemented by a PA 900 shown in Figure 9. The PA 900 comprises an in- phase PAi and a quadrature PAQ Each of the PAi and PAQ is a dual polarity PA and has the same structure and operates in the same way as the PA 600 shown in Figure 6. The in-phase PAi is for amplifying I input signal Vin-I and outputting I signal Vout-I. The quadrature PAQ is for amplifying Q input signal Vin-Q and outputting Q signal Vout-Q. The two inductors L21, L22 of the two power amplifier circuits are connected in series with each other and in parallel with the load RL such that the I and Q output signals Vout-I, Vout-Q are combined to an output signal Vout and provided to the load RL. To simplify the drawing, the name annotations for the components in the I and Q power amplifier circuits are the same except for the voltage sources and output voltages for the I and Q power amplifier circuits.

[0062] The MOS transistor in the PAi and PAQ operates as a switch, connecting its two supply voltages together when closing, making the output signal amplitude equal to the difference of the two supply voltages. The direction of the current flow through the MOS transistor will depend on which supply voltage is larger. The current flowing out from one voltage supply will flow into the other voltage supply and charge it, and the two voltage supplies will take turns charging each other in this way. This results in an automatic healing of electromigration damage of metals in inductors and transistors as the direct current (DC) current will flow in opposite directions for positive and negative output signal amplitudes. Moreover, the common-mode voltage can have larger amplitude which will not cause additional power losses, and the common mode voltage can be chosen freely, so the output signal amplitude to supply voltage characteristics can be linear to minimize the bandwidth expansion.

[0063] The power amplifier circuits PAi, PA2, . . . PAN according to embodiments herein operates as a switched mode amplifier with supply modulation, so high efficiency can be obtained at both peak power and in power back-off conditions. The power amplifier circuit PAi, PA2, . . . PAN has linearly modulated supply voltages and dual polarity output signal amplitude which allows the signal trajectory to pass directly through the origin of the constellation plane with purely linear signal behaviour. In the following, issues and implementation of antenna beamforming will be discussed. In antenna beamforming, the main lobe represents the desired direction of the beam, while sidelobes are lobes of radiated energy that occur in directions other than the main lobe. Sidelobes can arise due to imperfections in the antenna array or signal processing algorithms, and they can interfere with adjacent signals or introduce noise into the system. Beamforming tapering can reduce the level of sidelobes in the beamforming pattern. Tapering in beamforming means that the magnitude of weights for signals to the antenna elements in an AAS can be set to different values, i.e. they are not all set to the same magnitude. The trade-off is that the main lobe will then be wider and have a reduced peak gain. Typically, this is accomplished by having higher signal amplitude near the centre of antenna array, and less near the edges of antenna array. To implement tapering, attenuators can be introduced for a subset of the antenna elements, or all antenna elements. The attenuators can be fixed or programmable. Figure 10 shows attenuators introduced in the transmitter arrangement 800 with purely cartesian supply modulated system shown in Figure 8(a), where only one signal chain is shown. Individual attenuator ATT may be placed between the output of the combined output signals from the cartesian PA and the corresponding antenna element. The attenuator ATT may be implemented with a circuit 1100 shown in Figure 11. The attenuator 1100 may be implemented off-chip or on-chip, resistors R1 and R2 set the attenuation and both resistors may be programmable. Metal-oxide-semiconductor (MOS) switches and fixed resistors may be used to implement the programmable resistors. Such programmable attenuators may be implemented for a subset or for all antenna elements. When the attenuators are implemented off-chip, i.e. on a carrier or PCB, it may be more feasible to use fixed attenuators. These are then used for a subset of antenna elements, typically near the edges of the antenna array. There may be one or more fixed attenuation values, and these attenuators are then typically put on antenna elements in perimeters of the antenna array,, with the highest attenuation value used closest to the edge of the antenna array, i.e. the first perimeter of the antenna array, and then the next highest attenuation value just inside the first perimeter, and so on. The attenuators can then be placed anywhere between the chip and antenna element, where there is room for it on the carrier or PCB. The attenuator 1100 may also be implemented on-chip, i.e. on the same die or chip as the PA circuits.

[0064] The beamforming tapering may also apply to the other proposed systems, e.g. as shown in Figure 7. Figure 12 shows some examples of supply modulators which can be used for the proposed transmitter arrangements 700, 800 shown in Figures 7-8, to generate a supply modulated voltage for PA, where (a) shows a single-ended buck converter 1210, (b) shows a single-ended hybrid-switching modulator 1220, (c) shows a differential buck converter 1230, and (d) shows a differential hybridswitching modulator 1240. The PA is represented as ZPA in the figures.

[0065] The differential buck converter 1230 comprises a differential Buck Converter and a differential inductor-capacitor (LC) filter and may be configured to generate a supply modulated voltage which may be a supply modulated differential voltage or may comprise a first and second supply modulated voltages, each of the first and second supply modulated voltages may be positive or negative. The single-ended buck converter 1210 comprises a single-ended Buck Converter and a single- ended inductor-capacitor (LC) filter and may be configured to generate a positive voltage and / or a negative voltage. For example, both positive and negative output voltages can be generated depending on the levels of VDD, VSS.

[0066] The differential hybrid-switching modulator 1240 comprises a differential linear amplifier Linear Amp, a differential switched amplifier Switched Amp, a pair of inductor L, and a Control Block. The differential hybrid-switching modulator 1240 may be configured to generate a supply modulated voltage which may be a supply modulated differential voltage or may comprise a first and second supply modulated voltages, each of the first and second supply modulated voltages may be positive or negative.

[0067] The single-ended hybrid-switching modulator 1220 comprises a single-ended liner amplifier Linear Amp, a single-ended switched amplifier Switched Amp, a pair of inductor L, and a Control Block. The single-ended hybrid-switching modulator 1220 may be configured to generate a positive voltage and / or negative voltage.

[0068] The key aspects with regards to the proposed transmitter arrangements 700, 800 is that the semiconductor technology used to implement the Buck Converter in the single-ended and differential buck converter and the Linear Amp, Control Block, and Switched Amp in the single-ended and differential hybrid-switching modulators can be a more sophisticated and advanced one, such as GaN, GaAs, etc. and a cost-effective solution which is not only limited to CMOS technology. For the off-chip components both the inductors L and capacitors C may use components with better performance than what is cost effective in the prior-art, and other more costly components may also be used, e.g. transformers for the differential modulators.

[0069] Therefore, according to embodiments herein, the SM may be implemented with both on-chip and off-chip components. The on-chip components may be implemented with more advanced semiconductor technology and the off-chip components may be implemented with higher performance discrete components to achieve a maximum performance of the SM without increase overall Bill-Of-Material of the transmitter arrangement 700, 800 compared to the solution with multiple supply modulators.

[0070] When the transmitter arrangement 700, 800 is implemented on a PCB, there is usually a power supply plane to supply power to different parts of the transmitter arrangement 700, 800. The single SM integrated circuit ICSM, IC4 may be placed close to the centre point of the power supply plane to mitigate delay variations. In this way, although the distances from the outputs of the single SM integrated circuit to the supply inputs of each of the power amplifier circuits PAi, PA2, . . . PAN will not be equal, the distance differences are minimized. The PAs near the center of the power supply plane will have almost zero distance to the SM, whereas those in the comers will have a maximum distance. However, by feeding the supply modulated voltages to the center point of the power supply plane, the PA in the comers will have the same distance to the SM, and thus delay variations are mitigated.

[0071] Those skilled in the art will understand that the PA 600, 900, the bipolar transmitter arrangement 700 and the Cartesian transmitter arrangement 800 according to embodiments herein may be implemented by any semiconductor technology, e.g. GaN, GaAs, N-type Metal Oxide Semiconductor (NMOS), P-type Metal Oxide Semiconductor (PMOS), Complementary Metal Oxide Semiconductor (CMOS), Silicon on Insulator (SOI) CMOS, fin field-effect transistor (finFET), MOSFET or Micro- Electro-Mechanical Systems (MEMS) technology, etc.

[0072] The transmitter arrangement 400, 700, 800 according to embodiments herein may be employed in various integrated circuits, electronic circuits or devices, communication devices or apparatus. Figure 13 shows a block diagram of a wireless communication device 1300 in which transmitter arrangement 400, 700, 800 according to embodiments herein may be implemented. The wireless communication device 1300 may comprise a receiver RX 1310, one or more AAS 1320 which may comprise one or more transmitter arrangement 400, 700, 800. The wireless communication device 1300 may comprise other units, where a processing unit PU 1330 and a memory Mem 1340 are shown. The wireless communication device 1300 may be a base station, or a user equipment or a mobile device for a cellular communication system.

[0073] Base station is a non-limiting term which means any type of communication node e.g. relay node, base transceiver station (BTS), access point (AP), transmission point, transmission node, transmission reception point (TRP), remote radio unit (RRU), remote radio head (RRH) node etc.

[0074] User equipment is a non-limiting term which means any terminal, wireless communication terminal, Machine Type Communication (MTC) device, Device to Device (D2D) terminal, or node e.g. smart phone, laptop, mobile phone, sensor, relay, mobile tablets or even a small base station communicating within a cell.

[0075] To summarize, embodiments herein provide a transmitter arrangement 400, 700, 800 and an AAS comprising one or more such transmitter arrangement. The transmitter arrangement 400, 700, 800 uses one single SM integrated circuit for supply modulation of N power amplifier circuits. Each PA in the N power amplifier circuits is a dual polarity power amplifier which can output both positive and negative output voltages. By using a single SM integrated circuit that can handle both positive and negative output voltages, very linear switched-mode power amplification can be used to improve power efficiency. Bandwidth expansion due to the non-linear transformation to polar coordinates is reduced or mitigated.

[0076] There are some advantages of embodiments herein for examples: a) By using a single SM integrated circuit, it can be fabricated with high performance components while still maintaining an attractive cost level of the whole system. The complete AAS requires only a single SM integrated circuit with one SM or a pair of SMs per antenna array or per antenna sub-array, which means it can be implemented in a more advanced technology with more expensive discrete components like inductors and transformers, ensuring high performance, while still reducing the overall product Bill-Of-Material (BOM) of the whole system compared to the solution with multiple SMs. b) Enabling optimal use of supply modulation within an AAS, by reducing or removing the well- known bandwidth expansion and by enabling the possibility for maximum performance from the single SM integrated circuit. c) The beamforming can be implemented by phase shifts without any signal modulation properties, e.g. in the LO phase, which results in a simplified implementation of the phase-shifter circuit and a low-complexity system. d) Enabling the maximum possible modulation bandwidth, by using a purely cartesian supply modulation, which also enables the transmitter arrangement to be used at higher frequencies where the bandwidths are higher. e) By only using a single SM integrated circuit with one SM or a pair of SMs per antenna array or per antenna sub-array, the use of low loss high Q components is possible without affecting the BOM, and the required amount of decoupling capacitance between the SM and PAs is also reduced, enabling the use of higher modulation bandwidth. f) By using the dual polarity PA with two supply voltages, an output signal Vout with both polarities, i.e. an output signal with opposite phases can be generated. The amplitude modulation is imposed on the two supply voltages which may be modulated individually between the first voltage level and the second voltage level depending on the desired output signal amplitude.

[0077] The word "comprise" or “comprising”, when used herein, shall be interpreted as non- limiting, i.e. meaning "consist at least of .

[0078] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

CLAIMS1. A transmiter arrangement (400, 700, 800) comprising: a number N of signal chains (Si, S2, . . . SN), wherein each signal chain comprises a transmiter circuit (TXi, TX2, . . . TXN), a power amplifier circuit (PAi, PA2, . . . PAN) and an antenna element (Anti, Ant2, . . . Ant ): a single baseband integrated circuit (ICBB, ICI) configured to receive data (D) to be transmited and generate a baseband signal; a single supply modulator integrated circuit (ICSM, IC4) configured to receive the baseband signal and generate a modulated supply voltage to each of the N power amplifier circuits (PAi, PA2, . . . PAN), wherein the modulated supply voltage comprises a first modulated supply voltage (VDDI) and a second modulated supply voltage (VDD2), and wherein a level of each of the first and a second modulated supply voltages is changing overtime, and the first and the second modulated supply voltage are alternately larger than the other such that a polarity of the voltage difference between the first and second modulated supply voltages is changing over time.

2. The transmiter arrangement (400, 700, 800) according to claim 1, wherein each signal chain is a bipolar envelope transmitter chain, and wherein each of the power amplifier circuits (PAi, PA2, . . . PAN) comprises a power amplifier with dual polarity (600) configured to receive the two modulated supply voltages (VDDI, VDD2) from the single supply modulator integrated circuit (ICSM, IC4), and a part of the baseband signal is input to each of the transmiter circuits (TXi, TX2, . . . TXN) for beamforming.

3. The transmiter arrangement (400, 700, 800) according to claim 1, wherein each signal chain is a cartesian transmiter chain, and wherein each power amplifier circuit (PAi,, . . . PAN) comprises a quadrature power amplifier (PAQ) comprising a power amplifier with dual polarity (600) and an in-phase power amplifier (PAi) comprising a power amplifier with dual polarity (600), the single supply modulator integrated circuit (IC4) comprises a first supply modulator (SMi) configured to generate a first and second modulated supply voltages (VIDDI, VIDD2) for the in-phase power amplifier (PAi), and a second supply modulator (SM2) configured to generate a first and second modulated supply voltages (VQDDI, VQDD2) for the quadrature power amplifier (PAQ), wherein for each power amplifier circuit (PAi, . . . PAN), outputs of the quadrature and in-phase power amplifiers (PAi, PAQ ) are combined to an output of the power amplifier circuit and coupled to the corresponding antenna element.

4. The transmiter arrangement (400, 700, 800) according to claim 3, wherein each transmiter circuit (TXi, TX2, . . . TXN) comprises a signal spliter and phase shifter configured to generate a quadrature signal (LOQ) for controlling the quadrature power amplifier (PAQ) in switched-modeoperation and an in-phase signal (LOi) for controlling the in-phase power amplifier (PAi) in switched-mode operation.

5. The transmitter arrangement (400, 700, 800) according to any one of claims 2-4, wherein the power amplifier with dual polarity (600) comprises: a first transistor arrangement (Ml) comprising a first terminal (Tl), a second terminal (T2) and a third terminal (T3); a first inductor (Ln); a second inductor (Ln): and a third inductor (L21, L22) coupled to the load (RL); wherein the first terminal (Tl) of the first transistor arrangement (Ml) is coupled to an input signal (Vin); the second terminal (T2) of the first transistor arrangement (Ml) is coupled to the first modulated supply voltage (VDDI) via the first inductor (Ln); the third terminal (T3) of the first transistor arrangement (Ml) is coupled to the second modulated supply voltage (VDD2) via the second inductor (L12); and the first and second inductors (Ln, L12) are coupled to the third inductor (L21, L22) such that voltages over the first and second inductors (Ln, L12) are transformed to the load (RL) and added constructively at the load (RL); and wherein the first transistor arrangement (Ml) is operating in a switching mode such that the output signal voltage (Vout) with either a negative or positive amplitude proportional to the difference between the first and second supply voltages (VDDI,VDD2) is created and provided to the load (RL).

6. The transmitter arrangement (400, 700, 800) according any one of claims 1-5, wherein each of the N signal chains or a subset of the N signal chains further comprises an attenuator (ATT) coupled between the output of each power amplifier circuit (PAi, PA2, . . . PAN) and the corresponding antenna element.

7. The transmitter arrangement (400, 700, 800) according to claim 6, wherein the attenuator is a programmable attenuator with variable attenuation or a fixed attenuator.

8. The transmitter arrangement (400, 700, 800) according to any one of claims 1-7, wherein the supply modulator integrated circuit (ICSM, IC4) is one or more of: a) a single-ended buck converter (1210); b) a single-ended hybrid-switching modulator (1220); c) a differential buck converter (1230);d) a differential hybrid-switching modulator (1240).

9. An antenna array system, AAS (1320), comprising one or more transmitter arrangement (400, 700, 800) according to any one of claims 1-8.

10. A wireless communication device (1300) comprising one or more AAS (1320) according to claim 9.

11. The wireless communication device (1300) according to claim 10, wherein the wireless communication device (1300) is a user equipment or a base station for a cellular communications system.

Images