Micro-electromechanical system apparatus and its fabrication method

Abstract

A layered structure (104) of the micro-electromechanical system apparatus comprises a sacrificial layer (106) between a first layer arrangement (108') and a second layer arrangement (110') of the layered structure (104). The sacrificial layer (106) comprises a trench (100) with a shape of a trench pattern (100'). The trench (100) extends through the sacrificial layer (106), and the trench pattern (106') defines a boundary to at least one cavity area (120) of micro-electromechanical system apparatus. The first layer element (108') comprises at least one hole (124) through the first layer arrangement (108') of the layered structure (104) and / or the second layer element (110') comprises an opening (700) through a second layer arrangement (110'). The first layer arrangement (108') and the second layer arrangement (110') are in contact with the sacrificial layer (106). The at least one hole (124) is smaller than the cavity area (120) which the at least one hole (124) is associated with, and the opening (700) is equal to or smaller than the cavity area (120) which the opening (700) is associated with. Each of the cavity area (120) includes a cavity (120') between the first layer arrangement (108') and the second layer arrangement (110'), the cavity (120') being laterally limited by a barrier structure (116) wall arrangement (116') of the trench (100).

Description

[0001] Micro- electromechanical system apparatus and its fabrication method

[0002] Field

[0003] The invention relates to a micro-electromechanical system apparatus and its fabrication method.

[0004] Background

[0005] Many MEMS structures require customized substrates to facilitate their release etch. For example, cavity silicon-on-insulator (CSOI) wafers were developed specifically to eliminate the need for a wet hydrofluoric release etch step after the deep reactive-ion etching (DRIE) defines the resonant structures. Thin film body acoustic resonators (FBAR) have also been shown to benefit from a long DR1E to remove the backside silicon from beneath the resonator.

[0006] However, during the course of the long etch process of the DR1E, the precision of the etch degrades and small amounts of roughness will increase. Eventually, as the etch reaches through the full wafer to a stop on the front side element (forming the membrane) the sidewall roughness and dimensional variation can be significant enough to cause variation in the membrane effective radius which degrades the quality of the end product. If this membrane is an integral element to a resonator, for example, the dimensional variation will translate to undesirable variation in the device resonance frequency or in sensitivity. Of course, the DR1E process, per se, may be tuned, but that does not solve the actual problem, and the tuning leads typically to deterioration of other process features and also the quality of the end product.

[0007] Brief description

[0008] The present invention seeks to improve in the micro-electromechanical system apparatus and its fabrication method.

[0009] The invention is defined by the independent claims. Embodiments are defined in the dependent claims. If one or more of the embodiments is considered not to fall under the scope of the independent claims, such an embodiment is or such embodiments are still useful for understanding features of the invention.

[0010] List of drawings

[0011] Example embodiments of the present invention are described below, by way of example only, with reference to the accompanying drawings, in which

[0012] Figures 1A to 1G illustrate examples of fabrication phases of a microelectromechanical system apparatus;

[0013] Figures 2A to 21 illustrate further examples of fabrication phases of a micro-electromechanical system apparatus;

[0014] Figure 3 illustrates an example of a photolithographic layer formed with a pattern of the trench pattern on the first layer arrangement;

[0015] Figure 4 illustrates an example of a circular unit of a microelectromechanical system apparatus;

[0016] Figure 5 illustrates an example of a conical unit of a microelectromechanical system apparatus;

[0017] Figure 6 illustrates an example of a matrix of circular units of a microelectromechanical system apparatus;

[0018] Figure 7 illustrates an example of a matrix of conical units of a microelectromechanical system apparatus;

[0019] Figure 8 illustrates an example of a single unit of a microelectromechanical system apparatus, the single unit having an open backside;

[0020] Figures 9 and 10 illustrate examples of locations of etch holes of a single unit of a micro-electromechanical system apparatus;

[0021] Figures 11 and 12 illustrate examples of the profiles of the etch holes; and

[0022] Figure 13 illustrates of an example of a flow chart of a fabrication method. Description of embodiments

[0023] The following embodiments are only examples. Although the specification may refer to "an" embodiment in several locations, this does not necessarily mean that each such reference is to the same embodiment's), or that the feature only applies to a single embodiment.

[0024] Single features of different embodiments may also be combined to provide other embodiments. Furthermore, words "comprising" and "including" should be understood as not limiting the described embodiments to consist of only those features that have been mentioned and such embodiments may also contain features / structures that have not been specifically mentioned. All combinations of the embodiments are considered possible if their combination does not lead to structural or logical contradiction.

[0025] The microelectromechanical system apparatus described in this document may replace those customized MEMS devices or devices that require long DR1E release processes, and it may be done in a cost saving manner. The structure builds a releasable membrane out of polysilicon or the like which is defined by confining barriers that ensure precision dimensions following release. That further improves critical aspects of the device such as resonant structures and variation of quality.

[0026] Many MEMS structures benefit from the use of a customized substrate to either facilitate their release or even improve the device performance. For example, silicon resonators etched through the thick device layer of an SOI wafer might stick to the substrate during the final HF release etch. To solve this problem (without resorting to supercritical drying or HF vapor processes), Cavity-Silicon- on-lnsulator (CS01) wafers were developed with cavities positioned in the handle directly above which the resonators are patterned. The resonator is thus released from the substrate directly following DR1E without the need for the HF etch. Alternatively, the performance of thin film bulk acoustic resonators (FBAR) has been shown to improve if the substrate can be removed from beneath the resonator using a long deep reactive ion etch (DR1E). This etch must extend from the wafer backside all the way through the substrate, terminating at an etch stop layer beneath the resonator.

[0027] Figs 1A to 1G illustrate examples of phases of the method of fabricating a unit of a micro-electromechanical system apparatus with a single cavity 120’. In general, micro-electromechanical system apparatus may comprise one or more cavities 120’ that may be arranged as an array, for example. Figs 1A to 1G show a layered structure 104 from side. As shown in Fig. 1A, a trench 100 of a trench pattern 102 is formed to the layered structure 104.

[0028] A purpose of the fabrication method is to form one or more sacrificial layers 106 and surround them by material layers (108, 110 and 116’). The surrounding layers (108, 110 and 114) are resistive to etchant(s) used to etch the one or more sacrificial layers 106. Removal of the one or more sacrificial layers 106 results in one or more cavities 120’ within the material layers (108, 110 and 116’). In this document, the word resistive may also mean resistant. Note that because layer 108 is etchant resistive, layer 118 does not necessarily need to be etchant resistive. Correspondingly, layer 116’ is etchant resistive, layer 118 does not necessarily need to be etchant resistive and layer 110 is etchant resistive, while layer 114 does not necessarily need to be etchant resistive. Note that layers 108, 110 and 116’ may be made of SiOz, SisN4 or AI2O3, for example.

[0029] In the fabricating process silicon Si is used as a material for the sacrificial layer 106 and the material layers resistive to the etchant(s) of the sacrificial layer 106 are made of silicon dioxide SiOz. Silicon may mean single crystalline silicon, polysilicon or amorphous silicon.

[0030] When silicon is used as a material of the sacrificial layer 106, a wall arrangement 116’ may be formed by depositing silicon dioxide on the walls of the trench 100 or the walls of the trench 100 may be thermally oxidized.

[0031] A refill layer 118 may then be, like the sacrificial layer 106, made of polycrystalline or amorphous silicon in order to allow planarizing. The wall arrangement 116’ comprises walls 116" between which the refill layer 118 is deposited. Because the refill layer 118 is polished, it only remains in the trench 100. The etchant resistive layer 110 is in contact with the sacrificial layer 106. In the case of a silicon on insulator substrate, the wall arrangement 116’ may be of silicon dioxide.

[0032] After these process steps, a chemical-mechanical planarization process (CMP) is carried out.

[0033] The layered structure 104 comprises a sacrificial layer 106 comprising sacrificial material between a first layer arrangement 108’ and a second layer arrangement 110’. The first layer arrangement 108’ and the second layer arrangement 110’ comprise etchant resistive layers 108, 110 and potentially other layers. The sacrificial layer 106 may then be amorphous silicon and / or polysilicon. A substrate 114 is included in the second layer arrangement 110’. The material of the substrate 114 may be freely chosen taking into account the process conditions and the knowledge of a person skilled in the art.

[0034] The trench 100 can be considered a groove. The trench 100 of the trench pattern 102 extends in a direction of a normal N of a surface of the sacrificial layer 106 through the sacrificial layer 106 that is inside the layered structure 104. The trench 100 forms a trench pattern 102 to the sacrificial layer 106 in lateral directions i.e. the pattern can observed from above of the layered structure 104. The trench pattern 102 can be seen in Figs. 4 and 5 (see also the corresponding pattern in Fig. 3 where pattern 102’ follows closely the trench pattern 102). The trench pattern 102 of the trench 100 may laterally confine a desired section of the sacrificial layer 106 and it may be circular or conical, for example. The trench pattern 102 defines a boundary that may enclose a cavity area 120 of a microelectromechanical system apparatus within the trench pattern 102. In other words, the trench pattern 102 defines the boundary of the cavity area 120 laterally or sidewise, while the top and bottom boundaries of the cavity area 120 are defined by layers 108 and 110. A plurality of trench patterns 102 may then define boundaries that may enclose the plurality of cavity areas 120 that may be utilized for fabrication of an array of micro-electromechanical system components. In an embodiment, the trench pattern 102, however, does not fully enclose a section of the sacrificial layer 106. In some cases, it may be enough the trench pattern 102 only partly forms an outline of the cavity area 120. Fig. IB shows how the barrier structure 116 of the trench 100 is formed. The barrier structure 116 comprises a wall arrangement 116’ with one or two walls that are resistive and / or immune to an etching process that is directed material of the sacrificial layer 106 at least part of which is removed by the etching process of the fabricating process. The wall arrangement 116’ may be formed by modifying a surface structure of the sacrificial layer 106 of the trench 100. Alternatively, etch resistive wall arrangement 116’ may be added to the trench 100. The adding may be performed by deposition, for example. The sacrificial layer 106 may comprise a polysilicon layer or, in the case of a silicon on insulator substrate, a single crystalline silicon layer.

[0035] In an embodiment, the thermal processing for the oxidation needed in the barrier structure 116 and the etchant resistive layers 108, 110 may be performed such that polycrystalline silicon is kept at a certain temperature, for example about 900°C without limiting to this, and inside gas which contains oxygen (O2 or H2O, for example) and potentially inert gas such as nitrogen without limiting to this. A person skilled in the art is familiar with the thermal process, perse.

[0036] As shown in Fig. 1C, a refill layer 118 of polysilicon or the like may be deposited on the layered structure 104. In that manner, the trench 100 may be refilled. The filling of the trench 100 may be performed prior to the removal of the sacrificial material of the sacrificial layer 106 within the layered structure 104 through the at least one hole 124.

[0037] As shown in Fig. ID, the refill layer 118 that refills the trench 100 may be planarized. The planarization may be performed by a chemical mechanical polishing (CMP), for example, which the person skilled in the art is familiar with. The purpose of the planarization is to make the surface flat.

[0038] In an embodiment, the planarization may be performed by an etch-back procedure which refers to etching a certain depth in a controlled manner. However, the etch-back procedure may produce a shallow recess at the trench 100 depending upon the over-etch process. The CMP process may be preferred for its characteristic negligible recess but may not always be required. A cross section of the trench 100, examples of which are illustrated in Figs. 11 and 12, may be rectangular or conical in a view from side. The rectangular cross section means the diameter of the trench is at least approximately constant as a function of depth of the trench 100. The conical cross section means the diameter of the trench 100 may vary linearly or non-linearly as function of the depth. In other words, the profile of the trench 100 may be etched as either a vertical trench such that the cross section is rectangular or a tapered trench such that the cross section varies as a function of the depth. The tapered trench may be more easily filled with desired material but does involve some geometric constraints (the trench width, taper, and polysilicon thickness are all inter-related).

[0039] It is a technical advantage that the trench 100 may be about micron in size / width or a sub-micron in size / width. That small size enables reducing dishing during chemical mechanical planarization (CMP), which results in improved planarity.

[0040] Next, an additional layer 122 can be deposited on the layered structure 104 as shown in Fig. IE. The additional layer 122 can be patterned and at least one hole 124, each of which may be called a ventilation hole, is formed through a first layer 108’ that includes the additional layer 122 as shown in Fig. IF. The additional layer 122 may include electrode layers 150, 154, piezoelectric layer 152 and a passivation layer 156 (see Fig. 21, for example). Fig. IF shows only one hole 124 but the number of holes 124 is not limited to one. That means the at least one hole 124 fully penetrates the first layer arrangement 108’ including the additional layer 122 and the first etchant resistive layer 108 up to the sacrificial layer 106. The hole 124 enables removal of material of the sacrificial layer 106. A cross sectional area of a single hole 124 alone or a total cross sectional area of the holes 124 relating to a single cavity area 120 is smaller than the cavity area 120 which the one or more holes 124 are associated with (the cavity area 120 is illustrated in Fig. 1G).

[0041] Additionally or alternatively, an opening 700 through a second layer arrangement 110’ may be formed in a similar manner. The opening 700 is equal to or smaller than the cavity area 120 which the opening 700 is associated with. That is explained in detail in association with Fig. 8. Fig. 1G illustrates the layered structure 104 that is etched through the at least one hole 124. Each hole 124 can be considered a ventilation hole. Sacrificial material of the sacrificial layer 106 is removed from the at least one cavity area 120 through the at least one hole 124 by a process of etching for forming at least one cavity 120’ within the layered structure 104. The cavity 120’ is confined by the barrier structure 116 because the barrier structure 116 is resistive or immune to an etching process. That is, the etching does not affect the barrier structure 116 or the wall arrangement 116’. The barrier structure 116 comprises a wall arrangement 116’ and a refill layer 118 within the trench 100 between walls 116" of the wall arrangement 116’. As material of the sacrificial layer 106 is removed, the cavity area 120 becomes hollow i.e. the layered structure of the microelectromechanical system apparatus comprises the cavity 120’. A layer on the cavity 120’ is a membrane 250 that can be used as a sensing element of a sensor such as a pressure sensor, or a transducer that may receive and / or transmit signals such as ultrasound, for example. In a similar manner, a plurality of cavities 120’ can be formed to the same layered structure 104 or to a different layered structure. The membrane 250 corresponds to the cavity area 120 of the micro-electromechanical system apparatus.

[0042] 1) In the first case, the passivation layer 156 may be etchant resistive, while the first etchant resistive layer 108 functions as the structural layer. The purpose of the structural layer is to move the stress neutral plane away from the piezoelectric layer.

[0043] 2) In the second case, the passivation layer 156 may serve as both the protective and structural layer.

[0044] Figs 2A to 21 also show an example of the layered structure 104 from side in various phases of a fabricating process of a micro-electromechanical system apparatus. The layered structure comprises polysilicon layer 114 or the like between second etchant resistive layer 110 and a third etchant resistive layer 130. In fabrication phase of Fig. 2A a sacrificial layer 106 is deposited on the second etchant resistive layer layer 110 or directly on the substrate 114. The etchant resistive layers 110 and 130 are layers resistive to the etchant that etch the sacrificial layer 106.

[0045] As shown in an example of Fig. 2B, a trench 100 of a trench pattern 102 is formed to the layered structure 104. The trench 100 can be formed by etching, for example. The trench 100 of the trench pattern 102 extends in a direction of a normal N of a surface of the sacrificial layer 106 through the sacrificial layer 106. The trench 100 forms the trench pattern 102 to the sacrificial layer 106 in lateral directions i.e. the pattern can be observed from above of the layered structure 104. The trench pattern 102 is similar to that described in Figs 1A to ID.

[0046] Fig. 2C illustrates an example of a barrier structure 116 of the trench 100. The barrier structure 116 comprises a wall arrangement 116’ with one or two walls. The barrier structure 116 or the one or two walls that are resistive and / or immune to an etching process that is directed material of the sacrificial layer 106 at least part of which is removed by the etching process of the fabrication process. The barrier structure 116 and the wall arrangement 116’ is similar to that described in Figs IB to ID.

[0047] Fig. 2C illustrates an example of the refill in the trench 100. The refill layer 118 may be deposited on the layered structure 104 and it will cover the first etchant resistive layer 108. The refill layer 118 is similar to that described in Figs IC to ID.

[0048] Fig. 2D illustrates an example of deposition of a first electrode layer 150 that is so called bottom electrode. In an embodiment, the first electrode layer 150 may include mainly molybdenum without limiting to this. The first electrode layer 150 is electrically conductive. The first electrode layer 150 may be patterned. Alternatively or additionally, the first electrode layer 150 may include or be made of platinum, aluminum or the like.

[0049] Fig. 2E illustrates an example of the layered structure 104 with piezoelectric layer 152 on the electrode layer 150. The piezoelectric layer 152 may be made of aluminum nitride (AIN), scandium doped AIN, lead zirconium titanate (PZT), or the like. The piezoelectric layer 152 may be patterned. Fig. 2F illustrates an example of deposition of a second electrode layer 154 on the piezoelectric layer 152. The second electrode layer 154 is so called top electrode. The second electrode layer 154 may be patterned and it may cover only a part of the piezoelectric layer 152. The second electrode layer 154 is electrically conductive. The second electrode layer 154 may of the same material as or different from the first electrode layer 150. A person skilled in the art is familiar with electrode materials, perse, in this kind of applications.

[0050] Fig. 2G illustrates an example of a passivation layer 156 on the second electrode layer 154. The passivation layer 156 may be an oxidized layer and it protects and supports the other layers. The passivation layer 156 may be of the same material as the first etchant resistive layer 108. In an embodiment, material of the passivation layer 156 may be silicon nitride, for example. Material of the passivation layer 156 may alternatively be silicon dioxide or the like depending on the materials of other layers.

[0051] Fig. 2H illustrates an example the layered structure 104 with a hole 124 through first layered arrangement 108’ that may include the passivation layer 156, the piezoelectric layer 152 and the first etchant resistive layer 108 up to the sacrificial layer 106. The hole 124 may be made by etching. Note that the inner surface of the hole 124 comprises the first etchant resistive layer 108, the passivation layerl56 and the piezoelectric layer 152 that are resistive to etching. That is, the hole 124 is also well defined and accurate in dimensions.

[0052] The passivation layer 156 or any etchant resistive layer is chosen to be resistive to etching performed during the final releasing step that is performed after steps 1A to 1G or 2A to 21. For example, if silicon is used as a sacrificial layer 106, silicon dioxide may be used as an etchant resistive layer.

[0053] Fig. 21 illustrates an example of etching of the sacrificial layer 106 through the hole 124. The etch agent may include xenon difluride. Because the sacrificial layer in the cavity area 120 is surrounded by etchant resistive layers 108, 110 and wall arrangement 116’ of the barrier structure 116, a well defined cavity 120’ is formed in the cavity area 120. The micro-electromechanical system apparatus may be used in acoustics, optics or in mechanics, for example. More detailed examples of the use of the barrier structure 116 within several micro-electromechanical system (MEMS) platforms in acoustics are piezoelectric micromachined ultrasonic transducer (PMUT), bulk acoustic wave (BAW) filters, microphones, capacitive micromachined ultrasonic transducer (CMUT), pressure sensors, mechanically movable mirrors or other objects etc.

[0054] The sacrificial layer 106 means a layer on which one or more layers, such as the membrane 250, can be deposited. The sacrificial layer 106 itself is on a supporting layer such as the second layer arrangement 110’. After the deposition of the one or more layers such as the first layer arrangement 108’ on the sacrificial layer 106, the sacrificial layer 106 is fully or partly removed. That makes the cavity 120’ between the second layer arrangement 110’ and the first layer arrangement 108’. Then the two layers separated by the cavity 120’ form a suspended or freestanding structure that is the membrane 250. An electrical connection with the suspended structure enables reception and / or transmission of signals that cause vibration to the suspended structure or are caused by the vibration of the suspended structure.

[0055] Because the etching, which is directed to the sacrificial layer 106 for removing the sacrificial layer 106, does not affect the barrier structure 116, the wall arrangement 116’ and the etchant resistive layers 108, 110 remain smooth and well defined. Thus, material roughness and dimensional variation of the cavity 120’ is eliminated or it is minimal. Thus, variation of the volume of the cavity 120’ and in the effective radius of the membrane 250, the variation being insignificant or within required tolerance, do not technically affect the operational frequency or sensitivity of the micro-electromechanical system apparatus.

[0056] In an implementation of an ultrasonic device, for example, the piezoelectric and electrode layers included in the first layer structure 108’, are constructed on the wafer frontside and then the device is released from the substrate that is a part of the second layer structure 110’ by etching away the backside of the wafer using the DR1E. These long etch processes can take over 1 hour per wafer. The effective radius of the membrane 250 and the cavity 120’ is determined by this long release etch process. Hence, the immunity of the barrier structure 116 to the etch process leads to improvement of the dimensions of the membrane 250, the cavity 120’ and the quality of the end product.

[0057] In an embodiment an example of which is illustrated in Fig. 3, a photolithographic layer 200 may be formed on the first layer arrangement 108’. The photolithographic layer 200 has a pattern 102’ similar to the trench pattern 102 and the form of the patterns 102, 102’ follow each other. A subtractive etching process may form the trench 100 through the sacrificial layer 106.

[0058] In an embodiment, the trench 100 may be filled by chemical vapor deposition process. The filled trench 100 may be planarized by chemical mechanical polishing. The planarization, which is illustrated in Fig. ID, means that a material level at the trench 100 is made to be at least approximately at the same level as material level directly adjacent to the trench 100.

[0059] In an embodiment an example of which is illustrated in Fig. 1G, an etching agent of the etching process to remove the sacrificial material may include xenon difluoride etching.

[0060] In an embodiment an example of which is illustrated in Fig. IE, the additional layer 122 included in first layer arrangement 108’ may be formed prior to the removal of the sacrificial material of the sacrificial layer 106.

[0061] Figs 4 and 5 illustrate examples of the trench pattern 120. In an embodiment, the thickness T of the barrier structure 116 may be in a range about 0.3 gm to about 2 gm. As a result, a minimum distance between two directly adjacent cavity areas 120 may also be about 2 gm to about 20 gm because the etching of the trench 100 and the sacrificial layer 106 can be made accurately, which is based on the etchant resistive barrier structure 116. That means the membranes 250 of directly adjacent operational units such as sensors or transducers may also be at a similar distance from each other. A device with a densely distributed units of the micro-electromechanical system apparatuses can thus be made as illustrated in Figs 6 and 7. A lithographically defined radius of the membrane 250 may offer the potential for better control of membrane resonance. The barrier structure 116 is defined on the sacrificial layer 106 (~0.5 gm thick but up to 5 gm or more, for example) on an oxide and then using conventional lithography and etching to form the trench 100 (< 1 gm, for example) through the sacrificial layer. The etched trench 100 may then be lined with insulators which are resistive to etching agent attack (for example, SiOz, Si3N4, AI2O3). Next, conformal filling with polysilicon is carried out to ensure the absence of voids within the filled trench and furthermore allows easy planarization with a CMP process design to stop on the upper mask layer i.e. the first etchant resistive layer 108. After CMP, an additional insulator deposition may be performed. The construction of the electrode and piezoelectric layers in the first layer arrangement 108’ and / or in the second layer arrangement 110’ may then carried out normally.

[0062] After the deposition and patterning of the piezoelectric and electrode layers that are included in the first layer arrangement 108’ to form the transducer or a sensor element, for example, a final lithography and etch step is needed to reveal the buried polysilicon layer. This opening need only be a small hole 124 or pattern of vent-like holes 124 to allow the etching agent gas access to the polysilicon. During the etching agent, the gas will etch and remove the now buried polysilicon from the area surrounded laterally by the barrier structure 116 thus forming the cavity 120’. The membrane 250 above the cavity 120’, which forms the basis of the ultrasonic transducer or a pressure sensor, for example, is fully defined by the surrounding barrier structure 116.

[0063] In an embodiment an example of which is illustrated in Fig. IE, a depth D of the barrier structure 115 may be between about 0.5 gm to about 25 gm. That can be controlled by the process forming the sacrificial layer 106 and the process of forming the trench 100.

[0064] In an embodiment, the depth D of the cavity 120’ may be between about 0.5 gm and about 25 gm.

[0065] In an embodiment, the second layer arrangement 110’ may comprise a substrate layer 114. The substrate material may be chosen considering the process conditions or applications and the knowledge of a person skilled in the art. In an embodiment, the substrate layer 114 may be made of silicon, for example.

[0066] Figs 6 and 7 show membranes 250 over the cavities 120’. The cavities 120’ and the membranes 250 can be defined precisely in the presented method. A full wafer can be released with no visible failures. Only two holes 124 have reference numbering but all the membranes 250 have the holes in Figs 6 and 7.

[0067] In an embodiment an example of which is illustrated in Fig. 8, an opening 700 may be formed through the second layer arrangement 110’ that comprises layers 110, 114 of each of the at least one cavity area 120, for example. The opening 700 may be considered an alternative to the hole 124. It can be considered that the opening 700 is on the backside of the layered structure 104 and the actual hole 124 is on the frontside of the layered structure 104. The circumference of the opening 700 may be deposited by SiOz, SisN4 or AI2O3 such the side walls 702 of the opening 700 are etch resistive. The sacrificial material of the sacrificial layer 106 belonging to the cavity area 120 may then be removed from within the layered structure 104 through the opening 700 for forming the cavity 120’ in a similar manner and in a corresponding fabricating phase with that of the hole 124 illustrated in Figs 1A to 1G. These kinds of structures with the barrier structure 116 enable reliable performance.

[0068] Figs 9 and 10 illustrate apparatus units of the micro-electromechanical system apparatus. Fig. 9 illustrates an example where there are plurality of holes 124 (only a few marked) through the membrane 250 and the first layer arrangement 108’. Fig. 9 also illustrates an example where there is a hole 124 in the middle of the conical unit. Fig. 10 illustrates an example where the holes 124 are oblong and curved. The first layer arrangement 108’ comprises electrically conductive layers for electric operation of the micro-electromechanical system apparatus in a manner that a person skilled in the art is familiar with. Thus, each of the units of the micro-electromechanical system apparatus may be used as a transducer, a sensor or a component causing mechanical movement, for example.

[0069] The layered structure presented in this document has the barrier structure 116 for each cavity 120’, the barrier structure 116 defining the dimensions of the membrane 250 and the cavity 120’ laterally. Note also that during the fabrication the trench pattern 100’ defines the shape of the barrier structure 116 because the wall arrangement 116’ of the trench 100 with the refill layer 118 between the walls form the barrier structure 116. There are a plurality of advantages of this approach over the prior art. Improved performance uniformity within devices, across wafer and from wafer to wafer, resulting in higher yield is one of them. Smaller spacing between the membranes 250 within an array, in turn, enhances the active area. Regarding a sensor such as a pressure sensor, variation between sensors can be minimized and calibration can be simplified. Regarding the PMUT, that leads to better transmit and receive performance and / or smaller array size. The PMUTs can be fabricated with frequencies from below 100 kHz and to above 15 MHz. There is also a possibility to reliably fabricate PMUT with different specifications (membrane dimensions) within a single wafer.

[0070] This document thus demonstrates the barrier structure 116 that confines the cavity 120’. These barrier structures 116 can withstand long over-etch times without leaking. It is possible to fabricate the device structure such that there is only a narrow strip of remaining silicon of the barrier structures 116 between membranes 250 for making a tightly packed membrane matrix.

[0071] This process eliminates topography, improves lithography and etch processes, and additionally eliminates stress-concentrations and related failures.

[0072] The barrier structure 116 can be fabricated with standard processes. The method can be applied to large and small wafer sizes and alternative fabrication sites.

[0073] In conclusion, isolating barriers based on shallow trenches etched through polysilicon or SOI device layers, filled and planarized, confine the XeFz release etch process. The result is a precisely defined cavity 120’ and membrane 250. A high degree of flatness after barrier creation is achieved. The filling layer 118 deposited on the wafer after etching the trench 100 also covers the top surface of the wafer. When the conformal deposition of the void-free trench filler layer 118 (polysilicon, for example) is performed, the material of the barrier structure 116 serves as both the lateral etch (XeFz) stopper and also vertical etch (CMP) stopper beneath the polysilicon. The trenches 100 can be made narrow (< 1 m) and the dishing of the trenches 100 is less than < 50 nm. That enables further lithographic steps to proceed unhindered by any significant topographic issues.

[0074] The confining barrier structures 116 offer the following benefits to MEMS devices in general:

[0075] 1) After the sacrificial material is consumed, the result is a free-standing membrane or structural element 250 over a lithographically defined cavity 120’.

[0076] 2) The process with the barrier structures 116 allows the fabrication of multiple free-standing membrane sizes in a single wafer or even within a single chip.

[0077] 3) The dimension of the membrane 250 is not dependent upon the quality of the DR1E release etch, which may therefore be accomplished by lower- performing recipe or etch tool.

[0078] 4) The process with the barrier structures 116 allows to make very small and very large diameter membranes 250 simultaneously and on the same wafer. Releasing the largest membranes by backside DR1E becomes impractical due to membrane fractures, whereas the membranes 250 confined by the barrier structures 116 are not subjected to the difficult DR1E process after release.

[0079] 5) The barrier structure 116 enables the fabrication of individual membrane array elements with very close (~2 pm) spacing. This is particularly relevant for the fabrication of dense arrays of devices.

[0080] 6) Flexible interconnecting passageways between adjacent elements offers the possibility of engineered backside dimensions of the opening 700 for acoustic tuning.

[0081] 7) With a sufficiently thick sacrificial layer 106 (for example, 10 pm of polysilicon) the cavity 120’ becomes deep enough to circumvent the need for a backside release etch. That means the opening 700 is not needed. This minimum thickness (or depth) is application specific, depending upon the device requirements. For example, film-bulk-micromachined resonators are not degraded by the squeeze-film damping and may thus use a thin release layer, whereas PMUTs require a thicker layer and deeper cavity 120’ to prevent squeeze-film damping without a backside release hole.

[0082] These benefits are applicable to a variety of MEMS devices such as FBARs, transducers, microphones and accelerometers, for example.

[0083] Figure 13 is a flow chart of the method of fabricating a microelectromechanical system apparatus. In step 1200, a trench pattern 100’ to a layered structure 104 is formed, the layered structure 104 comprising a sacrificial layer 106 between a first layer arrangement 108’ and a second layer arrangement 110’, the trench 100 of the trench pattern 100’ extending through a sacrificial layer 106 that is between first layer arrangement 108’ and a second layer arrangement 110’ of the layered structure 104, and the trench pattern 106’ defining a boundary to at least one cavity area 120 of micro-electromechanical system apparatus.

[0084] In step 1202, a barrier structure 116 is formed to the trench 100, the barrier structure 116 comprising a wall arrangement 116’ and a refill layer 118 within the trench 100 between walls 116" of the wall arrangement 116’, the barrier structure 116 being made resistive to an etching process of sacrificial material of the layer 106 and a thickness T of the barrier structure 116 being in a range 0.3 gm to 2 gm.

[0085] In step 1204, relating to each of the cavity areas 120, at least one hole 124 through a first layer arrangement 108’ is formed, which is formed on and in contact with the sacrificial layer 106.

[0086] In step 1206, sacrificial material of the sacrificial layer 106 is removed from the at least one cavity area 120 through the at least one hole 124 by a process of etching for forming at least one cavity 120’ within the layered structure 104, each of the at least one cavity 120’ being laterally confined by the barrier structure 116.

[0087] It will be obvious to a person skilled in the art that, as technology advances, the inventive concept can be implemented in various ways. The invention and its embodiments are not limited to the example embodiments described above but may vary within the scope of the claims.

Claims

What is claimed is:

1. A method of fabricating a micro-electromechanical system apparatus, c h a r a c t e r i z e d by forming (1200) a trench pattern (102) to a layered structure (104), the layered structure (104) comprising a sacrificial layer (106) between a first layer arrangement (108’) and a second layer arrangement (110’), a trench (100) of the trench pattern (102) extending through the sacrificial layer (106), and the trench pattern (102) defining a boundary to at least one cavity area (120) of microelectromechanical system apparatus; forming (1202) a barrier structure (116) to the trench (100), the barrier structure (116) comprising a wall arrangement (116’) and a refill layer (118) within the trench (100) between walls (116") of the wall arrangement (116’), the barrier structure (116) being made resistive to an etching process of sacrificial material of the layer (106)and a thickness (T) of the barrier structure (116) being in a range 0.3 gm to 2 gm; forming (1204), relating to each of the cavity areas (120), at least one hole (124) through the first layer arrangement (108’), which is formed on and in contact with the sacrificial layer (106); and removing (1206) sacrificial material of the sacrificial layer (106) from the at least one cavity area (120) through the at least one hole (124) or the opening (700) by a process of etching for forming at least one cavity (120’) within the layered structure (104), each of the at least one cavity (120’) being laterally confined by the barrier structure (116).

2. The method of claim 1, c h a r a c t e r i z e d by forming a photolithographic layer (200) with a pattern (102’) corresponding to the trench pattern (106’) on the first layer arrangement (108’), and forming the trench pattern (102) and the trench (100) based on the pattern (102’) of the photolithographic layer (200) in a subtractive etching process.

3. The method of claim 1, characterized by filling the trench (100) prior to the removal of the sacrificial material of the sacrificial layer (106) through the at least one hole (124).

4. The method of claim 1 or 3, characterized by filling the trench (100) by chemical vapor deposition process, and planarizing the filled trench (100) by chemical mechanical polishing.

5. The method of claim 1, characterized by forming the barrier structure (116) by a thermal oxidation or a deposition process.

6. The method of claim 1, characterized in that an etching agent of the etching process to remove the sacrificial material includes xenon difluoride etching.

7. The method of claim 1, characterized by forming additional layers (122) prior to the removal of the sacrificial material of the sacrificial layer (106).

8. The method of claim 1, characterized by forming an opening (700) through a second layer arrangement (110’) of the layered structure (104), the at least one hole (124) being smaller than the cavity area (120) which the at least one hole (124) is associated with, and the opening (700) being equal to or smaller than the cavity area (120) which the opening (700) is associated with.

9. The method of claim 1, characterized by making a depth (D of the cavity (120’) equal to or less than 25pm.

10. The method of claim 1, characterized by forming an opening (700) through the second layer arrangement (110’) of each of the at least one cavity area (120), and removing the sacrificial material of the sacrificial layer (106) belonging to each of the at least one cavity area (120) within the layered structure (104).

11. The method of claim 10, c h a r a c t e r i z e d in that the second layer arrangement (110’) comprises a substrate layer (114).

12. The method of claim 1, c h a r a c t e r i z e d in that the sacrificial layer (106) and the refill layer (118) comprise polysilicon or amorphous silicon layers or, in the case of a silicon on insulator substrate, a single crystalline silicon layer, and in either of these cases the wall arrangement (116’) is of silicon dioxide.

13. A micro-electromechanical system apparatus, c h a r a c t e r i z e d in that a layered structure (104) of the micro-electromechanical system apparatus comprises a sacrificial layer (106) between a first layer arrangement (108’) and a second layer arrangement (110’) of the layered structure (104); the sacrificial layer (106) comprises a trench (100) with a shape of a trench pattern (100’), the trench (100) extending through the sacrificial layer (106), and the trench pattern (106’) defining a boundary to at least one cavity area (120) of micro-electromechanical system apparatus; a barrier structure (116) of the trench (100) comprises a wall arrangement (116’) and a refill layer (118) within the trench (100) between walls (116") of the wall arrangement (116’), the barrier structure (116) being resistive to an etching process of sacrificial material of the layer (106), and a thickness (T) of the barrier structure (116) being in a range 0.3 gm to 2 gm; the first layer element (108’) comprises at least one hole (124) through the first layer arrangement (108’) of the layered structure (104) and / or the second layer element (110’) comprises an opening (700) through the second layer arrangement (110’), the first layer arrangement (108’) and the second layer arrangement (110’) being in contact with the sacrificial layer (106), the at least one hole (124) being smaller than the cavity area (120) which the at least one hole (124) is associated with, and the opening (700) being equal to or smaller than the cavity area (120) which the opening (700) is associated with; and each of the cavity area (120) including a cavity (120’) between the first layer arrangement (108’) and the second layer arrangement (110’), the cavity(120’) being laterally limited by a barrier structure (116) of a wall arrangement (116’) of the trench (100).

14. The apparatus of claim 13, characterized in that the microelectromechanical system apparatus is fabricated by the method steps of claim 1.

15. The apparatus of claim 13 or claim 14, characterized in that the micro-electromechanical system apparatus is additionally fabricated by any of the method steps of claim 2 to 12.

Images