Method for manufacturing light emitting element and light emitting element

Abstract

Provided are: a method for manufacturing a light emitting element in which the light emissions of a plurality of light emitting regions can be controlled individually; and a light emitting element.　This method for manufacturing a light emitting element comprises: a step for preparing a semiconductor structure that has a substrate, an n-side semiconductor layer, an active layer, and a p-side semiconductor layer, as well as a plurality of conductive layers that are disposed on a fourth surface positioned to the side of the p-side semiconductor layer which is reverse of the active layer, a first insulating layer that covers the fourth surface and the plurality of conductive layers and that has a first n-side opening positioned above a third surface of the n-side semiconductor layer and first p-side openings positioned above each of the plurality of conductive layers, and a wafer that has a first n-side electrode which is disposed in the first n-side opening and is in contact with the third surface and p-side electrodes which are disposed in each of the plurality of first p-side openings and are in contact with one conductive layer among the plurality of conductive layers; a step for removing the substrate and exposing the first surface of the n-side semiconductor layer; and, after the step for exposing the first surface, a step for separating the semiconductor structure into a plurality of element parts.

Description

Light-emitting device manufacturing method and light-emitting device

[0001] The present disclosure relates to a method for manufacturing a light-emitting device and a light-emitting device.

[0002] For example, as disclosed in Patent Document 1, a method for manufacturing a light-emitting element is known that includes a step of forming a semiconductor layer on a first substrate, a step of bonding a second substrate to the semiconductor layer, and then a step of removing the first substrate used to form the semiconductor layer.

[0003] JP 2015-32809 A

[0004] An object of the present disclosure is to provide a method for manufacturing a light-emitting element capable of individually controlling the light emission of a plurality of light-emitting regions, and a light-emitting element.

[0005] According to one aspect of the present disclosure, a method for manufacturing a light-emitting element includes: a semiconductor structure including a substrate; an n-side semiconductor layer disposed on the substrate and having a first surface located on the substrate side, a second surface located opposite the first surface, and a third surface located opposite the first surface; an active layer disposed on the second surface; and a p-side semiconductor layer disposed on the active layer, wherein the third surface is exposed from the active layer and the p-side semiconductor layer; a plurality of conductive layers disposed on a fourth surface of the p-side semiconductor layer located opposite the active layer; and a conductive layer covering the fourth surface and the plurality of conductive layers and located above the third surface. the first insulating layer having a first n-side opening and a first p-side opening located above each of the plurality of conductive layers, a first n-side electrode disposed in the first n-side opening and in contact with the third surface, and a p-side electrode disposed in each of the plurality of first p-side openings and in contact with one of the plurality of conductive layers; removing the substrate in the wafer to expose the first surface of the n-side semiconductor layer; and separating the semiconductor structure into a plurality of element portions by removing the n-side semiconductor layer, the active layer, and the p-side semiconductor layer after the step of exposing the first surface.

[0006] According to one aspect of the present disclosure, a light-emitting element is a semiconductor structure having an n-side semiconductor layer, an active layer disposed on the n-side semiconductor layer, and a p-side semiconductor layer disposed on the active layer, wherein the n-side semiconductor layer has a first surface, a second surface opposite to the first surface and located on the active layer side, a third surface located opposite to the first surface and exposed from the active layer and the p-side semiconductor layer, and a through-hole defined by a side surface of the n-side semiconductor layer connecting the third surface and the first surface and penetrating the n-side semiconductor layer; a first insulating layer covering the third surface, the fourth surface, and the plurality of conductive layers, and having a first n-side opening overlapping the through hole in a plan view and a first p-side opening located above each of the plurality of conductive layers; a first n-side electrode disposed in the first n-side opening and in contact with the third surface; a second n-side electrode disposed in the through hole and in contact with the first n-side electrode; and a p-side electrode disposed in each of the plurality of first p-side openings and in contact with one of the plurality of conductive layers.

[0007] According to the present disclosure, it is possible to provide a method for manufacturing a light-emitting element capable of individually controlling the light emission of a plurality of light-emitting regions, and a light-emitting element.

[0008] FIG. 1 is a schematic plan view of the light-emitting element according to the first embodiment; FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1; FIG. 3 is a schematic cross-sectional view illustrating a step of a manufacturing method for the light-emitting element according to the first embodiment; FIG. 4 is a schematic cross-sectional view illustrating a step of a manufacturing method for the light-emitting element according to the first embodiment; FIG. 5 is a schematic cross-sectional view taken along line VI-VI in FIG. 5; FIG. 6 is a schematic cross-sectional view illustrating a step of a manufacturing method for the light-emitting element according to the first embodiment; FIG. 7 is a schematic cross-sectional view taken along line VIII-VIII in FIG. 7; FIG. 8 is a schematic cross-sectional view taken along line X-X in FIG. 9; FIG. 10 is a schematic cross-sectional view illustrating a step of a manufacturing method for the light-emitting element according to the first embodiment; FIG. 11 is a schematic cross-sectional view taken along line XII-XII in FIG. 11; FIG. 12 is a schematic cross-sectional view taken along line XIV-XIV in FIG. 13; FIG. 14 is a schematic cross-sectional view illustrating a step of a manufacturing method for the light-emitting element according to the first embodiment; FIG. 15 is a schematic cross-sectional view taken along line XVII-XVII in FIG. FIG. 28 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic plan view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic cross-sectional view taken along line XXI-XXI of FIG. 20. FIG. 29 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment. FIG. 29 is a schematic cross-sectional view illustrating one step of the manufacturing method for the light-emitting element according to the first embodiment.FIG. 1 is a schematic plan view of a light-emitting element according to a second embodiment; FIG. 2 is a schematic plan view for explaining one step of a manufacturing method for a light-emitting element according to the second embodiment; FIG. 3 is a schematic plan view for explaining one step of a manufacturing method for a light-emitting element according to the second embodiment; FIG. 4 is a schematic plan view for explaining one step of a manufacturing method for a light-emitting element according to the second embodiment; FIG. 5 is a schematic cross-sectional view of a light-emitting element according to a third embodiment; FIG. 6 is a schematic cross-sectional view for explaining one step of a manufacturing method for a light-emitting element according to the third embodiment; FIG. 7 is a schematic cross-sectional view for explaining one step of a manufacturing method for a light-emitting element according to the third embodiment.

[0009] Hereinafter, embodiments will be described with reference to the drawings. The dimensions, materials, shapes, relative positions, and the like of components described in the embodiments are not intended to be limiting unless otherwise specified, and are merely illustrative examples. The sizes and positional relationships of components shown in each drawing may be exaggerated for clarity. In the following description, the same names and symbols indicate the same or similar components, and detailed descriptions will be omitted as appropriate. Cross-sectional views may also be shown as end views showing only the cut surface.

[0010] In the following description, terms indicating specific directions or positions (e.g., "above," "below," and other terms including these terms) may be used. However, these terms are used merely to facilitate understanding of relative directions or positions in the referenced drawings. As long as the relative direction or position relationship indicated by terms such as "above" and "below" in the referenced drawings is the same, the arrangement in drawings other than those disclosed herein, actual products, etc., does not need to be the same as in the referenced drawings. In this specification, the positional relationship expressed as "above (or below)" includes, for example, when two components are assumed to exist, a case in which the two components are in contact with each other, and a case in which the two components are not in contact with each other and one component is located above (or below) the other component. Furthermore, unless otherwise specified, a component covering an object to be covered includes a case in which the component is in contact with the object to be covered and directly covers the object to be covered, and a case in which the component is not in contact with the object to be covered and indirectly covers the object to be covered.

[0011] In the drawings shown below, directions may be indicated by the X-axis, Y-axis, and Z-axis. The X-axis, Y-axis, and Z-axis are perpendicular to each other. For example, in this specification, the direction along the X-axis is the first direction X, the direction along the Y-axis is the second direction Y, and the direction along the Z-axis is the third direction Z. Also, in this specification, the direction of the arrow on the Z-axis is the main light extraction direction.

[0012] [Light-emitting element according to the first embodiment] A light-emitting element 1 according to the first embodiment will be described with reference to Figures 1 and 2. The light-emitting element 1 according to the first embodiment includes a semiconductor structure 10, a conductive layer 20 which is a plurality of first conductive layers, a first insulating layer 31, a first n-side electrode 41, a second n-side electrode 42, and a p-side electrode 43. Each component will be described below. Note that in cross-sectional views such as Figure 2, the semiconductor structure 10 is not hatched to make it easier to see the boundaries between layers in the semiconductor structure 10.

[0013] <Semiconductor Structure> The semiconductor structure 10 is made of a nitride semiconductor. In this specification, the term "nitride semiconductor" refers to, for example, In ｘ Al ｙ Ga １－ｘ－ｙ The term "nitride semiconductor" includes semiconductors of all compositions in which the composition ratios x and y in the chemical formula N (0≦x≦1, 0≦y≦1, x+y≦1) are varied within their respective ranges. Furthermore, in the above chemical formula, those that further contain a Group V element other than N (nitrogen) and those that further contain various elements added to control various physical properties such as conductivity type are also included in the "nitride semiconductor." The shape of the semiconductor structure 10 in a planar view is, for example, substantially rectangular. When the shape of the semiconductor structure 10 in a planar view is substantially rectangular, the length of one side of the semiconductor structure 10 is, for example, 10 μm or more and 600 μm or less.

[0014] As shown in FIG. 2, the semiconductor structure 10 has an n-side semiconductor layer 11 , an active layer 12 disposed on the n-side semiconductor layer 11 , and a p-side semiconductor layer 13 disposed on the active layer 12 .

[0015] The active layer 12 is located between the n-side semiconductor layer 11 and the p-side semiconductor layer 13 in the third direction Z. The active layer 12 is a light-emitting layer that emits light and has, for example, an MQW (Multiple Quantum Well) structure including multiple barrier layers and multiple well layers. The active layer 12 emits light with a peak wavelength of, for example, 210 nm or more and 580 nm or less.

[0016] The p-side semiconductor layer 13 includes a semiconductor layer containing a p-type impurity, such as Mg. The p-side semiconductor layer 13 has a fourth surface 13A located on the opposite side of the active layer 12 in the third direction Z.

[0017] The n-side semiconductor layer 11 includes a semiconductor layer containing an n-type impurity. The n-type impurity is, for example, Si. The n-side semiconductor layer 11 has a first surface 11A, a second surface 11B, a third surface 11C, and a through-hole H. Light emitted by the active layer 12 is extracted to the outside of the semiconductor structure 10 mainly through the first surface 11A. The second surface 11B is located on the active layer 12 side, opposite the first surface 11A in the third direction Z. The active layer 12 and the p-side semiconductor layer 13 are disposed on the second surface 11B. The third surface 11C is located on the opposite side of the first surface 11A in the third direction Z, and is exposed from the active layer 12 and the p-side semiconductor layer 13.

[0018] 1, the third surface 11C is located in the center of the semiconductor structure 10 in a plan view. In the example shown in FIG. 1, the shape of the third surface 11C in a plan view is annular. The third surface 11C is surrounded by the fourth surface 13A of the p-side semiconductor layer 13 in a plan view. The area of ​​the fourth surface 13A is larger than the area of ​​the third surface 11C. In this specification, the term "plan view" means that the light-emitting element is observed from the first surface 11A side or the fourth surface 13A side.

[0019] 2, the n-side semiconductor layer 11 has an inner side surface 11D connecting the third surface 11C and the first surface 11A. A through hole H is defined by the inner side surface 11D of the n-side semiconductor layer 11. The through hole H penetrates the n-side semiconductor layer 11 in the third direction Z. As shown in FIG. 1, an annular third surface 11C surrounds the through hole H in a planar view. The shape of the through hole H in a planar view can be, for example, a circle, an ellipse, a rectangle, or a polygon with pentagons or more sides.

[0020] 1, the semiconductor structure 10 has two outer edges 10A extending in a first direction X and two outer edges 10A extending in a second direction Y in a plan view, and the shape of the semiconductor structure 10 in a plan view can be, for example, a quadrilateral shape such as a square or a rectangle. The shape of the semiconductor structure 10 in a plan view may also be a substantially square or substantially rectangular shape with at least one corner chamfered.

[0021] <Conductive Layer> In the example shown in FIG. 1 , a plurality of conductive layers 20 are disposed on the fourth surface 13A of the p-side semiconductor layer 13. The conductive layers 20 are in contact with the fourth surface 13A and electrically connected to the p-side semiconductor layer 13. As shown in FIG. 1 , for example, four conductive layers 20 are disposed on the fourth surface 13A, spaced apart from each other in the first direction X and the second direction Y. The conductive layers 20 have the function of diffusing current supplied through a p-side electrode 43 (described later) in the plane direction of the p-side semiconductor layer 13. In plan view, the light emission intensity of the active layer 12 in the portion overlapping with the conductive layer 20 tends to be higher than that of the active layer 12 not overlapping with the conductive layer 20. Examples of materials for the conductive layer 20 include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO, and In. ２ O ３ For example, a metal having a reflectance of 70% or more for the peak wavelength of light emitted by the active layer 12 may be used as the material of the conductive layer 20. Examples of metals having a reflectance of 70% or more for the peak wavelength of light emitted by the active layer 12 include Ag and Al. The shape of the conductive layer 20 in a plan view is, for example, substantially rectangular. When the shape of the conductive layer 20 in a plan view is substantially rectangular, the length of one side of the conductive layer 20 is, for example, 5 μm or more and 250 μm or less.

[0022] <First insulating layer> The first insulating layer 31 covers the third face 11C of the n-side semiconductor layer 11, the fourth face 13A of the p-side semiconductor layer 13, and the plurality of conductive layers 20. The first insulating layer 31 also covers the side face of the p-side semiconductor layer 13 connecting the third face 11C and the fourth face 13A, the side face of the active layer 12, and part of the side face of the n-side semiconductor layer 11. Examples of materials for the first insulating layer 31 include silicon oxide (SiO ２ ) can be used.

[0023] The first insulating layer 31 has a first n-side opening 31n and a plurality of first p-side openings 31p. As shown in FIG. 1 , the first n-side opening 31n is positioned to overlap the through hole H and the third surface 11C in a planar view. The first n-side opening 31n is positioned inside the outer edge of the annular third surface 11C in a planar view. A portion of the third surface 11C is exposed from the first insulating layer 31 through the first n-side opening 31n. The first p-side openings 31p are positioned above the plurality of conductive layers 20 (below in FIG. 2 ). In a planar view, the first p-side openings 31p are positioned to overlap the conductive layers 20. A portion of the conductive layers 20 is exposed from the first insulating layer 31 through the first p-side openings 31p.

[0024] <First n-side electrode> The first n-side electrode 41 is disposed in the first n-side opening 31n and contacts a portion of the third surface 11C. On the third surface 11C, the first n-side electrode 41 is electrically connected to the n-side semiconductor layer 11. The first n-side electrode 41 is also disposed in a region immediately below the through-hole H inside the annular third surface 11C. The first n-side electrode 41 is also disposed on the first insulating layer 31 around the third surface 11C. The first n-side electrode 41 can be, for example, a single metal layer containing Ti, Rh, Au, Pt, Al, Ag, or Ru, or a laminated structure including at least two of these metal layers.

[0025] <Second n-side electrode> The second n-side electrode 42 is disposed in the through hole H. The second n-side electrode 42 contacts the first n-side electrode 41 located in the region directly below the through hole H and is electrically connected to the first n-side electrode 41. The second n-side electrode 42 also contacts the inner surface 11D of the n-side semiconductor layer 11 in the through hole H and is electrically connected to the n-side semiconductor layer 11. The second n-side electrode 42 is not disposed on the first surface 11A. The second n-side electrode 42 is preferably made of a metal having a reflectance of 70% or more for the peak wavelength of light emitted by the active layer 12. For example, the second n-side electrode 42 can be made of Al or Ag.

[0026] The first n-side electrode 41 contacts the third surface 11C of the n-side semiconductor layer 11, and the second n-side electrode 42 contacts the inner surface 11D of the n-side semiconductor layer 11, thereby reducing the resistance of the electrical connection between the n-side semiconductor layer 11 and the n-side electrodes (the first n-side electrode 41 and the second n-side electrode 42). This reduces the forward voltage Vf of the light-emitting element 1.

[0027] <P-Side Electrode> The p-side electrode 43 is disposed in each of the multiple first p-side openings 31p and is in contact with one of the multiple conductive layers 20. At least one p-side electrode 43 is disposed in contact with one conductive layer 20. Each conductive layer 20 is electrically connected to each p-side electrode 43 disposed on each conductive layer 20. The p-side electrode 43 is also disposed on the first insulating layer 31 around the first p-side opening 31p. The p-side electrode 43 can be, for example, a single metal layer containing a metal listed as a material for the first n-side electrode 41, or a laminated structure including at least two of these metal layers.

[0028] According to this embodiment, by disposing multiple conductive layers 20 in the p-side semiconductor layer 13 and individually controlling the current supply to each p-side electrode 43 disposed on each conductive layer 20, it is possible to individually control the light emission of multiple light-emitting regions 200 corresponding to the regions where the multiple conductive layers 20 are disposed. The first n-side electrode 41 and the second n-side electrode 42, which are n-side electrodes, function as a common electrode when individually controlling the light emission of the multiple light-emitting regions 200. For a given area of ​​the light-emitting element 1 in a planar view, using a single n-side electrode common to the multiple light-emitting regions 200 can reduce the area of ​​the third surface 11C for electrical connection to the n-side electrode in a planar view compared to a light-emitting element having multiple n-side electrodes electrically connected to each of the multiple light-emitting regions 200. As a result, the area of ​​the active layer 12 can be relatively increased, thereby improving the luminance of the light-emitting element 1.

[0029] For example, assume that light emission control is performed to cause one light-emitting region 200A of two adjacent light-emitting regions 200 in FIG. 2 to emit light and the other light-emitting region 200B not to emit light. In this case, the second n-side electrode 42 disposed on the inner surface 11D of the n-side semiconductor layer 11 in the through-hole H reflects the light emitted from one light-emitting region 200A toward the light-emitting region 200A, thereby reducing propagation to the other light-emitting region 200B. This increases the difference in luminance between the light-emitting region 200A that is the target for light emission and the light-emitting region 200B that is not the target for light emission, thereby enhancing the contrast between light and dark. Note that the number of light-emitting regions 200 divided according to the number of conductive layers 20 is not limited to four, and may be two or more.

[0030] As shown in FIG. 2 , the width of the semiconductor structure 10 in each light-emitting region 200 in a cross-sectional view decreases from the fourth surface 13A toward the first surface 11A. The active layer 12 is located closer to the fourth surface 13A than to the first surface 11A. Therefore, compared to when the width of the semiconductor structure 10 in each light-emitting region 200 increases from the fourth surface 13A toward the first surface 11A in a cross-sectional view, the area of ​​the active layer 12 can be increased, thereby improving the brightness of the light-emitting element 1. As shown in FIG. 2 , the angle between the outer surface 10E and the fourth surface 13A is an acute angle. The angle between the outer surface 10E and the fourth surface 13A is, for example, 70° or greater and 85° or less.

[0031] <Coating Layer> The light-emitting element 1 may further include a coating layer 50. The coating layer 50 covers the first insulating layer 31, the first n-side electrode 41, and the plurality of p-side electrodes 43. The coating layer 50 can reflect light traveling from the active layer 12 toward the fourth surface 13A, and light reflected within the semiconductor structure 10 toward the fourth surface 13A, toward the first surface 11A, which is the main light extraction surface, thereby improving the brightness of the light-emitting element 1.

[0032] The covering layer 50 may include, for example, a dielectric multilayer film 51 disposed on the first insulating layer 31 so as to cover the first n-side electrode 41 and the plurality of p-side electrodes 43. The reflectance of the dielectric multilayer film 51 for the peak wavelength of light emitted by the active layer 12 is, for example, 70% or more. The covering layer 50 may further include a metal film 52 disposed on a surface of the dielectric multilayer film 51 opposite to the first insulating layer 31. The metal film 52 may be, for example, a single metal layer containing Al or Ti, or a laminate structure including these metal layers. The reflectance of the metal film 52 for the peak wavelength of light emitted by the active layer 12 is, for example, 70% or more.

[0033] The light-emitting element 1 may further include an n-side pad electrode 61, a p-side pad electrode 62, and a second insulating layer 32. In this case, the covering layer 50 has a second n-side opening 50n and a second p-side opening 50p. At the second n-side opening 50n, a portion of the first n-side electrode 41 is exposed from the covering layer 50. At the second p-side opening 50p, a portion of the p-side electrode 43 is exposed from the covering layer 50. The second insulating layer 32 has a third n-side opening 32n overlapping the second n-side opening 50n in a plan view and a third p-side opening 32p overlapping the second p-side opening 50p in a plan view. At the third n-side opening 32n, a portion of the first n-side electrode 41 is exposed from the covering layer 50 and the second insulating layer 32. At the third p-side opening 32p, a portion of the p-side electrode 43 is exposed from the covering layer 50 and the second insulating layer 32.

[0034] <n-Side Pad Electrode> The n-side pad electrode 61 is disposed on the covering layer 50 via the second insulating layer 32, and is connected to the first n-side electrode 41 at the second n-side opening 50n and the third n-side opening 32n. The first n-side electrode 41 is electrically connected to an external circuit via the n-side pad electrode 61. The n-side pad electrode 61 can be, for example, a single metal layer containing Ti, Rh, Au, Pt, Ru, or Al, or a laminated structure containing at least two of these metal layers.

[0035] For example, the covering layer 50 has a plurality of second n-side openings 50 n, and the second insulating layer 32 has a plurality of third n-side openings 32 n. The n-side pad electrode 61 is disposed in the plurality of second n-side openings 50 n and the plurality of third n-side openings 32 n, and is connected to the first n-side electrode 41 at the plurality of second n-side openings 50 n and the plurality of third n-side openings 32 n.

[0036] <P-Side Pad Electrode> The p-side pad electrode 62 is disposed on the covering layer 50 via the second insulating layer 32, and is connected to the p-side electrode 43 at the second p-side opening 50p and the third p-side opening 32p. The p-side electrode 43 is electrically connected to an external circuit via the p-side pad electrode 62. The p-side pad electrode 62 can be, for example, a single metal layer containing a metal listed as a material for the n-side pad electrode 61, or a laminated structure containing at least two of these metal layers.

[0037] The covering layer 50 has a plurality of second p-side openings 50p corresponding to the plurality of p-side electrodes 43. The second insulating layer 32 has a plurality of third p-side openings 32p corresponding to the plurality of p-side electrodes 43. A p-side pad electrode 62 is disposed in each of the plurality of second n-side openings 50n and the plurality of third n-side openings 32n, and each p-side pad electrode 62 is connected to a corresponding p-side electrode 43.

[0038] <Second insulating layer> The second insulating layer 32 is disposed in the third direction Z between the covering layer 50 and the n-side pad electrode 61 and between the covering layer 50 and the p-side pad electrode 62. The second insulating layer 32 is also disposed in the second n-side opening 50n between the covering layer 50 and the n-side pad electrode 61, and in the second p-side opening 50p between the covering layer 50 and the p-side pad electrode 62. Examples of materials for the second insulating layer 32 include SiO ２ The second insulating layer 32 insulates the metal film 52 of the covering layer 50 from the n-side pad electrode 61, and insulates the metal film 52 from the p-side pad electrode 62. Note that if the covering layer 50 does not include the metal film 52 and is made of the dielectric multilayer film 51, the second insulating layer 32 may be omitted.

[0039] <Protective Film> The light-emitting element 1 may further include a protective film 70. The protective film 70 covers the first surface 11A and the outer side surface 10E of the semiconductor structure 10. The protective film 70 is also disposed in the through-hole H, and covers the inner side surface 11D of the semiconductor structure 10 and the second n-side electrode 42. The protective film 70 may be, for example, a SiO ２ An insulating film containing silicon nitride (SiN) or silicon oxynitride (SiON) can be used.

[0040] The first surface 11A, which is the main light extraction surface, preferably has a plurality of convex portions 11F, which can improve the light extraction efficiency from the first surface 11A. When the first surface 11A is a rough surface having a plurality of convex portions 11F, the arithmetic mean roughness Ra of the first surface 11A is, for example, 0.05 μm or more and 1 μm or less.

[0041] [Method for Manufacturing Light-Emitting Element According to First Embodiment] Next, a method for manufacturing the light-emitting element 1 according to the first embodiment will be described with reference to FIGS.

[0042] <Step of Preparing a Wafer> The method for manufacturing the light-emitting element 1 according to the first embodiment includes the step of preparing a wafer W shown in FIGS.

[0043] 16 and 17 , the wafer W has the above-mentioned semiconductor structure 10, a plurality of conductive layers 20, a first insulating layer 31, a first n-side electrode 41, and a plurality of p-side electrodes 43. The wafer W also has a substrate 101 that supports the semiconductor structure 10. The semiconductor structure 10 is disposed on the substrate 101. The first surface 11A of the n-side semiconductor layer 11 is located on the substrate 101 side in the third direction Z.

[0044] The process of preparing the wafer W may include the steps described below with reference to FIGS.

[0045] As shown in FIG. 3, the semiconductor structure 10 is formed on a substrate 101. For example, the semiconductor structure 10 can be formed by sequentially forming an n-side semiconductor layer 11, an active layer 12, and a p-side semiconductor layer 13 on the substrate 101 by MOCVD (Metal Organic Chemical Vapor Deposition). The substrate 101 may be, for example, sapphire having a C-plane, an R-plane, or an A-plane as its principal surface, or spinel (MgAl ２ O ４ Alternatively, the substrate 101 may be a conductive substrate such as SiC (including 6H, 4H, and 3C), ZnS, ZnO, GaAs, or Si.

[0046] 4 to 6 , a portion of the p-side semiconductor layer 13, a portion of the active layer 12, and a portion of the n-side semiconductor layer 11 are removed from the fourth surface 13A side of the p-side semiconductor layer 13 to expose a portion of the n-side semiconductor layer 11, thereby forming the third surface 11C. The p-side semiconductor layer 13, the active layer 12, and the n-side semiconductor layer 11 can be removed by, for example, reactive ion etching (RIE). Before the above-described through holes H are formed, the shape of the third surface 11C in a plan view can be, for example, a circle, an ellipse, a rectangle, or a polygon with 5 or more sides.

[0047] As shown in FIG. 4, a plurality of third surfaces 11C are formed, spaced apart from one another in the first direction X and the second direction Y. The semiconductor structure 10 is separated into a plurality of element portions by a process described below. FIG. 4 shows, for example, regions that will become four element portions. For example, one third surface 11C is formed in the center of a region that will become one element portion. FIG. 5 shows an enlarged view of a region that will become one element portion. FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 5. In the subsequent plan views and cross-sectional views, except for FIG. 28, a region that will become one element portion is shown.

[0048] 7 and 8 , a plurality of conductive layers 20 are disposed on the fourth surface 13A of the p-side semiconductor layer 13. As shown in Fig. 7 , in a region that becomes one element portion, for example, four conductive layers 20 are disposed spaced apart from each other in the first direction X and the second direction Y. The conductive layers 20 can be formed by, for example, a sputtering method or a vapor deposition method. In the example shown in Fig. 7 , a plurality of conductive layers 20 are disposed around the third surface 11C, spaced apart from the third surface 11C.

[0049] 9 and 10 , a first insulating layer 31 is formed to cover the fourth surface 13A of the p-side semiconductor layer 13 and the plurality of conductive layers 20. The first insulating layer 31 has a first n-side opening 31n located above the third surface 11C and first p-side openings 31p located above each of the plurality of conductive layers 20. A portion of the third surface 11C of the n-side semiconductor layer 11 is exposed in the first n-side opening 31n. A portion of the conductive layer 20 is exposed in the first p-side opening 31p. The first insulating layer 31 also covers the side surface of the p-side semiconductor layer 13 connecting the fourth surface 13A and the third surface 11C, the side surface of the active layer 12, and a portion of the side surface of the n-side semiconductor layer 11. The first insulating layer 31 can be formed by, for example, a sputtering method, a vapor deposition method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like.

[0050] 11 and 12 , a first n-side electrode 41 and a p-side electrode 43 are formed. The first n-side electrode 41 is disposed in the first n-side opening 31n and contacts the third surface 11C. The p-side electrode 43 is disposed in each of the multiple first p-side openings 31p and contacts one of the multiple conductive layers 20. The first n-side electrode 41 is also formed on the first insulating layer 31 located in the periphery of the first n-side opening 31n. The p-side electrode 43 is also formed on the first insulating layer 31 located in the periphery of the first p-side opening 31p. The first n-side electrode 41 and the p-side electrode 43 can be formed by a method such as sputtering, evaporation, or CVD (Chemical Vapor Deposition).

[0051] The wafer W may further include the above-described covering layer 50, second insulating layer 32, n-side pad electrode 61, and p-side pad electrode 62. The covering layer 50, second insulating layer 32, n-side pad electrode 61, and p-side pad electrode 62 can be formed by the steps shown in FIGS.

[0052] As shown in FIGS. 13 and 14 , a covering layer 50 is formed to cover the first insulating layer 31, the first n-side electrode 41, and the p-side electrode 43. The covering layer 50 has a second n-side opening 50n located above the first n-side electrode 41 located on the first insulating layer 31, and a second p-side opening 50p located above the p-side electrode 43. A portion of the first n-side electrode 41 is exposed in the second n-side opening 50n. A portion of the p-side electrode 43 is exposed in the second p-side opening 50p. As described above, the covering layer 50 can include a dielectric multilayer film 51 and a metal film 52. The dielectric multilayer film 51 can be formed by a method such as sputtering, vapor deposition, CVD, or ALD. The metal film 52 can be formed by a method such as sputtering, vapor deposition, or CVD.

[0053] 15 , a second insulating layer 32 is formed to cover the covering layer 50. The second insulating layer 32 has a third n-side opening 32n located inside the second n-side opening 50n in a plan view and exposing a portion of the first n-side electrode 41, and a third p-side opening 32p located inside the second p-side opening 50p in a plan view and exposing a portion of the p-side electrode 43. The second insulating layer 32 also covers the side surfaces of the covering layer 50 that define the second n-side opening 50n and the side surfaces of the covering layer 50 that define the second p-side opening 50p. The second insulating layer 32 can be formed by a method such as sputtering, vapor deposition, CVD, or ALD.

[0054] 16 and 17 , an n-side pad electrode 61 and a p-side pad electrode 62 are formed. The n-side pad electrode 61 is formed in the third n-side opening 32n and on the second insulating layer 32. The n-side pad electrode 61 contacts the first n-side electrode 41 in the third n-side opening 32n and is electrically connected to the first n-side electrode 41. The p-side pad electrode 62 is formed in the third p-side opening 32p and on the second insulating layer 32. The p-side pad electrode 62 contacts the p-side electrode 43 in the third p-side opening 32p and is electrically connected to the p-side electrode 43. The n-side pad electrode 61 and the p-side pad electrode 62 can be formed by a method such as sputtering or vapor deposition, for example.

[0055] According to this embodiment, the covering layer 50 has a plurality of second n-side openings 50n, and the second insulating layer 32 has a plurality of third n-side openings 32n. The n-side pad electrode 61 is disposed in the plurality of second n-side openings 50n and the plurality of third n-side openings 32n and is connected to the first n-side electrode 41 through the plurality of second n-side openings 50n and the plurality of third n-side openings 32n. Hereinafter, the second n-side openings 50n and the third n-side openings 32n may be collectively referred to simply as the n-side opening. According to this embodiment, as shown in FIGS. 11 , 16 , and 17 , the n-side openings are disposed in positions that do not overlap with the first n-side openings 31n of the first insulating layer 31 in a plan view. For example, the n-side openings are disposed above the first n-side electrode 41, which is disposed in a region where the p-side semiconductor layer 13, the conductive layer 20, and the first insulating layer 31 are stacked. This reduces the step that occurs on the n-side pad electrode 61, thereby improving the bonding between the n-side pad electrode 61 and the wiring substrate or the like.

[0056] As a reference example, it is conceivable that the n-side pad electrode 61 is connected to the first n-side electrode 41 at one n-side opening that is arranged at a position overlapping the first n-side opening 31n of the first insulating layer 31 and at a position overlapping the conductive layer 20 in a plan view. In this case, a step is likely to occur in the n-side pad electrode 61.

[0057] <Step of removing the substrate and exposing the first surface> The manufacturing method of the light-emitting element 1 according to the first embodiment includes, after the step of preparing the wafer W, the step of removing the substrate 101 in the wafer W and exposing the first surface 11A of the n-side semiconductor layer 11.

[0058] 18 , before removing the substrate 101, the wafer W is bonded to a support member 102, and the substrate 101 is removed while the wafer W is supported by the support member 102. The wafer W is bonded to the support member 102 via a bonding member 103 so that the fourth surface 13A of the wafer W faces the support member 102. In the example of FIG. 18 , the bonding member 103 is disposed between the second insulating layer 32 and the support member 102 so as to cover the n-side pad electrode 61 and the p-side pad electrode 62. The material of the support member 102 may be the same as that of the substrate 101. The material of the bonding member 103 may be, for example, a resin such as an epoxy resin, an acrylic resin, or a polyimide resin.

[0059] If the substrate 101 is a sapphire substrate, for example, the substrate 101 can be removed by a laser lift-off method. If the substrate 101 is a silicon substrate, for example, the substrate 101 can be removed by etching.

[0060] 19 , the first surface 11A of the n-side semiconductor layer 11 is exposed. After the first surface 11A is exposed, the n-side semiconductor layer 11 may be ground from the first surface A side, as necessary, to reduce the thickness of the n-side semiconductor layer 11.

[0061] In the method for manufacturing the light-emitting element 1 according to the first embodiment, after the step of exposing the first surface 11A, the steps shown in Fig. 20 to Fig. 27 can be performed. Note that some or all of the steps shown in Fig. 20 to Fig. 27 can be omitted as necessary.

[0062] 20 and 21 , a portion of the n-side semiconductor layer 11 located above the first n-side electrode 41 is removed from the first surface 11A, and a through-hole H that exposes the first n-side electrode 41 from the n-side semiconductor layer 11 is formed in the n-side semiconductor layer 11. For example, the portion of the n-side semiconductor layer 11 can be removed by RIE. The through-hole H extends from the first surface 11A to the third surface 11C. As shown in FIG. 20 , the third surface 11C is left in a ring shape surrounding the center of the through-hole H in a plan view. The first n-side electrode 41 is in contact with the ring-shaped third surface 11C and is exposed in the through-hole H.

[0063] <Step of Roughening the First Surface> After exposing the first surface 11A, the first surface 11A is roughened as shown in FIG. 22 . For example, the first surface 11A can be roughened by wet etching using an alkaline solution such as TMAH (tetramethylammonium hydroxide). Roughening the first surface 11A forms a plurality of convex portions 11F on the first surface 11A. This improves the light extraction efficiency from the first surface 11A. The step of roughening the first surface 11A can be performed before or after the step of forming the through holes H.

[0064] The step of roughening the first surface 11A is preferably performed after the step of forming the through holes H and before the step of forming the second n-side electrode 42. This allows the surface of the inner surface 11D that has been damaged by RIE when forming the through holes H to be removed by wet etching in the roughening step, thereby reducing the contact resistance between the second n-side electrode 42 and the inner surface 11D.

[0065] <Step of Forming Second n-Side Electrode> The second n-side electrode 42 is formed in the through hole H. The step of forming the second n-side electrode 42 includes a step of forming a conductive layer 142, which is a second conductive layer, continuously over the through hole H and the first surface 11A, as shown in FIG. 23 . The conductive layer 142 formed in the through hole H contacts the first n-side electrode 41 at the lower end of the through hole H. The conductive layer 142 formed in the through hole H is formed along the inner surface 11D of the n-side semiconductor layer 11 and contacts the inner surface 11D. A space is secured inside the conductive layer 142 formed along the inner surface 11D. The conductive layer 142 can be formed by, for example, a sputtering method, a vapor deposition method, or the like.

[0066] The process of forming the second n-side electrode 42 includes the steps of: forming a resin member 143A continuously on the conductive layer 142 on the first surface 11A and on the conductive layer 142 in the through hole H, as shown in FIG. 24; and removing the resin member 143A on the conductive layer 142 on the first surface 11A, and leaving the resin member on the conductive layer 142 in the through hole H as a mask member 143B, as shown in FIG. 25.

[0067] For example, a liquid resin member can be successively supplied onto the conductive layer 142 on the first surface 11A and onto the conductive layer 142 inside the through-hole H, and then cured to form the resin member 143A. For example, the resin member 143A on the conductive layer 142 on the first surface 11A can be removed by RIE, and the resin member on the conductive layer 142 inside the through-hole H can be left as the mask member 143B.

[0068] The step of forming the second n-side electrode 42 includes a step of removing the conductive layer 142 on the first surface 11A by using a mask member 143B, as shown in FIG. 26 . The conductive layer 142 on the first surface 11A can be removed by, for example, wet etching using the mask member 143B. By controlling the wet etching treatment time, the second n-side electrode 42 in contact with the first n-side electrode 41 below the mask member 143B remains, as shown in FIG. 26 . It is also preferable that the second n-side electrode 42 in contact with the inner surface 11D of the n-side semiconductor layer 11 remains.

[0069] 27, after the conductive layer 142 on the first surface 11A is removed, the mask member 143B in the through hole H is removed. For example, the mask member 143B can be removed by RIE.

[0070] As described above, by forming the second n-side electrode 42 in the through hole H through the steps of forming a conductive layer 142 continuously on the through hole H and the first surface 11A, forming a mask member 143B on the conductive layer 142 in the through hole H, and removing the conductive layer 142 on the first surface 11A using the mask member 143B, the second n-side electrode 42 can be easily formed in the through hole H at a position where it contacts the first n-side electrode 41.

[0071] The second n-side electrode 42 is in contact with the first n-side electrode 41. Furthermore, the second n-side electrode 42 is in contact with the inner surface 11D of the n-side semiconductor layer 11 that defines the through hole H. By forming the second n-side electrode 42 in the through hole H, as described above, it is possible to reduce the resistance of the electrical connection between the n-side semiconductor layer 11 and the n-side electrodes (the first n-side electrode 41 and the second n-side electrode 42). It is also possible to reduce the propagation of light emitted from the light-emitting region 200 that is the target of light emission to light-emitting regions 200 that are not the target of light emission.

[0072] <Process of separating the semiconductor structure into a plurality of element portions> The manufacturing method of the light-emitting element 1 according to the first embodiment includes a process of separating the semiconductor structure 10 into a plurality of element portions 100 by removing the n-side semiconductor layer 11, the active layer 12, and the p-side semiconductor layer 13, as shown in Figures 28 and 29, after the process of exposing the first surface 11A.

[0073] Fig. 28 is a schematic plan view of a region including four element portions 100 as viewed from the first surface 11A side. Fig. 29 is a schematic cross-sectional view of one element portion 100 taken along line XXIX-XXIX in Fig. 28 .

[0074] For example, by sequentially removing the n-side semiconductor layer 11, the active layer 12, and the p-side semiconductor layer 13 from the first surface 11A side by RIE, a plurality of grooves 150 extending in the first direction X and the second direction Y are formed as shown in Fig. 28. As shown in Fig. 29, the grooves 150 reach the first insulating layer 31 in the third direction Z. The grooves 150 are defined by the first insulating layer 31 and the outer side surface 10E of the semiconductor structure 10 in each element portion 100. In a plan view, each element portion 100 is surrounded by the grooves 150.

[0075] According to this embodiment, after removing the substrate 101, the n-side semiconductor layer 11, the active layer 12, and the p-side semiconductor layer 13 are removed from the exposed first surface 11A side to separate the semiconductor structure 10 into multiple element portions 100. Because etching of the semiconductor structure 10 progresses from the first surface 11A side, the opening end of the groove 150 closer to the first surface 11A is exposed to the etching gas for a longer period of time. Therefore, the opening width of the groove 150 tends to decrease from the opening end closer to the first surface 11A side toward the lower end closer to the fourth surface 13A side. The active layer 12 is located closer to the fourth surface 13A than the first surface 11A. Therefore, by removing the semiconductor structure 10 from the first surface 11A side to perform element isolation, the area of ​​the active layer 12 is less likely to be reduced compared to when the semiconductor structure 10 is removed from the fourth surface 13A side to perform element isolation. This improves the brightness of the light-emitting element 1.

[0076] <Step of Forming Protective Film> The manufacturing method of the light-emitting element 1 according to the first embodiment may include a step of forming a protective film 70 as shown in Fig. 2 after separating the semiconductor structure 10 into a plurality of element portions 100. The protective film 70 covers the outer side surface 10E and the first surface 11A of the semiconductor structure 10. The protective film 70 is also disposed in the through-hole H, and covers the inner side surface 11D of the semiconductor structure 10 and the second n-side electrode 42. The protective film 70 can be formed by, for example, a CVD method, a sputtering method, or the like.

[0077] After separating the semiconductor structure 10 into a plurality of element portions 100 in the process shown in Figures 28 and 29, the first insulating layer 31, the covering layer 50, and the second insulating layer 32 can be removed at the position of the groove 150, thereby separating the semiconductor structure 10 into a plurality of light-emitting elements 1.

[0078] After singulating into the light-emitting elements 1, the bonding member 103 is removed to separate the light-emitting elements 1 from the support member 102, thereby exposing the n-side pad electrode 61 and the p-side pad electrode 62, which are electrodes for connection to an external circuit. For example, the bonding member 103 made of a resin material can be removed by irradiating it with laser light from the support member 102 side, thereby separating the light-emitting elements 1 from the support member 102.

[0079] 30 is a schematic plan view of a light-emitting element 2 according to a second embodiment. The configuration of the light-emitting element 2 according to the second embodiment is basically the same as that of the light-emitting element 1 according to the first embodiment, and the light-emitting element 2 according to the second embodiment will be mainly described with respect to the configuration that differs from that of the light-emitting element 1 according to the first embodiment.

[0080] In the light-emitting element 2 according to the second embodiment, the third surface 11C of the n-side semiconductor layer 11, the first n-side opening 31n of the first insulating layer 31 exposing the third surface 11C, and the first n-side electrode 41 in contact with the third surface 11C in the first n-side opening 31n are arranged along the first direction X between the multiple conductive layers 20 in a plan view. This makes it possible to increase the contact area between the first n-side electrode 41 and the third surface 11C compared to the light-emitting element 1 of the first embodiment, and to reduce the forward voltage Vf of the light-emitting element 2 of the second embodiment.

[0081] Furthermore, the through hole H and the second n-side electrode 42 in contact with the first n-side electrode 41 at the through hole H are arranged in the first direction X between the plurality of conductive layers 20 in a plan view. This allows the second n-side electrode 42 to reduce light propagating between the plurality of light-emitting regions 200 divided corresponding to the plurality of conductive layers 20.

[0082] 30 , four conductive layers 20 are arranged spaced apart from one another in the first direction X and the second direction Y. In this case, the third surface 11C, the first n-side opening 31n, the first n-side electrode 41, the through-hole H, and the second n-side electrode 42 are preferably arranged along the first direction X and the second direction Y. This makes it possible to increase the contact area between the first n-side electrode 41 and the third surface 11C, and further reduce the amount of light propagating between the multiple light-emitting regions 200.

[0083] 30 , the third surface 11C, the first n-side opening 31n, the first n-side electrode 41, the through hole H, and the second n-side electrode 42 do not reach the outer edge 10A of the semiconductor structure 10 in each of the first direction X and the second direction Y. In this case, the semiconductor structure 10 is not separated in the first direction X and the second direction Y by the through hole H, and therefore the mechanical strength of the light-emitting element 2 can be increased.

[0084] Alternatively, the third surface 11C, the first n-side opening 31n, the first n-side electrode 41, the through hole H, and the second n-side electrode 42 may reach the outer edge 10A of the semiconductor structure 10 in each of the first direction X and the second direction Y. In this case, the semiconductor structure 10 is partitioned in the first direction X and the second direction Y by the through hole H and the second n-side electrode 42 arranged in the through hole H in accordance with the arrangement of the plurality of conductive layers 20. This can further reduce the propagation of light between the light-emitting regions 200, increase the difference in luminance between the light-emitting region 200 that is the target of light emission and the light-emitting region 200 that is not the target of light emission, and make the contrast between light and dark more pronounced.

[0085] [Method for Manufacturing Light-Emitting Element According to Second Embodiment] A method for manufacturing the light-emitting element 2 according to the second embodiment will be described with reference to FIGS.

[0086] 31 , the third surface 11C is formed along the first direction X and the second direction Y. A plurality of conductive layers 20 are formed on the fourth surface 13A of the p-side semiconductor layer 13 so as to sandwich the third surface 11C in each of the first direction X and the second direction Y.

[0087] 32 , the first n-side opening 31n of the first insulating layer 31 is formed between the plurality of conductive layers 20 along the first direction X and the second direction Y in a plan view. The third surface 11C extending in the first direction X and the second direction Y is exposed in the first n-side opening 31n extending in the first direction X and the second direction Y.

[0088] 33 , the first n-side electrode 41 is formed between the plurality of conductive layers 20 along the first direction X and the second direction Y in a plan view. In the first n-side opening 31n extending in the first direction X and the second direction Y, the first n-side electrode 41 extending in the first direction X and the second direction Y is in contact with the third surface 11C extending in the first direction X and the second direction Y.

[0089] 34 , a through-hole H is formed in the n-side semiconductor layer 11, extending in the first direction X and the second direction Y along the first n-side electrode 41 and exposing the first n-side electrode 41 from the n-side semiconductor layer 11. Thereafter, a second n-side electrode 42 is formed in the through-hole H, extending in the first direction X and the second direction Y along the first n-side electrode 41 and in contact with the first n-side electrode 41.

[0090] When manufacturing a light-emitting element 2 in which the through-hole H and the second n-side electrode 42 reach the outer edge 10A of the semiconductor structure 10 in each of the first direction X and the second direction Y, before the groove 150 is formed and the semiconductor structure 100 is separated into the plurality of element sections 100, the second n-side electrode 42 extends continuously in the first direction X and the second direction Y between the plurality of regions that will become the plurality of element sections 100. Therefore, a step of removing the second n-side electrode 42 at the position where the groove 150 and the second n-side electrode 42 intersect is required.

[0091] 35 is a schematic cross-sectional view of a light-emitting element 3 according to a third embodiment. The light-emitting element 3 according to the third embodiment will be mainly described with respect to the configuration different from that of the light-emitting element 1 according to the first embodiment.

[0092] In the light-emitting element 3 according to the third embodiment, the upper end 42A of the second n-side electrode 42 is continuous with the first surface 11A, and the entire inner surface 11D connecting the first surface 11A and the third surface 11C is covered by the second n-side electrode 42. This allows the second n-side electrode 42 to further reduce the propagation of light between the light-emitting regions 200, and increases the difference in luminance between the light-emitting regions 200 that are the target of light emission and the light-emitting regions 200 that are not the target of light emission, thereby making the contrast between light and dark more pronounced.

[0093] [Method for Manufacturing Light-Emitting Element According to Third Embodiment] A method for manufacturing the light-emitting element 3 according to the third embodiment will be described with reference to FIGS. 36 and 37. FIG.

[0094] In the manufacturing method of the light-emitting element 3 according to the third embodiment, the process of forming the second n-side electrode 42 includes the steps of forming a conductive layer 142 continuously on the through-hole H and the first surface 11A, as shown in FIG. 36, and removing the conductive layer 142 on the first surface 11A so that the first surface 11A and the upper end 42A of the second n-side electrode 42, which is part of the conductive layer 142 remaining in the through-hole H, are continuous, as shown in FIG. 37.

[0095] The conductive layer 142 on the first surface 11A can be removed by grinding. At this time, the first surface 11A may also be ground slightly, so it is preferable to form the conductive layer 142 on the first surface 11A before roughening so that the roughened surface does not disappear.

[0096] After removing the conductive layer 142 on the first surface 11A, the second n-side electrode 42 in the through hole H is formed of, for example, SiO ２ The first surface 11A can be roughened by wet etching or dry etching the first surface 11A in a state where the first surface 11A is covered with a mask member made of the material.

[0097] Embodiments of the present disclosure may include the following method for manufacturing a light-emitting element and the light-emitting element.

[0098] a semiconductor structure including: a substrate; an n-side semiconductor layer disposed on the substrate and having a first surface located on the substrate side, a second surface located opposite the first surface, and a third surface located opposite the first surface; an active layer disposed on the second surface; and a p-side semiconductor layer disposed on the active layer, wherein the third surface is exposed from the active layer and the p-side semiconductor layer; a plurality of conductive layers disposed on a fourth surface located on the side opposite the active layer in the p-side semiconductor layer; a first insulating layer covering the fourth surface and the plurality of conductive layers, and having a first n-side opening located above the third surface and a first p-side opening located above each of the plurality of conductive layers; a first n-side electrode disposed in the first n-side opening and in contact with the third surface; and a p-side electrode disposed in each of the plurality of first p-side openings and in contact with one of the plurality of conductive layers; Item 2. The method for manufacturing a light-emitting element according to item 1, further comprising: after the step of exposing the first surface, removing the n-side semiconductor layer, the active layer, and the p-side semiconductor layer to separate the semiconductor structure into a plurality of element portions. [Item 3] The method for manufacturing a light-emitting element according to item 1, further comprising: after the step of exposing the first surface, removing a portion of the n-side semiconductor layer from the first surface side, and forming a through-hole in the n-side semiconductor layer to expose the first n-side electrode from the n-side semiconductor layer; and forming a second n-side electrode in the through-hole so as to be in contact with the first n-side electrode. [Item 4] The method for manufacturing a light-emitting element according to Item 2, further comprising: after the step of exposing the first surface, a step of removing a part of the n-side semiconductor layer from the first surface side, and forming a through-hole in the n-side semiconductor layer, the through-hole extending in the first direction along the first n-side electrode and exposing the first n-side electrode from the n-side semiconductor layer; and a step of forming a second n-side electrode in the through-hole, the second n-side electrode extending in the first direction along the first n-side electrode and in contact with the first n-side electrode.[Item 5] The method for manufacturing a light-emitting element according to item 3 or 4, wherein the step of forming the second n-side electrode comprises: forming a conductive layer continuously on the through hole and the first surface; forming a mask member on the conductive layer in the through hole; and removing the conductive layer on the first surface using the mask member. [Item 6] The method for manufacturing a light-emitting element according to item 5, wherein the step of forming the mask member comprises: forming a resin member continuously on the conductive layer on the first surface and on the conductive layer in the through hole; and removing the resin member on the conductive layer on the first surface, leaving the resin member on the conductive layer in the through hole. [Item 7] The method for manufacturing a light-emitting element according to any one of items 3 to 6, further comprising: roughening the first surface after the step of forming the through hole and before the step of forming the second n-side electrode. [Item 8] The method for manufacturing a light-emitting element according to any one of Items 1 to 7, wherein in the step of preparing a wafer, the wafer has: a covering layer covering the first insulating layer, the first n-side electrode, and the plurality of p-side electrodes and having a plurality of second n-side openings located above the p-side electrode, an n-side pad electrode disposed on the covering layer and connected to the first n-side electrode, and a plurality of p-side pad electrodes disposed on the covering layer and connected to the plurality of p-side electrodes, wherein the n-side pad electrode is disposed in the plurality of second n-side openings and is connected to the first n-side electrode in the plurality of second n-side openings. [Item 9] The method for manufacturing a light-emitting element according to Items 3 or 4, wherein the step of forming the second n-side electrode includes the steps of: forming a conductive layer continuous with the through hole and the first surface; and removing the conductive layer on the first surface so that the first surface and upper ends of the second n-side electrodes are continuous.[Item 10] A semiconductor structure having an n-side semiconductor layer, an active layer disposed on the n-side semiconductor layer, and a p-side semiconductor layer disposed on the active layer, wherein the n-side semiconductor layer has a first surface, a second surface opposite to the first surface and located on the active layer side, a third surface opposite to the first surface and exposed from the active layer and the p-side semiconductor layer, and a through hole defined by a side surface of the n-side semiconductor layer connecting the third surface and the first surface and penetrating the n-side semiconductor layer; a plurality of conductive layers disposed on a fourth surface located on the opposite side of the active layer in the p-side semiconductor layer; a first insulating layer covering the third surface, the fourth surface, and the plurality of conductive layers, and having a first n-side opening positioned to overlap the through hole in a plan view and a first p-side opening positioned above each of the plurality of conductive layers; a first n-side electrode disposed in the first n-side opening and in contact with the third surface; and a second n-side electrode disposed in the through hole and in contact with the first n-side electrode. a p-side electrode disposed in each of the first p-side openings and in contact with one of the plurality of conductive layers. [Item 11] The light-emitting device according to item 10, wherein the third surface, the first n-side opening, the first n-side electrode, the through hole, and the second n-side electrode are disposed between the plurality of conductive layers along a first direction in a plan view.

[0099] The embodiments of the present disclosure have been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. All forms that can be implemented by a person skilled in the art through appropriate design modifications based on the above-described embodiments of the present disclosure also fall within the scope of the present disclosure, as long as they include the gist of the present disclosure. In addition, within the scope of the concept of the present disclosure, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations also fall within the scope of the present disclosure.

[0100] 1 to 3...light-emitting element, 10...semiconductor structure, 10E...outer surface, 11...n-side semiconductor layer, 11A...first surface, 11B...second surface, 11C...third surface, 11D...inner surface, 11F...convex portion, 12...active layer, 13...p-side semiconductor layer, 13A...fourth surface, 20...conductive layer (first conductive layer), 31...first insulating layer, 31n...first n-side opening, 31p...first p-side opening, 32...second insulating layer, 32n...third n-side opening, 32p...third p-side opening, 41...first n-side electrode, 42...second n-side electrode, 43...p-side electrode, 50...covering layer, 50n...second n-side opening, 50p...second p-side opening, 51...dielectric multilayer film, 52...metal film, 61...n-side pad electrode, 62...p-side pad electrode, 70...protective film, 100...element portion, 101...substrate, 102...support member, 103...bonding member, 142...conductive layer (second conductive layer), 143A...resin member, 143B...mask member, 150...groove, 200...light-emitting region, H...through hole, W...wafer

Claims

1. A semiconductor structure including: a substrate; an n-side semiconductor layer disposed on the substrate and having a first surface located on the substrate side, a second surface located opposite the first surface, and a third surface located opposite the first surface; an active layer disposed on the second surface; and a p-side semiconductor layer disposed on the active layer, wherein the third surface is exposed from the active layer and the p-side semiconductor layer; a plurality of conductive layers disposed on a fourth surface located on the p-side semiconductor layer opposite the active layer; a first insulating layer covering the fourth surface and the plurality of conductive layers, and having a first n-side opening located above the third surface and a first p-side opening located above each of the plurality of conductive layers; a first n-side electrode disposed in the first n-side opening and in contact with the third surface; and a p-side electrode disposed in each of the plurality of first p-side openings and in contact with one of the plurality of conductive layers; after the step of exposing the first surface, removing the n-side semiconductor layer, the active layer, and the p-side semiconductor layer to separate the semiconductor structure into a plurality of element portions.

2. The method for manufacturing a light-emitting element according to claim 1, wherein the third surface, the first n-side opening, and the first n-side electrode are arranged along the first direction between the plurality of conductive layers in a planar view.

3. The method for manufacturing a light-emitting element according to claim 1, further comprising the steps of: after the step of exposing the first surface, removing a portion of the n-side semiconductor layer from the first surface side and forming a through-hole in the n-side semiconductor layer that exposes the first n-side electrode from the n-side semiconductor layer; and forming a second n-side electrode in the through-hole that contacts the first n-side electrode.

4. The method for manufacturing a light-emitting element according to claim 2, further comprising the steps of: after the step of exposing the first surface, removing a portion of the n-side semiconductor layer from the first surface side, and forming a through-hole in the n-side semiconductor layer that extends in the first direction along the first n-side electrode and exposes the first n-side electrode from the n-side semiconductor layer; and forming a second n-side electrode in the through-hole that extends in the first direction along the first n-side electrode and contacts the first n-side electrode.

5. A method for manufacturing a light-emitting element as described in claim 3 or 4, wherein the step of forming the second n-side electrode comprises the steps of: forming a conductive layer continuously in the through hole and on the first surface; forming a mask member on the conductive layer in the through hole; and removing the conductive layer on the first surface using the mask member.

6. A method for manufacturing a light-emitting element as described in claim 5, wherein the step of forming the mask member comprises the steps of: forming a resin member continuously on the conductive layer on the first surface and on the conductive layer inside the through-hole; and removing the resin member on the conductive layer on the first surface and leaving the resin member on the conductive layer inside the through-hole.

7. The method for manufacturing a light-emitting element according to any one of claims 3 to 6, further comprising the step of roughening the first surface after the step of forming the through-hole and before the step of forming the second n-side electrode.

8. A method for manufacturing a light-emitting element described in any one of claims 1 to 7, wherein in the step of preparing the wafer, the wafer has: a covering layer covering the first insulating layer, the first n-side electrode, and the plurality of p-side electrodes and having a plurality of second n-side openings located above the p-side electrodes; an n-side pad electrode arranged on the covering layer and connected to the first n-side electrode; and a plurality of p-side pad electrodes arranged on the covering layer and connected to the plurality of p-side electrodes, wherein the n-side pad electrode is arranged in the plurality of second n-side openings and is connected to the first n-side electrode at the plurality of second n-side openings.

9. A method for manufacturing a light-emitting element as described in claim 3 or 4, wherein the step of forming the second n-side electrode comprises the steps of: forming a conductive layer continuous with the through hole and the first surface; and removing the conductive layer on the first surface so that the first surface and the upper end of the second n-side electrode are continuous.

10. A semiconductor structure having an n-side semiconductor layer, an active layer disposed on the n-side semiconductor layer, and a p-side semiconductor layer disposed on the active layer, wherein the n-side semiconductor layer has a first surface, a second surface opposite the first surface and located on the active layer side, a third surface opposite the first surface and exposed from the active layer and the p-side semiconductor layer, and a through hole defined by a side surface of the n-side semiconductor layer connecting the third surface and the first surface and penetrating the n-side semiconductor layer; a plurality of conductive layers disposed on a fourth surface located on the opposite side of the active layer in the p-side semiconductor layer; a first insulating layer covering the third surface, the fourth surface, and the plurality of conductive layers, and having a first n-side opening positioned to overlap the through hole in a plan view and first p-side openings positioned above the plurality of conductive layers; a first n-side electrode disposed in the first n-side opening and in contact with the third surface; and a second n-side electrode disposed in the through hole and in contact with the first n-side electrode. a p-side electrode disposed in each of the plurality of first p-side openings and in contact with one of the plurality of conductive layers.

11. The light-emitting element described in claim 10, wherein the third surface, the first n-side opening, the first n-side electrode, the through hole, and the second n-side electrode are arranged along the first direction between the plurality of conductive layers in a planar view.

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