Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which inhibition of connection between a base electrode layer and an internal electrode layer is suppressed and deterioration in moisture resistance is also suppressed. In this multilayer ceramic capacitor (1), the base electrode layer contains a second metal different from a first metal as a main component, the base electrode layer has a first region (71) and a second region (72) from a laminate (2) side, the thickness of the first region (71) in the length direction L is 1.5 times or more the distance between internal electrode layers, the particle diameter of the second metal in the first region (71) is 80% or more and 120% or less of the distance between the internal electrode layers, the content of a glass 90 in the first region (71) is 10% or less, and the content of the glass (90) in the second region (72) is 20% or more and 50% or less.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors having base electrode layers are known. The base electrode layers are formed by sintering a base electrode paste for the base electrode layer. The base electrode paste contains glass to lower the sintering temperature of the base electrode paste. Patent Document 1 discloses a multilayer ceramic capacitor in which the distribution of glass in the base electrode layer is adjusted.

[0003] Patent Application No. 2020-166300

[0004] Glass is an insulator. It may impair the connection between the base electrode layer and the internal electrode layer. It may also deteriorate the moisture resistance. To date, no technology has been proposed to suppress the connection impediment and deterioration of moisture resistance caused by glass.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor that suppresses the obstruction of the connection between the base electrode layers and the internal electrode layers and also suppresses the deterioration of moisture resistance.

[0006] The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate including first and second main surfaces opposing each other in a lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes having base electrode layers disposed on the first and second end surfaces, respectively, and connected to the internal electrode layers, The internal electrode layer contains a first metal as a main component, the base electrode layer contains a second metal different from the first metal as a main component, the base electrode layer has a first region and a second region from the laminate side, the thickness of the first region in the longitudinal direction is 1.5 times or more the distance between the internal electrode layers, the particle diameter of the second metal in the first region is 80% or more and 120% or less of the distance between the internal electrode layers, the glass content in the first region is 10% or less, and the glass content in the second region is 20% or more and 50% or less.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that suppresses the obstruction of the connection between the base electrode layer and the internal electrode layer and also suppresses the deterioration of moisture resistance.

[0008] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. 1. FIG. 3 is a cross-sectional view taken along line 102-102 in FIG. 1. FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. 1. FIG. 5 is an enlarged view of the portion corresponding to the frame 100 in FIG. 2. FIG. 6 is a table showing evaluation results of examples and comparative examples.

[0009] (Multilayer Ceramic Capacitor) A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is an external perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure.

[0010] 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes spaced apart from each other at both ends of the laminate 2. The external electrodes include a first external electrode 41 and a second external electrode 42, which will be described later.

[0011] The arrow T in FIG. 1 indicates the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 2. The arrow W indicates the width direction W of the multilayer ceramic capacitor 1 and the laminate 2. The width direction W is a direction perpendicular to the stacking direction T. The arrow L indicates the length direction L of the multilayer ceramic capacitor 1 and the laminate 2. The length direction L is a direction perpendicular to the stacking direction T and the width direction W. The stacking direction T, the width direction W, and the length direction L are perpendicular to one another. In figures other than FIG. 1, the arrows T, W, and L each indicate the same directions as those described above.

[0012] Of the pair of external electrodes, one external electrode is provided at one end of the laminate 2 in the length direction L, and the other external electrode is provided at the other end of the laminate 2 in the length direction L. One external electrode is referred to as a first external electrode 41. The other external electrode is referred to as a second external electrode 42.

[0013] (1) Laminate The laminate 2 will be described with reference to Fig. 2, Fig. 3, and Fig. 4 in addition to Fig. 1. Fig. 2 is a cross-sectional view taken along line 101-101 of Fig. 1. Fig. 3 is a cross-sectional view taken along line 102-102 of Fig. 1. Fig. 4 is a cross-sectional view taken along line 103-103 of Fig. 1. As shown in Fig. 2, the laminate 2 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers. The internal electrode layers include first internal electrode layers 31 and second internal electrode layers 32, which will be described later.

[0014] The two surfaces of the laminate 2 facing each other in the stacking direction T are called the first main surface 3 and the second main surface 4. The two surfaces of the laminate 2 facing each other in the width direction W are called the first side surface 5 and the second side surface 6. The two surfaces of the laminate 2 facing each other in the length direction L are called the first end surface 7 and the second end surface 8.

[0015] The corners and ridges of the rectangular parallelepiped laminate 2 are preferably rounded. A corner is a portion where three faces of the laminate 2 intersect, and a ridge is a portion where two faces of the laminate 2 intersect. Concaves or the like may be formed on some or all of the main surface, side surface, and end surface.

[0016] (Dielectric Layers) The total number of dielectric layers 20 included in the laminate 2 is preferably 15 to 700. The total number refers to the sum of the number of dielectric layers 20 included in the effective layer portion 10 (described later) and the number of dielectric layers 20 included in the outer layer portion.

[0017] The ceramic material contained in the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ Furthermore, ceramic materials containing these main components and additionally containing subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, and Mg compounds may also be used.

[0018] The multilayer ceramic capacitor 1 of this embodiment is an example of a multilayer ceramic electronic component. When a piezoelectric ceramic is used in the laminate, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials.

[0019] Furthermore, when a semiconducting ceramic is used in the laminate, the laminated ceramic electronic component functions as a thermistor element.Specific examples of semiconducting ceramic materials include spinel ceramic materials.

[0020] Furthermore, when magnetic ceramic is used for the laminate, the laminated ceramic electronic component functions as an inductor element.

[0021] When the internal electrode layer functions as an inductor element, the internal electrode layer becomes a coil-shaped conductor.Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0022] The thickness of one dielectric layer 20 is preferably 0.3 μm or more and 10 μm or less.

[0023] There are no particular limitations on the dimensions of the laminate 2. For example, it is preferable that the dimension of the laminate 2 in the length direction L is 0.5 mm or more and 18 mm or less, the dimension of the laminate 2 in the width direction W is 0.2 mm or more and 10 mm or less, and the dimension of the laminate 2 in the stacking direction T is 0.2 mm or more and 10 mm or less.

[0024] (2) Internal Electrode Layers The internal electrode layers will now be described. The internal electrode layers include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 are internal electrode layers exposed at the first end face 7. The second internal electrode layers 32 are internal electrode layers exposed at the second end face 8. Figure 3 shows the first internal electrode layers 31.

[0025] The first internal electrode layer 31 has a first opposing portion 33 opposing the second internal electrode layer 32, and a first lead portion 35 extending from the first opposing portion 33 to the first end face 7. The second internal electrode layer 32 has a second opposing portion 34 opposing the first internal electrode layer 31, and a second lead portion 36 extending from the second opposing portion 34 to the second end face 8.

[0026] The shape of the first opposing portion 33 of the first internal electrode layer 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or angled (tapered). Alternatively, the corners may be tapered, with an inclination in either direction.

[0027] Similarly, the shape of the second opposing portion 34 of the second internal electrode layer 32 is preferably rectangular, although not particularly limited thereto. However, the corners may be rounded or angled (tapered). Alternatively, the corners may be tapered, with an inclination increasing in either direction.

[0028] The shape of the first lead portion 35 of the first internal electrode layer 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or angled (tapered). Alternatively, the corners may be tapered, with an inclination in either direction.

[0029] Similarly, the shape of the second lead portion 36 of the second internal electrode layer 32 is preferably rectangular, although not particularly limited thereto. However, the corners may be rounded or angled (tapered). Alternatively, the second lead portion 36 may be tapered, with a slope increasing in either direction.

[0030] In the above description, the corner portion refers to a portion located at a corner of the outer shape of the internal electrode layer when the internal electrode layer is viewed in a cross section parallel to the length direction L and width direction W of the laminate 2.

[0031] The width in the width direction W of the first opposing portion 33 of the first internal electrode layer 31 and the width in the width direction W of the first lead portion 35 of the first internal electrode layer 31 may be the same width, or one of the widths may be formed narrower. Similarly, the width in the width direction W of the second opposing portion 34 of the second internal electrode layer 32 and the width in the width direction W of the second lead portion 36 of the second internal electrode layer 32 may be the same width, or one of the widths may be formed narrower.

[0032] The first internal electrode layer 31 and the second internal electrode layer 32 can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0033] (First Metal) The metal contained as the main component of the internal electrode layer is called the first metal. The metal contained as the main component is the metal with the highest weight content among the metals contained in the internal electrode layer. The first metal is preferably Ni.

[0034] In the multilayer ceramic capacitor 1 of this embodiment, capacitance is formed by opposing portions of the internal electrode layers facing each other via the dielectric layer 20. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0035] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less.

[0036] The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 700 or less.

[0037] (Effective Layer Portion and Outer Layer Portion) The division of the laminate 2 will be described. First, the division of the laminate 2 in the stacking direction T will be described. As shown in Figures 2 and 4, the laminate 2 can be divided into an effective layer portion 10, a first outer layer portion 12, and a second outer layer portion 13 in the stacking direction T.

[0038] The effective layer portion 10 is the portion of the laminate 2 included between the position of the internal electrode layer closest to the first main surface 3 and the position of the internal electrode layer closest to the second main surface 4 in the stacking direction T.

[0039] The first outer layer portion 12 is a portion of the laminate 2 included between the first main surface 3 and the position of the internal electrode layer closest to the first main surface 3 in the stacking direction T. In other words, the first outer layer portion 12 is a part of the laminate 2 included between the effective layer portion 10 and the first main surface 3. The first outer layer portion 12 is located on the first main surface 3 side of the laminate 2, and is an assembly of multiple dielectric layers 20 located between the first main surface 3 and the position of the internal electrode layer closest to the first main surface 3.

[0040] The second outer layer portion 13 is a portion of the laminate 2 included between the second main surface 4 and the position of the internal electrode layer closest to the second main surface 4 in the stacking direction T. In other words, the second outer layer portion 13 is a part of the laminate 2 included between the effective layer portion 10 and the second main surface 4. The second outer layer portion 13 is located on the second main surface 4 side of the laminate 2, and is an assembly of multiple dielectric layers 20 located between the second main surface 4 and the position of the internal electrode layer closest to the second main surface 4.

[0041] As described above, the region sandwiched between the first outer layer portion 12 and the second outer layer portion 13 is the effective layer portion 10. In the effective layer portion 10, the internal electrode layers face each other in the stacking direction T connecting the first main surface 3 and the second main surface 4. The first outer layer portion 12 and the second outer layer portion 13 are collectively referred to as the outer layer portion.

[0042] (Core Portion and Side Gap Portion) Next, the division of the laminate 2 in the width direction W will be described. As shown in FIGS. 3 and 4 , the laminate 2 can be divided into a core portion 25, a first side gap portion 15, and a second side gap portion 16 in the width direction W. The core portion 25 refers to the portion of the laminate 2 in which an internal electrode layer is provided in the width direction W. The first side gap portion 15 is the portion of the laminate 2 between the core portion 25 and the first side surface 5. The second side gap portion 16 is the portion of the laminate 2 between the core portion 25 and the second side surface 6. The first side gap portion 15 and the second side gap portion 16 are not provided with an internal electrode layer, and only a dielectric layer 20 is provided. The first side gap portion 15 and the second side gap portion 16 are collectively referred to as a side gap portion. The side gap portion is also called a W gap.

[0043] (External Electrodes) The external electrodes include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is connected to the first internal electrode layer 31 and is disposed on the first end face 7. The first external electrode 41 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the first external electrode 41 is formed to extend from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0044] The second external electrode 42 is connected to the second internal electrode layer 32 and is disposed on the second end face 8. The second external electrode 42 may also be disposed on part of the first main surface 3 and part of the second main surface 4, part of the first side surface 5 and part of the second side surface 6. In this embodiment, the second external electrode 42 is formed to extend from on the second end face 8 to part of the first main surface 3 and part of the second main surface 4, part of the first side surface 5 and part of the second side surface 6.

[0045] The first external electrode 41 and the second external electrode 42 each have a base electrode layer and a plating layer. The base electrode layer included in the first external electrode 41 is referred to as a first base electrode layer 51, and the base electrode layer included in the second external electrode 42 is referred to as a second base electrode layer 52.

[0046] (Base Electrode Layer) The base electrode layer is configured as a baking layer. The baking layer will be described. The baking layer contains a glass component and a metal. The glass component of the baking layer contains at least one element selected from, for example, B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains at least one element selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0047] (Second Metal) The metal contained as the main component of the base electrode layer is called the second metal. The second metal is a metal different from the first metal. The metal contained as the main component is the metal with the highest weight content among the metals contained in the base electrode layer. The second metal is preferably Cu.

[0048] The baked layer may be formed in a plurality of layers. The baked layer is formed by applying a base electrode paste, which is a conductive paste containing a glass component and a metal, to the laminate and baking it. The baked layer may be baked simultaneously with the internal electrode layer and the dielectric layer, or may be baked after the internal electrode layer is baked.

[0049] At the center position in the stacking direction T connecting the first main surface 3 and the second main surface 4 of the baking layer located at the first end surface 7 and the second end surface 8, the thickness in the length direction L connecting the first end surface 7 and the second end surface 8 of the baking layer is preferably, for example, approximately 2 μm or more and 40 μm or less.

[0050] Furthermore, when a baked layer is provided as a base electrode layer on a portion of the first main surface 3 and a portion of the second main surface 4, as well as on a portion of the first side surface 5 and a portion of the second side surface 6, the thickness in the stacking direction T connecting the first main surface 3 and the second main surface 4 at the center of the length direction L connecting the first end surface 7 and the second end surface 8 of the base electrode layer located on the first main surface 3 and the second main surface 4, and the first side surface 5 and the second side surface 6, is preferably, for example, approximately 2 μm or more and 40 μm or less.

[0051] (Plating Layer) Next, the plating layer will be described. The plating layer includes a first plating layer and a second plating layer. The first plating layer is a plating layer included in the first external electrode 41. The second plating layer is a plating layer included in the second external electrode 42.

[0052] The plating layer may be formed of multiple layers. In this embodiment, the first plating layer and the second plating layer each include two plating layers. When the plating layer has a two-layer structure, preferably, one layer is a Ni plating layer and the other layer is a Sn plating layer. In this embodiment, each plating layer includes a Ni plating layer and a Sn plating layer.

[0053] The Ni plating layer included in the first plating layer is the first Ni plating layer 63, and the Ni plating layer included in the second plating layer is the second Ni plating layer 64. The Sn plating layer included in the first plating layer is the first Sn plating layer 65, and the Sn plating layer included in the second plating layer is the second Sn plating layer 66.

[0054] The first Ni plating layer 63 is disposed so as to cover the first base electrode layer 51. The second Ni plating layer 64 is disposed so as to cover the second base electrode layer 52. The first Sn plating layer 65 is disposed so as to cover the first Ni plating layer 63. The second Sn plating layer 66 is disposed so as to cover the second Ni plating layer 64.

[0055] The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component. The Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, allowing for easier mounting. Therefore, it is preferable that the plating layers be Ni plating layer and Sn plating layer in order from the plating layer in contact with the base electrode layer. Note that the number of plating layers may be three or more, and the plating layers may be mainly composed of metal species other than Ni and Sn.

[0056] The material constituting the plating layer is not limited to the above examples, and may include at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0057] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0058] (Base Electrode Layer) The base electrode layer of the multilayer ceramic capacitor 1 of this embodiment will be specifically described with reference to Fig. 5. Fig. 5 is an enlarged view of a portion corresponding to the frame 100 in Fig. 2. Fig. 5 shows a first base electrode layer 51 included in the first external electrode 41. The matters described below regarding the first base electrode layer 51 also apply to the second base electrode layer 52.

[0059] 5 , the first base electrode layer 51 mainly contains glass 90 and second metal particles 92. The first base electrode layer 51 also has a first region 71 and a second region 72 from the laminate 2 side. The first region 71 and the second region 72 are distinguished by the particle diameter of the contained second metal particles 92.

[0060] 5, the distance between adjacent internal electrode layers is indicated by a distance 201. The distance 201 is called the internal electrode layer distance 201. The internal electrode layer distance 201 is also the thickness of the dielectric layer 20 in the stacking direction T. In a region of a predetermined area in the base electrode layer, if the particle diameter of the second metal particles 92 is larger than the internal electrode layer distance 201, the region is determined to be the first region 71. If the particle diameter of the second metal particles 92 is equal to or smaller than the internal electrode layer distance 201, the region is determined to be the second region 72.

[0061] The first region 71 is in contact with the first end face 7 of the laminate 2. A first Ni plating layer 63 is provided on the surface of the second region 72 opposite to the first region 71.

[0062] (Length direction thickness of first region) The thickness of the base electrode layer in the length direction L is indicated by thickness 210. The thickness of the first region 71 in the length direction L is indicated by thickness 211. The thickness 211 of the first region 71 in the length direction L is 1.5 times or more the distance 201 between the internal electrode layers. By making the thickness 211 1.5 times or more the distance 201 between the internal electrode layers, it becomes easy to suppress the obstruction of the connection between the base electrode layer and the internal electrode layer.

[0063] (Particle diameter of metal in first region) As described above, the internal electrode layer contains a first metal as a main component, and the base electrode layer contains a second metal as a main component. The second metal is different from the first metal. The first metal can be Ni. The second metal can be Cu. In the multilayer ceramic capacitor 1 of this embodiment, the particle diameter of the second metal in the first region 71 is 80% or more and 120% or less of the distance 201 between the internal electrode layers.

[0064] If the particle diameter of the second metal in the first region 71 is less than 80% of the distance 201 between the internal electrode layers, the connection between the base electrode layer and the internal electrode layer is likely to be hindered. If the particle diameter of the second metal in the first region 71 exceeds 120% of the distance 201 between the internal electrode layers, the strength of the boundary between the first region 71 and the second region 72 is likely to be reduced.

[0065] (Glass Content) The base electrode layer contains glass 90 in addition to metal. The glass 90 content in the second region 72 is higher than the glass 90 content in the first region 71. The glass 90 content in the first region 71 is 10% or less. The glass 90 content in the second region 72 is 20% or more and 50% or less. If the glass 90 content in the first region 71 exceeds 10%, the metal content in the first region 71 is likely to decrease, and the connection between the base electrode layer and the internal electrode layer is likely to be impaired. If the glass 90 content in the second region 72 is less than 20%, it becomes difficult to lower the sintering temperature of the base electrode paste when forming the base electrode layer. If the glass 90 content in the second region 72 exceeds 50%, it becomes difficult to suppress deterioration of moisture resistance.

[0066] (Metal Particle Diameter) The particle diameter of the second metal particles 92 in the first region 71 is larger than the particle diameter of the second metal particles 92 in the second region 72. Here, the particle diameter refers to the circle-equivalent diameter. This makes it easy to suppress deterioration of moisture resistance in the second region 72 while suppressing impediments to connection between the base electrode layer and the internal electrode layer in the first region 71.

[0067] The large particle size of the second metal in the first region 71 makes it easier to suppress the obstruction of the connection between the base electrode layer and the internal electrode layer in the first region 71. Furthermore, the large particle size of the second metal in the first region 71 makes it easier for the glass 90 in the first region 71 to move to the second region 72. This is because the glass 90 in the first region 71 is more likely to be pushed out into the second region 72 during the grain growth of the second metal in the first region 71.

[0068] In the second region 72, the portion located on the plating layer side contains a relatively smaller amount of glass 90 than the portion located on the first region 71 side. This is because the portion located on the plating layer side is relatively less affected by glass that has migrated from the first region 71. However, the glass content in the portion located on the plating layer side is never smaller than that in the first region 71. This is because glass does not often migrate to other portions in the portion located on the plating layer side, as in the first region 71. The portion located on the plating layer side refers to, for example, a portion extending from the plating layer side to 30% of the thickness 212 in the longitudinal direction L.

[0069] (Porosity) The porosity of the first region 71 can be set to 10% or less. Setting the porosity of the first region 71 to 10% or less makes it easier to suppress deterioration of moisture resistance.

[0070] The characteristics of the multilayer ceramic capacitor 1 of this embodiment will be described in more detail below. (Regarding Conductivity) The glass content in the first region 71 is 10% or less. By making the thickness 211 of the first region 71 1.5 times or more the distance 201 between the internal electrode layers, the region containing the insulator glass 90 at 10% or less becomes large. Therefore, when a voltage is applied to the multilayer ceramic capacitor 1, many current paths can be secured in the base electrode layer, improving the conductivity of the base electrode layer and, ultimately, the conductivity of the external electrodes.

[0071] Specifically, because glass is an insulator, it may impair the connection between the base electrode layer and the internal electrode layer. When the glass content of the first region 71 is 10% or less, the amount of glass, which is an insulator, is small, so many current paths can be secured within the base electrode layer. This improves the conductivity of the base electrode layer. On the other hand, when the glass content of the first region 71 is 10% or more, the amount of glass, which is an insulator, is large, so the conductivity within the base electrode layer decreases.

[0072] (Regarding moisture resistance) Glass has a high affinity with water. Therefore, glass may deteriorate moisture resistance. On the other hand, glass can lower the sintering temperature of the base electrode paste. When the glass content of the second region 72 is 20% or more and 50% or less, it becomes possible to adjust the sintering temperature during sintering, that is, to lower the sintering temperature, while ensuring moisture resistance.

[0073] If the glass content of the second region 72 is less than 20%, the sintering temperature may not be adjusted sufficiently, which may result in poor sintering. Poor sintering reduces the moisture resistance reliability of the base electrode layer. On the other hand, if the glass content of the second region 72 is more than 50%, the presence of a large amount of glass, which is an insulator, makes it difficult to ensure good conductivity within the base electrode layer.

[0074] Note that as the particle diameter of the second metal, such as Cu, in the first region 71 increases, the thickness 211 of the first region 71 in the longitudinal direction L tends to increase. Therefore, by making the particle diameter of the second metal in the first region 71 larger than the particle diameter of the second metal in the second region 72, for example, the thickness 211 of the first region 71 in the longitudinal direction L can be increased. Furthermore, a low glass content in the first region 71 means that glass is extruded into the second region 72. Therefore, the glass content in the second region 72 is likely to be higher than the glass content in the first region 71.

[0075] For example, by making the particle size of the second metal in the first region 71 larger than the particle size of the second metal in the second region 72, that is, by promoting grain growth in the first region 71 more than in the second region 72, it is possible to promote the movement of glass from the first region 71 to the second region 72. This movement of glass from the first region 71 to the second region 72 is thought to occur during the sintering process of the base electrode paste.

[0076] In the multilayer ceramic capacitor 1 of this embodiment, for example, two regions with different glass contents can be created using one type of base electrode paste, without using two types of base electrode paste with different glass contents.

[0077] (Method for Measuring Metal Particle Size, Glass Content, etc.) The method for measuring the particle size and glass content of the second metal of the multilayer ceramic capacitor 1 will be described. First, a cross section of the multilayer ceramic capacitor 1 is exposed. Specifically, the cross section is polished from the first side surface 5 or the second side surface 6 of the multilayer ceramic capacitor 1 to the center of the width direction W of the multilayer ceramic capacitor 1 to expose a cross section parallel to the length direction L and the stacking direction T. The cross section parallel to the length direction L and the stacking direction T is called the LT cross section. Next, the exposed LT cross section is observed and imaged using a digital microscope. The observation and image capturing conditions are a magnification of 400x and a field of view of 750 μm × 750 μm. Metal, glass, and other components are identified from the captured image. Areas where no metal or glass is detected are considered voids. Image analysis software is then used to determine the metal particle size, glass content, porosity, and other parameters from the area of ​​the image. The glass content and porosity are expressed as area percentages relative to a given field of view in the cross section. The particle diameter can be determined as a circle-equivalent D50 diameter by analyzing an image of the LT cross section using image analysis software. The internal electrode layer distance 201 can also be determined from the image of the LT cross section.

[0078] (Method for Identifying First Region and Second Region) A method for identifying the first region 71 and the second region 72 will be described. As described above, the first region 71 is a region of a predetermined area in which the particle diameter of the second metal particles 92 is larger than the internal electrode interlayer distance 201. The second region 72 is a region of a predetermined area in which the particle diameter of the second metal particles 92 is equal to or smaller than the internal electrode interlayer distance 201. The particle diameter here does not mean the average particle diameter, but refers to the particle diameter of each individual second metal particle 92, such as particle 921 shown in FIG. 5 as an example of the second metal particle 92.

[0079] Specifically, the particle diameter of the second metal particles 92 in the first region 71 and the second region 72 here means the largest particle diameter in the first region 71 and the largest particle diameter in the second region 72. Also, the region of a predetermined area means a rectangular region of 6 μm × 6 μm.

[0080] (Examples and Comparative Examples) Examples and Comparative Examples will be described with reference to Fig. 6. Fig. 6 is a table showing the evaluation results of the examples and comparative examples.

[0081] Experiments were conducted in which the glass content of the base electrode paste in each experimental example was different for each comparative example and example, and the results of moisture resistance and ESR (equivalent series resistance) depending on the glass content of the first and second regions were confirmed. The glass content is shown as area % as described above. The glass content of the base electrode paste is the sum of the glass content of the first region and the glass content of the second region.

[0082] The moisture resistance reliability was evaluated for each sample using the following method. First, each sample was mounted on a wiring board using eutectic solder. Next, the insulation resistance value of each sample was measured. Next, the wiring board was placed in a high-temperature, high-humidity chamber, and a direct current of 6.3 V was applied between a pair of external electrodes of each sample in an environment of 65°C and 95% RH for 500 hours. Next, the insulation resistance value of each sample after the moisture resistance test was measured.

[0083] The insulation resistance value of each sample after the test was measured, and samples with an insulation resistance value of 1 MΩ or more were evaluated as "Good", and samples with an insulation resistance value of less than 1 MΩ were evaluated as "Poor". The moisture resistance reliability test was conducted on 50 samples prepared for each sample number.

[0084] Before measuring the ESR, the multilayer ceramic capacitors were heat-treated in an air atmosphere at 150°C for 1 hour, then mounted on a measurement board. 24±2 hours after the heat treatment, the ESR was measured using a network analyzer at a measurement frequency of 10 MHz. 50 capacitors were measured, and the average values ​​were used as the values ​​in the table. A value of 150 MΩ or less was evaluated as "Good," and a value of 150 MΩ or more was evaluated as "Poor."

[0085] (Specifications of Samples in Examples and Comparative Examples) The specifications of the samples used in Experimental Example 1 will be described. According to the manufacturing method of the multilayer ceramic capacitor 1 described above, a multilayer ceramic capacitor 1 having the following specifications was fabricated. The size of the multilayer ceramic capacitor 1, L dimension (length direction) × W dimension (width direction) × T dimension (thickness direction), is as follows: L dimension [mm]: 0.4, W dimension [mm]: 0.2, T dimension [mm]: 0.2

[0086] The thickness of the internal electrodes was 0.40 μm, the thickness of the ceramic layers was 0.5 μm, the number of laminated layers was 220, the dielectric constant was 4000 F / m, and the capacitance was 1.0 μF.

[0087] The external electrodes included a base electrode layer and a plating layer, and the base electrode layer was made of Cu and had a two-layer structure consisting of a Ni plating layer and a Sn plating layer. The thickness of the external electrodes was 21 μm. Specifically, the thickness of the base electrode layer was 15 μm, the thickness of the Ni plating layer was 3 μm, and the thickness of the Sn plating layer was 3 μm.

[0088] The glass content in the base electrode layer was adjusted to the glass content described in each Example and Comparative Example. The glass content in the base electrode paste is the sum of the glass content in the first region and the glass content in the second region.

[0089] As shown in Examples 1 to 5 in Fig. 6, when the ratio of (thickness of the first region) / (distance between internal electrode layers) was 1.5 or more, the glass content of the first region was 10% or less, and the glass content of the second region was 20% or more and 50% or less, both the moisture resistance and ESR were evaluated as "good." On the other hand, as shown in Comparative Examples 1 to 5, when even one of the above requirements was not satisfied, none of the samples was evaluated as "good" for both the moisture resistance and the ESR.

[0090] (Dimensions of the Multilayer Ceramic Capacitor) The dimension in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is defined as dimension L. The dimension L is preferably 0.4 mm or more and 2.1 mm or less. The dimension in the stacking direction T of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is defined as dimension T. The dimension T is preferably 0.3 mm or more and 1.3 mm or less. The dimension in the width direction W of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is defined as dimension W. The dimension W is preferably 0.2 mm or more and 1.3 mm or less.

[0091] (Method for manufacturing a multilayer ceramic capacitor) A method for manufacturing a multilayer ceramic capacitor will be described. (1) A dielectric sheet and a conductive paste for an internal electrode layer are prepared. The conductive paste for the dielectric sheet and the internal electrode layer contains a binder and a solvent. Known binders and solvents can be used.

[0092] (2) A dielectric sheet on which no internal electrode layer pattern is formed, and a conductive paste for internal electrode layers is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing, to prepare a dielectric sheet on which a first internal electrode layer pattern is formed and a dielectric sheet on which a second internal electrode layer pattern is formed.

[0093] (3) A predetermined number of dielectric sheets on which no internal electrode layer pattern is printed are stacked to form a portion that will become an outer layer portion on the first main surface side, and a dielectric sheet on which a first internal electrode layer pattern is printed and a dielectric sheet on which a second internal electrode layer pattern is printed are stacked in this order on top of that to form a portion that will become an effective layer portion, and further a predetermined number of dielectric sheets on which no internal electrode layer pattern is printed are stacked on top of the portion that will become the effective layer portion to form a portion that will become an outer layer portion on the second main surface side, thereby producing a laminated sheet.

[0094] (4) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block. At this time, corners and ridges of the laminated block may be rounded by barrel polishing or the like.

[0095] (5) The laminated block is cut into a predetermined size corresponding to the dimensions of the laminated chip, thereby manufacturing the laminated chip.

[0096] (6) The laminated chip is fired to produce a laminate. The firing temperature is preferably 900° C. or higher and 1400° C. or lower, although it depends on the materials of the dielectric and internal electrode layers.

[0097] (Base Electrode Layer) (7) A conductive paste for the external electrodes is applied to both end surfaces of the laminate and baked to form baked layers for the external electrodes. The baked layers function as base electrode layers. The baking temperature is preferably 700°C or higher and 900°C or lower.

[0098] The base electrode layer will be described in more detail. (7-1) A base electrode paste containing a filler of a second metal (Cu), glass, and a binder is prepared. The average particle diameter (circular equivalent diameter) of the filler is set to 1 / 2 or less of the thickness of the internal electrode layer. Only one type of base electrode paste is prepared. Multiple types of paste may be applied in layers, but the glass content of the multiple types of pastes should be the same.

[0099] (7-2) The paste for the base electrode is sintered under predetermined sintering conditions. Because the average particle size of the filler is set to 1 / 2 or less of the thickness of the internal electrode layer, it is in contact with the first metal (Ni) of the internal electrode layer more. Because of this contact, the glass remains near the internal electrode layer during sintering and grows into grains. During the grain growth process, the glass is moved to the second region.

[0100] (7-3) The region where the second metal (Cu) grains grow near the internal electrode layer (the region after the glass has been moved) becomes the first region. Because the glass is moved, the amount of glass in the first region becomes extremely small. The region where the moved glass exists becomes the second region.

[0101] (8) Then, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating. In this manner, the multilayer ceramic capacitor 1 body is obtained.

[0102] The above explanation also applies to the second external electrode.

[0103] Although the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0104] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate including first and second main surfaces opposing each other in a lamination direction, first side surfaces and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first end surfaces and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes having base electrode layers disposed on the first end surfaces and the second end surfaces and connected to the internal electrode layers, wherein the internal electrode layers contain a first metal as a main component, and the base electrode layer contains a second metal different from the first metal as a main component, the base electrode layer having a first region and a second region from the laminate side, the thickness of the first region in the length direction being 1.5 times or more the distance between the internal electrode layers, and the particle diameter of the second metal in the first region being 80% or more and 120% or less of the distance between the internal electrode layers, A multilayer ceramic capacitor, wherein the first region has a glass content of 10% or less, and the second region has a glass content of 20% or more and 50% or less.

[0105] <2> The multilayer ceramic capacitor according to <1>, wherein a particle diameter of the second metal in the first region is larger than a particle diameter of the second metal in the second region.

[0106] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the second region has an inner region having a relatively high glass content and an outer region having a relatively low glass content.

[0107] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein a plating layer is disposed in contact with the second region.

[0108] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first region has a porosity of 10% or less.

[0109] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 First main surface 4 Second main surface 5 First side surface 6 Second side surface 7 First end surface 8 Second end surface 10 Effective layer portion 12 First outer layer portion 13 Second outer layer portion 15 First side gap portion 16 Second side gap portion 20 Dielectric layer 25 Core portion 31 First internal electrode layer 32 Second internal electrode layer 41 First external electrode 42 Second external electrode 51 First base electrode layer 52 Second base electrode layer 63 First Ni plating layer 64 Second Ni plating layer 65 First Sn plating layer 66 Second Sn plating layer 71 First region 72 Second region 90 Glass 92 Particles of second metal 921 Particles L Length direction T Stacking direction W Width direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate including first and second main surfaces opposing each other in the lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes having base electrode layers disposed on the first end surfaces and the second end surfaces and connected to the internal electrode layers, wherein the internal electrode layers contain a first metal as a main component, and the base electrode layer contains a second metal different from the first metal as a main component, the base electrode layer having a first region and a second region from the laminate side, the thickness of the first region in the length direction being 1.5 times or more the distance between the internal electrode layers, and the particle diameter of the second metal in the first region being 80% or more and 120% or less of the distance between the internal electrode layers, A multilayer ceramic capacitor, wherein the first region has a glass content of 10% or less, and the second region has a glass content of 20% or more and 50% or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the particle size of the second metal in the first region is larger than the particle size of the second metal in the second region.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the second region has an inner region with a relatively high glass content and an outer region with a relatively low glass content.

4. The multilayer ceramic capacitor according to claim 1, wherein a plating layer is disposed in contact with the second region.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the porosity of the first region is 10% or less.

Images