Doherty amplification circuit

Abstract

A Doherty amplification circuit (10) to which a D-ET mode or an SPT mode is applied comprises: a power amplifier (11) used as a carrier amplifier; a power amplifier (12) used as a peak amplifier; and a synthesizer (22) including an input terminal (221) connected to an output terminal of the power amplifier (11), an input terminal (222) connected to an output terminal of the power amplifier (12), and an output terminal (223). The size of the power amplifier (12) is smaller than the size of the power amplifier (11).

Description

Doherty amplifier circuit

[0001] The present invention relates to a Doherty amplifier circuit.

[0002] In recent years, wide modulation bandwidths (channel bandwidths) have been used for signals transmitted by wireless communication devices such as smartphones, tablet computers, and IoT (Internet of Things) devices. Technologies for improving the efficiency of power amplifier circuits that amplify signals with such wide modulation bandwidths have been proposed.

[0003] For example, Patent Document 1 discloses a digital-envelope tracking (D-ET) mode in which a plurality of discrete voltages are selectively supplied to a Doherty amplifier circuit based on an envelope signal.

[0004] For example, Patent Document 2 discloses a symbol power tracking (SPT) mode in which the level of the power supply voltage is modulated in units of one symbol based on the power of the symbol interval.

[0005] US Patent Application Publication No. 2020 / 0350866 US Patent No. 10,686,407

[0006] However, when the D-ET mode or the SPT mode is applied to a Doherty amplifier circuit, the efficiency may decrease.

[0007] Therefore, the present invention provides a Doherty amplifier circuit that can suppress the decrease in efficiency of the Doherty amplifier circuit due to the D-ET mode or the SPT mode.

[0008] A Doherty amplifier circuit according to one aspect of the present invention is a Doherty amplifier circuit to which a digital-envelope tracking (D-ET) mode or a symbol power tracking (SPT) mode is applied, and includes a first power amplifier used as a carrier amplifier, a second power amplifier used as a peak amplifier, and a combiner including a first input terminal connected to an output end of the first power amplifier, a second input terminal connected to an output end of the second power amplifier, and a first output terminal, wherein the size of the second power amplifier is smaller than the size of the first power amplifier.

[0009] According to the present invention, it is possible to suppress a decrease in efficiency of a Doherty amplifier circuit due to the D-ET mode or the SPT mode.

[0010] FIG. 1A is a graph showing an example of a change in power supply voltage in APT mode. FIG. 1B is a graph showing an example of a change in power supply voltage in A-ET mode. FIG. 1C is a graph showing an example of a change in power supply voltage in D-ET mode and SPT mode. FIG. 2A is a diagram showing frames, subframes, slots, and symbols. FIG. 2B is a diagram showing an example of a change in power supply voltage in SPT mode. FIG. 3 is a circuit configuration diagram of a communication device according to an embodiment. FIG. 4 is a graph showing the relationship between output power and efficiency in Doherty amplifier circuits according to an embodiment and a comparative example. FIG. 5 is a flowchart showing the operation of the Doherty amplifier circuit according to the embodiment. FIG. 6 is a diagram showing the state of the Doherty amplifier circuit in HP mode and in D-ET mode / SPT mode. FIG. 7 is a graph showing the relationship between output power and efficiency in HP mode and in D-ET mode / SPT mode. FIG. 8 is a diagram showing the state of the Doherty amplifier circuit in HP mode and in APT mode. Fig. 9 is a graph showing the relationship between input power and efficiency in HP mode and APT mode. Fig. 10 is a diagram showing the state of the Doherty amplifier circuit in LP mode and APT mode. Fig. 11 is a graph showing the relationship between input power and efficiency in LP mode and APT mode. Fig. 12 is a circuit configuration diagram of a Doherty amplifier circuit according to Modification 1. Fig. 13 is a circuit configuration diagram of a Doherty amplifier circuit according to Modification 2.

[0011] As a technology for highly efficient amplification of high-frequency signals, a tracking mode is described below, in which a power supply voltage that is dynamically adjusted over time based on the high-frequency signal is supplied to a power amplifier. The tracking mode is a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. There are several types of tracking modes, but here, the average power tracking (APT) mode, analog envelope tracking (A-ET) mode, D-ET mode, and SPT mode are described.

[0012] First, the APT mode, A-ET mode, and D-ET mode will be explained with reference to Figures 1A, 1B, and 1C. In Figures 1A, 1B, and 1C, the horizontal axis represents time and the vertical axis represents voltage. The thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation signal.

[0013] 1A is a graph showing an example of the transition of the power supply voltage in the APT mode, which is a mode in which the power supply voltage is varied to a plurality of discrete voltage levels in units of one frame based on the average power.

[0014] A frame is a unit that constitutes a high-frequency signal (modulated signal). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame includes 10 subframes, each subframe includes multiple slots, and each slot includes multiple symbols. The subframe length is 1 millisecond, and the frame length is 10 milliseconds.

[0015] In addition, the APT mode may include a mode in which the voltage level is varied in units larger than one frame based on the average power, and may also include a mode in which the voltage level is varied in units smaller than one frame (e.g., subframe or slot units) based on the average power.

[0016] 1B is a graph showing an example of the transition of the power supply voltage in the A-ET mode. The A-ET mode is a mode in which the power supply voltage is continuously varied based on the envelope signal. In the A-ET mode, the power supply voltage can track the envelope of the modulating signal.

[0017] The envelope signal is a signal that indicates the envelope of the modulated signal. The envelope value is, for example, (I ２ +Q ２) where (I, Q) represents a constellation point. A constellation point is a point that represents a digitally modulated signal on a constellation diagram. (I, Q) is determined, for example, by a Baseband Integrated Circuit (BBIC) based on the transmitted information.

[0018] 1C is a graph showing an example of the transition of the power supply voltage in the D-ET mode and the SPT mode. The D-ET mode is a mode in which the power supply voltage is varied to a plurality of discrete voltage levels within one frame based on an envelope signal. In the D-ET mode, the power supply voltage can track the envelope of the modulating signal, and the power supply voltage level varies at shorter time intervals than in the APT mode.

[0019] The SPT mode is a mode in which the level of the power supply voltage is modulated in units of one symbol based on the power of the symbol interval. In other words, in the SPT mode, the level of the power supply voltage can be changed in units of one symbol.

[0020] Here, the SPT mode will be described with reference to Figures 2A and 2B. Figure 2A is a diagram showing frames, subframes, slots, and symbols. Figure 2B is a diagram showing changes in the level of the power supply voltage in the SPT mode. Note that Figures 2A and 2B show the relationship between frames, subframes, slots, and symbols in 5G NR and LTE.

[0021] As shown in Fig. 2A, a frame is a unit of a high-frequency signal having a length of 10 milliseconds and includes 10 subframes. A subframe is a unit of a high-frequency signal having a length of 1 millisecond and includes 2 slots. A slot is a unit of a high-frequency signal having a length of 0.5 milliseconds and includes 6 symbols. A symbol is a unit of a high-frequency signal having a length of 71 microseconds and includes a cyclic prefix (CP).

[0022] As shown in Figure 2B, in SPT mode, the level of the power supply voltage is modulated in units of one symbol. At this time, the voltage level is changed in the CP section. For example, in symbol "1", the voltage level is changed to a higher voltage level in the CP, and in symbol "2", the voltage level is changed to a lower voltage level in the CP. Note that the voltage level does not have to be changed, as in symbol "5". The level of the power supply voltage can be modulated based on the data signal in each symbol section.

[0023] (Embodiments) Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0024] Note that each drawing is a schematic diagram in which emphasis, omission, or adjustment of proportions has been appropriately made, and is not necessarily an exact illustration, and may differ from the actual shape, positional relationship, and proportion. In each drawing, the same reference numerals are used to denote substantially the same components, and duplicated explanations may be omitted or simplified.

[0025] In the following description, "connected" includes not only direct connection by connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and that they are arranged in series on a path connecting A and B. "A path connecting A and B" means a path made up of a conductor electrically connecting A to B.

[0026] "Terminal" means a point where a conductor within an element terminates. Note that terminal is understood to mean any point on the conductor between elements or the entire conductor, not just a single point, provided the impedance of the conductor between elements is sufficiently low.

[0027] The "filter passband" is the portion of the frequency spectrum transmitted by the filter, defined as the frequency band between two frequencies 3 dB above the minimum power insertion loss.

[0028] The term "transmission band" refers to a frequency band used for transmission in a communication device, and the term "reception band" refers to a frequency band used for reception in a communication device. For example, in a frequency division duplex (FDD) band, different frequency bands (e.g., an uplink band and a downlink band) are used as the transmission band and the reception band. For example, in a time division duplex (TDD) band, the same frequency band is used as the transmission band and the reception band.

[0029] The "size of the power amplifier" means the area of ​​the emitter region when viewed in plan if the amplifying transistor is a bipolar transistor, and means the length of the gate width if the amplifying transistor is a FET.

[0030] Terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "rectangle," and numerical ranges do not only indicate the strict meaning, but also include a substantially equivalent range, for example, an error of a few percent.

[0031] [1. Circuit Configuration of Communication Device 6] An exemplary circuit configuration of the communication device 6 according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a circuit configuration diagram of the communication device 6 according to this embodiment.

[0032] 3 is an exemplary circuit diagram, and communication device 6 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of communication device 6 provided below should not be construed as limiting.

[0033] The communication device 6 according to the present embodiment can be used to provide wireless connectivity. For example, the communication device 6 can be implemented in a UE in a cellular network (also referred to as a mobile network), such as a mobile phone, a smartphone, a tablet computer, or a wearable device. In another example, the communication device 6 can provide wireless connectivity to an Internet of Things (IoT) sensor device, a medical / healthcare device, a car, an unmanned aerial vehicle (UAV) (also known as a drone), or an automated guided vehicle (AGV). In yet another example, the communication device 6 can provide wireless connectivity in a wireless access point or a wireless hotspot.

[0034] The communication device 6 includes a high-frequency circuit 1 , an antenna 2 , an RFIC (Radio Frequency Integrated Circuit) 3 , a BBIC (Baseband Integrated Circuit) 4 , and a tracker circuit 5 .

[0035] The high-frequency circuit 1 can transmit high-frequency signals between the antenna 2 and the RFIC 3. The circuit configuration of the high-frequency circuit 1 will be described later.

[0036] The antenna 2 is connected to the antenna connection terminal 100 of the high-frequency circuit 1. The antenna 2 can receive a high-frequency signal from the high-frequency circuit 1 and transmit it to the outside of the communication device 6. The antenna 2 may also receive a high-frequency signal from the outside of the communication device 6 and output it to the high-frequency circuit 1. The antenna 2 does not have to be included in the communication device 6. The communication device 6 may also include one or more antennas in addition to the antenna 2.

[0037] The RFIC 3 is an example of a signal processing circuit that processes high-frequency signals. Specifically, the RFIC 3 can perform signal processing on a transmission signal input from the BBIC 4 by up-conversion or the like, and output the high-frequency transmission signal generated by the signal processing to the high-frequency circuit 1. Furthermore, the RFIC 3 can perform signal processing on a high-frequency reception signal input via the reception path of the high-frequency circuit 1 by down-conversion or the like, and output the reception signal generated by the signal processing to the BBIC 4. The RFIC 3 may also have a control unit that controls switches, power amplifiers, and the like included in the high-frequency circuit 1. Note that part or all of the functions of the RFIC 3 as a control unit may be included outside the RFIC 3, and may be included in, for example, the BBIC 4 or the high-frequency circuit 1.

[0038] The BBIC 4 is a baseband signal processing circuit that processes signals using a frequency band lower than the high-frequency signal transmitted by the high-frequency circuit 1. The signals processed by the BBIC 4 include, for example, image signals for image display and / or audio signals for calls via a speaker. The BBIC 4 does not necessarily have to be included in the communication device 6.

[0039] The tracker circuit 5 can supply a power supply voltage for operating the Doherty amplifier circuit 10 in the D-ET mode and / or the SPT mode. Additionally, the tracker circuit 5 can also supply a power supply voltage for operating the Doherty amplifier circuit 10 in the APT mode.

[0040] [2. Circuit Configuration of High-Frequency Circuit 1] Next, the circuit configuration of the high-frequency circuit 1 according to this embodiment will be described with reference to Fig. 3. Note that Fig. 3 is an exemplary circuit configuration diagram, and the high-frequency circuit 1 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1 provided below should not be interpreted in a limiting manner.

[0041] The high-frequency circuit 1 includes a Doherty amplifier circuit 10 , filters 41 , 42 , 43 and 44 , switch circuits 51 and 52 , and an antenna connection terminal 100 .

[0042] The antenna connection terminal 100 is an external connection terminal of the high frequency circuit 1 , and is connected to the antenna 2 outside the high frequency circuit 1 and to the switch circuit 51 inside the high frequency circuit 1 .

[0043] The Doherty amplifier circuit 10 is an amplifier circuit that achieves high efficiency by using multiple power amplifiers as carrier amplifiers and peak amplifiers. In the Doherty amplifier circuit 10, a carrier amplifier refers to a power amplifier that operates regardless of whether the power of the input signal (high-frequency signal) is low or high. Basically, a carrier amplifier operates in class A or class AB. In the Doherty amplifier circuit 10, a peak amplifier refers to a power amplifier that mainly operates when the power of the input signal is high. Basically, a peak amplifier operates in class C.

[0044] The filter 41 is a band-pass filter having a pass band that includes the transmission band of band A. The filter 41 is connected between the switch circuits 51 and 52.

[0045] The filter 42 is a band-pass filter having a pass band that includes the transmission band of band B. The filter 42 is connected between the switch circuits 51 and 52.

[0046] The filter 43 is a band-pass filter having a pass band that includes the transmission band of band C. The filter 43 is connected between the switch circuits 51 and 52.

[0047] The filter 44 is a band-pass filter having a pass band that includes the transmission band of band D. The filter 44 is connected between the switch circuits 51 and 52.

[0048] The filters 41 to 44 may be, but are not limited to, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, LC resonant filters, dielectric resonant filters, or any combination thereof.

[0049] Bands A to D are frequency bands for communication systems built using radio access technology (RAT) and are defined in advance by standardization organizations (e.g., 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers)). Examples of communication systems include 5G NR systems, LTE systems, and WLAN (Wireless Local Area Network) systems.

[0050] The switch circuit 51 is connected between the antenna connection terminal 100 and the filters 41 to 44, and includes a common terminal 510 and selection terminals 511, 512, 513, and 514. The common terminal 510 is connected to the antenna connection terminal 100. The selection terminals 511 to 514 are connected to the filters 41 to 44, respectively.

[0051] In such a connection configuration, the switch circuit 51 can exclusively connect the common terminal 510 to the selection terminals 511 to 514, for example, based on a control signal from the RFIC 3. The switch circuit 51 is configured, for example, as an SP4T (Single-Pole Quadruple-Throw) type switch circuit.

[0052] The switch circuit 52 is connected between the Doherty amplifier circuit 10 and the filters 41 to 44, and includes a common terminal 520 and selection terminals 521, 522, 523, and 524. The common terminal 520 is connected to the Doherty amplifier circuit 10. The selection terminals 521 to 524 are connected to the filters 41 to 44, respectively.

[0053] In such a connection configuration, the switch circuit 52 can exclusively connect the common terminal 520 to the selection terminals 521 to 524 based on, for example, a control signal from the RFIC 3. The switch circuit 52 is configured, for example, by an SP4T type switch circuit.

[0054] 3. Circuit Configuration of Doherty Amplifier Circuit 10 Next, the circuit configuration of the Doherty amplifier circuit 10 according to this embodiment will be described with reference to FIG.

[0055] 3 is an exemplary circuit diagram, and the Doherty amplifier circuit 10 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore, the description of the Doherty amplifier circuit 10 provided below should not be construed as limiting.

[0056] The Doherty amplifier circuit 10 includes power amplifiers 11, 12, and 13, a divider 21, a combiner 22, bias circuits 31 and 32, a switch 33, a capacitor 34, a high-frequency input terminal 101, a high-frequency output terminal 102, and a power supply voltage terminal 103.

[0057] The radio frequency input terminal 101 is an external connection terminal of the Doherty amplifier circuit 10. The radio frequency input terminal 101 is connected to the RFIC 3 outside the Doherty amplifier circuit 10, and is connected to the distributor 21 inside the Doherty amplifier circuit 10. The Doherty amplifier circuit 10 can receive transmission signals of bands A to D from the RFIC 3 via the radio frequency input terminal 101.

[0058] The radio frequency output terminal 102 is an external connection terminal of the Doherty amplifier circuit 10. The radio frequency output terminal 102 is connected to the common terminal 520 of the switch circuit 52 outside the Doherty amplifier circuit 10, and is connected to the combiner 22 inside the Doherty amplifier circuit 10. The Doherty amplifier circuit 10 can supply the amplified transmission signals of bands A to D to the switch circuit 52 via the radio frequency output terminal 102.

[0059] The power supply voltage terminal 103 is an external connection terminal of the Doherty amplifier circuit 10. The power supply voltage terminal 103 is connected to the tracker circuit 5 outside the Doherty amplifier circuit 10, and is connected to the power amplifiers 11 to 13 inside the Doherty amplifier circuit 10. The Doherty amplifier circuit 10 can receive a power supply voltage from the tracker circuit 5 via the power supply voltage terminal 103.

[0060] The power amplifier 11 is an example of a first power amplifier and is used as a carrier amplifier. The power amplifier 11 is a power stage (output stage) of a multi-stage amplifier circuit, and can amplify the high-frequency signal amplified by the power amplifier 13 using a power supply voltage supplied from the tracker circuit 5. The input terminal of the power amplifier 11 is connected to the distributor 21, and the output terminal of the power amplifier 11 is connected to the combiner 22.

[0061] The power amplifier 12 is an example of a second power amplifier and is used as a peak amplifier. The power amplifier 12 is a power stage (output stage) of a multi-stage amplifier circuit, and can amplify the high-frequency signal amplified by the power amplifier 13 using the power supply voltage supplied from the tracker circuit 5. The input terminal of the power amplifier 12 is connected to the distributor 21, and the output terminal of the power amplifier 12 is connected to the combiner 22.

[0062] The size of the power amplifier 12 is smaller than the size of the power amplifier 11. As a result, in the Doherty amplifier circuit 10 (present embodiment), fluctuations in output power and efficiency due to operation and non-operation of the peak amplifier are smaller than in a Doherty amplifier circuit (comparative example) in which the size of the peak amplifier is equal to the size of the carrier amplifier, and the difference in output power at which peak efficiency can be obtained (back-off) is smaller.

[0063] 4 is a graph showing the relationship between output power and efficiency in the Doherty amplifier circuits according to the present embodiment and a comparative example. In FIG. 4, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit. In the Doherty amplifier circuit according to the comparative example, the size of the peak amplifier is equal to the size of the carrier amplifier, and a back-off of 6 dB is obtained. In the Doherty amplifier circuit 10 according to the present embodiment, the size of the peak amplifier is smaller than the size of the carrier amplifier, and therefore a back-off of 3 dB, which is smaller than the 6 dB back-off, is obtained.

[0064] The power amplifier 13 is an example of a third power amplifier and serves as a drive stage (input stage) of a multistage amplifier circuit. An input terminal of the power amplifier 13 is connected to the radio frequency input terminal 101, and an output terminal of the power amplifier 13 is connected to the divider 21. The power amplifier 13 does not necessarily have to be included in the Doherty amplifier circuit 10.

[0065] The power amplifiers 11 to 13 may be configured with heterojunction bipolar transistors (HBTs) and may be manufactured using semiconductor materials. Examples of the semiconductor material that may be used include silicon germanium (SiGe) and gallium arsenide (GaAs). The amplifying transistors of the power amplifiers 11 to 13 are not limited to HBTs. For example, the power amplifiers 11 to 13 may be configured with high electron mobility transistors (HEMTs) or metal-semiconductor field effect transistors (MESFETs). In this case, gallium nitride (GaN) or silicon carbide (SiC) may be used as the semiconductor material. Furthermore, different types of amplifying transistors may be used for the power amplifiers 11 and 12 and the power amplifier 13. For example, the power amplifiers 11 and 12 may be configured with HBTs, and the power amplifier 13 may be configured with a complementary metal oxide semiconductor (CMOS).

[0066] The divider 21 is connected between the power amplifier 13 and the power amplifiers 11 and 12, and can divide the high-frequency signal amplified by the power amplifier 13 into two high-frequency signals having a phase difference of 90 degrees and supply them to the power amplifiers 11 and 12, respectively. Specifically, the divider 21 includes an input terminal 211 and output terminals 212 and 213. The input terminal 211 is an example of a third input terminal and is connected to the output terminal of the power amplifier 13. The output terminal 212 is an example of a second output terminal and is connected to the input terminal of the power amplifier 11. The output terminal 213 is an example of a third output terminal and is connected to the input terminal of the power amplifier 12. Note that the divider 21 does not necessarily have to be included in the Doherty amplifier circuit 10. In this case, the Doherty amplifier circuit 10 may have two high-frequency input terminals for respectively receiving the two high-frequency signals that have already been divided.

[0067] In FIG. 3 , a quadrature hybrid coupler (90-degree hybrid coupler) is used as the divider 21. The quadrature hybrid coupler of the divider 21 may be, for example, a parallel plate coupler, a lumped constant coupler, a quarter-wavelength line coupler, or a branch-line coupler, but is not limited to these. Furthermore, the divider 21 is not limited to a quadrature hybrid coupler. For example, the divider 21 may be a 180-degree hybrid coupler or an in-phase divider (e.g., a Wilkinson divider). In this case, a phase adjustment circuit may be connected to the 180-degree hybrid coupler or the in-phase divider.

[0068] The combiner 22 is connected between the power amplifiers 11 and 12 and the high-frequency output terminal 102, and can combine two high-frequency signals amplified by the power amplifiers 11 and 12, which have a phase difference of 90 degrees, and supply the combined signal to the high-frequency output terminal 102. Specifically, the combiner 22 includes input terminals 221 and 222, an output terminal 223, and a quarter-wave line 224. The input terminal 221 is an example of a first input terminal and is connected to the output terminal of the power amplifier 11. The input terminal 222 is an example of a second input terminal and is connected to the output terminal of the power amplifier 12. The output terminal 223 is an example of a first output terminal and is connected to the high-frequency output terminal 102. The quarter-wave line 224 is connected between the input terminal 221 and the output terminal 223, and can shift the phase of the high-frequency signal amplified by the power amplifier 11 by −90 degrees (delay by 90 degrees). Furthermore, the quarter-wave line 224 can rotate the load impedance by 180 degrees on the Smith chart.

[0069] The bias circuit 31 is connected to the power amplifier 11 and can supply a bias current to the power amplifier 11. The bias circuit 31 can supply a bias current according to a power control level.

[0070] The bias circuit 32 is connected to the power amplifier 12 and can supply a bias current to the power amplifier 12. The bias circuit 31 can supply a bias current according to the power control level.

[0071] The switch 33 and the capacitor 34 are connected in series between a path connecting the output terminal of the power amplifier 11 and the input terminal 221 of the combiner 22 and ground. In FIG. 3 , the capacitor 34 is connected between the switch 33 and ground. Specifically, one end of the switch 33 is connected to the path connecting the output terminal of the power amplifier 11 and the input terminal 221 of the combiner 22, and the other end of the switch 33 is connected to the capacitor 34. One of the two electrodes of the capacitor 34 is connected to the switch 33, and the other of the two electrodes of the capacitor 34 is connected to ground. Note that the switch 33 may be connected between the capacitor 34 and ground. Furthermore, the switch 33 and the capacitor 34 do not have to be included in the Doherty amplifier circuit 10.

[0072] In such a connection configuration, the switch 33 can switch between conductive and non-conductive states based on, for example, a control signal from the RFIC 3. The switch 33 is configured by, for example, a single-pole single-throw (SPST) type switch circuit.

[0073] 3, other circuit elements, wiring, etc. may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawing. For example, in the Doherty amplifier circuit 10, an impedance matching circuit may be inserted between the power amplifier 13 and the divider 21.

[0074] 4. Operation of Doherty Amplifier Circuit 10 The operation of the Doherty amplifier circuit 10 described above will be described with reference to Fig. 5. Fig. 5 is a flowchart showing the operation of the Doherty amplifier circuit 10 according to this embodiment.

[0075] First, as shown in Fig. 5, a determination is made between a high power (HP) mode and a low power (LP) mode (S100). The HP mode is a mode that is applied when the power control level is equal to or greater than a threshold level. On the other hand, the LP mode is a mode that is applied when the power control level is less than the threshold level. The threshold level can be determined in advance experimentally and / or empirically.

[0076] If the HP mode is determined in step S100 (HPM in S100), the switch 33 is set to the OFF state (S102). That is, the switch 33 is open, and the capacitor 34 is not connected between the path connecting the power amplifier 11 and the combiner 22 and ground. Furthermore, the bias circuit 31 supplies a bias current Ib11 to the power amplifier 11 (carrier amplifier) ​​(S104). As a result, the power amplifier 11 operates in class A or class AB. Furthermore, the bias circuit 32 supplies a bias current Ib21 to the power amplifier 12 (peaking amplifier) ​​(S106). The bias current Ib21 is an example of a first bias current, and has a smaller current value than the bias current Ib22, which will be described later. As a result, the power amplifier 12 operates in class C. In this state, the D-ET mode, the SPT mode, or the APT mode is applied to the Doherty amplifier circuit 10 (S108). For example, when the modulation bandwidth (channel bandwidth) of the high frequency signal is less than the threshold width, the D-ET mode or the SPT mode may be applied, and when the modulation bandwidth of the high frequency signal is equal to or greater than the threshold width, the APT mode may be applied.

[0077] On the other hand, if the LP mode is determined in step S100 (LPM in S100), the switch 33 is set to the ON state (S112). That is, the switch 33 is closed, and the capacitor 34 is connected between the path connecting the power amplifier 11 and the combiner 22 and ground. Furthermore, the bias circuit 31 does not supply a bias current to the power amplifier 11 (carrier amplifier) ​​(S114). As a result, the power amplifier 11 does not operate. Furthermore, the bias circuit 32 supplies a bias current Ib22 to the power amplifier 12 (peaking amplifier) ​​(S116). The bias current Ib22 is an example of a second bias current and has a current value greater than the bias current Ib21. As a result, the power amplifier 12 operates in class A or class AB. In this state, the APT mode is applied to the Doherty amplifier circuit 10 (S118).

[0078] Each of the above modes will now be described in detail with reference to FIGS.

[0079] Fig. 6 is a diagram showing the state of the Doherty amplifier circuit in HP mode and D-ET mode / SPT mode. Fig. 7 is a graph showing the relationship between output power and efficiency in HP mode and D-ET mode / SPT mode. In Fig. 7, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit 10.

[0080] 6, in the HP mode and the D-ET / SPT mode, the switch 33 is opened, and the bias circuits 31 and 32 supply bias currents Ib11 and Ib21 to the power amplifiers 11 and 12, respectively. As a result, the power amplifiers 11 and 12 operate in class AB (or class A) and class C, respectively. Furthermore, the power amplifiers 11 to 13 are supplied with a power supply voltage Vcc1 that varies among a plurality of discrete voltage levels Vcc11 to Vcc13 within one frame based on the envelope or symbol.

[0081] As a result, the relationship between output power Pout and power-added efficiency Eff is obtained as shown in FIG. 7 . At voltage level Vcc13, a 3 dB back-off is achieved by operating and deactivating the peak amplifier and the resulting change in load impedance. Achieving a 3 dB back-off, which is smaller than the 5 dB back-off corresponding to the PAPR (Peak-to-Average Power Ratio) of a typical high-frequency signal, allows the voltage level of power supply voltage Vcc1 to be switched before power amplifiers 11 and 12 saturate, thereby suppressing gain fluctuations. This reduces the difficulty of digital pre-distortion (DPD) and contributes to reducing distortion.

[0082] At lower output power Pout, the power supply voltage Vcc1 is supplied at a voltage level Vcc12, which is lower than the voltage level Vcc13, thereby expanding the high-efficiency region.At even lower output power Pout, the power supply voltage Vcc1 is supplied at a voltage level Vcc11, which is lower than the voltage level Vcc12, thereby further expanding the high-efficiency region.This makes it possible to achieve high efficiency in the 5 dB back-off region, which corresponds to the PAPR of a typical high-frequency signal.

[0083] Fig. 8 is a diagram showing the state of the Doherty amplifier circuit in HP mode and APT mode. Fig. 9 is a graph showing the relationship between input power and efficiency in HP mode and APT mode. In Fig. 9, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit 10.

[0084] 8, in the HP mode and the APT mode, the switch 33 is opened, and the bias circuits 31 and 32 supply bias currents Ib11 and Ib21 to the power amplifiers 11 and 12, respectively. As a result, the power amplifiers 11 and 12 operate in class AB (or class A) and class C, respectively. Furthermore, the power amplifiers 11 to 13 are supplied with a power supply voltage Vcc2 that fluctuates among a plurality of discrete voltage levels in one-frame units based on the average power.

[0085] As a result, the relationship between output power Pout and power-added efficiency Eff is obtained as shown in Figure 9. A 3 dB back-off is achieved by operating and not operating the peak amplifier and by changing the load impedance accordingly. Such an APT mode may be used when it is difficult to apply the D-ET mode or SPT mode in the HP mode.

[0086] Fig. 10 is a diagram showing the state of the Doherty amplifier circuit in LP mode and APT mode. Fig. 11 is a graph showing the relationship between input power and efficiency in LP mode and APT mode. In Fig. 11, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit 10.

[0087] 10, in the LP mode and the APT mode, the bias circuit 31 does not supply a bias current to the power amplifier 11, and the bias circuit 32 supplies a bias current Ib22 having a current value greater than the bias current Ib21 to the power amplifier 12. As a result, the power amplifier 11 is shut down (SD), and the power amplifier 12 operates in class AB (or class A). Furthermore, the power amplifiers 11 to 13 are supplied with a power supply voltage Vcc2 that fluctuates among a plurality of discrete voltage levels in one-frame units based on the average power.

[0088] At this time, the switch 33 is closed, causing the output impedance of the power amplifier 11 to be in a short state and rotated 180 degrees on the Smith chart by the quarter-wave line 224. Therefore, the impedance of the power amplifier 11 as viewed from the output terminal 223 is in an open state.

[0089] As a result, the relationship between the output power Pout and the power-added efficiency Eff is obtained as shown in Fig. 11. The smaller-sized power amplifier 12 operates and the larger-sized power amplifier 11 is stopped, thereby reducing the power consumption of the Doherty amplifier circuit 10. Furthermore, by applying the APT mode, the power consumption of the tracker circuit 5 is also reduced.

[0090] [5. Summary] As described above, the Doherty amplifier circuit 10 according to the present embodiment is a Doherty amplifier circuit 10 to which the D-ET mode or the SPT mode is applied, and includes a power amplifier 11 used as a carrier amplifier, a power amplifier 12 used as a peak amplifier, and a combiner 22 including an input terminal 221 connected to an output end of the power amplifier 11 and an input terminal 222 and an output terminal 223 connected to the output end of the power amplifier 12, and the size of the power amplifier 12 is smaller than the size of the power amplifier 11.

[0091] According to this, since the peak amplifier is smaller than the carrier amplifier, fluctuations in output power and efficiency due to operation and non-operation of the peak amplifier are reduced, and a smaller back-off is realized. Further efficiency improvement can be achieved by the synergistic effect of the smaller back-off provided by the Doherty amplifier circuit and the D-ET mode or SPT mode. Furthermore, the voltage level of the power supply voltage Vcc1 can be switched before the power amplifiers 11 and 12 reach saturation, thereby suppressing gain fluctuations. As a result, the difficulty of digital predistortion can be reduced, contributing to distortion reduction.

[0092] Also, for example, in the Doherty amplifier circuit 10 according to this embodiment, in the HP mode in which the power control level is equal to or higher than the threshold level, the power amplifiers 11 and 12 may operate, and in the LP mode in which the power control level is lower than the threshold level, the power amplifier 12 may operate and the power amplifier 11 may be shut down.

[0093] This allows for high output power by operating the two power amplifiers 11 and 12 in HP mode, while high efficiency can be achieved by shutting down the larger power amplifier 11 in LP mode.

[0094] Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the combiner 22 may include a quarter-wave line 224 connected between the input terminal 221 and the output terminal 223 .

[0095] In this way, impedance conversion according to the output of the peak amplifier is performed by the quarter-wave line 224, and power efficiency can be improved.

[0096] For example, the Doherty amplifier circuit 10 according to this embodiment may further include a switch 33 and a capacitor 34 connected in series between the path connecting the output end of the power amplifier 11 and the input terminal 221 and ground.

[0097] According to this, by opening and closing the switch 33, it is possible to adjust the impedance (phase) of the power amplifier 11 as viewed from the output terminal 223 of the combiner 22.

[0098] Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the switch 33 may be opened in the HP mode, and the switch 33 may be closed in the LP mode.

[0099] According to this, since the switch 33 is closed in the LP mode, the impedance of the power amplifier 11 as viewed from the output terminal 223 of the combiner 22 can be made closer to an open state when the power amplifier 11 is shut down. Therefore, it is possible to prevent the high frequency signal amplified by the power amplifier 12 from leaking to the power amplifier 11 side, and it is possible to improve power efficiency.

[0100] Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the power amplifier 12 may operate in class C in the HP mode, and may operate in class A or class AB in the LP mode.

[0101] According to this, by operating the power amplifier 12 in class C in the HP mode, it can be operated as a peak amplifier, thereby improving power efficiency. On the other hand, by operating the power amplifier 12 in class A or class AB in the LP mode, it is possible to shut down the power amplifier 11, thereby improving power efficiency at low output power.

[0102] For example, the Doherty amplifier circuit 10 according to this embodiment may further include a bias circuit 32 configured to supply a bias current to the power amplifier 12, and in the HP mode, the bias circuit 32 may supply a bias current Ib21 to the power amplifier 12, and in the LP mode, the bias circuit 32 may supply a bias current Ib22 having a current value greater than the bias current Ib21 to the power amplifier 12.

[0103] According to this, in the HP mode, the current value of the bias current of the power amplifier 12 can be reduced to operate it as a peak amplifier, thereby improving power efficiency. On the other hand, in the LP mode, the current value of the bias current of the power amplifier 12 can be increased to shut down the power amplifier 11, thereby improving power efficiency at low output power.

[0104] Furthermore, for example, in the Doherty amplifier circuit 10 according to the present embodiment, the D-ET mode, the SPT mode, or the APT mode may be applied in the HP mode, and the APT mode may be applied in the LP mode.

[0105] This allows the D-ET mode, SPT mode, or APT mode to be applied in the HP mode, which requires high output power, and by prioritizing improvement of the power-added efficiency in the Doherty amplifier circuit 10, it is possible to improve the power efficiency of the communication device 6. On the other hand, the APT mode can be applied in the LP mode, which does not require high output power, and by prioritizing suppression of power consumption in the tracker circuit 5, it is possible to improve the power efficiency of the communication device 6.

[0106] Furthermore, for example, in the Doherty amplifier circuit 10 according to the present embodiment, in the HP mode, when the modulation bandwidth of the high frequency signal is less than the threshold width, the D-ET mode or the SPT mode may be applied, and in the HP mode, when the modulation bandwidth of the high frequency signal is equal to or greater than the threshold width, the APT mode may be applied.

[0107] According to this, when the modulation bandwidth is wide and the envelope changes drastically, making tracking in the D-ET mode or SPT mode more difficult, applying the APT mode can improve power efficiency.On the other hand, when the modulation bandwidth is narrow and tracking is easier, applying the D-ET mode or SPT mode can improve power efficiency.

[0108] For example, the Doherty amplifier circuit 10 according to this embodiment may further include a power amplifier 13, and a distributor 21 including an input terminal 211 connected to the output terminal of the power amplifier 13, an output terminal 212 connected to the input terminal of the power amplifier 11, and an output terminal 213 connected to the input terminal of the power amplifier 12.

[0109] This allows the high-frequency signal amplified by power amplifier 13 to be supplied to both power amplifiers 11 and 12, thereby reducing the number of power amplifiers compared to when power amplifiers are connected individually to power amplifiers 11 and 12.

[0110] (Modification 1) Modification 1 of the embodiment will be described. This modification is different from the above embodiment mainly in that a quadrature hybrid coupler is used as a combiner. This modification will be described below with reference to FIG. 12, focusing on the differences from the above embodiment.

[0111] 12 is a circuit diagram of a Doherty amplifier circuit 10A according to this modification. Note that FIG. 12 is an exemplary circuit diagram, and the Doherty amplifier circuit 10A can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the Doherty amplifier circuit 10A provided below should not be construed as limiting.

[0112] The Doherty amplifier circuit 10A includes power amplifiers 11, 12, and 13, a divider 21, a combiner 22A, bias circuits 31 and 32, a switch 33, a capacitor 34, a high-frequency input terminal 101, a high-frequency output terminal 102, and a power supply voltage terminal 103.

[0113] The combiner 22A is a quadrature hybrid coupler that can combine two high-frequency signals having a phase difference of 90 degrees that have been amplified by the power amplifiers 11 and 12, and supply the combined signal to the high-frequency output terminal 102. Specifically, the combiner 22A includes input terminals 221 and 222 and an output terminal 223. The input terminal 221 is an example of a first input terminal and is connected to the output terminal of the power amplifier 11. The input terminal 222 is an example of a second input terminal and is connected to the output terminal of the power amplifier 12. The output terminal 223 is an example of a first output terminal and is connected to the high-frequency output terminal 102.

[0114] The quadrature hybrid coupler of the combiner 22A may be, for example, a parallel plate coupler, a lumped constant coupler, a quarter wavelength line coupler, or a branch line coupler, but is not limited to these.

[0115] As described above, in the Doherty amplifier circuit 10A according to this embodiment, the combiner 22A may be a quadrature hybrid coupler.

[0116] This makes it possible to omit the quarter-wave line in the combiner 22A, thereby realizing a reduction in the size of the Doherty amplifier circuit 10A.

[0117] (Modification 2) Modification 2 of the embodiment will be described. This modification is different from the above embodiment mainly in that two drive stages are connected to two power stages individually. This modification will be described below with reference to FIG. 13, focusing on the differences from the above embodiment.

[0118] 13 is a circuit diagram of a Doherty amplifier circuit 10B according to this modification. Note that FIG. 13 is an exemplary circuit diagram, and the Doherty amplifier circuit 10B can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the Doherty amplifier circuit 10B provided below should not be construed as limiting.

[0119] The Doherty amplifier circuit 10B includes power amplifiers 11, 12, 13a, and 13b, a divider 21, a combiner 22, bias circuits 31 and 32, a switch 33, a capacitor 34, a high-frequency input terminal 101, a high-frequency output terminal 102, and a power supply voltage terminal 103.

[0120] The power amplifier 13a is an example of a third power amplifier. The input terminal of the power amplifier 13a is connected to the output terminal 212 of the distributor 21, and the output terminal of the power amplifier 13a is connected to the input terminal of the power amplifier 11. The power amplifiers 13a and 11 respectively constitute the drive stage and the power stage of a multi-stage amplifier circuit. The power amplifier 13a may be shut down in the LP mode and the APT mode, similar to the power amplifier 11.

[0121] The power amplifier 13b is an example of a fourth power amplifier. The input terminal of the power amplifier 13b is connected to the output terminal 213 of the distributor 21, and the output terminal of the power amplifier 13b is connected to the input terminal of the power amplifier 12. The power amplifiers 13b and 12 respectively constitute a drive stage and a power stage of a multi-stage amplifier circuit.

[0122] As described above, the Doherty amplifier circuit 10B according to this embodiment may further include a power amplifier 13a connected to the input terminal of the power amplifier 11 and a power amplifier 13b connected to the input terminal of the power amplifier 12.

[0123] With this, power amplifiers 13a and 13b are connected to power amplifiers 11 and 12 individually, so that when power amplifier 11 is shut down, power amplifier 13a can also be shut down, thereby improving power efficiency at low output power.

[0124] While the Doherty amplifier circuit according to the present invention has been described above based on the embodiments, the Doherty amplifier circuit according to the present invention is not limited to the above embodiments. The present invention also includes other embodiments realized by combining any of the components in the above embodiments, modifications obtained by applying various modifications to the above embodiments that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above Doherty amplifier circuit.

[0125] For example, in the circuit configuration of the Doherty amplifier circuit according to each of the above embodiments, other circuit elements, wiring, etc. may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, in the Doherty amplifier circuit 10, a phase adjustment circuit may be connected between the distributor 21 and the power amplifier 11.

[0126] The following describes the features of the Doherty amplifier circuits described based on the above embodiments.

[0127] <1> A Doherty amplifier circuit to which a digital-envelope tracking (D-ET) mode or a symbol power tracking (SPT) mode is applied, comprising: a first power amplifier used as a carrier amplifier; a second power amplifier used as a peak amplifier; and a combiner including a first input terminal connected to an output end of the first power amplifier, a second input terminal connected to an output end of the second power amplifier, and a first output terminal, wherein the size of the second power amplifier is smaller than the size of the first power amplifier.

[0128] <2> The Doherty amplifier circuit according to <1>, wherein in a high power (HP) mode in which a power control level is equal to or higher than a threshold level, the first power amplifier and the second power amplifier operate, and in a low power (LP) mode in which a power control level is lower than the threshold level, the second power amplifier operates and the first power amplifier is shut down.

[0129] <3> The Doherty amplifier circuit according to <2>, wherein the combiner includes a quarter-wave line connected between the first input terminal and the first output terminal.

[0130] <4> The Doherty amplifier circuit according to <2>, wherein the combiner is a quadrature hybrid coupler.

[0131] <5> The Doherty amplifier circuit according to <3> or <4>, further comprising a switch and a capacitor connected in series between a path connecting the output end of the first power amplifier and the first input terminal and ground.

[0132] <6> The Doherty amplifier circuit according to <5>, wherein the switch is open in the HP mode, and the switch is closed in the LP mode.

[0133] <7> The Doherty amplifier circuit according to any one of <2> to <6>, wherein in the HP mode, the second power amplifier operates in class C, and in the LP mode, the second power amplifier operates in class A or class AB.

[0134] <8> The Doherty amplifier circuit according to any one of <2> to <7>, further comprising a bias circuit configured to supply a bias current to the second power amplifier, wherein in the HP mode, the bias circuit supplies a first bias current to the second power amplifier, and in the LP mode, the bias circuit supplies a second bias current, the current value of which is larger than that of the first bias current, to the second power amplifier.

[0135] <9> The Doherty amplifier circuit according to any one of <2> to <8>, wherein a D-ET mode, an SPT mode, or an average power tracking (APT) mode is applied in the HP mode, and an APT mode is applied in the LP mode.

[0136] <10> The Doherty amplifier circuit according to <9>, wherein, in the HP mode, when a modulation bandwidth of a high-frequency signal is less than a threshold width, a D-ET mode or an SPT mode is applied, and in the HP mode, when the modulation bandwidth of the high-frequency signal is equal to or greater than the threshold width, an APT mode is applied.

[0137] <11> The Doherty amplifier circuit according to any one of <1> to <10>, further comprising: a third power amplifier; and a divider including a third input terminal connected to an output terminal of the third power amplifier, a second output terminal connected to an input terminal of the first power amplifier, and a third output terminal connected to an input terminal of the second power amplifier.

[0138] <12> The Doherty amplifier circuit according to any one of <1> to <10>, further comprising: a third power amplifier connected to an input terminal of the first power amplifier; and a fourth power amplifier connected to an input terminal of the second power amplifier.

[0139] The present invention can be widely used as a Doherty amplifier circuit disposed in the front end of communication devices such as mobile phones.

[0140] REFERENCE SIGNS LIST 1 High frequency circuit 2 Antenna 3 RFIC 4 BBIC 5 Tracker circuit 6 Communication device 10, 10A, 10B Doherty amplifier circuit 11, 12, 13, 13a, 13b Power amplifier 21 Distributor 22, 22A Combiner 31, 32 Bias circuit 33 Switch 34 Capacitor 41, 42, 43, 44 Filter 51, 52 Switch circuit 100 Antenna connection terminal 101 High frequency input terminal 102 High frequency output terminal 103 Power supply voltage terminal 211, 221, 222 Input terminal 212, 213, 223 Output terminal 224 1 / 4 wavelength line 510, 520 Common terminal 511, 512, 513, 514, 521, 522, 523, 524 Selection terminal

Claims

1. A Doherty amplifier circuit to which a digital-envelope tracking (D-ET) mode or a symbol power tracking (SPT) mode is applied, comprising: a first power amplifier used as a carrier amplifier; a second power amplifier used as a peak amplifier; and a combiner including a first input terminal connected to an output end of the first power amplifier, a second input terminal connected to an output end of the second power amplifier, and a first output terminal, wherein the size of the second power amplifier is smaller than the size of the first power amplifier.

2. The Doherty amplifier circuit of claim 1, wherein in a high power (HP) mode in which a power control level is equal to or greater than a threshold level, the first power amplifier and the second power amplifier operate, and in a low power (LP) mode in which a power control level is less than the threshold level, the second power amplifier operates and the first power amplifier is shut down.

3. The Doherty amplifier circuit according to claim 2, wherein the combiner includes a quarter-wave line connected between the first input terminal and the first output terminal.

4. The Doherty amplifier circuit according to claim 2, wherein the combiner is a quadrature hybrid coupler.

5. The Doherty amplifier circuit according to claim 3 or 4, further comprising a switch and a capacitor connected in series between a path connecting the output end of the first power amplifier and the first input terminal and ground.

6. The Doherty amplifier circuit of claim 5, wherein the switch is open in the HP mode and the switch is closed in the LP mode.

7. The Doherty amplifier circuit according to any one of claims 2 to 6, wherein in the HP mode, the second power amplifier operates in class C, and in the LP mode, the second power amplifier operates in class A or class AB.

8. The Doherty amplifier circuit according to any one of claims 2 to 7, further comprising a bias circuit configured to supply a bias current to the second power amplifier, wherein in the HP mode, the bias circuit supplies a first bias current to the second power amplifier, and in the LP mode, the bias circuit supplies a second bias current to the second power amplifier, the second bias current having a current value greater than that of the first bias current.

9. The Doherty amplifier circuit according to any one of claims 2 to 8, wherein the D-ET mode, the SPT mode, or the Average Power Tracking (APT) mode is applied in the HP mode, and the APT mode is applied in the LP mode.

10. The Doherty amplifier circuit according to claim 9, wherein, in the HP mode, when the modulation bandwidth of the high frequency signal is less than a threshold width, the D-ET mode or the SPT mode is applied, and, in the HP mode, when the modulation bandwidth of the high frequency signal is equal to or greater than the threshold width, the APT mode is applied.

11. The Doherty amplifier circuit according to any one of claims 1 to 10, further comprising: a third power amplifier; and a divider including a third input terminal connected to the output end of the third power amplifier, a second output terminal connected to the input end of the first power amplifier, and a third output terminal connected to the input end of the second power amplifier.

12. The Doherty amplifier circuit according to any one of claims 1 to 10, further comprising: a third power amplifier connected to the input terminal of the first power amplifier; and a fourth power amplifier connected to the input terminal of the second power amplifier.

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